WO2013008441A1 - Active matrix substrate and method for manufacturing same - Google Patents

Abstract

An active matrix substrate (20a) is provided with: gate electrodes (25) provided on an insulating substrate (10a) and having a second conductor film (28) formed from copper; a barrier layer (29) provided on the gate electrodes (25) and formed from silicon nitride; a planarization film (26) provided on the barrier layer (29) and formed from a baked SOG material; a gate insulating layer (12) provided so as to cover the gate electrodes (25), the barrier layer (29) and the planarization film (26); and a semiconductor layer (13) provided on the gate insulating film (12) and having channel regions (C) provided so as to be on top of the gate electrodes (25).

Description

Active matrix substrate and manufacturing method thereof

The present invention relates to an active matrix substrate and a manufacturing method thereof, and more particularly to an active matrix substrate using a planarizing film and a manufacturing method thereof.

In the active matrix substrate, for example, a thin film transistor (hereinafter also referred to as “TFT”) is provided as a switching element for each pixel which is the minimum unit of an image.

In addition, in order to improve the reliability of the active matrix substrate, it is necessary to form TFTs and wirings formed on the substrate with high accuracy. In such an active matrix substrate, for example, an electrode is formed on an insulating substrate. In addition, a wiring pattern is formed in a concavo-convex shape, and a flattening film which is an insulating film is formed to cover and flatten the concavo-convex pattern. This planarizing film is generally composed of an SOG (Spin on Glass) material, liquid SiO ₂ , a polymer film, or the like.

In general, an active matrix substrate includes a gate electrode, a source electrode, and a drain electrode that constitute the above-described TFT. In order to prevent excessive etching due to an etching process in the manufacturing process, these are provided. The electrode is formed of a laminated film composed of a plurality of conductive films. For example, in the case of a gate electrode, a titanium film is formed as the first conductive film on the lower layer side, and a copper film is formed as the second conductive film on the upper layer side. And the above-mentioned planarization film is formed on the surface of this gate electrode (for example, refer to patent documents 1).

JP 2011-86954 A

Here, for example, an SOG material mainly composed of silanol (Si (OH) ₄ ) is applied to the entire substrate on which the gate electrode is formed, and then flattened by baking at a high temperature (eg, 350 ° C.). When the film is formed, a dehydration polymerization reaction occurs in the SOG material, moisture is generated, and the copper film constituting the gate electrode is oxidized by the moisture, so that the resistance of the gate electrode constituted by the copper film increases. There was a problem.

Moreover, copper diffuses from the copper film into the SOG material by the firing. As a result, there has been a problem that the dielectric constant of the SOG material is increased and the insulation is lowered.

Therefore, the present invention has been made in view of such a point, and the object of the present invention is to prevent copper film oxidation and to diffuse copper when forming a planarizing film on the surface of the copper film. It is an object of the present invention to provide an active matrix substrate and a method for manufacturing the same.

In order to achieve the above object, an active matrix substrate of the present invention includes an insulating substrate, a gate electrode provided on the insulating substrate and having a conductive film formed of copper, a gate electrode provided on the gate electrode, and silicon nitride. A formed barrier layer, a planarization film formed on the barrier layer and formed of a fired SOG material, a gate insulating layer provided to cover the gate electrode, the barrier layer, and the planarization film, and a gate A semiconductor layer provided on the insulating layer and having a channel region provided so as to overlap with the gate electrode; and a source electrode provided on the semiconductor layer so as to overlap with the gate electrode and to face each other across the channel region; A drain electrode, a semiconductor layer, a protective layer covering the source electrode and the drain electrode, and a pixel electrode provided on the protective layer are provided.

According to this configuration, the barrier layer formed of silicon nitride is provided between the gate electrode having the conductive film formed of copper and the planarization film formed of the fired SOG material. In this case, when the SOG material is applied to the entire substrate on which the gate electrode is formed and then baked at a high temperature to form a planarization film, a dehydration polymerization reaction occurs in the SOG material and moisture is generated. However, it is possible to prevent copper constituting the gate electrode from being oxidized by moisture. In addition, the diffusion of copper from the conductive film into the SOG material can be prevented by firing. Therefore, an increase in the resistance of the gate electrode can be suppressed, and an increase in the dielectric constant of the SOG material can be suppressed to prevent a decrease in the insulating property of the planarization film.

In the active matrix substrate of the present invention, an interlayer insulating layer may be provided on the protective layer, and a pixel electrode may be provided on the interlayer insulating layer.

In the active matrix substrate of the present invention, the semiconductor layer may be an oxide semiconductor layer.

In the active matrix substrate of the present invention, the oxide semiconductor layer includes at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn). It is preferable to consist of a metal oxide.

According to the same configuration, the oxide semiconductor layer made of these materials has high mobility even if it is amorphous, so that the on-resistance of the switching element can be increased.

In the active matrix substrate of the present invention, the oxide semiconductor layer is preferably made of indium gallium zinc oxide (IGZO).

According to the same configuration, good characteristics such as high mobility and low off-state current can be obtained in the thin film transistor.

In the active matrix substrate of the present invention, the semiconductor layer may be a silicon-based semiconductor layer.

The manufacturing method of the active matrix substrate of the present invention includes a gate electrode forming step of forming a gate electrode having a conductive film formed of copper on an insulating substrate, and silicon nitride on the insulating substrate so as to cover the gate electrode. A barrier layer forming step for forming the formed barrier layer; a planarizing film forming step for forming a planarizing film on the barrier layer by applying and baking an SOG material on the barrier layer; Forming a gate insulating layer so as to cover the oxide film, forming a semiconductor layer having a channel region provided on the gate insulating layer so as to overlap the gate electrode, and a semiconductor A source drain and a drain electrode are formed on the layer so as to overlap the gate electrode and to face each other with the channel region interposed therebetween. And forming step, the semiconductor layer, characterized in that it comprises at least a protective layer forming step of forming a protective layer covering the source electrode, and a drain electrode and a pixel electrode forming step of forming a pixel electrode on the protective layer.

According to this configuration, a gate layer formed of silicon nitride is formed between a gate electrode having a conductive film formed of copper and a planarization film formed of a baked SOG material. Even when a dehydration polymerization reaction occurs in the SOG material and moisture is generated when the planarization film is formed by applying the SOG material to the entire substrate on which the electrodes are formed and then baking at a high temperature. It is possible to prevent the copper constituting the gate electrode from being oxidized by moisture. In addition, the diffusion of copper from the conductive film into the SOG material can be prevented by firing. Therefore, an increase in the resistance of the gate electrode can be suppressed, and an increase in the dielectric constant of the SOG material can be suppressed to prevent a decrease in the insulating property of the planarization film.

In the manufacturing method of the active matrix substrate of the present invention, the barrier layer on the gate electrode may be removed in the planarization film forming step.

According to this configuration, for example, when the planarization film is patterned by dry etching in the planarization film forming step, the barrier layer damaged by this dry etching does not remain on the gate electrode. Therefore, when forming the gate insulating layer, it is possible to prevent the occurrence of a disadvantage that the device characteristics of the thin film transistor are deteriorated due to an increase in defects at the interface between the barrier layer on the gate electrode constituting the thin film transistor and the gate insulating layer. It becomes possible.

In the manufacturing method of the active matrix substrate of the present invention, the semiconductor layer may be formed using the same photomask in the semiconductor layer forming step and the source / drain forming step, and the source electrode and the drain electrode may be formed. .

According to this configuration, the active matrix substrate can be manufactured with a smaller number of masks than when separate photomasks are used in the semiconductor layer forming step and the source / drain forming step. Therefore, the manufacturing cost can be reduced and the yield can be effectively suppressed from decreasing.

According to the present invention, an increase in the resistance of the gate electrode can be suppressed, and an increase in the dielectric constant of the SOG material can be suppressed to prevent a decrease in the insulating property of the planarization film.

1 is a cross-sectional view of a liquid crystal display panel including an active matrix substrate according to a first embodiment of the present invention. 1 is a plan view of an active matrix substrate according to a first embodiment of the present invention. It is the top view to which the pixel part and terminal part of the active matrix substrate which concern on the 1st Embodiment of this invention were expanded. FIG. 4 is a cross-sectional view taken along line AA in FIG. 3. It is explanatory drawing which shows the manufacturing process of the active matrix substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the opposing board | substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the active matrix substrate which concerns on the 2nd Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the active matrix substrate which concerns on the 3rd Embodiment of this invention in a cross section. It is sectional drawing of the active matrix substrate which concerns on the modification of this invention. It is explanatory drawing which shows the manufacturing process of the active matrix substrate which concerns on the modification of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the active matrix substrate which concerns on the other modification of this invention in a cross section. It is sectional drawing of the active matrix board | substrate which concerns on the other modification of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

(First embodiment)
FIG. 1 is a cross-sectional view of a liquid crystal display panel including an active matrix substrate according to the first embodiment of the present invention, and FIG. 2 is a plan view of the active matrix substrate according to the first embodiment of the present invention. is there. FIG. 3 is an enlarged plan view of the pixel portion and the terminal portion of the active matrix substrate according to the first embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line AA of FIG.

As shown in FIG. 1, the liquid crystal display panel 50 includes an active matrix substrate 20a and a counter substrate 30 provided so as to face each other, and a liquid crystal layer 40 provided between the active matrix substrate 20a and the counter substrate 30. I have. The liquid crystal display panel 50 also adheres the active matrix substrate 20a and the counter substrate 30 to each other, and seals 37 provided in a frame shape to enclose the liquid crystal layer 40 between the active matrix substrate 20a and the counter substrate 30. It has.

Further, in the liquid crystal display panel 50, as shown in FIG. 1, a display region D for displaying an image is defined in the inner portion of the sealant 37, and a terminal region T is formed in a portion protruding from the counter substrate 30 of the active matrix substrate 20a. Is stipulated.

As shown in FIGS. 2, 3 and 4, the active matrix substrate 20a includes an insulating substrate 10a and a plurality of scanning wirings 11a provided in the display region D so as to extend parallel to each other on the insulating substrate 10a. A plurality of auxiliary capacitance lines 11b provided between the scanning lines 11a and extending in parallel to each other, and a plurality of signal lines 16a provided to extend in parallel to each other in a direction orthogonal to the scanning lines 11a are provided. Yes. The active matrix substrate 20a includes a plurality of TFTs 5a provided for each intersection of the scanning wirings 11a and the signal wirings 16a, that is, for each pixel, and a protective layer 17 provided so as to cover the TFTs 5a. The interlayer insulating layer 18 provided so as to cover the protective layer 17, the plurality of pixel electrodes 19a provided in a matrix on the interlayer insulating layer 18 and connected to the respective TFTs 5a, and the pixel electrodes 19a are covered. And an alignment film (not shown).

As shown in FIGS. 2 and 3, the scanning wiring 11a is drawn out to the gate terminal region Tg of the terminal region T (see FIG. 1), and is connected to the gate terminal 19b in the gate terminal region Tg.

As shown in FIG. 3, the auxiliary capacity line 11b is connected to the auxiliary capacity terminal 19d via the auxiliary capacity main line 16c and the relay line 11d. Here, the auxiliary capacity trunk line 16c is connected to the auxiliary capacity line 11b via the contact hole Cc formed in the gate insulating layer 12, and is connected to the relay line via the contact hole Cd formed in the gate insulating layer 12. 11d.

2 and 3, the signal wiring 16a is drawn out as a relay wiring 11c to the source terminal region Ts in the terminal region T (see FIG. 1), and is connected to the source terminal 19c in the source terminal region Tg. Yes. Further, as shown in FIG. 3, the signal wiring 16 a is connected to the relay wiring 11 c through a contact hole Cb formed in the gate insulating layer 12.

3 and 4, the TFT 5a includes a gate electrode 25 provided on the insulating substrate 10a, a planarizing film 26 provided on the gate electrode 25 and formed of a spin-on glass material, and the gate electrode 25. And the gate insulating layer 12 provided so as to cover the planarizing film 26. In addition, the TFT 5 a includes a semiconductor layer 13 having a channel region C provided in an island shape so as to overlap the gate electrode 25 on the gate insulating layer 12, and the gate region 25 on the semiconductor layer 13. A source electrode 16aa and a drain electrode 16b are provided so as to be opposed to each other.

Here, as shown in FIG. 3, the gate electrode 25 is a portion protruding to the side of the scanning wiring 11a. The gate electrode 25 is provided on the insulating substrate 10a, and is provided on the first conductive film 27 formed of a metal other than copper (for example, titanium) and the first conductive film 27, and is formed of copper. The second conductive film 28 is used.

Further, as shown in FIG. 3, the source electrode 16aa is a portion protruding to the side of the signal wiring 16a. As shown in FIG. 4, the source electrode 16aa is formed by a laminated film of the first conductive layer 14a and the second conductive layer 15a. It is configured.

Furthermore, as shown in FIGS. 3 and 4, the drain electrode 16b is composed of a laminated film of a first conductive layer 14b and a second conductive layer 15b. The drain electrode 16b is connected to the pixel electrode 19a via a contact hole Ca formed in the laminated film of the protective layer 17 and the interlayer insulating layer 18, and overlaps the auxiliary capacitance line 11b via the gate insulating layer 12. This constitutes an auxiliary capacity.

The semiconductor layer 13 is formed of a silicon layer. For example, a lower intrinsic amorphous silicon layer 13a and an n ⁺ amorphous silicon layer (electrode contact layer) doped with an n-type impurity (for example, phosphorus) thereabove. ) 13b.

As shown in FIG. 6C, which will be described later, the counter substrate 30 includes an insulating substrate 10b, a black matrix 21 provided in a lattice shape on the insulating substrate 10b, and a red color provided between each lattice of the black matrix 21. And a color filter layer having a colored layer 22 such as a green layer and a blue layer. The counter substrate 30 includes a common electrode 23 provided so as to cover the color filter layer, a photo spacer 24 provided on the common electrode 23, and an alignment film (not shown) provided so as to cover the common electrode 23. ).

The liquid crystal layer 40 is made of a nematic liquid crystal material having electro-optical characteristics.

In the liquid crystal display panel 50 configured as described above, in each pixel, when a gate signal is sent from the gate driver (not shown) to the gate electrode 25 via the scanning wiring 11a and the TFT 5a is turned on, the source driver ( A source signal is sent from the not-shown source electrode 16aa to the source electrode 16aa via the signal wiring 16a. Then, a predetermined charge is written into the pixel electrode 19a through the semiconductor layer 13 and the drain electrode 16b. At this time, a potential difference is generated between each pixel electrode 19a of the active matrix substrate 20a and the common electrode 23 of the counter substrate 30, and the liquid crystal layer 40, that is, the liquid crystal capacitance of each pixel, and the liquid crystal capacitance connected in parallel to the liquid crystal layer. A predetermined voltage is applied to the auxiliary capacitor. In the liquid crystal display panel 50, an image is displayed by adjusting the light transmittance of the liquid crystal layer 40 by changing the alignment state of the liquid crystal layer 40 according to the magnitude of the voltage applied to the liquid crystal layer 40 in each pixel. .

Here, in the present embodiment, as shown in FIG. 4, a barrier layer 29 made of silicon nitride is formed on the gate electrode 25 and between the gate electrode 25 and the planarizing film 26. There is a feature in that.

In the present embodiment, the barrier layer 29 made of silicon nitride is provided on the second conductive film 28 made of copper. Therefore, for example, silanol (Si After applying the SOG material containing (OH) ₄ ) as a main component, baking is performed at a high temperature (for example, 350 ° C.) to form a dehydration polymerization reaction in the SOG material to form moisture when forming the planarizing film 26. Even when this occurs, it is possible to prevent copper constituting the gate electrode 25 from being oxidized by the moisture. Accordingly, it is possible to prevent the resistance of the second conductive film 28 made of copper constituting the gate electrode 25 from increasing. In addition, since the firing can prevent copper from diffusing from the second conductive film 28 into the SOG material, it is possible to prevent inconveniences such as an increase in the dielectric constant of the SOG material and a decrease in insulation. Can do.

Therefore, an increase in the resistance of the gate electrode 25 can be suppressed, and an increase in the dielectric constant of the SOG material can be suppressed to prevent a decrease in the insulating property of the planarizing film 26.

As the metal forming the first conductive film 27, a metal that has non-diffusibility and can be etched simultaneously with the copper forming the second conductive film 28 is preferably used. Examples thereof include titanium (Ti), molybdenum nitride (MoN), titanium nitride (TiN), tungsten (W), molybdenum-titanium alloy (MoTi), molybdenum-tungsten alloy (MoW), and the like.

In this embodiment, the SOG material is used as a material for forming the planarizing film 26, so that the scanning wiring 11a and each upper layer (that is, the signal wiring 16a, the drain electrode 16b, the pixel electrode 19a, and the common electrode) are formed. 23) can be reduced. Accordingly, the signal delay is reduced, and the film thickness of the scanning wiring 11a itself can be reduced. In addition, a large and high-definition liquid crystal display panel 50 can be manufactured.

Next, an example of a method for manufacturing the liquid crystal display panel 50 of the present embodiment will be described with reference to FIGS. FIG. 5 is a cross-sectional view illustrating the manufacturing process of the active matrix substrate according to the first embodiment of the present invention, and FIG. 6 is a cross-sectional view illustrating the manufacturing process of the counter substrate according to the first embodiment of the present invention. It is explanatory drawing shown by. Note that the manufacturing method of this embodiment includes an active matrix substrate manufacturing process, a counter substrate manufacturing process, and a liquid crystal injection process.

First, the TFT and active matrix substrate manufacturing process will be described.

<Gate electrode formation process>
First, for example, a titanium film (thickness of 5 to 100 nm) for the first conductive film 27 and a copper film (thickness of the second conductive film 28) are formed on the entire insulating substrate 10a such as a glass substrate by sputtering. (100 to 500 nm) are sequentially formed. Thereafter, by performing resist patterning, wet etching, and resist peeling cleaning by photolithography using a first photomask having a predetermined pattern shape on these films, as shown in FIG. Then, a gate electrode 25 composed of a laminated film of the first and second conductive films 27 and 28 is formed. At this time, the scanning wiring 11a, the auxiliary capacitance wiring 11b, and the relay wirings 11c and 11d shown in FIG. 3 are also formed at the same time.

<Barrier layer forming step>
Next, a silicon nitride film (having a thickness of about 50 nm) is formed on the entire substrate on which the gate electrode 25, the scanning wiring 11a, the auxiliary capacitance wiring 11b, and the relay wirings 11c and 11d are formed by CVD or sputtering. A barrier layer 29 is formed on the insulating substrate 10a so as to cover the gate electrode 25 and the auxiliary capacitance line 11b.

<Planarization film formation process>
Next, on the barrier layer 29, for example, an SOG material mainly composed of silanol (Si (OH) ₄ ) is applied by spin coating or slit coating, and then baked at 350 ° C. to obtain silicon oxide ( to form a SiO ₂₎ layer.

Next, the silicon oxide layer is subjected to resist patterning by photolithography using a second photomask having a predetermined pattern shape, dry etching, and resist peeling and cleaning, as shown in FIG. 5B. Then, a patterned planarization film 26 (having a thickness of 100 to 3000 nm) is formed on the barrier layer 29.

In addition, as SOG material, the thing which has an alkoxysilane and organosiloxane resin as a main component can also be used.

At this time, as described above, since the barrier layer 29 is provided on the second conductive film 28 made of copper, when the dehydration polymerization reaction occurs in the SOG material due to firing, moisture is generated. Even if it exists, it can prevent that the copper which comprises the gate electrode 25 is oxidized with the said water | moisture content. Further, the above baking can prevent copper from diffusing from the second conductive film 28 into the SOG material.

<Gate insulation layer formation process>
Next, for example, a silicon nitride film (thickness of about 200 nm to 500 nm) is formed by CVD on the entire substrate on which the planarizing film 26 is formed, and the gate electrode 25, the auxiliary capacitance line 11b, the barrier layer 29, and the like. The gate insulating layer 12 is formed so as to cover the planarization film 26.

Note that the gate insulating layer 12 may have a two-layer structure. In this case, for example, a silicon oxide film (SiOx), a silicon oxynitride film (SiOxNy, x> y), a silicon nitride oxide film (SiNxOy, x> y), or the like is used in addition to the above-described silicon nitride film (SiNx). be able to.

Further, from the viewpoint of preventing diffusion of impurities and the like from the insulating substrate 10a, a silicon nitride film or a silicon nitride oxide film is used as a lower gate insulating layer, and a silicon oxide film, as an upper gate insulating layer, Alternatively, a structure using a silicon oxynitride film is preferable.

For example, a silicon nitride film having a thickness of 100 to 200 nm is formed as a lower gate insulating layer using SiH ₄ and NH ₃ as reaction gases, and N ₂ O and SiH ₄ are reacted as an upper gate insulating layer. A silicon oxide film with a thickness of 50 nm to 100 nm can be formed as a gas.

Further, from the viewpoint of forming a dense gate insulating layer 12 with a low gate leakage current at a low film formation temperature, it is preferable to include a rare gas such as argon gas in the reaction gas and mix it in the insulating film.

<Semiconductor layer formation process>
Next, for example, an intrinsic amorphous silicon film (thickness 30 to 300 nm) and an n ⁺ amorphous silicon film (thickness 50 to 150 nm) doped with phosphorus are applied to the entire substrate on which the gate insulating layer 12 is formed by plasma CVD. As shown in FIG. 5C, the semiconductor layer 13 in which the intrinsic amorphous silicon layer 13a and the n ⁺ amorphous silicon layer 13b are stacked is formed. Then, the semiconductor layer 13 is patterned by performing resist patterning by photolithography using a third photomask having a predetermined pattern shape, dry etching, and resist peeling cleaning.

<Source drain formation process>
Next, for example, a titanium film (thickness 5 to 100 nm), a copper film (100 to 500 nm), and the like are sequentially formed on the entire substrate on which the semiconductor layer 13 is formed by a sputtering method. Thereafter, resist patterning by photolithography using a fourth photomask having a predetermined pattern shape, wet etching of the copper film, dry etching (plasma etching) on the titanium film and the n ⁺ amorphous silicon layer 13b, and the resist As shown in FIG. 5D, the signal wiring 16a (see FIG. 3), the source electrode 16aa, the drain electrode 16b, and the auxiliary capacity trunk line 16c (see FIG. 3) are formed by performing the peeling and cleaning of The channel region C of the semiconductor layer 13 is exposed.

In this embodiment, as the metal film constituting the source electrode 16aa and the drain electrode 16b, a titanium film and a copper film having a laminated structure are exemplified. However, for example, a metal such as an aluminum film, a tungsten film, a tantalum film, or a chromium film is used. The source electrode 16aa and the drain electrode 16b may be formed by a film, or a film of an alloy film or metal nitride thereof.

In addition, as a conductive material, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂₎ ), Zinc oxide (ZnO), titanium nitride (TiN), or the like may be used.

As the etching process, either dry etching or wet etching described above may be used. However, when processing a large area substrate, it is preferable to use dry etching. As an etching gas, a fluorine-based gas such as CF ₄ , NF ₃ , SF ₆ , or CHF ₃ , a chlorine-based gas such as Cl ₂ , BCl ₃ , SiCl ₄ , or CCl ₄ , an oxygen gas, or the like can be used. Alternatively, an inert gas such as argon may be added.

<Protective layer forming step>
Next, for example, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the entire substrate on which the source electrode 16aa and the drain electrode 16b are formed (that is, the TFT 5a is formed) by plasma CVD. Then, as shown in FIG. 5E, a protective layer 17 covering the TFT 5a (that is, covering the semiconductor layer 13, the source electrode 16aa and the drain electrode 16b) is formed to a thickness of about 100 to 500 nm.

The protective layer 17 is not limited to a single layer structure, and may have a two-layer structure or a three-layer structure.

<Interlayer insulation layer formation process>
Next, a photosensitive organic insulating film made of a photosensitive acrylic resin or the like is applied to the entire substrate on which the protective layer 17 is formed by spin coating or slit coating to a thickness of about 1.0 μm to 3.0 μm. To do.

Next, the organic insulating film is subjected to resist patterning, exposure and development by photolithography using a fifth photomask having a predetermined pattern shape, and resist peeling and cleaning, as shown in FIG. As described above, the interlayer insulating layer 18 having an opening corresponding to the contact hole Ca is formed on the surface of the protective layer 17.

<Contact hole formation process>
Next, by using the interlayer insulating layer 18 as a mask, dry etching using a predetermined etching gas (for example, CF ₄ gas and O ₂ gas) is performed, and a part of the protective layer 17 is removed, whereby FIG. As shown in FIG. 3, a contact hole Ca is formed in the protective layer 17 and the interlayer insulating layer 18.

<Pixel electrode formation process>
Next, a transparent conductive film such as an ITO film (thickness: about 50 nm to 200 nm) made of indium tin oxide is formed on the entire substrate on which the protective layer 17 and the interlayer insulating layer 18 are formed by sputtering. Thereafter, by patterning the resist by photolithography using the sixth photomask having a predetermined pattern shape, exposure and development, wet etching of the ITO film, and peeling and cleaning of the resist with respect to the transparent conductive film, As shown in FIG. 4, a pixel electrode 19a, a gate terminal 19b, a source terminal 19c, and an auxiliary capacitance terminal 19d (see FIG. 3) are formed.

Note that when the transmissive liquid crystal display panel 50 is formed, the pixel electrode 19a is made of indium oxide containing tungsten oxide, indium zinc oxide, indium oxide containing titanium oxide, indium tin oxide, or the like. Can do. In addition to indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), and the like can also be used.

When the reflective liquid crystal display panel 50 is formed, a conductive metal thin film having reflectivity is made of titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, and alloys thereof. A film can be used, and this metal thin film can be used as the pixel electrode 19a.

Thus, in this embodiment, the active matrix substrate 20a can be manufactured by using six photomasks.

As described above, the active matrix substrate 20a shown in FIG. 4 can be manufactured.

<Opposite substrate manufacturing process>
First, by applying a photosensitive resin colored in black, for example, by spin coating or slit coating to the entire substrate of the insulating substrate 10b such as a glass substrate, the coating film is exposed and developed to obtain a figure. As shown in FIG. 6A, the black matrix 21 is formed to a thickness of about 1.0 μm.

Next, a photosensitive resin colored in red, green or blue, for example, is applied to the entire substrate on which the black matrix 21 is formed by spin coating or slit coating. Thereafter, the coating film is exposed and developed to form a colored layer 22 (for example, a red layer) of a selected color with a thickness of about 2.0 μm as shown in FIG. The same process is repeated for the other two colors to form the other two colored layers 22 (for example, a green layer and a blue layer) with a thickness of about 2.0 μm.

Further, by depositing, for example, a transparent conductive film such as an ITO film on the substrate on which the colored layers 22 of the respective colors are formed by sputtering, the common electrode 23 has a thickness as shown in FIG. It is formed to have a thickness of about 50 nm to 200 nm.

Finally, after a photosensitive resin is applied to the entire substrate on which the common electrode 23 is formed by spin coating or slit coating, the coating film is exposed and developed, as shown in FIG. 6C. The photo spacer 24 is formed to a thickness of about 4 μm.

The counter substrate 30 can be manufactured as described above.

<Liquid crystal injection process>
First, a polyimide resin film is applied to each surface of the active matrix substrate 20a manufactured in the active matrix substrate manufacturing process and the counter substrate 30 manufactured in the counter substrate manufacturing process by a printing method, and then the coating film is applied. On the other hand, an alignment film is formed by baking and rubbing treatment.

Next, for example, a seal material 37 made of UV (ultraviolet) curing and thermosetting resin is printed in a frame shape on the surface of the counter substrate 30 on which the alignment film is formed, and then a liquid crystal is formed inside the seal material 37. Drip the material.

Furthermore, after the counter substrate 30 onto which the liquid crystal material is dropped and the active matrix substrate 20a on which the alignment film is formed are bonded together under reduced pressure, the bonded bonded body is released to atmospheric pressure. The surface and the back surface of the bonded body are pressurized.

And after irradiating UV light to the sealing material 37 pinched | interposed into the said bonding body, the sealing material 37 is hardened by heating the bonding body.

Finally, the unnecessary part is removed by dividing the bonded body in which the sealing material 37 is cured by, for example, dicing.

As described above, the liquid crystal display panel 50 of the present embodiment can be manufactured.

According to the present embodiment described above, the following effects can be obtained.

(1) In this embodiment, a barrier formed of silicon nitride between the gate electrode 25 having the second conductive film 28 formed of copper and the planarizing film 26 formed of the baked SOG material. The layer 29 is provided. Therefore, when the planarizing film 26 is formed by applying the SOG material to the entire substrate on which the gate electrode 25 is formed and then baking it at a high temperature, a dehydration polymerization reaction occurs in the SOG material and moisture is generated. Even in this case, it is possible to prevent the copper constituting the gate electrode 25 from being oxidized by moisture. Moreover, it is possible to prevent copper from diffusing from the second conductive film 28 into the SOG material by firing. Therefore, an increase in the resistance of the gate electrode 25 can be suppressed, and an increase in the dielectric constant of the SOG material can be suppressed to prevent a decrease in the insulating property of the planarizing film 26. As a result, a large and high-definition liquid crystal display panel 50 can be manufactured.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 7 is an explanatory view showing in cross section the manufacturing process of the active matrix substrate according to the second embodiment of the present invention.

The present embodiment is characterized in that the barrier layer 29 formed of silicon nitride is produced and the barrier layer 29 on the gate electrode 25 is removed when the planarizing film 26 is formed.

More specifically, when manufacturing the active matrix substrate 20a in the present embodiment, first, similarly to FIG. 5A described in the first embodiment, the gate electrode forming step and the barrier layer are performed. A formation process is performed.

<Planarization film formation process>
Next, as in the first embodiment described above, for example, an SOG material mainly composed of silanol (Si (OH) ₄ ) is applied to the entire substrate on which the barrier layer 29 is formed by spin coating or slit coating. After coating, a silicon oxide (SiO ₂ ) layer is formed by baking at 350 ° C.

Next, the silicon oxide layer is subjected to resist patterning by photolithography using a second photomask having a predetermined pattern shape, dry etching, and resist peeling and cleaning, as shown in FIG. 7A. Then, a planarizing film 26 (having a thickness of 100 to 3000 nm) is formed on the barrier layer 29.

At this time, in this embodiment, as shown in FIG. 7A, when dry etching is performed on the silicon oxide layer constituting the planarizing film 26, the barrier layer 29 on the gate electrode 25 is etched. At the same time, dry etching is performed to remove the barrier layer 29.

Here, when the above-described silicon oxide layer is dry-etched, the etched portion of the barrier layer 29 (that is, the barrier layer 29 on the gate electrode 25) is damaged by the etching. As in the embodiment, when the barrier layer 29 is formed on the gate electrode 25 and the gate insulating layer 12 is formed so as to cover the barrier layer 29 in that state, the barrier layer 29 and the gate insulating layer 12 on the gate electrode 25 are formed. Exposure to the atmosphere occurs at the interface between the barrier layer 29 and the damaged interface between the barrier layer 29 and the gate insulating layer 12, and as a result, the device characteristics of the TFT 5a deteriorate.

On the other hand, as in this embodiment, when dry etching is performed on the silicon oxide layer, the barrier layer 29 on the gate electrode 25 is simultaneously dry etched to remove the barrier layer 29 on the gate electrode 25. As a result, the damaged barrier layer 29 does not remain on the gate electrode 25. Therefore, when the gate insulating layer 12 is formed, it is possible to prevent a disadvantage that the device characteristics of the TFT 5a are deteriorated due to an increase in defects at the interface between the barrier layer 29 and the gate insulating layer 12.

Even in this embodiment, when the SOG material is applied and baked, the barrier layer 29 is not removed and is provided on the second conductive film 28 constituting the gate electrode 25. As in the case of the first embodiment described above, even when dehydration polymerization occurs in the SOG material due to firing and moisture is generated, copper constituting the gate electrode 25 is oxidized by the moisture. Can be prevented. Further, the above baking can prevent copper from diffusing from the second conductive film 28 into the SOG material.

Thereafter, similarly to FIGS. 5C to 5E described in the first embodiment, the gate insulating layer forming step, the semiconductor layer forming step, the source / drain forming step, the protective layer forming step, and the interlayer insulating layer forming are performed. By performing the process, the opening forming process, and the pixel electrode forming process, the active matrix substrate 20a shown in FIG. 7B can be manufactured.

The liquid crystal display panel 50 of this embodiment can be manufactured by performing the counter substrate manufacturing process and the liquid crystal injection process described in the first embodiment.

According to the present embodiment described above, the following effects can be obtained in addition to the above-described effect (1).

(2) In the present embodiment, the barrier layer 29 on the gate electrode 25 is removed in the planarization film forming step. Accordingly, the barrier layer 29 damaged by the dry etching when the planarizing film 26 is formed does not remain on the gate electrode 25. Therefore, when forming the gate insulating layer 12, the barrier layer 29, the gate insulating layer 12, It is possible to prevent the occurrence of inconvenience that the device characteristics of the TFT 5a are deteriorated due to an increase in defects at the interface.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 8 is an explanatory view showing in cross section the manufacturing process of the active matrix substrate according to the third embodiment of the present invention.

In the first embodiment described above, the active matrix substrate 20a is manufactured by using six photomasks. However, in this embodiment, the active matrix substrate is used by using five photomasks. It is characterized in that 20a is produced.

More specifically, when manufacturing the active matrix substrate 20a according to the present embodiment, first, as in FIGS. 5A and 5B described in the first embodiment, the first photomask is used. After performing a gate electrode formation process using, a barrier layer formation process is performed, and then a planarization film formation process is performed using a second photomask.

<Gate insulation layer process>
Next, for example, a silicon nitride film (thickness of about 200 nm to 500 nm) is formed on the entire substrate on which the planarizing film 26 has been formed by a CVD method, and as shown in FIG. Then, the gate insulating layer 12 is formed so as to cover the storage capacitor line 11b, the barrier layer 29, and the planarizing film 26.

<Semiconductor layer / source / drain formation process>
Next, for example, an intrinsic amorphous silicon film (thickness 30 to 300 nm) and an n ⁺ amorphous silicon film (thickness 50 to 150 nm) doped with phosphorus are applied to the entire substrate on which the gate insulating layer 12 is formed by plasma CVD. As shown in FIG. 8A, the semiconductor layer 13 in which the intrinsic amorphous silicon layer 13a and the n ⁺ amorphous silicon layer 13b are stacked is formed.

Next, for example, a titanium film 14 (thickness 5 to 100 nm), a copper film 15 (100 to 500 nm), and the like are sequentially formed on the entire substrate on which the semiconductor layer 13 has been formed by sputtering.

Next, a photoresist is formed on the entire substrate on which the titanium film 14 and the copper film 15 are formed, and this photoresist is patterned into a predetermined shape using half exposure using a third photomask, As shown in FIG. 8B, a photoresist 36 is formed.

Next, as shown in FIG. 8C, the photoresist 36 is ashed to remove a portion corresponding to the channel region C of the photoresist 36. Next, using this photoresist 36 as a mask, wet etching of the copper film 15 is performed, dry etching (plasma etching) on the titanium film 14 and the n ⁺ amorphous silicon layer 13b, and peeling and cleaning of the photoresist 36 are performed. 8D, the signal wiring 16a (see FIG. 3), the source electrode 16aa, the drain electrode 16b, and the auxiliary capacitance trunk line 16c (see FIG. 3) are formed, and the channel region C of the semiconductor layer 13 is formed. Expose.

Thereafter, similarly to FIG. 5E described in the first embodiment, the active matrix substrate is formed by performing the protective layer forming step, the interlayer insulating layer forming step, the opening forming step, and the pixel electrode forming step. 20a is produced.

At this time, the fifth and sixth photomasks described in the above embodiment are used as the fourth and fifth photomasks, and a total of five photomasks form a thin film transistor.

That is, in the present embodiment, in the semiconductor layer forming step and the source / drain forming step, the semiconductor layer 13 is formed using the same photomask (third photomask), and the source electrode 16aa and the drain electrode 16b are formed. It is configured to do.

Then, the gate electrode 25 and the planarization film 26 are formed using the first photomask and the second photomask, and the semiconductor layer 13, the source electrode 16aa, and the drain electrode 16b are formed using the third photomask. The interlayer insulating layer 18 is formed using the fourth photomask, and the pixel electrode 19a is formed using the fifth photomask.

According to the present embodiment described above, the following effects can be obtained in addition to the above-described effect (1).

(3) In the present embodiment, in the semiconductor layer forming step and the source / drain forming step, the semiconductor layer 13 is formed using the same photomask (third photomask), and the source electrode 16aa and the drain electrode 16b are formed. It is set as the structure to form. Therefore, since the active matrix substrate 20a can be manufactured with a smaller number of masks (5) than in the first embodiment using separate photomasks in the semiconductor layer forming step and the source / drain forming step, the manufacturing cost is reduced. This can be reduced, and the decrease in yield can be effectively suppressed.

Note that the above embodiment may be modified as follows.

In the above embodiment, the interlayer insulating layer 18 is formed on the protective layer 17, but from the viewpoint of simplifying the manufacturing process, the interlayer insulating layer 18 is formed as in the active matrix substrate 20a shown in FIG. The pixel electrode 19a may be formed on the protective layer 17 without being provided.

In this case, first, the gate electrode forming step, the planarizing film forming step, the gate insulating layer forming step, the semiconductor layer forming step, and the source / drain forming step shown in FIGS. 5A to 5D are performed. Thereafter, as a protective layer forming step, for example, a silicon oxide film, a silicon nitride film, a nitrided oxide film is formed on the entire substrate on which the source electrode 16aa and the drain electrode 16b are formed (that is, the TFT 5a is formed) by plasma CVD. A silicon film or the like is formed, and a protective layer 17 is formed so as to cover the semiconductor layer 13, the source electrode 16aa, and the drain electrode 16b as shown in FIG.

Next, as a contact hole forming step, patterning by photolithography using the above-described fifth photomask, dry etching of the protective layer 17, peeling of the resist, and washing are performed on the protective layer 17 in FIG. As shown, a contact hole Ca reaching the drain electrode 16 b is formed in the protective layer 17.

Next, as a pixel electrode forming step, a transparent conductive film such as an ITO film (thickness: about 50 nm to 200 nm) made of indium tin oxide is formed on the protective layer 17 by sputtering. Thereafter, patterning by photolithography using the above-described sixth photomask, wet etching of the transparent conductive film, peeling of the resist, and cleaning are performed on the transparent conductive film, as shown in FIG. The electrode 19a is formed. Even in such a configuration, the same effect as the above (1) can be obtained.

Moreover, in the said embodiment, although the silicon-type semiconductor layer was used as a semiconductor layer, a semiconductor layer is not limited to this, For example, the oxide which consists of indium gallium zinc oxide (IGZO) instead of a silicon-type semiconductor layer. The semiconductor layer may be used as the semiconductor layer of the TFT 5a.

In this case, first, the gate electrode forming step, the barrier layer forming step, the planarizing film forming step, and the gate insulating layer forming step shown in FIGS. 5A to 5C are performed. Thereafter, as a semiconductor layer forming step, for example, an IGZO-based oxide semiconductor film (having a thickness of about 30 to 300 nm) is formed on the entire substrate on which the gate insulating layer 12 is formed by plasma CVD. Thereafter, by performing resist patterning by photolithography using the above-described third photomask, dry etching, and resist peeling cleaning, the oxide semiconductor layer 35 is patterned as shown in FIG.

Next, as a source / drain formation step, for example, a titanium film (thickness 30 to 100 nm), a copper film (100 to 400 nm), and the like are sequentially formed on the entire substrate on which the oxide semiconductor layer 35 is formed by a sputtering method. . Then, resist patterning by photolithography using the above-mentioned fourth photomask, wet etching of the copper film, dry etching (plasma etching) on the titanium film, and stripping and cleaning of the resist are performed as shown in FIG. As shown in FIG. 3B, the signal wiring 16a (see FIG. 3), the source electrode 16aa, the drain electrode 16b, and the auxiliary capacitance trunk line 16c (see FIG. 3) are formed, and the channel region R of the oxide semiconductor layer 35 is exposed. Let

Thereafter, similarly to FIG. 5E described in the first embodiment, the protective layer forming step, the interlayer insulating layer forming step, the opening forming step, and the pixel electrode forming step are performed, so that FIG. The active matrix substrate 20a shown can be produced. Even in such a configuration, the same effect as the above (1) can be obtained.

Note that although the IGZO (In—Ga—Zn—O) -based semiconductor is exemplified as the oxide semiconductor included in the oxide semiconductor layer 35, the oxide semiconductor includes (In—Si—Zn—O) -based, (In— Al—Zn—O), (Sn—Si—Zn—O), (Sn—Al—Zn—O), (Sn—Ga—Zn—O), (Ga—Si—Zn—O) System, (Ga—Al—Zn—O) system, (In—Cu—Zn—O) system, (Sn—Cu—Zn—O) system, (Zn—O) system, (In—O) system, etc. There may be.

That is, the oxide semiconductor layer 35 is not limited to an oxide semiconductor layer made of indium gallium zinc oxide (IGZO), but is made of indium (In), gallium (Ga), aluminum (Al), copper (Cu), zinc (Zn). ), Magnesium (Mg), and cadmium (Cd), a material made of a metal oxide containing at least one kind may be used.

Since the oxide semiconductor layer 35 made of these materials has high mobility even if it is amorphous, the on-resistance of the switching element can be increased. Therefore, the difference in output voltage at the time of data reading becomes large, and the S / N ratio can be improved. For example, in addition to IGZO (In—Ga—Zn—O), oxide semiconductor films such as InGaO ₃ (ZnO) ₅ , Mg _x Zn _1-x O, Cd _x Zn _1-x O, and CdO can be given. it can.

Further, in each of the above embodiments, the SOG film that does not have photosensitivity is exemplified, but the SOG film may have photosensitivity.

In each of the above embodiments, the active matrix substrate 20a in which the electrode of the TFT 5a connected to the pixel electrode 19a is used as the drain electrode 16b is illustrated. However, in the present invention, the TFT electrode connected to the pixel electrode is used as the source electrode. The present invention can also be applied to an active matrix substrate.

In each of the above embodiments, a liquid crystal display panel provided with an active matrix substrate has been exemplified as the display panel. However, the present invention includes an organic EL (Electro-Luminescence) display panel, an inorganic EL display panel, an electrophoretic display panel, and the like. It can be applied to other display panels.

As described above, the present invention relates to the present active matrix substrate and its manufacturing method, and is particularly useful for an active matrix substrate using a planarizing film and its manufacturing method.

5a TFT
10a Insulating substrate 11a Scanning wiring 12 Gate insulating layer 13 Semiconductor layer 13a Intrinsic amorphous silicon layer 13b Amorphous silicon layer 16a Signal wiring 16aa Source electrode 16b Drain electrode 17 Protective layer 18 Interlayer insulating layer 19a Pixel electrode 20a Active matrix substrate 25 Gate electrode 26 Flat 27. First conductive film 28 Second conductive film (conductive film)
29 Barrier layer 30 Counter substrate 35 Oxide semiconductor layer 36 Photo resist 37 Sealing material 40 Liquid crystal layer 50 Liquid crystal display panel

Claims (9)

An insulating substrate;
A gate electrode provided on the insulating substrate and having a conductive film formed of copper;
A barrier layer provided on the gate electrode and formed of silicon nitride;
A planarization film provided on the barrier layer and formed of a fired SOG material;
A gate insulating layer provided to cover the gate electrode, the barrier layer, and the planarization film;
A semiconductor layer provided on the gate insulating layer and having a channel region provided so as to overlap the gate electrode;
A source electrode and a drain electrode provided on the semiconductor layer so as to overlap the gate electrode and to face each other across the channel region;
A protective layer covering the semiconductor layer, the source electrode and the drain electrode;
An active matrix substrate comprising: a pixel electrode provided on the protective layer. 2. The active matrix substrate according to claim 1, wherein an interlayer insulating layer is provided on the protective layer, and the pixel electrode is provided on the interlayer insulating layer. 3. The active matrix substrate according to claim 1, wherein the semiconductor layer is an oxide semiconductor layer. The oxide semiconductor layer is made of a metal oxide containing at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn). The active matrix substrate according to claim 3. The active matrix substrate according to claim 4, wherein the oxide semiconductor layer is made of indium gallium zinc oxide (IGZO). 3. The active matrix substrate according to claim 1, wherein the semiconductor layer is a silicon-based semiconductor layer. Forming a gate electrode having a conductive film formed of copper on an insulating substrate; and
A barrier layer forming step of forming a barrier layer formed of silicon nitride on the insulating substrate so as to cover the gate electrode;
A planarization film forming step of forming a planarization film on the barrier layer by applying and baking an SOG material on the barrier layer;
Forming a gate insulating layer so as to cover the barrier layer and the planarizing film; and
A semiconductor layer forming step of forming a semiconductor layer having a channel region provided on the gate insulating layer so as to overlap the gate electrode;
A source / drain formation step of forming a source electrode and a drain electrode on the semiconductor layer so as to overlap the gate electrode and to face each other with the channel region interposed therebetween;
A protective layer forming step of forming the protective layer covering the semiconductor layer, the source electrode, and the drain electrode;
And a pixel electrode forming step of forming the pixel electrode on the protective layer. A method for manufacturing an active matrix substrate, comprising: The method of manufacturing an active matrix substrate according to claim 7, wherein the barrier layer on the gate electrode is removed in the planarization film forming step. 8. The semiconductor layer forming step and the source / drain forming step, wherein the semiconductor layer is formed using the same photomask, and the source electrode and the drain electrode are formed. A method for manufacturing an active matrix substrate.

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