WO2013007705A1

WO2013007705A1 - Electronic device based on a gallium compound over a silicon substrate, and manufacturing method thereof

Info

Publication number: WO2013007705A1
Application number: PCT/EP2012/063442
Authority: WO
Inventors: Giovanni Abagnale
Original assignee: STMicroelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 2011-07-08
Filing date: 2012-07-09
Publication date: 2013-01-17
Anticipated expiration: 2014-01-08
Also published as: ITTO20110603A1

Abstract

An electronic device includes a silicon substrate (2) having a first side and a second side. A structural layer of gallium nitride (6) is formed over the first side of the silicon substrate and includes an active area of the electronic device. A transition layer (8) is provided between the substrate and the structural layer. The transition layer electrically and/or thermally insulated the substrate and the structural layer from one another. A via hole (20) made of a conductive material extends through the structural layer and the transition layer. The via hole is electrically and/or thermally connected to the active area of the electronic device and to the substrate.

Description

ELECTRONIC DEVICE BASED ON A GALLIUM COMPOUND OVER A SILICON SUBSTRATE, AND MANUFACTURING METHOD THEREOF

TECHNICAL FIELD

The present invention relates to a semiconductor electronic device based on a gallium compound, for example gallium nitride (GaN), formed on a silicon (Si) substrate, and to a method for manufacture thereof.

BACKGROUND

Gallium nitride has encountered and is encountering increasing interest in the field of semiconductors thanks to the chemical and physical properties that make it one of the best candidates in providing high-power and high-frequency devices, as well as optoelectronic devices operating in hostile environmental conditions (high temperatures, high-energy radiation, high frequencies, etc.). One of the main reasons that hinder development of GaN devices is the poor quality of the layer deposited or grown on a substrate made of a material other than gallium nitride. This occurs, in particular, as regards GaN layers grown on a silicon substrate.

Currently, GaN "bulks" on which a GaN layer is homoepitaxially grown are not available. Some of the substrates used comprise silicon-carbide (SiC) or sapphire substrates, but these substrates are costly, have an insulating nature, and are not available in large diameters.

The biggest obstacle in providing devices made of gallium nitride on silicon is due to the lattice mismatch between GaN and Si, and to the different thermal coefficient. These factors cause a high density of crystallographic defects (dislocations and cracks) of the entire GaN layer, affecting operation of the electronic devices thus obtained. In order to overcome the above problem, a plurality of techniques have been developed in order to minimize the effects of these mismatches, for example described in "Investigation of buffer growth temperatures for MOVPE of GaN on Si(l l l)," Journal of Crystal Growth 248 (2003) 578-582, and in "Growth and Characterisation of AlGaN/GaN HEMT on Silicon Substrates," phys. stat. sol. (a) 194, No. 2, 464-467 (2002).

The drawback of these techniques is that of creating markedly defective areas at the interface (transition layer) and/or insulating layers that cannot be used as active part of the electronic devices that comprise them.

Moreover known is to provide through vias made through the silicon substrate (or, alternatively, the SiC substrate), throughout the thickness of the substrate until they contact a metallization formed on the back of the substrate. Said through vias are generally filled by metal. In these solutions, given that the through vias are very deep, the total filling of the through vias with metal is not technically feasible. The metallization hence is obtained only along the walls of the through vias, inevitably leaving hollow areas in which the presence of air does not favor thermal dissipation. There is hence a further problem linked to the poor thermal dissipation.

SUMMARY

The embodiments described herein provide an electronic device based on a gallium compound, for example gallium nitride, formed on a silicon substrate that will be able to overcome the drawbacks of the known art.

An electronic device based on a gallium compound, for example gallium nitride, is formed on a silicon substrate, and a method for its manufacture is provided.

In an embodiment, the electronic device comprises: a substrate of a first semiconductor material having a first side and a second side; a structural layer, of a second semiconductor material different from the first semiconductor material, formed over the first side of the substrate and including an active area of said electronic device; a transition layer, arranged between the substrate and the structural layer, the transition layer insulating electrically and/or thermally the substrate and the structural layer from one another; and a via hole, of a conductive type, extending through the structural layer and the transition layer, and being configured so as to connect electrically and/or thermally the active area of the electronic device to the substrate.

In an embodiment, the electronic device comprises: a first layer of a silicon-based semiconductor material having a first side and a second side; a second layer of a gallium based semiconductor material epitaxially grown above the first layer, said second layer including a transition layer on said first side, a buffer layer on said transition layer and a structural layer on said buffer layer; and a via extending through the structural layer, buffer layer and transition layer of said second layer to make contact with said first layer.

In an embodiment, a method for manufacturing an electronic device on a substrate of a first semiconductor material having a first side and a second side comprises: forming a structural layer of a second semiconductor material different from the first semiconductor material, comprising an active area, on the first side of the substrate; forming a transition layer, between the substrate and the structural layer, the transition layer insulating electrically and/or thermally the substrate and the structural layer from one another; and forming a via hole, of a conductive type, through the structural layer and the transition layer so as to connect electrically and/or thermally the active area of the electronic device with the substrate.

In an embodiment, a method for manufacturing an electronic device on a first layer of a silicon-based semiconductor material having a first side and a second side comprises: epitaxially growing a second layer of a gallium based semiconductor material above the first layer, said second layer including a transition layer on said first side, a buffer layer on said transition layer and a structural layer on said buffer layer; and forming a via extending through the structural layer, buffer layer and transition layer of said second layer to make contact with said first layer.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:

Figure 1 shows a cross-sectional view of a generic electronic device according to an embodiment of the present invention;

Figure 2 shows a cross-sectional view of a generic electronic device according to a further embodiment of the present invention;

Figure 3 shows a Schottky diode obtained according to one embodiment of the present invention;

Figure 4 shows an HEMT obtained according to one embodiment of the present invention;

Figure 5 shows an HEMT obtained according to a further embodiment of the present invention; and Figures 6a-6d show successive steps of manufacture of the HEMT of Figure 5.

DETAILED DESCRIPTION OF THE INVENTION

Figure 1 is a cross-sectional view of an electronic device 1 according to one embodiment. The electronic device 1 is formed in a wafer 100 comprising a substrate 2 made of semiconductor material, in particular silicon, formed on a front side 2a of which are (by means of steps of epitaxial growth and/or deposition) one or more layers made of gallium nitride (GaN) and/or alloys of gallium nitride, for example aluminum gallium nitride (AlGaN). The substrate 2 is a substrate with low electrical resistivity (high conductivity) and is, according to one embodiment, doped by dopant species of an N type (the implantation dose is chosen according to the need). According to a different embodiment, the substrate 2 is doped by dopant species of a P type.

The layers of gallium nitride comprise at least one between a buffer layer 4 of gallium nitride of an intrinsic type (not doped) and a barrier layer 6 of doped gallium nitride. Figure 1 shows an embodiment comprising both the buffer layer 4 and the barrier layer 6, in which the barrier layer 6 is formed on top of, and adjacent to, the buffer layer 4.

Present at the interface between the substrate 2 and the buffer layer 4 are one or more transition layers 8 (just one transition layer is shown in Figure 1), made of gallium nitride and compounds such as AlGaN or AIN, arranged in a number and in combinations such as to reduce the lattice mismatch between the various materials. The transition layer 8 is a layer with high lattice defectiveness, due to the techniques used to reduce the lattice mismatches, as is already encountered in the known art. The buffer layer 4 and barrier layer 6 form an active layer 12 of the electronic device 1. Formation of the active layer 12 comprises, for example, steps of epitaxial growth of gallium nitride and/or alloys of gallium nitride. Known processes of growth of gallium nitride on silicon lead, as has been said, to formation of one or more interface layers having a high defectiveness (in the figure these one or more defective layers are designated as a whole by the reference number 8, and are referred to in what follows as "transition layer 8"). In fact, in order to reduce the lattice mismatch between silicon and GaN, set between these two layers are one or more layers of composite materials, for example, a plurality of A1N and/or AlGaN layers, each having a thickness comprised between approximately 30 nm and 400 nm and a variable composition as regards the aluminum content (i.e., a composition ranging between approximately 5% and 99% for each layer). This process has the effect of generating planar defects and/or dislocations that propagate as far as the surface of the wafer, starting from the substrate. In order to prevent said defectiveness, formed during the epitaxial growth are intermediate layers, referred to as "buffer layers", in which annihilation of the defects takes place but leaving, obviously, a region of the entire epitaxy that is markedly defective.

The barrier layer 6 is having a doping of a P type or an N type according to the particular embodiment of the electronic device 1, in a way depending upon the electrical characteristics that are to be obtained for the electronic device 1.

According to one embodiment, formed at a surface region 6a of the barrier layer 6 are one or more conduction terminals of the electronic device 1, comprising implanted regions 14 and/or front-contact terminals 16 (in particular, metallizations) in electrical contact with the implanted regions 14, which define an active area 15 of the electronic device 1. For the purposes of the present disclosure "active area 15" is meant to indicate, as a whole, the region of the electronic device 1 in which phenomena of transport of electrical charge take place. The active area 15 can consequently comprise implanted regions or generic conduction terminals of the electronic device 1. It is evident that the electronic device 1 can have a plurality of active areas 15, separated from one another by field-insulation regions (not shown).

The electronic device 1 further comprises a passivation layer 19, for protecting the surface region 6a of the barrier layer 6.

Moreover formed at a back side 2b of the substrate 2 are one or more back-contact terminals 18 (in particular, metallizations, only one of which is shown in Figure 1).

The electronic device 1 further comprises one or more via holes, or trenches (only one of which is shown in Figure 1 and is designated by the reference number 20), configured for connecting the front-contact terminals 16 with the substrate 2, passing through the barrier layer 6, the buffer layer 4, and the transition layer 8. Each via hole 20 can be formed indifferently inside or outside the active area 15 of the electronic device 1.

The via hole 20 shown in Figure 1 comprises an internal filling portion made of conductive material, for example metal or doped polysilicon, forming a conductive region 20a, which extends from the surface region 6a until it reaches and comes into electrical contact with the substrate 2. A surface electrical connection 24 is moreover formed in such a way as to connect electrically the conductive region 20a of the via hole 20 with a respective front-contact terminal 16.

Optionally, according to the particular application of the electronic device 1 and the electrical characteristics of the buffer layer 4 and barrier layer 6, the via hole 20 further comprises an insulating region 20b surrounding the conductive region 20a and configured so as to insulate the conductive region 20a electrically from the buffer layer 4 and the barrier layer 6.

In this way, a conductive connection between the back-contact terminal 18 and the respective front-contact terminal 16 is provided through the via hole 20.

According to a different embodiment, shown in Figure 2, one or more via holes 20 having a respective conductive region 20a (only one via hole 20 is shown in Figure 2) are formed in a point corresponding to a respective front-contact terminal 16, in such a way that the conductive region 20a of the via hole 20 is in electrical contact with the front-contact terminal 16 via the implanted region 14. In top plan view, hence, the via hole 20 is formed partially or totally aligned with at least one portion of a respective front-contact terminal 16. In this case, the surface electrical connection 24 is not present.

The provision of structures of the type shown in Figures 1 and 2 enables production of electronic devices made of gallium nitride (and alloys of gallium nitride) on a silicon substrate that have a low cost, maintaining the electrical performance typical of gallium nitride.

The advantages of the embodiments shown in Figures 1 and 2 lie in the fact that GaN layers can be grown on layers that are highly insulating both from the thermal standpoint and from the electrical standpoint (such as oxides or nitrides) and/or highly defective, without this entailing a reduction of the performance of the device and/or a reduced dissipation of heat and/or difficulty of integration in circuits or packages of a known type. In fact, the electrical and/or thermal conduction can take place between the front and the back of the wafer through the via holes formed as described before, overcoming the main problems that hinder development of devices made of GaN on silicon. The substrate 2 is, according to embodiments, <111> Si and/or <100> Si with low resistivity (for example, with a value comprised between approximately 0.005 Ω-cm and approximately 0.5 Ω-cm), with a thickness comprised between approximately 500μπι and approximately 1500μπι. The structure of the electronic device 1 with vertical connection between the front of the electronic device 1 (e.g., at the active area) and the substrate enables the passage through the barrier preventing the need for the transition layer 8 with high density of defects, and without this affecting the efficiency of the electronic device 1. There is moreover an improvement in the dissipation of heat through the substrate 2, via the conductive region 20a of the via hole 20 in contact with the substrate 2. In this way, the silicon substrate 2 is an integral part of the electronic device 1 , and not a mere substrate having the function of support for the active layer 12 of gallium nitride.

The transition layer 8 typically has a thickness comprised between approximately Ιμπι and approximately 5μπι. The active layer 12 comprises, as has been said, one or more layers of GaN, or alloys of GaN, which constitute the active part of the device, with a thickness, barrier concentration, and type of alloy (for example, GaN and/or Al_xGa_yN) chosen appropriately according to the device to be obtained (for example, but not only, HEMTs, Schottky diodes, MESFETs, etc.).

The metallizations of the contacts on the front 6a can be made using different variants known in the literature, such as, for example, formation of AlSiCu/Ti, Al/Ti, or W-plug contacts or the like.

The electrical contact with the back 2b of the substrate 2 is provided through metallization of the wafer back, possibly forming "bumps" designed to enable a vertical integration of the electronic device 1.

The advantages of this configuration extend, not only to gallium nitride, but also to electronic devices comprising a layer with high defectiveness set between the substrate and a layer, including the active area of the electronic device, formed on top of the defective layer.

It is here pointed out that the problem is, however, particularly felt in the case of GaN layers grown on a silicon substrate. Embodiments that have a germanium (Ge) substrate grown on which are gallium- arsenide (GaAs) layers do not present the same problem, or present it only to a minimum extent, in so far as the lattice mismatch between Ge and GaAs is minimal.

Figure 3 shows an electronic device of the type described with reference to Figures 1 and 2 configured so as to operate as Schottky diode, according to one embodiment.

The Schottky diode 40 comprises a substrate 42 of doped silicon with a doping of an N+ type grown on a front side 42' of which is an AIN/AlGaN/GaN layer 43. The Schottky diode 40 further comprises, formed in the body layer 43 and facing the top surface 43' of the body layer 43, an anode region 44, defined by a ring structure 45 provided by implantation of dopant species of a P type, and connected to an anode-biasing terminal through an anode metallization 47. The Schottky diode 40 further comprises a cathode region 46, which is formed in the body layer 43, faces the top surface 43' of the body layer 43, and surrounds the anode region 44 on the outside. The cathode region 46 is formed, for example, by implantation of dopant species of an N type, to form a region with N++ doping. The cathode region 46 is moreover electrically connected to a cathode-biasing terminal through a cathode metallization 49, formed on top of the body layer 43. The anode region 44 and the cathode region 46 define an active-area region 53 of the Schottky diode 40. The body layer 43 comprises a transition layer 48, set at the interface with the substrate 42, similar to the transition layer 8. In a way not shown in the figure, the body layer 43 can comprise a plurality of successive layers, for example with different doping values, of gallium nitride or its alloys.

The cathode and anode metallizations 49, 47 are insulated from one another by a passivation layer 51, formed on the top surface 43' of the body layer 43.

The Schottky diode 40 further comprises a via hole, or trench, 50, extending starting from the top surface 43' of the body layer 43 as far as the substrate 42, passing through the transition layer 48. According to one embodiment, the via hole 50 is formed, in top plan view, in a portion of the top surface 43' of the body layer 43 external to the area defined by the cathode region 46. The via hole 50 includes a conductive portion 50a, for example made of metal (e.g., Al, AlCu, W, AlSiCu, AITi, or the like), or doped polysilicon, electrically connected to the anode metallization 47 by a surface electrical connection 52.

According to one embodiment, the body layer 43 has a thickness comprised between approximately 2μπι and approximately 5μπι. The transition layer 48 has a thickness comprised between approximately 0.4μπι and approximately 3μπι, for example. Consequently, the via hole 50 extends for a depth comprised between approximately 2μπι and approximately 5μπι. Moreover formed on a back side 42" of the substrate 42, opposite to the front side 42', is a back metallization 54, in electrical contact with the substrate 42. The back metallization 54 has the function of cathode contact and enables biasing of the cathode region 46 from the back of the substrate 42.

According to a different embodiment (not shown), the via hole 50 is electrically connected to the anode region 44. In this case, the contact for biasing the cathode region 46 is set in an area corresponding to the front side of the Schottky diode 30 (i.e., in an area corresponding to the top surface 43'), whereas the contact for biasing of the anode region 44 is provided in an area corresponding to the back side 42" of the substrate 42, electrically connected to the back metallization 54, for example in the form of conductive bumps.

Irrespective of the embodiment, the via hole 50 can include, optionally, an insulation layer 50b that coats the internal walls of the via hole 50 and is designed to insulate the conductive portion 50a of the via hole 50 electrically from the body layer 43. The insulation layer 50b is, for example, silicon oxide, or silicon nitride, or polyimide.

The insulation layer 50b can be omitted if the electronic device is provided for radio- frequency applications and not for power applications.

Figure 4 shows a transistor 60 configured so as to operate as HEMT (high-electron- mobility transistor) device, according to a further embodiment.

HEMTs, also known as HFETs (heterostructure field-effect transistors) are known electronic devices, which include a heterojunction, i.e., a junction between two semiconductors with different bandgap. Semiconductors used for this purpose are, for example, gallium nitride (GaN) and aluminum gallium nitride (AlGaN). The HEMT exploits formation of electrons with high electronic mobility present in the potential well generated by the heterojunction between the two semiconductors. This layer of high-mobility electrons is referred to as 2DEG (2- dimensional electron gas) layer, and constitutes the channel of the HEMT.

The transistor 60 of Figure 4 comprises: a silicon substrate 62, for example having a doping of an N type; a buffer layer 64, for example made of GaN of an intrinsic type, formed on a top side 62' of the substrate 62; and a barrier layer 66, for example made of AlGaN, formed on top of the buffer layer. Moreover shown in Figure 4 is a transition layer 68, set between the substrate 62 and the buffer layer 64. The transition layer 68 is generated during the steps of formation of the buffer layer 64 on the silicon substrate 62, as has been described previously.

The transistor 60 further comprises, in a known way: a source region (or terminal) 70, in contact with a separation region 71 made of AlGaN, and in electrical connection by the tunnel effect with the underlying channel identified by arrows 77; a drain region (or terminal) 72, in contact with a separation region 73 made of AlGaN, and in electrical connection by the tunnel effect with the underlying channel identified by the arrows 77; and a gate region (or terminal) 74. The latter is formed in an area corresponding to a front side 66' of the transistor 60 (i.e., on the free side of the barrier layer 66). In use, by appropriately biasing the gate region 74, a current i flows between the source region 70 and the gate region 74 according to the path defined by the arrows 77.

The source region 70, drain region 72, and gate region 74, together with the portions of the buffer layer 64 and barrier layer 66 in which the current i flows define an active area 69 of the transistor 60.

The source region 70, drain region 72, and gate region 74 are insulated from one another by a passivation layer 81, formed on the front side 66' of the transistor 60.

According to an aspect, the transistor 60 further comprises a back metallization 75, formed on a back side 62" of the substrate 62, in electrical contact with the substrate 62.

According to a further aspect, the transistor 60 comprises a trench 76 extending from the front side 66' of the transistor 60 towards the substrate 62, as far as the substrate 62, traversing the barrier layer 66, the buffer layer 64, and the transition layer 68. The via hole 76 comprises an internal conductive portion 76a, for example made of metal or doped polysilicon, in direct electrical contact with the substrate 62. According to one aspect, the via hole 76 further comprises an internal insulating portion 76b, formed adjacent to the side walls of the via hole 76 in such a way as to insulate the internal conductive portion 76a electrically from the barrier layer 66, from the buffer layer 64, and from the transition layer 68.

The internal insulating portion 76b can be omitted if the electronic device is provided for radio-frequency applications and not for power applications.

The via hole 76 (and in particular the internal conductive portion 76a) is moreover electrically connected, by means of a conductive strip 79, to one between the source region 70, the drain region 72 and the gate region 74. Figure 4 shows the transistor 60 in which the internal conductive portion 76a of the via hole 76 is connected to the drain region 72, by means of an appropriate metallization.

Figure 5 shows an alternative embodiment of the transistor 60 of Figure 4, according to a further aspect. Figure 5 shows a transistor 80 of the same type as the transistor 60 described with reference to Figure 4, but in this case the via hole 76 is formed in an area corresponding to one between the source region 70 and the drain region 72. More in particular, the via hole 76 is at least partially aligned, in top plan view, with one between the source region 70 and the drain region 72. The internal conductive portion 76a of the via hole 76 is in electrical contact with the drain region 72, and forms an electrical connection between the drain region 72 and the back metallization 75, exploiting the substrate 62.

The top metallization of the drain region 72 and the conductive strip 79 are not present. In use, the transistor 60 or the transistor 80 operate in a known way.

Figures 6a-6d show steps of a manufacturing method that can be used for producing the transistor 80 of Figure 5.

Figure 6a shows the transistor 80 in an intermediate manufacturing step, following upon a series of manufacturing steps of a known type.

In greater detail, the transistor 80 of Figure 6a is obtained with the process steps described in what follows.

A substrate 62 of semiconductor material, in particular silicon, is provided.

Then, formed, for example by means of epitaxial growth of gallium nitride on the substrate 62, is a buffer layer 64 of a non-doped type (i-GaN) having a thickness comprised between approximately 0.6 μπι and approximately 1 μπι. This step leads to formation of the transition layer 68, at the interface with the substrate 62. In this step the defects due to the lattice mismatch are formed and propagate.

Then, formed on top of the buffer layer 64, for example by means of epitaxial growth, is a barrier layer 66 having a thickness of between approximately Ιμπι and approximately 1.5μπι. The barrier layer 66 is made, according to one embodiment, of doped gallium nitride of an N type, or else, according to a further embodiment, of aluminum gallium nitride (AlGaN).

Next (Figure 6b), according to one embodiment, the barrier layer 66 is selectively etched in a portion in which, during subsequent steps, the drain region 72 will be formed. The etch is, for example, of a dry type (for example, RIE - reactive ion etching - or DRIE - deep reactive ion etching).

Etching of the barrier layer 66 is aimed at formation of the via hole 76 of Figure 5. For this purpose, etching of the barrier layer 66 is, for example, made using a chloride-based solution, until the buffer layer 64 is reached. Also the buffer layer 64 is etched using the same method. Then etching of the transition layer 68 is carried out using the same method, until the substrate 62 is reached. The etching method can be monitored in such a way as to reach the substrate 62 and stop at the substrate 62, or else so as to etch the substrate 62 only partially.

Then, a layer of insulating material is formed on the internal walls of the via hole 76 to form the internal insulating portion 76b (for example, via a PECVD process).

Finally, a step of deposition of conductive material inside the via hole 76 is carried out to form the internal conductive portion 76a. The internal conductive portion 76a can be formed with various techniques of deposition of a known type.

Then (Figure 6c), the method of manufacture of the transistor 80 continues according to steps in themselves known. In particular, the source region 70 and drain region 72 are formed. The source region 70 comprises a portion 71 of GaAl, and the drain region 72 is formed at least partially on top of the conductive portion 76a of the via hole 76, in such a way that it is in electrical contact therewith. An insulating layer, or passivation layer, 81 is then formed on the front of the wafer that carries the transistor 80 in such a way as to insulate the source region 70 and drain region 72 laterally from one another.

The steps of the method described further comprise forming (Figure 6d) the gate region 74. For this purpose, the passivation layer 81 is selectively etched in an area corresponding to the portion of the front side 66' in which the gate region 74 is to be formed, so as to form an opening 85. Together with this step, the passivation layer 81 is moreover etched at the source region 70 to define an opening 86 in which the source metallization is formed. A step of deposition of a metal layer, for example by evaporation or sputtering, and a subsequent step of photolithographic definition, leads to formation of the gate region 74 and of the source metallization, to obtain the transistor 80 of Figure 5.

It is evident that, according to a further embodiment (not shown in the figure), the via hole 76 can be formed in electrical contact with the source region 70, and not with the drain region 72. In this case, the source metallization is not formed, and a drain metallization is, instead, formed.

The method described can be applied, with the appropriate variants, to form the transistor 60 of Figure 4. In this case, the step of formation of the via hole 76 is carried out after the step of formation of the passivation layer 81 and comprises, prior to the step of etching of the barrier layer 66, the step of etching of the passivation layer 81. In addition, the passivation layer 81 is also etched in an area corresponding to the drain region 72 to form an opening designed to enable formation of the electrical contact with the via hole 76, via the conductive strip 79.

It is evident that the method of formation of the via hole 76 described is not limited to production of an HEMT, but can be integrated in steps of a method for manufacturing any type of electronic device.

From an examination of the characteristics of the invention, the advantages that it affords are evident.

In particular, it is possible to produce devices made of GaN on a low-cost substrate (silicon wafers) overcoming the obstacles inherent in the heteroepitaxial growth of GaN on silicon, which causes formation of highly defective interfaces and/or interlayers with low thermal and electrical conductivity. This enables heterostructures to be obtained via epitaxial growth with a high design flexibility, in no way limiting the choice of the best methodology of growth of GaN (or its alloys) according to the particular requirements, and on an industrial scale.

In addition, the silicon substrate forms an active part of the electronic device produced and is not simply a support on which the epitaxy is carried out.

The structure moreover enables an efficient dissipation of the heat generated by the electronic device during use, thanks to the possibility of providing metal contacts within the active area of the electronic device itself. In addition, any problems inherent in formation of air pockets, which limit thermal dissipation, are prevented. In fact, given that the via holes are shallow (in particular, they have a depth that is defined by the thickness of the epitaxy grown on top of the substrate and is independent of the thickness of the substrate itself), whatever the technique used for filling the via hole, the via hole is always completely filled. In this way, any empty areas that would be formed in the case of very deep trenches or vias (in particular ones passing right through the substrate as well as right through the epitaxy formed on top of it) are prevented.

Finally, the formation of metal contacts towards the substrate within the active area, enables reduction of the "pitch" of the device.

Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the sphere of protection of the present invention, as defined in the annexed claims.

In particular, the present invention is not limited to structures made of gallium (or its alloys, for example GaN) grown on silicon, but can be extended to generic structures in which the substrate is electrically and/or thermally insulated by an overlying active layer (for example, on account of the presence of an undesirable electrically and/or thermally insulating interface layer).

In addition, the teachings are not limited to a particular electronic device, such as, for example, the Schottky diode of Figure 3 or the HEMT of Figures 4 and 5, but can be extended to any electronic device having a structure such that the substrate is electrically insulated by an overlying active layer (for example, but not only, a GaN MOSFET integrated on a silicon substrate).

Claims

1. An electronic device (1 ; 40; 60; 80), comprising:

a substrate (2; 42; 62) of a first semiconductor material having a first side and a second side;

a structural layer (12), of a second semiconductor material different from the first semiconductor material, formed over the first side of the substrate and including an active area (15; 53; 69) of said electronic device;

a transition layer (8; 48; 68), arranged between the substrate and the structural layer, the transition layer insulating electrically and/or thermally the substrate and the structural layer from one another; and

a via hole (20; 76), of a conductive type, extending through the structural layer and the transition layer, and being configured so as to connect electrically and/or thermally the active area of the electronic device to the substrate.

2. The electronic device according to claim 1, wherein the via hole comprises a conductive portion (20a) extending between and in electrical contact with the active area of the electronic device and the substrate.

3. The electronic device according to claim 2, wherein the via hole comprises an insulating portion (20b), which extends between an internal wall of the via hole and the conductive portion and is configured so as to insulate the conductive portion electrically from the structural layer.

4. The electronic device according to any one of the preceding claims, wherein the first semiconductor material is silicon and the second semiconductor material is a gallium compound.

5. The electronic device according to claim 4, wherein the gallium compound is selected from the group consisting of gallium nitride and aluminum gallium nitride.

6. The electronic device according to any one of the preceding claims, further comprising a first conduction terminal (18; 54; 75), formed at the second side of the substrate and in electrical contact with the substrate, said active area being electrically connected to the first conduction terminal by means of the via hole and the substrate.

7. The electronic device according to claim 6, wherein the structural layer includes a second conduction terminal (44; 70) and a third conduction terminal (46; 72), said third conduction terminal being electrically connected to the active area and to the via hole in such a way that, in use, an electric current flows between the second conduction terminal and the first conduction terminal through said active area, said third conduction terminal, said via hole, and said substrate.

8. The electronic device according to claim 7, wherein the second conduction terminal is an anode terminal and the third conduction terminal is a cathode terminal, said electronic device being configured for operating as a Schottky diode (40).

9. The electronic device according to claim 7, wherein the second conduction terminal is a source terminal and the third conduction terminal is a drain terminal, said electronic device further comprising a control terminal and being configured for operating as a transistor (60; 80).

10. A method for manufacturing an electronic device (1 ; 40; 60; 80) on a substrate of a first semiconductor material having a first side and a second side, comprising the steps of:

forming a structural layer (12) of a second semiconductor material different from the first semiconductor material, comprising an active area (15; 53; 69), on the first side of the substrate;

forming a transition layer (8; 48; 68), between the substrate and the structural layer, the transition layer insulating electrically and/or thermally the substrate and the structural layer from one another; and

forming a via hole (20; 76), of a conductive type, through the structural layer and the transition layer so as to connect electrically and/or thermally the active area of the electronic device with the substrate.

11. The method according to claim 10, wherein forming the via hole comprises: removing selective portions of the structural layer and of the transition layer; and forming inside the via hole a conductive portion (20a) extending between and in electrical contact with the active area of the electronic device and the substrate.

12. The method according to claim 11, wherein forming the via hole further comprises forming an insulating portion (20b) between the internal wall of the via hole and the conductive portion so as to insulate electrically the conductive portion from the structural layer.

13. The method according to any one of claims 9-12, wherein the first semiconductor material is silicon and wherein the step of forming the structural layer comprises forming at least one layer made of a gallium compound.

14. The method according to claim 13, wherein the gallium compound is selected from the group consisting of gallium nitride and aluminum gallium nitride.

15. The method according to any one of claims 9- 14, further comprising:

forming a first conduction terminal (18; 54; 75) in an area corresponding to the second side of the substrate and in electrical contact with the substrate; and

connecting the active area electrically to the first conduction terminal by means of the via hole and the substrate.

16. The method according to claim 15, further comprising:

forming a second conduction terminal (44; 70) and a third conduction terminal (46;

72) in the active area;

electrically connecting said third conduction terminal to the active area and to the via hole;

operating, during use, the electronic device (1 ; 40; 60; 80) in such a way that an electric current flows between the second conduction terminal (44; 70) and the first conduction terminal (54; 75) through said active area, said third conduction terminal, said via hole, and said substrate.

17. An electronic device, comprising:

a first layer (2; 42; 62) of a silicon-based semiconductor material having a first side and a second side;

a second layer (12) of a gallium based semiconductor material epitaxially grown above the first layer, said second layer including a transition layer on said first side, a buffer layer on said transition layer and a structural layer on said buffer layer; and

a via (20; 76) extending through the structural layer, buffer layer and transition layer of said second layer to make contact with said first layer.

18. The electronic device of claim 17, further comprising a metallization layer above said second layer, said via being in electrical contact with a conductive element of said metallization layer.

19. The electronic device of claim 18, further comprising a doped region formed in an upper surface of the structural layer, said conductive element being in electrical contact with said doped region.

20. The electronic device of claim 17, further comprising a doped region formed in an upper surface of the structural layer, said via being in electrical contact with an underside of said doped region.

21. A method for manufacturing an electronic device on a first layer of a silicon- based semiconductor material having a first side and a second side, comprising:

epitaxially growing a second layer of a gallium based semiconductor material above the first layer, said second layer including a transition layer on said first side, a buffer layer on said transition layer and a structural layer on said buffer layer; and

forming a via extending through the structural layer, buffer layer and transition layer of said second layer to make contact with said first layer.

22. The method of claim 21, further comprising forming a metallization layer above said second layer having a conductive element in electrical contact with said via.

23. The method of claim 22, further comprising forming a doped region in an upper surface of the structural layer, and wherein forming the metallization layer comprises making electrical contact between said conductive element and said doped region.

24. The method of claim 21, further comprising forming a doped region in an upper surface of the structural layer, and wherein forming said via comprises forming said via to be in electrical contact with an underside of said doped region.