WO2013080921A1 - Device-inherent information generation/output device, device-inherent information generation method and generation program - Google Patents

Abstract

[Problem] To provide a device-inherent information generation/output device that is resistant to effects of environmental changes such as a temperature change, and is capable of stably outputting fixed inherent information. [Solution] The device-inherent information generation/output device (10) comprises: a device physical information generation means (110) that contains multiple circuits for which inherent information is to be detected; a higher-level circuit detection unit (121) that detects a physical characteristic of each circuit; a group detection unit (122) that creates a group by selecting M number of circuits, starting from the sequential rank of the numerical value of a physical characteristic detected at a first time; and a registration circuit estimation unit (123) that generates a first inherent information item from the physical characteristic. The group detection unit selects N number of circuits, N being a larger number than M, starting from the sequential rank of a physical characteristic detected at a second time that is after the first time. The registration circuit estimation unit: from among the N number of circuits, selects the M number of circuits, said selected circuits being arbitrarily defined; generates a second inherent information item from the physical characteristic for said selected M number of circuits; and compares said second inherent information item to the first inherent information item.

Description

Device specific information generation / output device, device specific information generation method, and generation program

The present invention relates to a device specific information generation / output device, a device specific information generation method, and a generation program, and more particularly to a device specific information generation / output device that generates specific information using a physical state inside the device.

In order to realize a safe information / communication system, from the viewpoint of information security, in communication between a host computer and a device (for example, a USB flash memory) connected thereto, a device that is a communication partner An authentication process for determining whether or not is genuine is necessary. The authentication process is premised on the presence of unique information (ID) that can uniquely identify the device, such as a serial number or an individual identification number.

However, if an attacker obtains the specific information from the memory in a legitimate device in some way, the attacker simply does not analyze the content of the acquired specific information and simply analyzes it. By copying it to the memory, the legitimate device can be illegally copied. This makes it possible for an attacker to impersonate the user of the legitimate device, and damage caused by such impersonation actually occurs.

In order to prevent such damage, there is also a tamper resistant technology that encrypts the contents of unique information stored in the memory, thereby making it difficult to read illegal data and analyze the contents. However, such a technique has a problem that special hardware and software are required, resulting in high costs.

In order to solve the problems described above, many researchers are currently actively researching the variation in physical characteristics that inevitably occur in the manufacturing process of devices that make up equipment. This is a technique for generating unique information of individual devices. This is called PUF (Physical Unclonable Function). Above all, a device that uses the variation in physical characteristics of semiconductor devices is called silicon PUF.

It is expected that it will be possible to identify individual electronic circuits using this silicon PUF, thereby preventing unauthorized duplication of electronic circuits. Hereinafter, silicon PUF is simply referred to as PUF.

FIG. 14 is an explanatory diagram showing a configuration of the terminal device 910 provided with unique information generation means using PUF according to the existing technology. The terminal device 910 is a peripheral device that can be detachably connected to the host computer 920 via an interface such as a USB, and an MPU (microprocessor) 911 that is a main body that executes a computer program, and a volatile memory that stores data. 912, a nonvolatile memory 913, an interface 914 that mediates connection between the host computer 20, and device physical information generation means 950.

The MPU 911 functions as the physical information mapping unit 960 by executing the unique information generation program. Accordingly, the MPU 911, the volatile memory 912, and the nonvolatile memory 913 together function as a device specific information generation / output device.

The device physical information generation means 950 is a device that is a specific detection target of physical characteristics, and is often configured by a combination of a plurality of identical circuits. Specifically, this includes, for example, a dynamic RAM (DRAM) element, an oscillation circuit such as a ring oscillator, and the like.

The physical information mapping unit 960 detects the physical feature from the device physical information generation unit 950 and outputs it to the host computer 920 as an output value (unique information) of the PUF. The host computer 920 authenticates the terminal device 910 with this unique information.

For example, there are the following technical literatures related to this. Among them, Non-Patent Document 1 describes an example of a typical technique related to silicon PUF. Non-Patent Document 2 describes trends in anti-counterfeiting technology using artifact metrics including PUF.

Non-Patent Document 3 describes a PUF that uses the randomness of wiring delay that inevitably occurs in the manufacturing process. Non-Patent Document 4 describes a PUF that utilizes the fact that the initial value of each bit when a static RAM (SRAM) is powered on becomes random.

In the technique of Non-Patent Document 4, the SRAM is the device physical information generation means 950 shown in FIG. 14, and the bit position in the SRAM is the output value of the PUF. The physical information mapping unit 960 outputs an initial value at the time of power-on of the bit position given as input information. In the authentication of the device terminal, the bit value is generated and registered in advance in the terminal device 910 as an initial setting process, and the bit value generated at that time in the terminal device 910 is registered in the initial setting process at the time of authentication. Match against a value.

Patent Document 1 describes a PUF technique in which unique information can be generated not only for SRAM but also for DRAM by a similar method. A DRAM expresses a bit by the presence or absence of electric charge in a capacitor (capacitor) constituting an element. The charged charge leaks over time. Accordingly, in order to prevent the loss of bits due to leakage of electrification, the DRAM must be refreshed by periodically reading and charging the charge.

¡Charge retention characteristics of each element are called retention characteristics, and are mainly determined by the magnitude of leakage current, and have variations that are difficult to predict. In the technique described in Patent Document 1, this variation in retention characteristics is used to stop the refresh process after charging and detect the position information of an element (= inverted bit) that loses charge early, and this is unique. It is used to generate information.

Patent Document 2 describes an information generating apparatus provided with a removing unit that removes an interfering factor for a signal component due to variations in the structure of elements and an extracting unit that outputs unique information on the variation state of the element group. . Patent Document 3 describes an authentication / authenticated device that uses spontaneous variation in output signal characteristics as individual-specific information. Patent Document 4 describes an amusement machine that uses an operation code generated from authentication data to detect an illegal act or malfunction due to exchange with an illegal substrate.

JP 2009-533741 A JP-A-2005-341065 JP 2006-221361 A JP 2011-152342 A

“Standard evaluation board SASEBO for side channel attacks”, National Institute of Advanced Industrial Science and Technology, Information Security Research Center, [Searched on November 16, 2011], Internet <URL: http://staff.aist.go.jp/akashi. satoh / SASEBO / en / index.html> Naoyuki Iwashita, “New Trends in Anti-Counterfeiting Technology: Possibility of Artifact Metrics in the Financial Field” (From Financial Research Vol. 28, No. 2), Bank of Japan, Institute for Financial Research, July 2009, [November 2011 Search on March 16], Internet <URL: http://www.imes.boj.or.jp/research/papers/japanese/kk28-2-5.pdf> G.E.Shu and S. Devadas, “Physically Unclonable Functions for Device Generationand Secret Key Generation,” Proc. 44th Design Automation Conference, pp.9-14. DanielE. Holcomb, Wayne P. Burleson, and Kevin Fu, “Power-Up SRAM State as anIdentifying Fingerprint and Source of True Random Numbers," IEEE Trans.Computers, vol.58, no.9, pp.1198-1210, pp.1198-1210 .

However, the PUF detects a slight variation in physical characteristics within the range allowed by the manufacturing standard of the device. Such physical characteristics are particularly susceptible to environmental influences such as temperature. For example, the time until the above-described DRAM bit is inverted after charging (retention characteristics) is greatly influenced by temperature, and the influence of each element on the influence is also large.

In experiments conducted by the inventors, the same DRAM device bit was charged under two temperature environments of −5 ° C. and 45 ° C. (which is within the usable temperature range according to the standard of the device). When the time until inversion was measured, the coincidence among the first fixed number of inversion bits was about 50%. As described above, even in the same device, if the unique information output is different when the usage environment is different, the reliability of device authentication by the PUF is greatly reduced.

In such a case, in order to stably output a specific information, a method using an error correction code having a high error correction capability can be considered. However, in order to use such an error correction code, a complicated method is required. Decoding processing is necessary, and the amount of leaked information from information held for error correction also increases, so a large-scale processor and memory are required. This also causes a high cost.

On the other hand, since environmental factors such as temperature continuously change physical information, for example, a bit having a short time until inversion at a certain temperature in a DRAM tends to be easily inverted at other temperatures. For example, it has been confirmed by experiments conducted by the inventors that the ten bits that first invert in DRAM at −5 ° C. tend to fall within the first 100 even at 45 ° C.

If this can be used for device authentication by PUF, the above problem may be solved. However, to select 10 out of the first 100 inversion bits at 45 ° C and reproduce the first 10 inversion bit positions at -5 ° C, all 10 out of 100 are selected. It is necessary to try the combination. This is not a practically feasible calculation because it requires about 2 to the 47th power, that is, about 140 trillion trials. Techniques that can solve the problems described above are not described in the above-mentioned Patent Documents 1 to 4 and Non-Patent Documents 1 to 4.

An object of the present invention is to provide a device-specific information generation / output device, a device-specific information generation method, and a generation program that are not easily affected by environmental changes such as temperature and that can stably output certain specific information. There is.

In order to achieve the above object, a device specific information generation / output apparatus according to the present invention detects device specific information related to authentication of an electronic device from an electronic device including a plurality of circuits, and outputs the device specific information generation output. A device physical information generation unit including a plurality of circuits for which specific information is to be detected; a higher-level circuit detection unit that detects physical characteristics of each circuit from the device physical information generation unit; and detection at a first time Group detection by selecting M circuits (M is an integer of 2 or more) based on the ranking of the numerical values of the generated physical characteristics and creating a group and storing information about the group in a nonvolatile memory provided in advance And a registered circuit estimation unit that generates and outputs first unique information from physical characteristics of the M circuits, and the group detection unit A function of selecting N circuits more than M based on the numerical order of the physical characteristics detected at the second time later is provided, and the registered circuit estimation unit can arbitrarily select any of the N circuits. A function of selecting M circuits, generating second unique information from the physical characteristics of the selected M circuits, and outputting the unique information if the first and second unique information match. It is characterized by providing.

To achieve the above object, a device specific information generation method according to the present invention detects device specific information related to authentication of an electronic device from an electronic device including a plurality of circuits and outputs the device specific information. Then, the upper circuit detection unit detects the physical characteristics of each circuit from the device physical information generation means including a plurality of circuits whose specific information is to be detected at the first time, and the numerical order of the detected physical characteristics Based on the above, the group detection unit selects M circuits (M is an integer of 2 or more) to create a group, and stores information about the group in a nonvolatile memory provided in advance by the group detection unit. The registered circuit estimation unit generates the first unique information from the physical characteristics of the individual circuits, and the device physical information generation unit generates the first unique information at a second time after the first time. The upper circuit detection unit detects the physical characteristics, and the group detection unit selects N circuits having more than M based on the numerical order of the physical characteristics detected at the second time. The registered circuit estimation unit selects any M circuits from among them, and the registered circuit estimation unit generates second unique information from the physical characteristics of the selected M circuits, and the first and second If the unique information matches, the registered circuit estimation unit outputs this unique information.

In order to achieve the above object, a device specific information generation program according to the present invention detects device specific information related to authentication of an electronic device from an electronic device including a plurality of circuits, and outputs the device specific information generation output device A procedure for detecting physical characteristics of each circuit from a device physical information generation unit including a plurality of circuits that are targets of detection of specific information at a first time is detected by a computer included in the device specific information generation / output device. A procedure for creating a group by selecting M (M is an integer of 2 or more) circuits based on the ranking of the numerical values of the physical characteristics, a procedure for storing information about the group in a nonvolatile memory provided in advance, A procedure for generating first specific information from physical characteristics of M circuits, and device physical information generation at a second time after the first time. A procedure for detecting physical characteristics of each circuit from the means, a procedure for selecting N circuits more than M based on the order of the numerical values of the physical characteristics detected at the second time, and an arbitrary one of the N circuits The procedure for selecting the M number of circuits, the procedure for generating the second unique information from the physical characteristics of the selected M circuits, and the unique information if the first and second unique information match. The output procedure is executed.

As described above, the present invention first generates first unique information from M circuits selected based on the order of physical characteristics at a first time, and at a second time after the first time. Arbitrary M circuits are selected from the N circuits selected based on the order of physical characteristics to generate second unique information, and whether or not the first and second unique information match is determined. Since the determination is made, the number of trials when selecting an arbitrary M out of N can be suppressed to a range that can be actually calculated.

As a result, a device specific information generation / output device, a device specific information generation method, and a generation with excellent characteristics that it is difficult to be influenced by environmental changes such as temperature and can stably output specific specific information. A program can be provided.

It is explanatory drawing shown about the more detailed structure of the physical information mapping means shown in FIG. It is explanatory drawing shown about the structure of the terminal device which concerns on the 1st Embodiment of this invention. FIG. 3 is a flowchart showing an operation related to a registration phase of the terminal device (device specific information generation / output device) shown in FIGS. 1 and 2. FIG. FIG. 3 is a flowchart showing an operation related to a use phase of the terminal device (device specific information generation / output device) shown in FIGS. 1 and 2. FIG. FIG. 3 is an explanatory diagram showing a more detailed configuration of the device physical information generation unit and the upper circuit detection unit shown in FIGS. It is explanatory drawing shown about the structure of the terminal device which concerns on the 2nd Embodiment of this invention. It is explanatory drawing shown about the more detailed structure of the physical information mapping means shown in FIG. FIG. 8 is a flowchart showing an operation related to a registration phase of the terminal device (device specific information generation / output device) shown in FIGS. 6 to 7. FIG. FIG. 8 is a flowchart showing an operation related to a use phase of the terminal device (device-specific information generation / output device) shown in FIGS. It is explanatory drawing shown about the structure of the terminal device which concerns on the 3rd Embodiment of this invention. It is explanatory drawing shown about the more detailed structure of the physical information mapping means shown in FIG. 12 is a flowchart showing an operation related to a registration phase of the terminal device (device specific information generation / output device) shown in FIGS. 12 is a flowchart showing an operation related to a use phase of the terminal device (device-specific information generation / output device) shown in FIGS. It is explanatory drawing shown about the structure of the terminal device provided with the specific information generation means by PUF which concerns on the existing technique.

(First embodiment)
Hereinafter, the configuration of the embodiment of the present invention will be described with reference to FIGS. 1 and 2 and FIG.
First, the basic content of the present embodiment will be described, and then more specific content will be described.
The device specific information generation / output device (terminal device 10) according to the present embodiment is a device specific information generation / output device that detects and outputs specific information related to authentication of an electronic device. The apparatus includes a device physical information generation unit 110 including a plurality of circuits for which specific information is to be detected, an upper circuit detection unit 121 that detects physical characteristics of each circuit from the device physical information generation unit, and a first time. Based on the order of numerical values of the detected physical characteristics, M (M is an integer of 2 or more) circuits are selected to create a group, and information about this group is stored in the nonvolatile memory 13 provided in advance. A group detection unit 122 and a registered circuit estimation unit 123 that generates and outputs first unique information from physical characteristics of M circuits. The group detection unit 122 has a function of selecting N circuits greater than M based on the numerical order of the physical characteristics detected at a second time after the first time, and a registration circuit The estimation unit 123 selects any M circuits from the N circuits, generates second specific information from the physical characteristics of the selected M circuits, and generates the first and second If the unique information matches, this unique information is output.

Here, the device physical information generation means 110 is a dynamic RAM formed of a plurality of elements (DRAM elements 110a, b, c,...), And the time until the upper circuit detection unit 121 reverses after charging each element. Is detected as a physical property. Further, the upper circuit detection unit 121 includes a refresh control function 121b for controlling the refresh stop time so that the number of elements whose bits are inverted after charging is in a predetermined range.

Further, the registration circuit estimation unit 123 performs authentication by transferring the first and second unique information to the host device (host computer 20), and the first and second unique information are determined depending on whether or not the authentication is successful. It is judged whether or not.

With this configuration, the terminal device 10 of the present embodiment is less susceptible to environmental changes such as temperature, and can stably output certain unique information.
Hereinafter, this will be described in more detail.

FIG. 2 is an explanatory diagram showing the configuration of the terminal device 10 according to the first embodiment of the present invention. The terminal device 10 is a peripheral device that can be detachably connected to the host computer 20 via an interface such as a USB, and an MPU (microprocessor) 11 that is a main body that executes a computer program, and a volatile memory that stores data. 12 and the non-volatile memory 13, an interface 14 that mediates connection between the host computer 20 and the device physical information generation means 110.

The MPU 11 functions as the physical information mapping unit 120 by executing the unique information generation program. Accordingly, the MPU 11, the volatile memory 12, and the nonvolatile memory 13 together function as a device specific information generation / output device. The interface 14 is a general interface related to a connection between a computer and a peripheral device such as a USB (Universal Serial Bus).

The device physical information generation means 110 is a device including a plurality of circuits that are specific detection targets of physical characteristics. Specifically, for example, an oscillator circuit such as a DRAM element or a ring oscillator corresponds to this. The physical information mapping unit 120 detects a physical feature from the device physical information generation unit 110 and outputs it to the host computer 20 as an output value of the PUF.

FIG. 1 is an explanatory diagram showing a more detailed configuration of the physical information mapping means 120 shown in FIG. The physical information mapping unit 120 includes an upper circuit detection unit 121, a group detection unit 122, and a registered circuit estimation unit 123. In addition, the upper circuit information 124 is stored in the volatile memory 12, and the registration group information 125 is stored in the nonvolatile memory 13.

In the present embodiment, a case where the device physical information generation unit 110 is a DRAM element will be described. In this case, the upper circuit detection unit 121 detects the physical information by setting the retention characteristic of the DRAM element as physical information to be detected, and detecting the bit that is refreshed after the DRAM element is charged and then refreshed for a predetermined time. can do.

Here, “upper” or “lower” of the circuit means the order determined by the numerical value of the physical characteristic detected by the PUF. For example, when the retention characteristic of a DRAM element is to be detected, based on the numerical value of the time for erasing the charge, the bit for losing the charge earlier is set as “upper”, and the bit for the other is set as “lower”.

The terminal device 10 performs two types of processing, a registration phase and a usage phase, which will be described later, according to each component described above, and generates unique information. The usage phase is always executed after the registration phase. Hereinafter, the operation of each of these elements will be described.

The upper circuit detection unit 121 selects an upper circuit (bit that quickly loses charge in the case of a DRAM element) with respect to physical information to be detected in the device physical information generation unit 110, and for each selected upper circuit. Is stored as the upper circuit information 124.

In the registration phase, the group detection unit 122 performs a process of storing the circuit group of the upper circuit information 124 in the nonvolatile memory 12 as the registered group information 125. In the use phase, processing for detecting a circuit that matches the group of the registered group information 125 is performed.

In the registration phase, the registration circuit estimation unit 123 performs processing for determining unique information and outputting it to the host computer 20. Further, in the usage phase, a circuit selected in the registration phase is estimated from the circuits detected by the group detection unit 122, specific information is generated, output to the host computer 20, and authentication is executed.

FIG. 3 is a flowchart showing an operation related to the registration phase of the terminal device 10 (device-specific information generation / output device) shown in FIGS. The registration phase is a process executed when the terminal device 10 is first connected to the host computer 20 and used.

First, the upper circuit detection unit 121 determines M upper circuits using information obtained from the device physical information generation unit 110 (step S201). M is determined according to the amount of specific information assumed.

Subsequently, the group detection unit 122 identifies the group of M circuits determined in step S201, and stores an index indicating the group in the nonvolatile memory 13 as registered group information 125 (step S202). As a specific method of grouping, there are a method of corresponding to upper or lower bits of an index for specifying a circuit, a method of determining according to a circuit location, and the like.

Then, the registered circuit estimation unit 123 determines, as specific information, a series in which the indexes in the group of M upper circuits specified up to step S202 are connected (step S203). When authentication based on challenge-response is performed with the host computer 20, information necessary for authentication is shared in advance using this unique information in the registration phase.

FIG. 4 is a flowchart showing an operation related to the use phase of the terminal device 10 (device-specific information generation / output device) shown in FIGS. The use phase is a process executed when the terminal device 10 that has already completed the registration phase shown in FIG. 3 is actually connected to the host computer 20 and used.

First, the upper circuit detection unit 121 determines N upper circuits (step S251). N is sufficiently smaller than the total number of circuits, and it is appropriate to set it as a certain range larger than M in the registration phase. That is, 0 <M <N <total number of circuits.

Subsequently, the group detection unit 122 identifies one corresponding to the M groups in the registered group information 125 from among the N circuits determined in step S251 (step S252).

Then, the registration circuit estimation unit 123 determines whether or not a registration phase group to which one or more circuits correspond in step S252 exists in the registration group information 125 (step S253). The process ends abnormally as “unique information generation failure” (step S257). As the subsequent processing, for example, there is a method of starting over from measurement of physical information.

If there is a corresponding registration phase group in step S253, the registered circuit estimation unit 123 generates a candidate for specific information using an arbitrary circuit from the corresponding N circuits (step S254), and Using this, authentication of the terminal device 10 is attempted with respect to the host computer 20 (step S255). If the authentication is successful, the process ends normally (step S256). If the authentication fails, another M circuits are selected and the process is repeated from step S253. If the authentication fails for all M combinations selected from the N circuits, the process proceeds to step S257 and ends abnormally.

FIG. 5 is an explanatory diagram showing a more detailed configuration of the device physical information generation unit 110 and the upper circuit detection unit 121 shown in FIGS. FIG. 5 shows an example in which the physical characteristics of the device physical information generating means 110 are detected as a plurality of DRAM elements 110a, 110b, 110c,... The upper circuit detection unit 121 includes an R / W (read / write) controller 121a and a refresh control function 121b.

The R / W controller 121a is a module that executes read / write processing of the DRAM elements 110a, 110b, 110c,. The refresh control function 121b controls the refresh stop time so that the number of bits to stop and invert after refreshing all or a part of the bits of the DRAM elements 110a, 110b, 110c,. . When the number of inverted bits is too small, the refresh stop time is lengthened, and when it is too large, the refresh is changed to a smaller value and the measurement is repeated.

In the registration phase of the present embodiment, the refresh control function 121b obtains the first M bit inversion positions, but it is difficult to control the refresh stop time so that the number of inversion bits is exactly M. Also in the registration phase, it is appropriate to set an appropriate range in the same manner as in the use phase, and control so that the number of inverted bits N is inserted between them, and select M from these.

By configuring as described above and identifying the upper components in advance in the registration phase, the terminal device 10 (device specific information generation / output device) of the present embodiment is used for generation of specific information. Part identification can be simplified. In the case of the DRAM described in the section of the problem to be solved by the invention, when the entire bits of the DRAM are divided into 64 groups, the inversion bits included in each group among the 100 inversion bits in the use phase. The number is about two on average.

The 10 inversion bits in the registration phase are included in the 100 inversion bits with a high probability. Assuming that 2 bits are candidates for each of the 10 groups in the registration phase, if the 2 ^ 10 candidates are tried in the use phase, the same inverted bits as in the registration phase can be reproduced.

If the DRAM size is 64 Mbits in the case of the above DRAM (position information is 26 bits), the information amount of a combination of 10 selected from these is 238 bits. On the other hand, if 64 = 2 ^ 6 groupings are performed by the method of the present embodiment, the information amount of the index in each inverted bit group becomes the information amount of 20 bits when one is selected from the group, The total of 10 groups is 200 bits.

As described above, according to the present embodiment, it is possible to reduce the amount of unique information generated from the same physical information and reduce the amount of calculation required for the generation.

(More specific operation example)
Hereinafter, a more specific operation example of the present embodiment will be described. Here, a DRAM element is used as the device physical information generation means 110, and the refreshed bit is stopped and inverted for the DRAM element as the upper circuit.

If the number of bits of the DRAM is 64M (= 2 ^ 26, hereinafter "A to the power B" is expressed as "A ^ B"), one bit (one circuit) is a 26-bit index (16-bit I / O can be expressed as a 4-bit bit order and a 22-bit address). Groups can be associated with the upper (or lower) bits of the index. If the upper bits corresponding to a group are 18 bits, the total number of groups is 2 ^ 18.

Also, since 26-18 = 8 bits per circuit is used as the unique information, the unique information generated from the M circuits in the registration phase is 8M bits. In order to generate 64-bit unique information, M = 8 is set. An example with this parameter is shown below.

In the registration phase, the upper circuit detection unit 121 controls the refresh stop time so that the number of inversion bits falls within a range including M = 8 as a lower limit. For example, it is conceivable to set the upper limit to 2 × M, that is, 16. Assume that M = 8 and 10 bits E1 to E10 represented by the next index are inverted during a certain refresh stop time in the registration phase. The following shows the address of each bit of E1 to E10 in hexadecimal (hex) format.

E1: 08160d6
E2: 0b1e806
E3: 16b12cd
E4: 177eeee1
E5: 1b978ae
E6: 204fe7f
E7: 29b9366
E8: 29c7f87
E9: 3264a39
E10: 392324a

For M = 8, for example, E1 to E8 are selected as registration phase circuits. Since the upper 18 bits correspond to a group, the group detection unit stores eight groups G1 to G8 represented by the following index in the nonvolatile memory as registered group information.
G1: 08160
G2: 0b1e8
G3: 16b12
G4: 177ee
G5: 1b978
G6: 204fe
G7: 29b93
G8: 29c7f

Since the lower 8 bits of the 26-bit index of the circuit is an index in the group, the unique information I is the next 64 bits for the circuits E1 to E8.
I: d6 06 cd e1 ae 7f 66 87

When the same group is generated, only one of them may be selected, and then M circuits may be selected.

In the use phase, the upper circuit detection unit 121 controls refresh so that inverted bits of about N = 2M to 10M (16 to 80) are generated with respect to M = 8 in the registration phase. The group detection unit reads the group index of G1 to G8 and finds one included in each group among N circuits.

Here, for example, it is assumed that N = 19 circuits from the next F1 to F19 are obtained as upper circuits for the registration phase.

F1: 08160d6
F2: 0bea055
F3: 0fd3fa1
F4: 165d693
F5: 16b12cd
F6: 177eeee1
F7: 19e7c50
F8: 1b6f798
F9: 1b978ae
F10: 204fe7f
F11: 23c8f04
F12: 29b9366
F13: 29c7f87
F14: 29c7feb
F15: 2fd322e
F16: 3264a39
F17: 346a468
F18: 3825018
F19: 3ccb504

Here, the group detection unit 122 identifies the circuits F1 to F8 corresponding to the registered group information G1 to G8 as follows.
G1: F1
G2: None G3: F5
G4: F6
G5: F9
G6: F10
G7: F12
G8: F13, F14

In this embodiment, the registered circuit detecting means 123 is for all the circuits corresponding to the group for G2 (2 ^ 8 = 256 in this embodiment), and for G8, F13 and F14. For other groups, a combination of one corresponding circuit is a candidate for a circuit in the registration phase. That is, in this case, the unique information in the registration phase can be specified by trying 256 × 2 = 512 unique information candidates. This is a significantly smaller number of trials than the above-mentioned “about 2 to the 47th power, that is, about 140 trillion times”, and is a calculation amount within a practically computable range.

As described in steps S253 and 255 of FIG. 4, if there are too many groups that do not have corresponding circuits, it is determined that there are no circuit candidates in the registration phase, and the processing of the registered circuit detection unit may be terminated. . In this embodiment, for example, if the total number of candidates is set to 2 ^ 20, the processing of the registered circuit detection means can be terminated abnormally when there is no corresponding circuit in three or more registered groups.

(Overall operation of the first embodiment)
Next, the overall operation of the above embodiment will be described.
The device specific information generation method according to the present embodiment is a device specific information generation / output device 10 that detects specific information related to authentication of an electronic device and outputs the specific information. The upper circuit detection unit detects the physical characteristics of each circuit from the device physical information generation means including a plurality of circuits (step S201 in FIG. 3), and the group detection unit detects M based on the numerical order of the detected physical characteristics. A group is created by selecting a circuit (M is an integer of 2 or more) (FIG. 3, step S202), and information about this group is stored in a non-volatile memory provided in advance with a group detection unit. The registered circuit estimation unit generates and outputs the first unique information from the physical characteristics of the circuit (step S203 in FIG. 3), and is detected at the second time after the first time. Based on the ranking of the numerical values of the physical characteristics, the group detection unit selects N circuits more than M (FIG. 4, step S251), and any M circuits from the N circuits are registered. The estimation unit selects (FIG. 4, steps S252 to 253), and the registered circuit estimation unit generates second unique information from the physical characteristics of the selected M circuits (FIG. 4, step S254). If the first and second unique information match, the registered circuit estimation unit outputs this unique information (FIG. 4, steps S255 to 256).

Here, each of the above-described operation steps may be programmed to be executable by a computer, and may be executed by the MPU 11 of the device specific information generation / output device 10 that directly executes each of the steps. The program may be recorded on a non-temporary recording medium, such as a DVD, a CD, or a flash memory. In this case, the program is read from the recording medium by a computer and executed.
By this operation, this embodiment has the following effects.

In the present embodiment, first unique information is first generated from M circuits selected based on the order of physical characteristics at a first time, and the physical characteristics at a second time after the first time. Arbitrary M circuits are selected from the N circuits selected based on the rank to generate second unique information, and it is determined whether or not the first and second unique information match. It is configured.

As a result, the refresh stop time is controlled so that the number of trials when selecting an arbitrary M out of N is reduced, that is, the number of elements whose bits are inverted after charging is within a predetermined range. can do. In other words, the unique information can be successfully generated without trying an excessive number, and the above-described problems can be solved.

(Second Embodiment)
In the second embodiment of the present invention, in addition to the configuration described as the first embodiment, the registration circuit estimation unit 423 stores the hash value of the first unique information in the nonvolatile memory 13. 423a and determining whether or not the first and second unique information match depending on whether or not the hash value of the second unique information matches the hash value of the first unique information .

With this configuration, in addition to obtaining the same effect as that described in the first embodiment, the unique information can be obtained only within the device without transferring the first and second unique information to the host device. It becomes possible to perform processing related to generation of.
Hereinafter, this will be described in more detail.

FIG. 6 is an explanatory diagram showing the configuration of the terminal device 310 according to the second embodiment of the present invention. The terminal device 310 has substantially the same configuration as the terminal device 10 according to the first embodiment shown in FIG. 2, but the physical information mapping unit 120 is replaced with another physical information mapping unit 420.

FIG. 7 is an explanatory diagram showing a more detailed configuration of the physical information mapping means 420 shown in FIG. Compared with the configuration of the physical information mapping unit 120 according to the first embodiment illustrated in FIG. 1, the physical information mapping unit 420 is configured such that the registered circuit estimation unit 123 is replaced with another registered circuit estimation unit 423, and is non-volatile. The physical information mapping unit 120 according to the first embodiment has the same configuration except that the hash value 426 is newly stored in the volatile memory 13. Therefore, the same elements as those in the first embodiment are referred to by the same names and reference numbers.

The registered circuit estimation unit 423 includes a hash function output function 423a. A hash value 426 of the generated unique information is calculated by the hash function output function 423a and stored in the nonvolatile memory 13.

Here, as a hash function usable as the hash function output function 423a, for example, a cryptographic hash function such as SHA-1 (Secure－１Hash Algorithm 1) or a hash function using a block cipher is used. It is desirable to suppress However, from the viewpoint of ease of mounting, it is also possible to use a checksum or a CRC (Cyclic Redundancy Check) code that is a simpler process.

When such a hash function is used, in order to specify one circuit in the registration phase, it is appropriate to set the length of the hash value to be equal to or greater than the number of unique information candidates. If the total number of candidates is set to 2 ^ 20, the hash value must also be 20 bits or more. When using a checksum, CRC code, etc., unique information is likely to leak by the size of the hash value, so it is desirable to set it as small as possible.

FIG. 8 is a flowchart showing an operation related to the registration phase of the terminal device 310 (device specific information generation / output device) shown in FIGS. Again, the same operations as those of the terminal device 10 shown in FIG. The operation shown in FIG. 8 is the same as the operation shown in FIG. 3 until step S203 for determining the unique information. Thereafter, the hash function output function 423a calculates the hash value of the determined unique information. The operation of storing (step S504) is performed to complete the registration phase.

FIG. 9 is a flowchart showing an operation related to the use phase of the terminal device 310 (device specific information generation / output device) shown in FIGS. Again, the same operations as those of the terminal device 10 shown in FIG. The operation shown in FIG. 9 is the same as the operation shown in FIG. 4 until step S253 for determining whether or not the registration group information 125 exists.

If there is a corresponding registration phase group in step S253, the hash function output function 423a generates a hash value of the candidate for the specific information (step S554), and this is stored in the nonvolatile memory 13 as the hash value 426. It is determined whether or not it matches the hash value that has been set (step S555). If it matches, the process ends normally, and if it does not match, the process is repeated from step S253 using another circuit. All other steps are the same as those shown in FIG.

As described above, by storing the hash value 426 of the unique information in the nonvolatile memory 13 by the hash function output function 423a, the uniqueness of the terminal device 310 is unique even if the host computer 20 is not authenticated. It becomes possible to determine whether or not the information generation is successful.

(Third embodiment)
In the third embodiment of the present invention, in addition to the configuration described as the first embodiment, the registered circuit estimation unit 723 includes a syndrome generation function 723a that stores a syndrome of the first unique information in a nonvolatile memory, A decoding function 723b that decodes the second unique information by using the syndrome of the first unique information, and the first and second unique information depending on whether or not the second unique information has been successfully decoded by the decoding function. It is configured to determine whether the information matches. In addition, the decoding function 723b uses the second specific information as an erasure error when there is no combination for selecting M circuits from the N circuits whose first and second specific information match. Decrypt.

With this configuration, in addition to obtaining the same effect as that described in the first embodiment, the unique information can be obtained only within the device without transferring the first and second unique information to the host device. The processing relating to the generation of can be performed more quickly and with higher reliability than in the second embodiment.
Hereinafter, this will be described in more detail.

FIG. 10 is an explanatory diagram showing the configuration of the terminal device 610 according to the third embodiment of the present invention. The terminal device 610 has substantially the same configuration as the terminal device 10 according to the first embodiment shown in FIG. 2, but the physical information mapping unit 120 is replaced with another physical information mapping unit 720.

FIG. 11 is an explanatory diagram showing a more detailed configuration of the physical information mapping means 720 shown in FIG. Compared with the configuration of the physical information mapping unit 120 according to the first embodiment illustrated in FIG. 1, the physical information mapping unit 720 is configured such that the registered circuit estimation unit 123 is replaced with another registered circuit estimation unit 723, and is non-volatile. Except that a new syndrome 726 is stored in the volatile memory 13, it has the same configuration as the physical information mapping unit 120 according to the first embodiment. Therefore, the same elements as those in the first embodiment are referred to by the same names and reference numbers.

The registered circuit estimation unit 723 includes a syndrome generation function 723a and a decoding function 723b. The syndrome generation function 723 a calculates a syndrome of the generated unique information and stores it as a syndrome 726 on the nonvolatile memory 13. Using the syndrome 726, the decryption function 723b performs a process of decrypting the hash value of the unique information candidate.

The syndrome here is a value obtained by multiplying the parity check matrix of the error correction code by the received sequence (vector). Here, as the error correction code, a code composed of symbols having the size of the intra-group index serving as a unit of unique information can be used. When M circuits are selected in the registration phase, an error correction code having a code length of M symbols is applied in syndrome generation.

FIG. 12 is a flowchart showing an operation related to the registration phase of the terminal device 610 (device specific information generation / output device) shown in FIGS. Again, the same operations as those of the terminal device 10 shown in FIG. The operation shown in FIG. 12 is the same as the operation shown in FIG. 3 until step S203 for determining the unique information. Thereafter, the syndrome generation function 723a calculates and stores the syndrome of the determined unique information. (Step S804) An operation is performed to end the registration phase.

FIG. 13 is a flowchart showing an operation related to the use phase of the terminal device 610 (device specific information generation / output device) shown in FIGS. Again, the same operations as those of the terminal device 10 shown in FIG. The operation shown in FIG. 9 is the same as the operation shown in FIG. 4 until step S253 for determining whether or not the registration group information 125 exists.

If there is a corresponding registration phase group in step S253, the decoding function 723b decodes the unique information candidate by using the syndrome 726 (step S854), and determines whether or not the unique information candidate has been successfully decoded (step S854). S855) If the decoding is successful, the process ends normally. If the decoding is not possible, the process is repeated from step S253 using another circuit. All other steps are the same as those shown in FIG.

A more detailed calculation example is shown. Consider a case where the example of the DRAM element shown as a detailed calculation example of the first embodiment is applied to the terminal device 610 according to the present embodiment. In this case, since the lower 8 bits per circuit are used as unique information, it is appropriate to apply a Reed-Solomon code on an 8-bit 1 symbol, that is, a Galois field GF (2 ^ 8).

The lower 8 bits of the latter half of the index of M inverted bits in the registration phase are D1,..., D8 and these are regarded as elements of GF (2 ^ 8). When the primitive element of GF (2 ^ 8) is expressed by α, when applying a Reed-Solomon code with one symbol correction, the syndrome S = (S1, S2) for D1,..., D8 calculated by the syndrome generation function 723a is The following equation 1 can be used. Here, addition + and multiplication • are operations of GF (2 ＾ 8).

Then, let B1,..., B8 be the second half of the index of the registered group corresponding inverted bits obtained in the use phase. The decoding function 723b calculates the syndrome S '= (S1', S2 ') by the following equation 2.

An error vector J = (J1,..., J8) can be obtained by performing a normal Reed-Solomon code decoding process using S ″ = S + S ′ = (S1 + S1 ′, S2 + S2 ′) as a syndrome. If correct decoding is possible, symbols other than the corrected portion are 0. At this time, B1 + J1,..., B8 + J8 are estimated as unique information in the registration phase.

Decoding processing can be applied to Bi in group i for which there is no corresponding inversion bit as an erasure error. If no error has occurred, use this code to register up to 2 erasure errors, that is, up to 2 groups with no corresponding inversion bit, without registering all the candidates. It is possible to generate phase specific information.

As described above, the syndrome 726 of the unique information is stored in the nonvolatile memory 13 by the syndrome generation function 723a and the decryption function 723b, and by using this, the authentication operation for the host computer 20 is not performed, and further the unique information is stored. Thus, it is possible to determine whether or not the generation of the unique information has succeeded without trying to decode all the candidates. In other words, this improves the reliability of the terminal device 610 and allows the processing related to generation of the unique information to be performed more quickly. Here, instead of the syndrome, the encoding process may be executed to calculate and store the parity.

(Extended embodiment)
The first to third embodiments described above can be extended in various ways without changing their gist. The expansion will be described below.

In the above-described embodiment, the case where the device physical information generation unit 110 is a DRAM element has been described. However, this can be replaced with an oscillation circuit such as a ring oscillator. In that case, the upper circuit detection unit 121 can determine the upper and lower levels of the circuit based on the oscillation frequency or the delay characteristics, using the oscillation frequency and delay characteristics of the circuit as the physical characteristics to be detected.

Also, in the usage phase shown in FIG. 4 and the like, the registered circuit estimation unit 123 may select only the upper circuit corresponding to each group in the registration phase. In this way, even if the upper circuit number N selected in the registration phase is increased, the number of registered circuit candidates can be reduced.

The present invention has been described with reference to the specific embodiments shown in the drawings. However, the present invention is not limited to the embodiments shown in the drawings, and any known hitherto provided that the effects of the present invention are achieved. Even if it is a structure, it is employable.

The summary of the new technical contents of the above-described embodiment is summarized as follows. In addition, although part or all of the said embodiment is summarized as follows as a novel technique, this invention is not necessarily limited to this.

(Appendix 1) A device-specific information generation / output device that detects specific information related to authentication of an electronic device from an electronic device including a plurality of circuits and outputs the specific information.
Device physical information generation means including the plurality of circuits to be detected by the unique information;
An upper circuit detection unit for detecting physical characteristics of each circuit from the device physical information generation unit;
Based on the order of the numerical values of the physical characteristics detected at the first time, M (M is an integer of 2 or more) circuits are selected to create a group, and information about this group is provided in advance. A group detection unit stored in the memory,
A registration circuit estimation unit that generates and outputs first unique information from the physical characteristics of the M circuits;
The group detection unit has a function of selecting N circuits more than the M based on the numerical order of the physical characteristics detected at a second time after the first time,
The registered circuit estimation unit selects any M circuits from the N circuits, generates second unique information from the physical characteristics of the selected M circuits, and A device specific information generating / outputting device comprising a function of outputting the specific information when the first and second specific information match.

(Supplementary Note 2) The device physical information generation means is a dynamic RAM configured by a plurality of elements,
2. The device specific information generation / output device according to appendix 1, wherein the upper circuit detection unit has a function of detecting, as the physical characteristic, a time until a bit is inverted after each element is charged.

(Supplementary note 3) The supplementary note 2 is characterized in that the high-order circuit detection unit has a refresh control function for controlling a refresh stop time so that the number of the elements whose bits are inverted after charging is in a predetermined range. The device specific information generation / output device described.

(Appendix 4) The device physical information generating means is a plurality of oscillation circuits,
The device specific information generation / output device according to appendix 1, wherein the upper circuit detection unit has a function of detecting an oscillation frequency of each of the oscillation circuits as the physical characteristic.

(Additional remark 5) The said registration circuit estimation part transfers the said 1st and 2nd specific information to a high-order apparatus, performs authentication, and the said 1st and 2nd specific information depends on whether this authentication is successful. The device specific information generating / outputting device according to appendix 1, further comprising a function of determining whether or not they match.

(Additional remark 6) The said registration circuit estimation part is provided with the hash function output function which memorize | stores the hash value of said 1st specific information in the said non-volatile memory, and the hash value of said 2nd specific information and said 1st The device unique information generation output according to appendix 1, further comprising a function of determining whether or not the first and second unique information match depending on whether or not the hash value of the unique information matches. apparatus.

(Additional remark 7) The said registration circuit estimation part decodes the said 2nd specific information by the syndrome of the 1st specific information, and the syndrome production | generation function which memorize | stores the syndrome of the said 1st specific information in the said non-volatile memory And a function for determining whether or not the first and second unique information match depending on whether or not the second unique information has been successfully decrypted by the decoding function. The device-specific information generating / outputting device according to appendix 1, characterized by:

(Supplementary note 8) The device specific information generation / output device according to supplementary note 7, wherein the syndrome generation function generates a syndrome of the first specific information using a Reed-Solomon code.

(Supplementary note 9) When there is no combination in which the decoding function selects M circuits from among the N circuits in which the first and second unique information match, the second error as the erasure error The device specific information generation / output apparatus according to appendix 7, wherein the device specific information is decoded.

(Additional remark 10) In the device specific information production | generation output device which detects the specific information which concerns on the authentication of the said electronic device from the electronic device containing a some circuit, and outputs this,
The upper circuit detection unit detects the physical characteristics of each circuit from the device physical information generation unit including the plurality of circuits to be detected for the specific information at the first time,
The group detection unit selects M circuits (M is an integer of 2 or more) based on the detected numerical order of the physical characteristics to create a group,
Information about this group is stored in a nonvolatile memory provided in advance by the group detection unit,
A registered circuit estimation unit generates first unique information from the physical characteristics of the M circuits,
The upper circuit detection unit detects the physical characteristics of each circuit from the device physical information generation means at a second time after the first time,
Based on the numerical order of the physical characteristics detected at the second time, the group detection unit selects N circuits more than the M,
The registered circuit estimation unit selects any M circuits from the N circuits,
The registered circuit estimation unit generates second specific information from the physical characteristics of the selected M circuits,
If the first and second unique information matches, the registered circuit estimation unit outputs the unique information.

(Additional remark 11) In the device specific information production | generation output device which detects the specific information which concerns on the authentication of the said electronic device from the electronic device containing a some circuit, and outputs this,
A computer included in the device specific information generation / output device,
A procedure for detecting physical characteristics of each circuit from a device physical information generating unit including the plurality of circuits to be detected for the specific information at a first time;
A procedure for creating a group by selecting M (M is an integer of 2 or more) circuits based on the order of the numerical values of the detected physical characteristics,
A procedure for storing information about this group in a non-volatile memory provided in advance;
Generating first unique information from the physical characteristics of the M circuits;
A procedure for detecting a physical characteristic of each circuit from the device physical information generating means at a second time after the first time;
Selecting N circuits greater than M based on the numerical order of the physical characteristics detected at the second time;
A procedure for selecting any M circuits from the N circuits;
Generating second specific information from the physical characteristics of the selected M circuits;
And a procedure for outputting the unique information if the first and second unique information match,
A device-specific information generation program characterized in that

This application claims priority based on Japanese Patent Application No. 2011-263432 filed on Dec. 1, 2011, the entire disclosure of which is incorporated herein.

The present invention can be used to enhance information security such as device authentication and retention of confidential information in electronic devices, particularly information devices.

10, 310, 610 Terminal equipment 11 MPU
DESCRIPTION OF SYMBOLS 12 Volatile memory 13 Non-volatile memory 14 Interface 20 Host computer 110 Device physical information production | generation means 110a, b, c, ... DRAM element 120, 420, 720 Physical information mapping means 121 Upper circuit detection part 121a R / W controller 121b Refresh control Function 122 Group detection unit 123, 423, 723 Registered circuit estimation unit 124 Upper circuit information 125 Registered group information 423a Hash function output function 426 Hash value 723a Syndrome generation function 723b Decode function 726 Syndrome

Claims (10)

A device-specific information generating / outputting device that detects and outputs unique information related to authentication of the electronic device from an electronic device including a plurality of circuits,
Device physical information generation means including the plurality of circuits to be detected by the unique information;
An upper circuit detection unit for detecting physical characteristics of each circuit from the device physical information generation unit;
Based on the order of the numerical values of the physical characteristics detected at the first time, M (M is an integer of 2 or more) circuits are selected to create a group, and information about this group is provided in advance. A group detection unit stored in the memory,
A registration circuit estimation unit that generates and outputs first unique information from the physical characteristics of the M circuits;
The group detection unit has a function of selecting N circuits more than the M based on the numerical order of the physical characteristics detected at a second time after the first time,
The registered circuit estimation unit selects any M circuits from the N circuits, generates second unique information from the physical characteristics of the selected M circuits, and A device specific information generating / outputting device comprising a function of outputting the specific information when the first and second specific information match. The device physical information generating means is a dynamic RAM configured by a plurality of elements;
2. The device specific information generation / output device according to claim 1, wherein the upper circuit detection unit has a function of detecting, as the physical characteristic, a time until a bit is inverted after each element is charged. 3. The device according to claim 2, wherein the upper circuit detection unit includes a refresh control function for controlling a refresh stop time so that the number of the elements whose bits are inverted after charging is in a predetermined range. Specific information generation output device. The device physical information generating means is a plurality of oscillation circuits,
The device specific information generation / output device according to claim 1, wherein the upper circuit detection unit has a function of detecting an oscillation frequency of each of the oscillation circuits as the physical characteristic. The registration circuit estimation unit performs authentication by transferring the first and second unique information to a host device, and whether or not the first and second unique information match depending on whether or not the authentication is successful. The device specific information generation / output device according to claim 1, further comprising a function of determining whether or not the device is unique. The registration circuit estimation unit has a hash function output function for storing the hash value of the first unique information in the nonvolatile memory, and the hash value of the second unique information and the hash of the first unique information 2. The device specific information generation / output apparatus according to claim 1, further comprising a function of determining whether or not the first and second specific information match depending on whether or not the values match. A function of generating a syndrome in which the registered circuit estimation unit stores the syndrome of the first unique information in the nonvolatile memory; and a function of decoding the second unique information by using the syndrome of the first unique information; And a function of determining whether or not the first and second unique information match depending on whether or not the second unique information has been successfully decoded by the decoding function. The device specific information generation output device according to claim 1. The decoding function decodes the second specific information as an erasure error when there is no combination for selecting M circuits from the N circuits where the first and second specific information match. The device specific information generation / output device according to claim 7, wherein In an electronic device including a plurality of circuits, a device specific information generating / outputting device for detecting specific information related to authentication of the electronic device and outputting it is provided.
The upper circuit detection unit detects the physical characteristics of each circuit from the device physical information generation unit including the plurality of circuits to be detected for the specific information at the first time,
The group detection unit selects M circuits (M is an integer of 2 or more) based on the detected numerical order of the physical characteristics to create a group,
Information about this group is stored in a nonvolatile memory provided in advance by the group detection unit,
A registered circuit estimation unit generates first unique information from the physical characteristics of the M circuits,
The upper circuit detection unit detects the physical characteristics of each circuit from the device physical information generation means at a second time after the first time,
Based on the numerical order of the physical characteristics detected at the second time, the group detection unit selects N circuits more than the M,
The registered circuit estimation unit selects any M circuits from the N circuits,
The registered circuit estimation unit generates second specific information from the physical characteristics of the selected M circuits,
If the first and second unique information matches, the registered circuit estimation unit outputs the unique information. In an electronic device including a plurality of circuits, a device specific information generating / outputting device for detecting specific information related to authentication of the electronic device and outputting it is provided.
A computer included in the device specific information generation / output device,
A procedure for detecting physical characteristics of each circuit from a device physical information generating unit including the plurality of circuits to be detected for the specific information at a first time;
A procedure for creating a group by selecting M (M is an integer of 2 or more) circuits based on the order of the numerical values of the detected physical characteristics,
A procedure for storing information about this group in a non-volatile memory provided in advance;
Generating first unique information from the physical characteristics of the M circuits;
A procedure for detecting a physical characteristic of each circuit from the device physical information generating means at a second time after the first time;
Selecting N circuits greater than M based on the numerical order of the physical characteristics detected at the second time;
A procedure for selecting any M circuits from the N circuits;
Generating second specific information from the physical characteristics of the selected M circuits;
And a procedure for outputting the unique information if the first and second unique information match,
A device-specific information generation program characterized in that

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