[go: up one dir, main page]

WO2012129271A1 - Filtre à réponse impulsionnelle finie pour la production de sorties ayant différentes phases - Google Patents

Filtre à réponse impulsionnelle finie pour la production de sorties ayant différentes phases Download PDF

Info

Publication number
WO2012129271A1
WO2012129271A1 PCT/US2012/029899 US2012029899W WO2012129271A1 WO 2012129271 A1 WO2012129271 A1 WO 2012129271A1 US 2012029899 W US2012029899 W US 2012029899W WO 2012129271 A1 WO2012129271 A1 WO 2012129271A1
Authority
WO
WIPO (PCT)
Prior art keywords
elements
frequency response
signal
sets
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2012/029899
Other languages
English (en)
Inventor
A. Martin Mallinson
Hu Jing YAO
Dustin Forman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ESS Technology Inc
Original Assignee
ESS Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/414,487 external-priority patent/US9287851B2/en
Application filed by ESS Technology Inc filed Critical ESS Technology Inc
Priority to CN201280022752.7A priority Critical patent/CN103765414B/zh
Priority to EP12760719.0A priority patent/EP2689348A4/fr
Publication of WO2012129271A1 publication Critical patent/WO2012129271A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters

Definitions

  • the present invention relates generally to electronic filters, and more particularly to finite impulse response (FIR) filters.
  • FIR finite impulse response
  • a computer processor may have a primary clock of 66 MHz while it is desirable to operate internally at 3.3 GHz. To do so, each 66 MHz clock interval must be divided into 50 equal parts, so that the 50 parts thus correspond to a clock of 3.3 GHz.
  • FIG. 1 shows a 100 MHz sine wave signal 102.
  • Such a signal has a clock period of 10 nanoseconds (ns), so that the first clock cycle shown starts at 0 and ends at 10 ns on the horizontal axis, where another clock cycle begins.
  • signal 102 also has a zero crossing at 5 ns, since a negative (where the signal is falling) edge falls halfway between the positive (rising) edge of the first clock cycle that begins at 0, and the positive edge of the second cycle that begins at 10 ns.
  • Signal 102 will thus have zero crossings that are regularly spaced every 5 ns. Typically, each zero crossing,
  • FIG. 2 shows the result of changing the signal frequency from 100 MHz, as in Figure 1, to a signal 202 of 150 MHz, while keeping the delay at 2.5 ns, resulting in a delayed signal 204. While each signal 202 and 204 has regularly spaced zero crossings, and there are still twice as many zero crossings as with only the original signal 202, the combined zero crossings of both signals are no longer equally spaced. Thus, the delayed signal 204 cannot be used to effectively make a faster clock than that of the original signal 202, since that faster clock will be irregular.
  • a circuit 300 contains controlled delay elements Dl to D8 that are used to sub-divide the time interval of successive clock cycles. The circuit 300 operates to adjust the delay of each individual delay element such that the time interval to the end of the delay line is substantially equal to the clock period.
  • Such prior art implementations require a controller, in this case the integrator 302 in Figure 3, and the use of a control feedback loop 304.
  • the controller operates to ensure that the delay intervals are uniform, so that an even division of the clock period results. This is necessary so that no output interval is substantially longer than any other, as would be the case if the output of the delay line were reached before the next clock input arrived.
  • the feedback loop 304 has associated stability criteria and a finite time interval (the inverse of the loop bandwidth) over which it operates.
  • the delay elements Dl to D8 themselves are necessarily adjustable, and the adjustability may conflict with the need to be free from the time uncertainty of the output of the delay line relative to its input,
  • jitter i.e., the fact that the delay will not be precisely the same for each input clock edge.
  • One embodiment describes a method of designing a finite impulse response filter having a delay line containing a plurality of delay elements, the method comprising: selecting a desired frequency response for the filter;
  • Another embodiment describes an apparatus comprising: an input configured to receive an input signal; a delay line comprising a plurality of delay elements in series and connected to the input for propagating the input signal; a first plurality of buffers, each buffer in the first plurality of buffers receiving the delayed input signal after the input signal has passed through a separate one of the plurality of delay elements; a first plurality of elements having impedance values, each of the first plurality of elements connected to a separate one of the first plurality of buffers and chosen to determine their impedances so that the sum of the outputs of the first plurality of elements produces a desired frequency response to the input signal; a first output connected to the first plurality of
  • a second plurality of buffers each buffer in the second plurality of buffers receiving the delayed input signal after the input signal has passed through a separate one of the plurality of delay elements; a second plurality of elements having impedances, each of the second plurality of elements connected to a separate one of the second plurality of buffers and chosen to determine their impedances so that the sum of the outputs of the second plurality of elements produces the same frequency response to the input signal as the first plurality of elements but at a different phase; and a second output connected to the second plurality of elements to produce a second output signal having the desired frequency response, at the different phase from the first output signal.
  • a finite impulse response filter comprising: an input configured to receive an input signal; a delay line comprising a plurality of delay elements in series and connected to the input for propagating the input signal; a plurality of buffers, each buffer receiving the delayed input signal after the input signal has passed through a separate one of the plurality of delay elements; a first plurality of elements having impedance values, each of the first plurality of elements connected to a separate one of the plurality of buffers and chosen to determine their impedances so that the sum of the element outputs produces a desired frequency response to the input signal; a first output connected to the first plurality of elements to produce a first output signal having the desired frequency response; a second plurality of elements having impedance values, each of the second plurality of elements connected to a separate one of the plurality of buffers and chosen to determine their impedances so that the sum of the element outputs produces the same frequency response to the input signal as the first plurality of elements but at a different phase; and
  • Still another embodiment describes a computer readable storage medium having embodied thereon instructions for causing a computing device to execute a method for designing a finite impulse response filter having a delay line containing a plurality of delay elements, the method comprising: selecting a desired frequency response for the filter; selecting a plurality of sets of elements having impedance values, one element from each set to be coupled to the delay line after each delay element, the values of the elements selected to determine their impedances so that for each set of elements the sum of the outputs of the elements is a signal of the same frequency response as, but a different phase from, the sum of the outputs of another set of elements; and for each set of elements, providing an output connected to all of the elements in the set that is separate from the outputs connected to the other sets of elements.
  • Another embodiment discloses a computing device for simulating the response of a finite impulse response filter to a set of data elements
  • a processor configured to: select a first set of weights to be applied to the set of data elements to generate a set of first weighted data elements, such that the sum of the first weighted data elements is a first signal of the selected frequency response; select a second set of weights to be applied to the set of data elements to generate a set of second weighted data elements, such that the sum of the second weighted data elements is a second signal of the selected frequency response at a different phase from the first signal of the selected frequency
  • Figure 1 is a graph of a clock signal, showing the effect of adding a delayed clock signal in one example.
  • Figure 2 is a graph of another clock signal, showing the effect of adding a delayed clock signal as in Figure 1.
  • Figure 3 is a block diagram of one example of a clock multiplier circuit of the prior art.
  • Figure 4 is a graph of the clock signal of Figure 2, showing the desired effect of adding a dela ed clock signal.
  • Figure 5 is a block diagram of a finite impulse response (FIR) filter as known in the art.
  • FIR finite impulse response
  • Figure 6 is a block diagram of a FIR filter having two outputs.
  • Figure 7 illustrates one example of two sets of Fourier coefficients, one derived from a sine approximation formula, and one derived from a cosine formula approximation.
  • Figure 8 illustrates the output signals resulting from the Fourier coefficients of Figure 7.
  • Figure 9 illustrates one possible set of Fourier coefficients for a low pass filter and the resulting filter output.
  • Figure 10 illustrates a method of changing a low pass filter to a band pass by altering the Fourier coefficients of Figure 9 by multiplying them by a sine wave.
  • Figure 11 illustrates an example of the difference in phase between signals for which the Fourier coefficients have been multiplied by a sine wave and a cosine wave.
  • Figure 12 illustrates two sets of Fourier coefficient sine waves in which the phase has been shifted by one-quarter cycle.
  • Figure 13 illustrates two sets of Fourier coefficients created from the sine waves of Figure 12 to generate two outputs.
  • Figure 14 is a flowchart of a method of designing a FIR filter providing multiple outputs of the same frequency response and differing phases according to one embodiment.
  • the present application describes the design and implementation of a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s).
  • the phase shift is constant and independent of the frequency of the output signal.
  • a circuit responds to a change in input frequency more quickly, since it is not limited by loop bandwidth, and generally has less jitter, since the delay elements are fixed and not compromised by an adjustment mechanism. It is believed that such a circuit or method is thus a significant improvement over the prior art.
  • a finite impulse response (FIR) filter is a type of electronic filter with a broad range of applications. FIR filters are widely used in both digital signal processing and digital video processing, and their construction is well known in the prior art.
  • FIR filter is a transversal filter, or tapped delay line filter, as shown in Figure 5.
  • the output of such a filter is a weighted combination of voltages taken from uniformly spaced taps.
  • the filter contains a plurality (here 7 are shown) of unit delay elements Ul to U7, each of which introduces a delay of time t.
  • the filter is considered to be of the Mth order, where M-1 is the number of delay elements, so the filter of Figure 5 is an 8 th order filter.
  • each of the delay elements Ul to U7 is connected to an element having an impedance value, typically through some buffering means, such as buffers Zl to Z7; here, the elements having impedance values are shown as resistors Rl to R7.
  • some buffering means such as buffers Zl to Z7; here, the elements having impedance values are shown as resistors Rl to R7.
  • capacitors, inductors, depletion mode MOSFETs, and other devices, and any device having an impedance that does not otherwise interfere with operation of the filter may be used to provide the desired impedance values as described herein.
  • each resistor causes the signal on the respective delay element to which it is attached to contribute to the output signal in inverse proportion to the resistor value.
  • the resistor is small, the signal on the attached delay element will have a large contribution to the. output voltage, while if the resistor is large the contribution to the output will be smaller.
  • Figure 6 shows a FIR filter similar to that of Figure 5, but with a second set of resistors R8 to R14 sharing the same delay line and buffers.
  • the second set of resistors is thus able to provide a second output simultaneously with the first output produced by resistors Rl to R7 without duplicating all of the circuit elements. It will be apparent that more outputs may be added by adding additional sets of resistors, so that a common delay line and buffers may be used to make a multi-output FIR filter.
  • a FIR filter By properly selecting the resistor values in a set of resistors, a FIR filter is designed to provide an output with a desired frequency response.
  • the resistor values are typically calculated by a software program which takes the desired frequency response as an input. Since the two sets of resistors Rl to R7 and R8 to R14 in Figure 6 are independent, it is thus possible to use the circuit of Figure 6 to generate two outputs having different frequency responses to a single input signal.
  • Each buffer/resistor combination Zl/Rl to Z7/R7 acts as a multiplier and multiplies the tap input to which it is connected by a filter coefficient referred to as the tap weight WA- so that the multiplier connected to the kth tap input Sn-k produces an output Sn-k *
  • Yn Wo * Sn + Wl * Sn-I + Wl * Sn-2 + . . . + WN * Sn-N or
  • CO e _£ " 2 then the Fourier transform is a sine wave that is also Gaussian with an inverse standard deviation, and of the form: where e is Euler's number (2.718281828), ⁇ is frequency and a is a parameter that determines the center position of the peak and the width of the bell shape of the frequency response.
  • a window function is a function with .a value of zero outside some chosen interval.
  • a common type of window function used in filters is a rectangular window, which lets a signal pass through when it is within the frequency bounds of the window, and results in a value of zero outside the window.
  • the use of an appropriate window function not only limits the series of coefficients to a finite number, but can also suppress the occurrence of Gibbs phenomena, the oscillations that occur due to the behavior of a Fourier series at a discontinuity as a result of the truncation of the series.
  • the Kaiser window is generally considered to be a "near perfect" window function, and, when applied to a sine wave, is believed to result in as close to an impulse response as is possible.
  • This expression is one degenerate case of the more general expression: where j is the square root of -1 and P is an arbitrary phase factor. For any value of P, this expression is also the Fourier transform of the Dirac function.
  • P is a scalar quantity with no dimension or units, and may be of any value. It will be appreciated that P operates on the coefficient equation "modulo 2TL,” i.e., only the remainder of P after dividing by 2 ⁇ has any effect, so that it always appears as if P is between zero and 2n. It will be apparent that this is due
  • phase shift will be one complete cycle and it will appear as if there is no phase shift at all.
  • Figure 7 shows plots representing two coefficient sets calculated in this fashion.
  • a first set of a hundred coefficients is derived from the sine approximation, and a second set of a hundred coefficients is derived from the cosine approximation. While the coefficients are discrete numbers, when they are plotted in sequence against 0-100 on the x-axis, graphing software produces the smooth curves 702 for the sine approximation and 704 for the cosine approximation as shown. It can be confirmed that these two coefficient sets produce outputs having the same frequency response, since they are developed from the same sinusoidal frequency, but have a phase difference of 90 degrees.
  • a FIR filter is constructed by using a set of resistors, such as resistors Rl to R7 in Figure 5, which correspond to the coefficients.
  • resistors Rl to R7 in Figure 5 As is well known in the art, the resistor values are the in verse of the coefficient values. As is also known, where a coefficient, and thus the
  • the resistor is driven by an inverse voltage by the use of, for example, differential buffers that give an inverse of the signal on the delay line.
  • Figure 8 shows the response of the two filters constructed using resistors corresponding to the coefficients of Figure 7, i.e., again the resistor values are the inverse of the coefficient values.
  • Output signal 802 results from resistors having values that are the inverse of coefficient values contained in curve 702
  • output signal 804 results from resistors having values that are the inverse of coefficient values contained in curve 704.
  • the frequency response is identical, but the time domain response is not; rather, there is a phase shift of 90 degrees between the two outputs, since the value of P differs by 90 degrees ( ⁇ /2) in the mathematical calculation of the coefficients as above.
  • the output signals of Figure 8 may be fed to a comparator to determine the zero crossings.
  • the subsequent gating of the comparator outputs may be used to generate twice as many equally spaced zero crossings as are in the clock input.
  • PA1108US Q(i) W(i) * sin (o) * & * i + Pj)
  • W is the selected window function
  • ⁇ is the desired center frequency of the filter
  • ⁇ is the unit delay
  • i is the index into the coefficients
  • j goes from 0 to N-l.
  • phase difference is 90 degrees
  • any desired phase difference may be obtained by appropriate selection of the value of P.
  • a clock signal may be multiplied by a desired number by selecting the desired number of values of P evenly spaced between 0 and 2 ⁇ , i.e., 0 to 360 degrees. While it may appear to be easiest to multiply a clock signal by a number by which 360 degrees is neatly divided, this is not necessary; using the described technique, it is easily possible to multiply a clock signal by any number even if that number is not a factor of 360, such as, for example, 11 or 17.
  • the coefficients for a FIR filter do not have to be calculated from original mathematical principles as described above, but rather can be the result of an iterative method using an approximation algorithm of some type.
  • One such well known algorithm is the Parks-McClellan algorithm, often considered to be a standard method of FIR filter design.
  • Such approximation algorithms are well known and available in computer code and software that is commercially available, such as MATLAB ® from MathWorksTM.
  • Figure 9 shows a curve 902 which is again the result of smoothing a set of discrete coefficients, and the resulting frequency response 904 from those coefficients, from an iterative method for a low pass filter operating at 100 MHz and passing a signal up to 4 MHz.
  • This filter may be converted into a band pass filter by multiplying the coefficient values by a sine function. Since the filter operates at 100 MHz, it thus has a delay of 10 ns in each coefficient.
  • the initial coefficients may be determined for a low pass filter, and the frequency shift equal to the desired center frequency of a band pass filter. However, this is not required, and the coefficients may be first determined for a band pass filter which is then shifted in frequency from its center frequency to a desired center frequency of the phase-shifting FIR filter.
  • the clock signal on a particular processor chip may typically vary as much as plus or minus 20 percent or more from the nominal value, so that the expected 16 ns interval between cycles could be closer to 10 or 20 ns in a given instance. Thus, it is desirable to allow for a clock that runs from, for example, 40 MHz to 100 MHz.
  • a suitable filter might be designed by obtaining a set of coefficients from MATLAB ® , or some other iterative method, for a 30 MHz low pass filter, and then multiplying the coefficients by a sine wave of 66 MHz (the desired center frequency) to obtain a bandpass filter that allows signals between 36 MHz and 96 MHz.
  • multiple outputs of fixed phase differences may be obtained by multiplying the coefficients by sine waves having a different value of P, thus insuring the desired clock multiplier regardless of the actual frequency of the original clock signal as long as it is within the limits of the bandpass filter.
  • Ci(i) W(i) * sin ( ⁇ * ⁇ * i + Pi)
  • the coefficient sets will appear as shown in Figure 12.
  • One coefficient sine wave 1202 starts at the beginning of a cycle, i.e., at a rising zero crossing and ends after one-quarter of a cycle.
  • the other coefficient wave 1204 starts one-quarter of a cycle earlier with the last quarter of a cycle and ends at the end of a cycle, i.e., at a falling zero crossing. Reversing one wave in its entirety results in the other wave.
  • one coefficient set is the same as the other set but reflected about the Y-axis, i.e., the values are the same but one set takes the coefficient values in one order and the other set takes the same values in reverse order.
  • the resulting coefficient values may in one example be as seen in Figure 13. Since a window function is also symmetrical about the Y-axis, the similarity of values is preserved.
  • This "reflecting" method is limited to making only two filters differing in phase by n/2, or 90 degrees, but it allows for simple construction of a circuit, as the construction of two identical sets of components is easier than arbitrary sets of elements.
  • the two identical sets of elements that make up the two FIR filters generally sets of resistors, in one instance are connected to the delay line in one order, and in the second instance are connected to the delay line in reverse order.
  • resistors Rl through R7 will have values corresponding to a set of coefficients, while resistors R8 to R14 will
  • Figure 14 is a flowchart of one embodiment of a method of designing a FIR filter as described herein. First, a desired frequency response is selected at step 1401.
  • step 1402 a plurality of sets of Fourier coefficients are determined, one for each desired output, each set of coefficients resulting in the same frequency response as the other sets, but each resulting in a different desired phase of the output signal. As above, any arbitrary number of outputs may be selected.
  • step 1403 sets of resistor values are determined, each set of resistor values corresponding to one of the sets of Fourier coefficients, and each resistor value in a set being the inverse of a different coefficient in the corresponding coefficient set.
  • Each set of resistors is attached to the delay line at step 1404, and a separate output connection created for each set of resistors at step 1405 so that each output of different phase may be separately accessed.
  • the sets of Fourier coefficients may be determined in various ways at step 1402.
  • the sets of coefficients are each calculated mathematically by including a different phase constant in the calculation of each set.
  • one set of coefficients is determined by an iterative method, and then that set of coefficients is multiplied by one or more sine waves of different phases to obtain the other sets of coefficients.
  • the iterative method may be performed by software such as, in one
  • the length of the filter is constrained so that the coefficient sinusoidal wave ends on a quarter-wave boundary, a first set of coefficients is determined, and a second set of coefficients is derived by reversing the order of the first set of coefficients.
  • the elements providing the desired impedance values need not be resistors, but may be, for example, capacitors, inductors or FETs connected as pass devices, depletion mode MOSFETs, or other devices, with the values of the elements (such as capacitance, inductance, etc.) selected to provide the desired impedance values.
  • the elements such as capacitance, inductance, etc.
  • PA1109US filed on even date herewith, entitled “System and Method for Series and Parallel Combinations of Electrical Elements,” the contents of which are incorporated herein.
  • resistors attached to the delay line at different points may be coupled to an output through an intermediate node rather than directly connected to the output, again possibly for the easier or more cost effective obtaining of the desired impedance values by sharing. How to calculate the effective resistance value from individual resistors connected in series and parallel in these situations is well understood by those of skill in the art.
  • each plurality of sets of resistors having a common frequency response different from another plurality of sets of resistors, but the outputs of each set of resistors in a plurality of sets differing in phase from other sets of resistors in that plurality of sets.
  • the data may be an analog signal.
  • the analog signal is then connected to the various sets of resistors or other impedance - devices constructed as described herein, and the resulting output signals are a set of filtered analog signals which still maintain a precise phase difference.
  • the outputs thus represent a series of time-delayed versions of the filtered input . signal, and the circuit is an analog delay generator, although the delay line is processing a digital signal.
  • the input may be analog data that is represented as a pulse width modulation (PWM) or sigma delta (SD) stream of digital data, and thus has a frequency component of the continuous analog signal present in the digital data stream.
  • PWM pulse width modulation
  • SD sigma delta
  • the filter may be designed to select the analog signal that is present in the data stream and derive various phase shifted versions of that analog signal.
  • Class-D audio uses PWM to impress the continuous audio signal onto the digital data stream.
  • the set of data elements thus implicitly includes the delay times of the delay elements of a particular delay line in a FIR filter.
  • a frequency response of a FIR filter is selected by a user, for example, by means of an input.
  • Such software engines may be used to implement the methods described herein.
  • two or more sets of weights are selected and applied to the set of data elements.
  • Each set of weights is selected so that the sum of the weighted data elements is a signal of the selected frequency response; however, the sum of the weighted data elements using one set of weights has a different ⁇ phase from the sum of the weighted data elements using another set of weights.
  • each set of weights is thus equivalent to the impedance values that would be used to obtain a selected output signal in an actual FIR filter, so that weighting the data elements is equivalent to the weighting of the delayed input signal in the actual FER filter.
  • a clock multiplier may start with a clock of 10 MHz, which is comparatively simple to make, to effectively obtain a 1 GHz clock without the use of, for example, PLL's.
  • the described method and apparatus can be implemented in numerous ways, including as a process, an apparatus, or a system.
  • the methods described herein may be implemented by program instructions for instructing a processor to perform such methods, and such instructions recorded on a computer readable storage medium such as a hard disk drive, floppy disk, o tical disc such as a compact disc (CD) or digital versatile disc (DVD), flash memory, etc.
  • the methods may also be incorporated into hard-wired logic if desired. It should be noted that the order of the steps of the methods described herein may be altered and still be within the scope of the disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Networks Using Active Elements (AREA)

Abstract

L'invention porte sur un procédé et un système pour concevoir et mettre en œuvre un filtre à réponse impulsionnelle finie (FIR) afin de créer une pluralité de signaux de sortie, chaque signal de sortie ayant la même fréquence mais a un décalage de phase différent de l'autre sortie ou des autres sorties. Des valeurs sont déterminées pour les résistances, ou d'autres éléments ayant des valeurs d'impédance, dans un filtre FIR ayant une pluralité de sorties, de sorte que chaque sortie ait la même réponse de fréquence mais une phase différente de celle de l'autre sortie ou des autres sorties. Ceci est accompli par l'inclusion d'un facteur de phase dans le calcul en domaine temporel des valeurs de résistance qui ne modifie pas la réponse dans le domaine fréquentiel. Le décalage de phase est constant et indépendant de la fréquence du signal de sortie.
PCT/US2012/029899 2011-03-22 2012-03-21 Filtre à réponse impulsionnelle finie pour la production de sorties ayant différentes phases Ceased WO2012129271A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201280022752.7A CN103765414B (zh) 2011-03-22 2012-03-21 用于产生具有不同相位的输出的有限冲激响应滤波器
EP12760719.0A EP2689348A4 (fr) 2011-03-22 2012-03-21 Filtre à réponse impulsionnelle finie pour la production de sorties ayant différentes phases

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161669420P 2011-03-22 2011-03-22
US614669420 2011-03-22
US13/414,487 2012-03-07
US13/414,487 US9287851B2 (en) 2011-03-22 2012-03-07 Finite impulse response filter for producing outputs having different phases

Publications (1)

Publication Number Publication Date
WO2012129271A1 true WO2012129271A1 (fr) 2012-09-27

Family

ID=46879722

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2012/029899 Ceased WO2012129271A1 (fr) 2011-03-22 2012-03-21 Filtre à réponse impulsionnelle finie pour la production de sorties ayant différentes phases

Country Status (1)

Country Link
WO (1) WO2012129271A1 (fr)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3050700A (en) 1959-01-19 1962-08-21 Rca Corp Phase shifting circuit
US4799025A (en) 1985-06-21 1989-01-17 U.S. Philips Corporation Digital FM demodulator using digital quadrature filter
EP0539776A2 (fr) 1991-10-26 1993-05-05 GRUNDIG E.M.V. Elektro-Mechanische Versuchsanstalt Max Grundig GmbH & Co. KG Dispositif pour obtenir, à partir d'un signal numérique, deux signaux de quadrature
EP1168615A1 (fr) * 2000-06-27 2002-01-02 Texas Instruments Incorporated Architecture transposé de filtre non-recursif
US20040139135A1 (en) * 2001-01-05 2004-07-15 Philip Druck N dimensional non-linear, static, adaptive, digital filter design using d scale non-uniform sampling
US20050168371A1 (en) * 1999-09-28 2005-08-04 Jiren Yuan Versatile charge sampling circuits
US7346645B2 (en) * 2004-11-05 2008-03-18 International Business Machines Corporation Architecture for transverse-form analog finite-impulse-response filter
US20120246607A1 (en) 2011-03-22 2012-09-27 Ess Technology, Inc. System and Method for Series and Parallel Combinations of Electrical Elements

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3050700A (en) 1959-01-19 1962-08-21 Rca Corp Phase shifting circuit
US4799025A (en) 1985-06-21 1989-01-17 U.S. Philips Corporation Digital FM demodulator using digital quadrature filter
EP0539776A2 (fr) 1991-10-26 1993-05-05 GRUNDIG E.M.V. Elektro-Mechanische Versuchsanstalt Max Grundig GmbH & Co. KG Dispositif pour obtenir, à partir d'un signal numérique, deux signaux de quadrature
US20050168371A1 (en) * 1999-09-28 2005-08-04 Jiren Yuan Versatile charge sampling circuits
EP1168615A1 (fr) * 2000-06-27 2002-01-02 Texas Instruments Incorporated Architecture transposé de filtre non-recursif
US20040139135A1 (en) * 2001-01-05 2004-07-15 Philip Druck N dimensional non-linear, static, adaptive, digital filter design using d scale non-uniform sampling
US7346645B2 (en) * 2004-11-05 2008-03-18 International Business Machines Corporation Architecture for transverse-form analog finite-impulse-response filter
US20120246607A1 (en) 2011-03-22 2012-09-27 Ess Technology, Inc. System and Method for Series and Parallel Combinations of Electrical Elements

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of EP2689348A4 *
WOODS ET AL.: "FPGA-based Implementation of Signal Processing Systems", 2008, pages 1 - 47, XP008171508, ISBN: 978-0-470-030, Retrieved from the Internet <URL:http://www.progetti.t3lab.itlvialablwp-contentluploads/download/20110517/FPGA-based%201mplementation%20of%20Complex%20Signal%20Processing%20System-tqw-darksiderg.pdf> [retrieved on 20120625] *

Similar Documents

Publication Publication Date Title
US9940415B2 (en) Finite impulse response filter for producing outputs having different phases
Hussain et al. Digital signal processing: an introduction with MATLAB and applications
Krishna et al. On design and applications of digital differentiators
Romero et al. Digital FIR Hilbert transformers: fundamentals and efficient design methods
CN105099457A (zh) 杂散音分散装置以及频率计测装置
KR960003063B1 (ko) 프로그램으로 분수 주파수를 분할할 수 있는 클럭 발생기
JP5337157B2 (ja) 試験装置、及び試験方法
CN105684314B (zh) 使用fir滤波器对固定模式抖动的抑制
RU2731251C2 (ru) Способ и устройство для преобразования частоты дискретизации потока выборок
US7768355B2 (en) Polyphase numerically controlled oscillator
WO2012129271A1 (fr) Filtre à réponse impulsionnelle finie pour la production de sorties ayant différentes phases
CN107154790A (zh) 基于fpga的反馈信号控制方法、系统及光模块调制器
US7529788B2 (en) Digital filter design method and device, digital filter design program, and digital filter
Abramovitch The multinotch, part II: Extra precision via Δ coefficients
Kapadia Digital filters: theory, application and design of modern filters
JPS6340367B2 (fr)
US8994422B2 (en) Use of Frequency addition in a PLL control loop
JP4989575B2 (ja) フィルタ及びフィルタの構成方法
TW200408813A (en) Digital filter design method and device, digital filter design program, and digital filter
Obara et al. Analysis of Oscillation Components in Instantaneous Frequency Estimation by Finite Order 2-D Hilbert Transformer
Ahmed et al. Low Pass FIR Filter Design and Analysis Using Hamming, Blackman and Kaiser Windows
Jiménez et al. On design of a multiplierless very Sharp Hilbert transformer by using identical subfilters
RU2553434C1 (ru) Формирователь квадратурных гармонических сигналов
RU2565504C1 (ru) Устройство допускового контроля частоты
Demirtas Minimax Design of Nonlinear Phase FIR Filters with Optimality Certificates

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12760719

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

REEP Request for entry into the european phase

Ref document number: 2012760719

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2012760719

Country of ref document: EP