WO2012123243A1 - System-on-a-chip including a programmable synthesizable core, and method for making such a system - Google Patents

Abstract

The invention relates to a system-on-a-chip (200, 408) comprising at least one programmable synthesizable core PSC (208, 209) and a dedicated block (201, 202, 203, 207). The PSC core and the dedicated block are synthesized together from a hardware description-language (HDL) model of the dedicated block (201, 202, 203, 207), as well as from a hardware description-language (HDL) model of the PSC core (306, 402) associated with a default configuration file (305, 401).

Description

 MONO-CHIP SYSTEM COMPRISING A SYNTHETICABLE PROGRAMMABLE HEART AND A METHOD OF MANUFACTURING SAME

 SYSTEM The invention relates to a single-chip system comprising a synthesizable programmable core and a method of manufacturing such a system. It applies in particular to the field of integrated circuits.

There are now several alternatives to implement applications on integrated circuits.

 A first possibility is to use integrated circuits designed specifically for a given application or set of applications. These circuits are designated by the acronym ASIC coming from the Anglo-Saxon expression "Application-Specific Integrated Circuit". They enable fast execution of applications and the cost of production is reduced when they are produced on a large scale. However, the design of such circuits is long and the development costs can be significant.

An alternative is to use programmable integrated circuits such as for example FPGA circuits, acronym from the English expression "Field Programmable Gate Array". The FPGA circuits are composed of a plurality of elementary logic cells that can be connected to each other by programming. The programming of an FPGA is implemented using a set of configuration bits for connecting the elementary cells in different ways. This set of configuration bits is usually grouped into a configuration file. This file is usually designated by the English word "bitstream". The configuration file can be stored outside the FPGA circuit in external nonvolatile memory. One of the advantages of FPGA chips is that they can be reprogrammed by modifying the configuration file. The implementation of a given application is facilitated because when an error is detected, it can be corrected by reprogramming the circuit without hardware modification. However, for a given application, because an FPGA circuit is not specialized, the silicon surface is larger than that required by an ASIC. In addition, its cost is higher and its performance in terms of less good running time. Another alternative is to integrate an FPGA circuit in a single-chip system also comprising specialized computing elements, said specialized computing elements being implemented in dedicated blocks, that is to say non-programmable blocks. Single-chip systems are usually referred to by the acronym SoC from the English expression "System on Chip". Since in this case the FPGA circuit is integrated within a SoC system, it is designated by the acronym eFPGA, the 'e' referring to the English word "embedded". FIG. 1 is a simplified representation of the design steps of a SoC system comprising an eFPGA circuit. Many difficulties are encountered.

 After specifying 100 what are the characteristics of the desired SoC system, two types of blocks must be designed. The first are the dedicated blocks and the second are the eFPGA blocks.

 To design dedicated blocks in a SoC, a synthesizable functional description 101 of said blocks must be produced. For this, a hardware description language HDL, acronym from the English expression "Hardware Description Language" is used. Commonly used examples of such languages are the VHDL and Verilog languages. The HDL languages are usually used to describe the expected operation of the dedicated blocks and allow their translation into a logical gate assembly, this logical gate assembly being obtained using a synthesis tool 102. More precisely, the result of the synthesis corresponds to a list of interconnections of logic gates 103, said list being usually presented in the form of a file designated by the English expression "netlist gate". This file corresponds to a list containing all the basic logic gates to be used for the implementation of the dedicated SoC blocks as well as information on how these doors are connected to each other.

With regard to the design of the eFPGA circuit, the designer must produce a hardware description 104 of the circuit and then use a generation tool 105 so as to generate from the hardware description an interconnection list of transistors 106, said list being presented usually in the form of a file referred to by the expression Anglo-Saxon "netlist transistor". A geometric file is also obtained. The generation tool to obtain these files is usually dedicated to eFPGA circuit design. It makes it possible to obtain in addition to the list of transistors and the geometrical file a simulation model. However, this simulation model is limited because it does not take into account all the physical phenomena related to the implementation of the eFPGA circuit on the SoC single chip system. Such an imperfect simulation model is nevertheless used to validate the system before the physical generation of the chip.

 It therefore appears that a first series of design operations

109, and a second series of design operations 1 10 are required to obtain a SoC integrating an eFPGA circuit, these series of operations being called design flows. The operations required for the implementation of the two streams are conducted independently of each other. The first stream 109 used for the synthesis of the dedicated blocks is called a flow of conventional design in the remainder of the description, the conventional term being used because this type of flow is similar to that used in the design of ASIC circuits. The second stream 1 10 is called the eFPGA stream.

 The lists 103, 106 obtained by the implementation of the conventional streams 109 and eFPGA 1 10 are then used at another stage of the design in order to obtain an image of the chip to be melted, this image being stored in files called geometric files 106, 1 12, also called "layout" file in English language.

 A disadvantage of this approach is that two independent streams 109, 1 10 are required. Designers must therefore decide as early as the specification phase of the single-chip system 100 of the distribution of functions required for the implementation of the targeted application or applications. Indeed, the functions necessary for the implementation of the chosen application can be implemented either in dedicated blocks or in eFPGA circuits. By way of example, a SoC will be obtained by implementing a first subset of functions in a dedicated block and a second-subset of functions in an eFGPA block.

Another disadvantage of this approach is that a number of errors can only be detected once the chip has melted. This is particularly due to the imperfections of the eFPGA block simulation model obtained with the aid of the generation tool 105 and with the production of geometric files 106, 1 12 with two independent processes 105, 107. These late detected errors result in a significant increase in the time and cost of developing the system. SoC because it is then necessary to correct the HDL models of the dedicated blocks to generate and synthesize new netlist files in order to correct these errors and then to melt a new chip to test it.

An object of the invention is in particular to overcome the aforementioned drawbacks.

 For this purpose, the subject of the invention is a single-chip system comprising at least one CPS synthesizable programmable core and a dedicated block. The CPS core and the dedicated block were synthesized together on the one hand from a model in the HDL hardware description language of the dedicated block and on the other hand from an HDL model of the CPS core associated with a configuration file by default.

 According to one aspect of the invention, the HDL model and the default configuration file of the CPS core have been generated from an initial HDL model corresponding to a non-programmable block. The HDL model of the CPS core associated with its default configuration file is functionally equivalent to the original HDL model.

 According to another aspect of the invention, the default configuration file is obtained by compiling the result of the synthesis of the initial HDL model, the architecture of the CPS core being taken into account by the compilation.

 The CPS core is synthesized, for example, using a standard cell library commonly used for ASIC synthesis.

 In one embodiment, memory elements are used for programming the CPS core. An initialization signal places the memory elements in a known state, said initialization signal being adapted so that the known states of the memory elements correspond to the values included in the default configuration file.

The initialization signal is for example adapted by retro-annotation of the HDL model of the CPS core in order to match each the default configuration file information when the memory element is set to 1 or reset.

 The memory elements are, for example, D flip-flops.

 According to one embodiment, the initialization signal is routed to the data inputs of flip-flops D.

 According to another embodiment, the initialization signal is routed to the SET or RESET inputs of the D flip-flops.

 The D flip-flops are for example chosen with a forcing input at 0 or with a forcing input at 1 so that said flip-flops are initialized by loading the values associated with them in the default configuration file.

 For example, the CPS core associated with its configuration file implements a memory controller.

 The invention also has a method for manufacturing a single-chip system as described above. The method comprises a step of generating a model in HDL hardware description language of a CPS synthesizable programmable core to implement functions described using an initial HDL model, a step of generating a file default configuration of the CPS core by synthesis and compilation of the initial HDL model, a step of synthesis of the CPS core and the dedicated block using the same synthesis tool, a step of generating a geometric file from the result of the synthesis and a step of casting the single chip system using said geometric file.

 According to one aspect of the invention, the synthesis is performed using a standard cell library commonly used for synthesizing ASICs.

 The HDL template and the default CPS core configuration file were generated from an initial HDL template corresponding to a non-programmable block so that the HDL model of the CPS core associated with its default configuration file is functionally equivalent to the initial HDL model.

Other features and advantages of the invention will become apparent with the aid of the following description given by way of non-limiting illustration, with reference to the appended drawings in which: FIG. 1 is a simplified representation of the design steps of a SoC system comprising an eFPGA circuit; FIG. 2 shows an example of a single-chip system according to the invention;

 FIG. 3 illustrates a first design phase making it possible to obtain a description in hardware description language of a CPS core as well as its configuration file;

 FIG. 4 illustrates how a SoC system according to the invention can be obtained from the HDL model of a CPS core and its configuration file;

 FIG. 5 illustrates how a SoC system comprising a CPS synthesizable programmable core can be set by default.

FIG. 2 shows an example of a single-chip system 200 according to the invention. This example SoC system comprises four dedicated blocks 201, 202, 203, 207 and three blocks called hard blocks 204, 205, 206.

 The hard blocks 204, 205, 206 correspond to blocks implementing functions commonly used in integrated circuits, such as memories, input-output interface circuits or PLLs, acronym from the English expression. -shows "Phase Locked Loop".

 The system further comprises an area in which appears a dedicated block 207 and two CPS synthesizable programmable cores 208, 209. A CPS heart 208, 209 is associated with at least one configuration file internally stored in the SoC or in a memory external. Such a file makes it possible to precisely program a CPS core after the chip of the mono-core system has been melted.

The dedicated blocks 201, 202, 203 having their own functionalities can be implemented using HDL models already used to implement dedicated blocks validated in the context of other SoCs. The designers can choose to reuse them directly, the risks of errors resulting from the implementation of these blocks being limited.

 The problem is different, for example when new functionalities have to be introduced in the SoC. In this case, an eFPGA type solution can be chosen. In this way, the new features are reprogrammable after the SoC has been melted. In the context of the invention, a new and innovative solution is proposed. A SoC according to the invention comprises one or more programmable synthesizable CPS cores 208, 209. Part of the new functionalities to be implemented in the SoC is allocated thereto, and the fact that these cores are programmable makes it possible to correct errors even after the production of the chip by modifying a configuration file. If the SoC is used for different versions of a product, the features implemented at CPS cores can also be adapted from one product to another by modifying the configuration file.

 Advantageously, the programmable logic of a CPS core is optimized to be able to achieve a given set of functions of a nature known a priori by the designer. For example, if a CPS core needs to implement a memory controller, the characteristic resources of a processor are useless and will not be included in the physical elements making up the core. In other words, a CPS core is a semi-dedicated block, which differs from FPGA and eFPGA type circuits whose architectures are developed to meet any need. FPGAs and eFPGAs are therefore often oversized, which is not the case for CPS cores.

FIGS. 3 and 4 show in a simplified manner the two design phases making it possible to obtain a SoC system according to the invention.

 FIG. 3 illustrates a first design phase making it possible to obtain an HDL model 307 of a CPS core, that is to say a description in the hardware description language of this core 306, as well as its configuration file 305.

In this example, the designers have chosen to implement an application 300 in which a first set of functions A is intended to be embedded in a dedicated block. A second set B of functions is divided into two subsets of functions B1 and B2. The subset of functions B1 is intended to be embedded in a dedicated block and the subset of functions B2 is intended to be embedded in a CPS core.

 A first step has the purpose of describing these sets of functions in hardware description language 300. An HDL model is obtained for each of them.

 A succession of steps is then applied to obtain from an initial HDL model 307 of the subset B2 an HDL model of the CPS core and its default configuration file.

 At first, the architecture of the CPS core must be determined 301. This can be described by the designer, for example using appropriate software. It is also possible to generate this architecture automatically or to select it from among different possible CPS core architectures included in a library. The architecture of a CPS core can also be refined for specific needs through the use of specialized modules or functions.

 The architecture of the CPS core is described by a hardware description language. On the other hand, the B2 function subset model is synthesized 303 from the initial HDL model 307 taking into account the architecture of the CPS core. The result of this synthesis is compiled 304 so as to produce a default configuration file 305 of the CPS core. A specific compilation tool is then required such as a conventional compilation tool for FPGA or eFPGA. The combination of the HDL 306 model of the CPS core and its default configuration file 305 is then functionally equivalent to the HDL model of an original non-programmable block 307 of the subset of B2 functions also called the initial HDL template, and can to be used in a classical synthesis flow.

Figure 4 illustrates how a SoC system according to the invention can be obtained from the HDL model and its configuration file.

The functional equivalence between the initial non-programmable 307 HDL model of the functional subset to be implemented on the core CPS, i.e., the subset B2 in this example, and the set consisting of the HDL template of said core 306, 402 associated with its default configuration file 305, 401 is essential for the design of a SoC according to the invention.

 This equivalence goes beyond that obtained when an eFPGA is used. In fact, in addition to having the same logical functionality, the initial HDL model and the set composed of the HDL model of the core and its default configuration file can be easily exchanged inside the synthesis stream. The physical part of the SoC implementing the subset of function is different depending on whether one or the other alternative is chosen. In particular, the silicon surface will be different. However, the initial HDL model and the composite set of the CPS core HDL model associated with its configuration file are both synthesizable by the same tools. This has the particular advantage of avoiding the implementation of an additional integration step when deciding on such a permutation.

 When the HDL 402 model of the CPS core and its configuration file 401 have been generated, they can be synthesized 404 together with the HDL model of the functional subset B1 and the HDL model of the function set A. After logical synthesis 404, a geometry file 406 may be generated 405 using a conventional tool and the SoC system 408 comprising a synthesizable programmable heart may be merged 407.

 In the case where the CPS core synthesis is implemented using a standard cell library, the equivalence is valid throughout the entire design process, including for placement and routing, it is for the geometrical file generation step. The SoC system can then be implemented using any integrated circuit manufacturing technology.

Figure 5 illustrates how a SoC system comprising a CPS synthesizable programmable core can be configured by default. A SoC according to the invention is a compromise between a SoC comprising an eFGPA and a SoC comprising only dedicated blocks. In other words, a SoC according to the invention is a semi-dedicated system. These systems are therefore useful for the implementation of one or more given applications, the CPS heart or hearts for programming some of the functions used by these applications. As explained above, there is functional equivalence between the initial HDL model and the HDL model of the CPS core associated with its default configuration file.

 For the purchaser of a SoC system according to the invention, it may be useful for it to be directly usable without having to program it, while leaving the possibility of fine-tuning later a subset of functions. For this, an advantageous embodiment of such a SoC system according to the invention comprises a technology that allows it to be configured by default when it is powered up.

 As a reminder, to be able to function the FPGA and eFPGA circuits must load the bits contained in a configuration file at memory points internal to these circuits, called memory points in the following description. These memory points are sequentially programmed from the configuration file usually stored on a storage medium external to the circuit to be programmed. This approach is typical when FPGA or eFPGA circuits are used because their configuration is not or does not need to be known at the time of their manufacture. Once the configuration file has been determined, when the system using an FPGA or an eFPGA is turned on, the bits of the configuration file are loaded. This operation is not instantaneous. In addition, an FPGA or an eFPGA is not available with a default configuration.

 The mono-chip system according to the invention advantageously allows to contain a default configuration of the CPS or cores without the purchaser of such a system having to perform any programming operation. For this, two alternatives are described below.

 Still as a reminder, an initialization signal is usually used in integrated circuits to put toggle memory elements in a known state. This signal is usually generated outside the circuit and is called the initialization signal. By default, the initialization signal loads 0 in all elements.

A first way to load the default configuration automatically is to modify this initialization signal so that it does not load only 0s in elements 501 for programming cells 500 of the CPS core, but 0's and 1's in accordance with the values of the default configuration file. The effect produced by the initialization signal is adapted at the time of writing of the HDL model of the CPS core. For that, after generation of the HDL model of the CPS core as well as its configuration file, the HDL model is retro-annotated in order to match each information of the default configuration file with a setting to 1 or a setting of 0. a memory point of the CPS heart when the initialization signal is applied.

 The initialization signal may be derived from the conventional initialization signal of a SoC, another signal or a combination between this initialization signal and another signal. Moreover, this technique of taking into account the default configuration at the level of the initialization signal advantageously allows a complete simulation of the operation of the SoC system from the HDL models of the CPS core and the other HDL models associated with the dedicated blocks and the hard blocks.

An alternative way of loading the default configuration of the CPS core automatically is to change the nature of the selected memory elements 501. In designing a SoC system according to the invention, standard cell libraries are used at the time of synthesis. These libraries allow the implementation of at least two types of memorizing elements. A first type of element is the latch D on state also called "latch" in English and a second type of element is the D flip-flop on front also called "flip-flop" flip-flop. A state D flip-flop takes up less space on a SoC than a front-end D flip-flop. The choice between these two types of memory elements is usually made at the time of writing the HDL model. After the synthesis, however, it remains possible to modify selected flip-flops for taking into account the values of the configuration file. The modification after synthesis consists of a replacement of flip-flops D with a forcing input at 0 RESET by a flip-flop D with a forcing input at 1 SET or the inverse according to the corresponding value of the configuration file, the signal of initialization being for example connected to this input. This modification can be implemented by manually updating or using a suitable software file "netlist pamper" generated from HDL models SoC. It remains possible to re-program the SoC using the conventional programming mode of a programmable circuit, that is to say by loading the bits of a configuration file 502 different from the default configuration file by the channel. of normal data 504 of the memory elements, for example by using the input D of a flip-flop D.

 One of the default configuration techniques can be applied to all or part of a CPS core. This advantageously allows the designer not to disclose the entire default configuration file.

Claims

Single-chip system (200, 408) characterized in that it comprises at least one CPS synthesizable programmable core (208, 209) and a dedicated block (201, 202, 203, 207), said CPS core and said dedicated block having were synthesized together from a model in HDL hardware description language of the dedicated block (201, 202, 203, 207) and from a model in hardware description language of an HDL model CPS core (306, 402) associated with a default configuration file (305, 401). A single chip system (200, 408) according to claim 1 wherein the HDL model (306) and the default configuration file (305) of the CPS core have been generated from an initial HDL template (307) corresponding to a non-programmable block, the HDL model of the CPS core (306) associated with its default configuration file (305) being functionally equivalent to the initial HDL model (307). Single-chip system (200, 408) according to one of claims 1 or 2 wherein the default configuration file is obtained by compiling (304) the result of the synthesis (303) of the initial HDL model (307), l architecture of the CPS core being taken into account (308) by the compilation (304). A single-chip system (200, 408) as claimed in any one of the preceding claims wherein the CPS core is synthesized using a standard cell library commonly used for synthesizing ASICs. A single-chip system (200, 408) according to any one of the preceding claims wherein memory elements (501) are used for programming the CPS core, an initialization signal putting said elements (501) in a known state, said initialization signal being adapted so that the states known memory elements (501) correspond to the values included in the default configuration file. A single-chip system (200, 408) according to claim 5 wherein the initialization signal is adapted by retro-annotation of the HDL model of the CPS core to match each information of the default configuration file to a setting of 1 or to a reset of a memory element. A single-chip system (200, 408) according to any one of the preceding claims wherein the memory elements (501) are flip-flops D. A single chip system (200, 408) according to claim 7 wherein the initialization signal is routed to the data inputs of the D flip-flops. A single-chip system (200, 408) according to claim 7 wherein the initialization signal is routed to the SET or RESET inputs of the D flip-flops. 10- Single-chip system (200, 408) according to one of claims 7 to 9 wherein the flip-flops D are selected with a forcing input at 0 (RESET) or with a forcing input at 1 (SET) so said latches are initialized by loading their associated values into the default configuration file (305). 1 1 - Single-chip system (200, 408) according to any one of the preceding claims wherein the CPS heart associated with its configuration file implements a memory controller. 12- A method of manufacturing a single-chip system according to any one of claims 1 to 1 1 comprising the following steps: generating (301) an HDL hardware description language model (306) of a CPS synthesizable programmable core to implement functions described using an initial HDL template (307);  generating (302) a default configuration file (305) of the CPS core (306) by synthesizing (303) and compiling (304) the initial HDL template (307);  synthesizing (404) the CPS core and the dedicated block using the same synthesis tool;  generating (405) a geometric file (406) from the result of the synthesis;  the font (407) of the single chip system using said geometric file (406). The method of claim 12 wherein the synthesis is performed using a standard cell library commonly used for synthesis of ASICs. 14- Method according to one of claims 12 or 13 wherein the HDL model (306) and the default configuration file (305) of the CPS core have been generated from an initial HDL model (307) corresponding to a non-programmable block such that the HDL model of the CPS core (306) associated with its default configuration file (305) is functionally equivalent to the initial HDL model (307).