WO2012122315A1

WO2012122315A1 - Microcontroller of a power adapter

Info

Publication number: WO2012122315A1
Application number: PCT/US2012/028141
Authority: WO
Inventors: Chia KO; Kevin D. Jones; Thomas Gill; Arian Jansen
Original assignee: Green Plug Inc
Current assignee: Green Plug Inc
Priority date: 2011-03-07
Filing date: 2012-03-07
Publication date: 2012-09-13
Anticipated expiration: 2013-09-07

Abstract

A microcontroller system comprising a multi-threaded processor, a memory sub-system connected with the processor, and one or more of a communication component, a clock/timer component, a fault component, a comparator component, an analog-to-digital converter (ADC) interfaced with the processor via a parallel data bus, a digital-to-analog converter (DAC), and/or a pulse-width modulation (PWM) component connected with the processor.

Description

Attorney Docket No.: 380533-995170

Microcontroller of a Power Adapter

CROSS REFERENCE TO PRIORITY

[0001] This PCT application claims priority to US Provisional application 61/450,077 filed March 7, 201 1.

TECHNICAL FIELD

[0002] The disclosed embodiments relate generally to power controls, power supplies, and to a medium for communication between two electronic systems; more particularly, to a power-efficient microcontroller.

BACKGROUND

[0003] From laptop computers and personal digital assistants to multimedia players and mobile phones, a wide variety of electronic devices require power from a power source, and rely on communication between two electronic systems to optimize their operation and collaboration. Conventional power adapters, that supply power to such devices, are typically limited in their operation, and often cannot accommodate different types of devices with varying power needs. In other words, it is a challenge to sustain the conversion efficiency and flexibility over a wide range of load conditions. For example, the pulse width modulation (PWM) output characteristics cannot be changed according to load conditions.

[0004] Furthermore, previous integrated digital power controllers have typically separated functionality, such as the loop regulation and system management functions, into different processing units. Thus, single thread cores were used to accommodate each separate functionality. Even if these functions are fully programmable, the development environment is cumbersome.

[0005] Therefore, there is a need for a controller in a power adapter with processing capabilities that can accommodate a wide range of load conditions and provide multi-thread processing.

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WEST\229565560.1 Attorney Docket No.: 380533-995170

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a better understanding of the aforementioned embodiments of the invention as well as additional embodiments thereof, reference should be made to the description of embodiments below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the figures.

[0007] FIG. 1 is a block diagram illustrating a power supply coupled to a power source and electronic devices in accordance with some embodiments.

[0008] FIG. 2 is a schematic illustrating a multi-port power supply coupled to devices in accordance with some embodiments.

[0009] FIG. 3 is a block diagram illustrating a microcontroller in accordance with some embodiments.

[0010] FIG. 4A is a block diagram illustrating portions of a power adapter in accordance with some embodiments.

[0011] FIG. 4B is a block diagram illustrating high and low voltage regions of a multiport power hub, according to some embodiments.

[0012] FIG. 5 is a schematic illustrating converter circuitry of a power adapter in accordance with some embodiments.

[0013] FIG. 6A is a signal diagram illustrating operation of pulse-width modulation

("PWM") synchronization of the PWM circuitry block of FIG. 3 in accordance with some embodiments.

[0014] FIG. 6B is another signal diagram illustrating operation of pulse-width modulation synchronization of the PWM circuitry block of FIG. 3 in accordance with some other embodiments.

[0015] FIG. 6C is another signal diagram illustrating operation of pulse-width modulation synchronization of the PWM circuitry block of FIG. 3 in accordance with some other embodiments.

[0016] FIGs. 7A-7C are signal diagrams illustrating a reset operation of the PWM circuitry block of FIG. 3 in accordance with some embodiments.

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[0017] FIGs. 8A-8B are signal diagrams illustrating a duty-cycle truncation operation of the PWM circuitry block of FIG. 3 in accordance with some embodiments.

[0018] FIGs. 9A-9B are signal diagrams illustrating a trigger hold-off operation of the

PWM circuitry block of FIG. 3 in accordance with some embodiments.

[0019] FIG. 10 is a signal diagram illustrating a PWM period capture operation of the

PWM circuitry block of FIG. 3 in accordance with some embodiments.

[0020] FIG. 1 1 is a block diagram illustrating a power supply coupled to a load device in accordance with some embodiments.

[0021] FIG. 12 is a flow diagram illustrating a process of supplying power by a power supply to a connected device in accordance with some embodiments.

[0022] FIG. 13 is a flow diagram illustrating a process of supplying power to a connected device in accordance with other embodiments.

[0023] FIG. 14 is a flow diagram illustrating a process of supplying power to a connected device in accordance with some other embodiments.

[0024] FIG. 15 is a screen shot of the graphical user interface (GUI) of a portable software tool Greenscape.

DETAILED DESCRIPTION

[0025] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a sufficient understanding of the subject matter presented herein. But it will be apparent to one of ordinary skill in the art that the subject matter may be practiced without these specific details. Moreover, the particular embodiments described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

[0026] FIG. 1 illustrates a power supply 106 coupled to a power source 108 and devices

102 (e.g. 102A, 102B) in accordance with some embodiments. The power supply 106 may be

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WEST\229565560.1 Attorney Docket No.: 380533-995170 electrically coupled to the power source 108, from which the power supply 106 receives electrical power to be supplied to devices 102. The power source may be a source of alternating current (AC) or direct current (DC) voltage. In some embodiments, the power source is a power outlet, such as a wall outlet. The power outlet may provide AC voltage, which is typically 1 10V in the United States and may be at other voltages outside the United States and/or depending upon local requirements. In some other embodiments, the power source is an outlet in an airplane armrest or in an automobile, such as a cigarette lighter socket, which provides 12V DC voltage. In further other embodiments, the power source is a motor, generator, battery, and so on that provides electricity. Depending on the particular embodiment, the power supply 106 may be configured for coupling to only a DC power source, only an AC power source, or either a DC or AC power source. The power supply 106 may be coupled to the power source 108 via a power cord, cable, or the like.

[0027] The power supply 106 may be electrically coupled to one or more devices 102.

The devices 102 may include any of a variety of electronic devices, including but not limited to consumer electronic devices, computer devices and peripherals (e.g., desktop computers, laptop computers, printers, scanners, monitors, laptop docking stations, and so on), portable hand-held devices (e.g., video players, still image players, game players, other portable media players, music recorders, video recorders, cameras, other media recorders, radios, medical equipment, calculators, cellular telephones, smart phones, other wireless communication devices, personal digital assistants, programmable remote controls, pagers and so on), small appliances, battery chargers, and power tools. Depending on the particular embodiment, if there are multiple devices 102 coupled to the power supply 106, the devices 102 may be coupled to the power supply 106 independently or in series or in parallel.

[0028] In some embodiments, the power supply 106 is a standalone unit, external to and distinct from devices to be powered by the power supply 106. The external power supply 106 may be electrically coupled to one or more devices via a power connection 1 10 (e.g., power cords, cables, induction, or other known ways of transmitting power). In some embodiments, both the power supply 106 and a device 102 A conform to a common connector or interface standard; the power connection 1 10 coupling the power supply 106 to a given device, such as the device 102A, includes standardized connectors on one or both ends of the connection, and may, in some embodiments, be non-detachably affixed to the power supply 106. Device 102A may be

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WEST\229565560.1 Attorney Docket No.: 380533-995170 designed to use the standardized connector and be coupled to the power supply 106 via the power connection 1 10. In other words, the power supply 106 serves as a universal power supply to any device that is designed to include the standardized connector.

[0029] In some embodiments, the power connection 1 10 may be a cable cord or harness that comprises a set of power lines and a single data communication wire. The single data communication wire may be capable of multiple functions, including the ability to provide bias power to drive a load processor (not shown) for communicating power requirements at initial power up to then enable full communication and full power to the respectively connected device. The small bias power activates the load processor without having to wait for power to the rest of the device 102. In some embodiments, the power supply 106 may detect connection and disconnection of devices 102 over the single data communication wire in the power connection 1 10 without waiting for the device 102 itself to power up or power down, or without waiting for some power up/down signal from the device 102. Instead of using a bulky multi-wire bundle to achieve multiple power functions, a thinner cable having a single communication line may be used as the power connection 1 10. The thinner cable allows for multiple power saving functions with only a single data communication line and a single set of power lines, embodiments of which will be further described in sections below. A multi-functional single data communication line in a thinner cord provides cost-saving benefits, is smaller and more convenient to the user, and allows for respective connectors to be as small as possible, with less wiring, less pins, a smaller size.

[0030] In some other embodiments, the power supply 106 and a device 102B uses different types of power connectors (not shown). For example, a device that is not designed to use the standardized connector (e.g., an older device) may have a power connector that is device or manufacturer specific and not conforming to the standard that is used by the power supply 106. In such embodiments, the power supply 106 may be coupled directly to the device 102B via a cord (not shown) that includes the standardized connector on one end and a device or manufacturer specific connector on the other end. In other words, the cord is customized to the connector on the device 102B because at least one connector on the cord is device or manufacturer specific. The cord may be a multi-functional harness or cord, as will be further described in later sections. Alternatively, an attachment, such as a dongle, may be coupled to the device 102B. The attachment "converts" the connector on the device 102B to the standardized

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WEST\229565560.1 Attorney Docket No.: 380533-995170 connector utilized by the power supply 106, thereby allowing coupling of the power supply 106 and the device 102B via a cord having the standardized connector on both ends. An example of such a connector converter 104 is shown in FIG. 1.

[0031] In some other embodiments, the power supply 106 may be integrated with the device 102 to be powered by the power supply 106. For example, the power supply 106 may be the internal power supply of a desktop computer, an audio/visual receiver or preamplifier, a power strip or surge protector, an uninterruptible power supply, or something similar. Furthermore, in some embodiments, other external devices may be electrically coupled to the power supply 106 that is integrated into another device. For example, returning to the example of the power supply 106 integrated with a desktop computer, other external devices may be coupled to the power supply that is integrated with the desktop computer. Other external devices may include, but is not limited to, computer devices and peripherals (e.g., laptop computers, printers, scanners, monitors, laptop docking stations, and so on), portable hand-held devices coupled to the desktop computer (e.g., video players, still image players, game players, other portable media players, music recorders, video recorders, cameras, other media recorders, radios, medical equipment, calculators, cellular telephones, smart phones, other wireless communication devices, personal digital assistants, programmable remote controls, pagers and so on), and battery chargers. The integrated power supply may supply power to the desktop computers as well as to the external devices coupled to the desktop computer. The integrated power supply may be coupled to the external devices via a thin one-wire cable enhanced with power-saving features as will be further described below.

[0032] The power supply 106 may come in a variety of sizes. For example, the power supply 106 may be implemented in a relatively small size for ease of portability and travel convenience. The power supply 106 may also be implemented as a relatively larger power supply size for home, office, or industrial use.

[0033] As described above, devices 102 that may be electrically coupled to the power supply 106 may encompass a variety of electronic devices, including but not limited to consumer electronic devices (e.g., mobile phones, cordless phones, smart phones, other wireless communication devices, baby monitors, televisions, digital cameras, camcorders, MP3 or video players, game players, CD or DVD players, VCRs, personal digital assistants (PDAs), other

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WEST\229565560.1 Attorney Docket No.: 380533-995170 media players, music recorders, video recorders, other media recorders, radios, medical equipment, calculators, programmable remote controls, pagers, and other portable handheld devices), computer devices (e.g., computers, network routers, non-volatile storage, printers, monitors, scanners), small appliances, battery chargers, and power tools. Some of these devices may include a battery or batteries and some may not. The battery (or batteries) may be rechargeable or non-rechargeable. Examples of rechargeable battery technologies include lithium-ion batteries, nickel cadmium batteries, and nickel metal hydride batteries. Examples of non-rechargeable battery technologies include alkaline and lithium batteries. For a device that does not have a battery or that has non-rechargeable batteries, the power supplied by the power supply 106 merely powers the device for operation. For a device that has a rechargeable battery, the power supplied by the power supply 106 powers the device for operation and/or recharges the battery. As it is known in the art, different devices and batteries have different power requirements for operation and/or battery charging. Thus, the power supply 106 needs to know the power requirements of the devices 102, in order to supply the proper amount of power.

[0034] FIG. 2 illustrates a multi-port power supply 220 coupled to devices 202 in accordance with some embodiments. Power supply 220 includes an input for receiving power from a power source 218. Power supply 220 has multiple output ports 206 (e.g., 206A, 206B, and 206C). Output ports 206 can be ports to accommodate any combination of connectors 207 (e.g., 207 Ά, 207B, and 207C), including but not limited to any combination of plugs, receptacles, sockets, magnetic power connectors, non-detachable cables, and so on. In one embodiment, the output ports 206 include a receptacle for receiving multi-purpose power connectors 207. In another embodiment, one or more cables 214 are non-detachably fixed to one or more output ports 206. Power supply 220 may also include a user interface for interaction with a user. In some embodiments, the user interface comprises a status light 222 (e.g., 222A, 222B, and 222C) associated with each output port 206 that may indicate whether a device 202 is being powered, whether the device 202 is being provided reduced power, or other statuses of power supply 220 or devices 202 connected to the power supply 220. Status lights 222 can indicate one or more statuses by blinking, changing colors, or the like. The user interface of power supply 220 may also include display 224, which may be an LCD screen, an LED, or an OLED display for displaying information to a user. In some embodiments, status information can be displayed on display 224 in addition to or in place of status lights 222. For example, the background color of

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WEST\229565560.1 Attorney Docket No.: 380533-995170 display 224 could change colors or blink based on the status of the devices 202 or the power supply 220. In other embodiments, where device 202 includes a display (not shown), power supply 220 may instruct device 202 to display certain information on the display of device 202. The display of device 202 may be an LCD screen, an LED, or an OLED display.

[0035] Furthermore, additional information about power supply 220 may be displayed on display 224. The user interface of power supply 220 may also include one or more input components so that a user can interact with power supply 220. Examples of one or more input components include buttons 226 (e.g., 226A and 226B). Buttons 226 may be used in connection with display 224 to allow a user to access information about power supply 220, any of the attached devices 202, and/or to program or otherwise interact with power supply 220. For example, display 224 may provide information about the operating mode or charge mode of power supply 220, current load and capacity information of output ports 206 and/or of power supply 220, the current time, and so on. Display 224 may also show information about the devices 202 currently and or previously connected to power supply 220 such as, device identification information, device power requirements, device battery identification information, device battery condition information, and so on. When a battery in device 202 is being charged, display 224 may indicate the amount of time left until the battery is fully charged.

[0036] Buttons 226 may also be used to set the operating mode or the charge mode of power supply 220. As shown by buttons 226, it is contemplated that multiple buttons or other control interfaces could be used, for example, to allow a user to more easily interact with power supply 220 or to provide access to more features or information. For example, the user interface of power supply 220 may include multiple control menus each with one or more control functions. In some embodiments, other input components are used in place of or in conjunction with buttons 226. For example, display 224 could be a touch screen and thus allow input from a user. Other forms of input components include but are not limited to a scroll wheel, dial, knob, joystick, trackball, and 5-way switch.

[0037] In some embodiments, devices 202 may use standardized connector 207A to be coupled to the power supply 220 via cable 214 having the standardized connectors 207A. By using standardized connectors 207 A, the power supply 220 can serve as a universal power supply 220 to any device that is designed to include a standardized plug, receptacle or other such

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WEST\229565560.1 Attorney Docket No.: 380533-995170 connectors. Standardized connector 207 A may be any one of, but is not limited to, plugs, receptacles, sockets, magnetic power connectors, non-detachable cables, other universal connectors, and so on. In other embodiments, the power supply 220 and devices 202 may use different types of power connectors. For example, devices 202 that are not designed to use the standard connector 207A may have a device- or manufacture-specific connector that connects to a device- or manufacture-specific power port 208B. The device- or manufacture-specific connector/port may not conform to the standard that is used by the power supply 220. In other embodiments, the device 202B may be connected to the power supply 220 via a bus adapter 212 to convert the connector at port 208B on the device 202B to the standardized connector 207B utilized by the power supply 220. On one end, the bus adapter 212 is coupled to the device 202B by a power cord 216. The power cord 216 may be directly coupled to the device 202B or may include device- or manufacture-specific connectors to connect to the device 202B at the power port 208B. On the other end, the bus adapter 212 is coupled to the power supply 220 by cable 214 having connectors 207B, 209 that conform to the standard used by the power supply 220. In other words, the bus adapter 212 may contain both standard connectors and device-specific connectors, thereby allowing the power supply 220 and the device 202B to be connected by one or more cables 214, 216.

[0038] In some embodiments, the device- or manufacture-specific connector/port may be for a legacy device 202C with a legacy port 208C. The legacy port 208C may receive a legacy connector (not shown) to connect to the power supply 220 via cable 214 having a connector 207C on the other end that is different from the legacy connector. In other embodiments, the legacy device 202C may be connected to the power supply 220 via a legacy adapter 210 to convert the connector on the legacy device 202C to the standardized connector utilized by the power supply 220. Similar to the bus adapter 212, the legacy adapter 210 may use a combination of standard and device-specific connectors to connect the legacy device 202C to the power supply 220 via cables 214, 216.

[0039] FIG. 3 is a block diagram illustrating a microcontroller 300 in accordance with some embodiments. The microcontroller 300 may be an integrated mixed signal system-on-chip device for providing control requirements of a power conversion system, such as a power adapter. The microcontroller 300 comprises a core processor 302 and memory sub-system 318 that services and communicates with a number of subcomponents. All control algorithms and

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WEST\229565560.1 Attorney Docket No.: 380533-995170 threshold behavior controls are performed in software on the core processor ("CPU") 302. The CPU 302 may be a hardware multi-threaded CPU, which is unlike conventional power-supply controller chips that consist of a single CPU with a single hardware thread. For example, a dual- threaded processor allows at least one of the threads to be dedicated to running time critical calculation without the use of interrupt service routines, eliminating any latency associated with interrupts and saving contexts. The hardware multi-threading may utilize zero-latency thread switching which ensures all control loop operations to be executed within predetermined time/cycle constraints required for real-time control. Simultaneous execution of multiple control loops, such as voltage regulation and DCM Power Factor Correction ("PFC") is possible along with adaptive over-voltage/current protection and "housekeeping" functions.

[0040] The microcontroller 300 includes a multi-channel (multiple input) analog-to- digital converter ("ADC") 306. In one example, the ADC 306 is a multi-bit pipeline converter with a multi-channel input MUX. The ADC 306 may include one or more track-and-hold circuits to allow simultaneous sampling of multiple channels of the ADC 306. Sampling can be initiated either by software, or by a trigger from a PWM 304, comparator-DAC 308, 312, or fault input 320 blocks. In any mode, each channel may be capable of generating its own interrupt, has its own buffer(s) for storing results from a conversion, and may elect to send its conversion results directly to an ADC port (not shown) on the processor core 302.

[0041] In operation, the ADC 306 may have a parallel data bus 307 designed to interface with the multi-threaded processor 302, with the aim to reduce data processing latency compared to currently existing digital power-supply controller chips. The ADC data bus 307 can be accessed by either hardware thread through a parallel ADC data port (not shown) of the ADC 306 and connected to the data bus 307. The ADC 306 may also include an ADC controller 303 configured to determine which of the ADC input channels will automatically send its analog-to- digital conversion result through the data bus 307 as soon as a conversion completes. The software of the CPU 302 retrieves each conversion result by reading the ADC data port connected to the data bus. The read returns only if new data (ADC conversion result) is available to be fetched at the port. Thus, if one of the CPU's 302 hardware threads is dedicated to reading and processing ADC conversion results, software execution is halted on the thread that attempted to read the port if there is no new data arriving at the port. As soon as a piece of data arrives at the port, software execution immediately resumes. This means there is zero

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WEST\229565560.1 Attorney Docket No.: 380533-995170 overhead in saving contexts, unlike in existing digital power-supply-controller chips where time- critical events are made known to the CPU via the use of interrupts. Furthermore, though the software execution on this hardware thread is stalled while waiting for data, the other hardware thread continues to run and execute on-going procedures such as house-keeping tasks. The two- threaded architecture is similar to having two processors. It eliminates interference between the on-going background/house-keeping tasks, and intermittent, high frequency real-time critical handlers. The use of interrupts for time-critical handlers can be completely eliminated due to the availability of separate hardware threads.

[0042] In the case where multiple ADC channels, each used for feedback for a different controlled output, all send their data through the same data bus 307 to the same port, and each output is controlled by a different control algorithm - software branching to the appropriate control algorithm location is necessary depending on which ADC channel the incoming data belongs to. Software branching is an overhead that adds to the ADC data processing latency. To eliminate this overhead, the branching can be performed while the ADC conversion is taking place. The ADC controller 303 may be designed such that as soon as a sample (e.g., a snap shot) is taken on an input ADC channel of interest, a user-pre-configured memory address corresponding to the location of the software algorithm (that is to process the conversion result from the channel of interest) is delivered through the data bus to the port. The software branching may take place as soon as this memory address data is read through the port, and the next read on the port will return with the actual ADC conversion result of the channel of interest. Since the CPU's program counter is already in the right location, processing can immediately begin. In other words, the time that the ADC 306 takes to perform a conversion on a sample is fully taken advantage of to do something useful - eliminating software overhead such as branching thus reducing data processing latency. This is another improvement over existing digital-power-supply-controller chips, where the ADC's 306 sample conversion time is fully added to the data processing latency.

[0043] The gains of using a microprocessor for controlling a power supply come at a cost of overhead power necessary for running time-critical calculations. This overhead usually deducts an insignificant percentage of efficiency from a power supply operating in nominal load conditions. However, when the power-supply is operating in low load or no-load conditions, such as burst-mode operation, the overhead can become significant. Minimizing this overhead to

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WEST\229565560.1 Attorney Docket No.: 380533-995170 compete with existing analog- control solutions while retaining microprocessor-based control is a major challenge for digital power-supply controllers. As the control algorithm is generally simpler during low- or no- load conditions, this requirement is met with the addition of a logic block or coprocessor which takes control when the power-supply enters low-load or no-load conditions. This allows the microprocessor to be disabled or put into the lowest power- consumption mode possible. Depending upon the application, the logic block/coprocessor can be designed to run a standalone operation, or act as an interim processor performing functions such as accepting data from the ADC, making a fixed set of calculations and updating the PWM block registers, either continuously or intermittently based on timeouts from an on-chip timer.

[0044] The ADC controller 303 may be user-configured to append additional information to the data delivered through the custom bus and port interface, such as ADC channel number, ADC overflow status, application-specific tags, and so on. The parallel data bus 307 and port interface may be sufficiently wide enough to include these additional information in a single read.

[0045] In some embodiments, the ADC 306 may be configured to support a number of different operational modes.

[0046] Single-Channel Burst Mode: Any one of the channels may be selected for conversion. The sample-hold circuit samples the selected channel for the number of times per burst as specified by the user.

[0047] Dual-Channel Burst Mode: A pair of ADC channels are sampled simultaneously by the corresponding sample-hold circuit. The sample-convert functions of both channels are interleaved if necessary and sampling is performed for the number of times per burst as specified by the user, per channel.

[0048] Continuous single-or Dual-Channel Sampling: This mode operates the same way as Single/Dual Channel burst mode, except the ADC samples and converts indefinitely. The channel(s) sampled can be changed on the fly with software writes or triggers from on-chip peripherals.

[0049] Continuous Multi-Channel Sampling: The user-selected ADC channels are sampled and converted in a round-robin fashion.

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[0050] A hardware-averaging and / or hardware summing feature is available for a user- selectable number of consecutive samples.

[0051] The microcontroller 300 includes a PWM module 304 which provides pulsed power signals configured to support a number of operating modes. In some embodiments, the PWM module 304 may be configured to operate independently, where each output waveform is configured independently. In some embodiments, the PWM module 304 may be configured to operate in complementary mode. In this mode, two output waveforms are complements of each other with the option of enforceable dead-times. In other embodiments, the PWM module 304 may be configured to operate in 180° synchronization. In this mode, two outputs with independent and varying periods and duty-cycles may be aligned 180 degrees out-of-phase.

[0052] The microcontroller 300 includes a number of internally generated asynchronous digital fault inputs by the fault block 320, which can be used in conjunction with any of the analog comparator inputs. These can be used to trigger processor 302 interrupts, PWM events and ADC conversions. The analog inputs feed into comparators 312, which may use programmable references controlled by a digital-to-analog converter (DAC) 308. The DAC and fault inputs may be controlled by various settings in the comparator/DAC block 308, 312. The software utilized by the microcontroller 300 may include configurable digital input/output capability to allow for various fault trigger input and general-purpose bi-directional interface combinations.

[0053] Configurations of the microcontroller 300 also includes clock/timer block 314 for providing clock signals and/or timers to various parts of the microcontroller 300 and peripheral components. The clock signal may be generated, for example, by an on-chip oscillator and PLL fed from an external crystal oscillator (not shown). All system blocks may have a gated clock feed and/or clock dividers. Clock deleters may be used for finer clock control. The clock/timer block 314 may also regulate internal clocks of the CPU 302 for processing tasks.

[0054] A separate peripheral timer may be used for scheduling interrupt driven events, such as for monitoring power signals of the CPUT 302, which may or may not use a separately derived clock. For example, a kick timer 316 may be utilized in a sense detection mechanism of the microcontroller 300 in a power adapter to detect the connection status of a load device.

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[0055] A communication block 310 of the microcontroller 300 operate as a communication channel to various parts of the microcontroller that provides control for establishing bi-directional communication between the CPU 302 and the load device (not shown).

[0056] FIG. 4A is a block diagram illustrating portions of a power adapter 400 in accordance with some embodiments. The power adapter 400 includes a microcontroller block 402, an auxiliary power supply 404, a rectifier circuit 410, a power factor correction block 412, a down converter 414, a communication link 416, and a connector 420. The microcontroller block 402 includes similar features as the microcontroller 300 of FIG. 3. A single controller, such as microcontroller block 402, may be utilized to control two converters, PFC 412 and down converter 414, and subsequently have the capability of tuning conversion control algorithms with respect to each other. The PFC 412 and main conversion 414 loops may effectively play off against each other such that dynamic adjustments may be made on both rather than on each independently. Similarly, a single algorithm may optimize the effect of both conversion loops.

[0057] The auxiliary power supply 404 provides power for the microcontroller 402 and may generate a stable Vref for the main output voltage sensing circuit (not shown).

[0058] The rectifier circuit 410 is configured to receive an AC input signal from an AC power source and rectifies the AC input to a DC output. The DC output is provided to the PFC block 412, which in turn is provided to the remaining power adapter system. The rectifier circuit 410 may be implemented in any number of ways.

[0059] The PFC block 412 provides an interface between AC power and the power conversion to DC power. The PFC block 412 is under software control of the microcontroller 402 and corrective control is applied from the PWM module 304, for example, via a high voltage drive circuit (not shown).

[0060] The down converter circuit 414 provides the main DC output of a power conversion. The main DC output may be sensed via an isolating transformer. The CPU 302 also monitors the down converter circuit 414 and makes corrective adjustments via software control.

[0061] The communication link 416 provides serial communication to a load device (not shown) connected via connector 420. The connector 420 terminates within the load device and

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WEST\229565560.1 Attorney Docket No.: 380533-995170 communication is established with the communication block 310 via the communication link 416. The communication link 416 may include a connection detect circuit, necessary isolation, and protection circuitry.

[0062] In some embodiments, the power adapter 400 may include a load detection sensing feature, which is a digital input that works with the Kick Timer 316 of FIG. 300 for the purpose of detecting the presence of a load (to the power supply in which the CPU 302 resides). The kick timer 316 monitors changes in the auxiliary power supply 404, by monitoring pulse signals to detect the presence or absence of a load device. If a load device is attached, the kick timer 316 recognizes the load by detecting a reflection in the pulse signal. This feature utilizes existing components, the kick timer 316 and auxiliary power supply 404, that are in use for other functions to provide an additional feature of a load device sensing mechanism.

[0063] The kick-timer 316 increments at a fixed interval and can be configured to timeout by a predetermined time. To prevent it from timing out, it must receive a kick in the form of a pulse (could be active low or active high).

[0064] FIG. 4B is a block diagram illustrating high and low voltage regions of a multiport power hub, according to some embodiments. A microcontroller 450 on the primary side of a high-voltage isolation barrier manages AC/DC conversions, and includes a power factor correction module 454, and power converter 456. The output can be variable for a single-port power supply, or fixed to serve as the input source for additional DC/DC converters 458. For a multi-port power hub, each additional microcontroller 452 on a secondary side of the high- voltage isolation barrier manages multiple variable power supplies at each respective connector port 462, and each with dedicated communication channels 460. Isolated communication is established between the primary-side microcontroller 450 and each secondary-side microcontroller 452.

[0065] The microcontroller 450 and 452 each includes communication interfaces which, when each coupled with the appropriate physical medium, form bi-directional communication links between: the microcontroller 450 and each microcontroller 452, the microcontroller 452 and each load (client) device, and/or the microcontrollers 450 and each load (client) device (not shown). FIG. 4B shows the use of the Greenwire Communication Interface (GO) on microcontrollers 450 and 452. When used for communication between the microcontrollers 450

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WEST\229565560.1 Attorney Docket No.: 380533-995170 and 452, or between 450 and each load device (not shown), the physical signaling of the GCI enables the use of low-cost, high-voltage-barrier bridging physical medium such as a single small transformer. When used for communication between the microcontroller 450 and each load device, or between 452 and each load device, the GCI couples to Greenwire, a single-wire, bi-directional, half-duplex physical medium, to form each communication link.

[0066] FIG. 5 illustrates one application of the microcontroller 300 of FIG. 3 in a power- factor correction 500, in accordance with some embodiments. The conversion circuitry 500 includes a rectifier bridge 502 to rectify an AC input signal and convert it to a DC output. A microprocessor 504 controls the PWM signal blocks 506, comparator block 508, and ADC block 550, thereby regulating the operations of the conversion circuitry 500. The conversion circuitry 500 includes components (resistors, capacitors, diodes, transformers, MOSFETs, opto-electrical devices, and so on) configured to form a feedback loop where voltage and/or current signals are supplied to ADC block 550 and/or comparator block 508, and drive signals are received from PWM blocks 506 to generate a voltage output Vout. Also, as described above, because Figure 5 illustrates various blocks of FIG. 3, 504, 506, 508, and 550 are part of the microcontroller.

[0067] The PWM signal blocks 506a, 506b provide pulsed signals, singularly or in pairs, and are controlled by the microprocessor 504 utilizing an algorithm to provide several operational modes for generating a desired voltage output. The PWM signal blocks 506a, 506b provide two PWM outputs with independently varying frequency (or period) or synchronization. It will be appreciated that the two PWM signal blocks 506a, 506b are mere illustrations and that more than two PWM signal blocks may be controlled by the microprocessor 504 or utilized by the conversion circuitry 500.

[0068] FIG. 6A is a signal diagram illustrating operation of synchronization of the PWM circuitry block 304 of FIG. 3 in accordance with some embodiments. The synchronization feature automatically synchronizes two PWM outputs (each having cycle-by- cycle varying periods due to a PWM Reset operation) such that they are 180° out-of-phase with each other. To achieve this with the greatest efficiency, the microprocessor 504 employs two digital, concurrent but independent processes. The first process synchronizes the two PWM outputs as illustrated in the signal diagram of FIG. 6A. Following a pulse on one PWM output, the pulse on the alternate PWM output will begin after the latest calculated minimum offset has elapsed and at least the

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WEST\229565560.1 Attorney Docket No.: 380533-995170 natural period since the last pulse on this output has expired. The natural period is defined as the PWM period that would have resulted from the PWM Reset operation if there is no minimum offset taking effect. The natural period is also called the captured period.

[0069] The minimum offset from a pulse on one PWM output to the next pulse on the alternate PWM output is calculated as half of the previous captured/natural period length on the PWM output that generated the most recent pulse.

[0070] The PWM pulses are also forced to strictly alternate between the two PWM outputs, even if two PWM resets occur on one PWM output before the next pulse on the other output.

[0071] The two PWM outputs can be enabled at the same time or one after another.

[0072] 1) If enabled one after another:

[0073] a. If at least one natural period on the first enabled output has elapsed before the second output is enabled, there is a known minimum offset to apply between the latest pulse of the first enabled output and the first pulse of the later enabled output.

[0074] b. Otherwise, an initial-offset can be configured via the appropriate control register which would force the first pulse on the later enabled output to occur no earlier than initial- offset from the assertion of the first pulse on the first-enabled output. The second pulse on the first enabled output is allowed to occur no earlier than two times the initial-offset, regardless of what first natural period of the first enabled output is.

[0075] If the initial offset is configured as zero then the first pulse on the later enabled

PWM output can assert anywhere within the first natural period of the first enabled output.

[0076] 2) If the two PWM outputs are enabled simultaneously as shown at t=0:

[0077] a. If initial-offset is not zero, the first pulse of one of the outputs (PWM1) will be delayed by initial offset, and the second pulse on the output whose first pulse is not delayed (PWMO) is allowed to occur no earlier than two times the initial-offset, regardless of what its first natural period is.

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WEST\229565560.1 Attorney Docket No.: 380533-995170

[0078] b. If initial-offset is zero, then the first pulses of both PWM outputs will begin simultaneously but the second pulse of one output will not be allowed to occur until one natural period of the other output has elapsed, which then provides a known minimum offset.

[0079] If the configured initial-offset is greater than the first natural period of the PWM output whose first pulse is not offset, half of this natural period is used as the offset for the first pulse of the other PWM output and the initial-offset is ignored.

[0080] Thus, the calculation of minimum offset is derived from the single most recent captured/natural period. The option also exists to allow the minimum offset calculation to be based on averaging multiple most recent captured/natural periods of both PWM outputs. This is called Capture Averaging.

[0081] FIG. 6B is another signal diagram illustrating operation of pulse-width modulation synchronization of the PWM circuitry block 304 of FIG. 3 in accordance with some other embodiments. FIG. 6B illustrates Pulse- Width Compensation. Pulse-width compensation increments or decrements the pulse-width of one PWM output based on a comparison between the latest period-captures (or capture averages if the averaging feature is enabled) for each PWM output. The pulse-width changes in the direction to balance the natural periods of the two PWM outputs, assuming that the greater the pulse-width, the longer the resulting natural period. The pulse-width of the compensating PWM output (PWMl) increases if the captured/natural period of the compensating PWM output is shorter than the other output (PWM0), and decreases if the captured/natural period of the compensating PWM output is longer than the other output. The step size of n is configurable via control registers. Only the last single captured/natural periods from the two PWM output are compared, but again, capture-averaging can be used such that the comparison is made based on a running average of multiple most recent natural periods on the two PWM outputs.

[0082] FIG. 6C is another signal diagram illustrating operation of pulse-width modulation synchronization of the PWM circuitry block of FIG. 3 in accordance with some other embodiments. In practice the synchronization operation makes up for differences in hardware circuitry and/or tolerances in electric components external to the CPU 302 being driven by the two synchronized PWM outputs. Due to these differences and/or tolerances, the same pulse-

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WEST\229565560.1 Attorney Docket No.: 380533-995170 width on both PWM outputs may end up with different natural periods. FIG. 6C illustrates the Carry-Over of the Amount of Compensation:

[0083] The primary adjustment to the pulse-widths of both PWM outputs comes from a digital feed-back control loop, which calculates and determines a new PWM pulse-width update at fixed/variable intervals. This means the pulse-width of the PWM outputs can vary significantly from interval to interval. However, the amount of pulse-width compensation, once determined, in general does not vary much. For this reason when a primary adjustment occurs, the currently used compensation amount is automatically added to the compensating PWM output. In FIG. 6C, the primary adjustment is shown as a software write to a pulse-width control register, though this could also have been implemented in digital circuitry.

[0084] It will be appreciated that the 180° Synchronization mode can be used on two pairs of Complementary PWM outputs, instead of 2 single PWMs as previously described.

[0085] FIGs. 7A-7C are signal diagrams illustrating a reset operation of the PWM circuitry block of FIG. 3 in accordance with some embodiments. First, it will be appreciated that on the CPU 302, by configuring appropriate registers, (e.g., 1 of 16 trigger sources such as 8 on- chip analog comparator outputs and 8 Fault digital inputs) may be selected for the operations of PWM Reset, Duty-Cycle Truncation, and PWM Override operation. A trigger ends the current PWM cycle and begins a new PWM cycle immediately.

[0086] As shown in FIG. 7A, when PWM Reset mode is operating, the actual period of the resulting PWM output is influenced by the incoming trigger and not merely by software writes to a base-period register that controls the PWM output. The actual period of the PWM output will match the setting in the base-period register only if no trigger comes in for a duration greater or equal to the configured base-period. On the PWM output, the period between two PWM resets (indicated by the vertical arrows) is referred to as the natural period of the PWM output.

[0087] Additional configuration of the appropriate control register causes the insertion of a delay between the trigger pulse and the actual resetting of the PWM, as shown in FIG. 7B. For the PWM Reset mode, the trigger is not level sensitive. Only the active-going edge causes a reset (after a reset delay, if that is non-zero). An interrupt (if enabled by register configuration) is generated when a PWM Reset occurs.

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WEST\229565560.1 Attorney Docket No.: 380533-995170

[0088] In some embodiments, the PWM Reset mode can be used on Complementary

PWM outputs as well, and it would operate as shown in FIG. 7C, which shows a pair of complementary PWMs instead of a single PWMn signal.

[0089] FIGs. 8A-8B are signal diagrams illustrating a duty-cycle truncation operation of the PWM circuitry block 304 of FIG. 3 in accordance with some embodiments. A trigger truncates a PWM output pulse for the current PWM period, as shown in FIG. 8A. With Complementary Output PWM pairs, as shown in FIG. 8B, the enforcement of Dead-Time can be configured.

[0090] In both FIGs. 8A and 8B, the Duty-Cycle Truncation trigger is level sensitive. If this trigger becomes active and remains active past a Trigger Hold-Off period (described in a following section), it takes effect once the hold-off period ends.

[0091] A Duty-Cycle Truncation operation is effective for at least one PWM cycle no matter how narrow the trigger pulse is, as long as the trigger pulse passes through filters internal and external to the GPP.

[0092] Unlike the PWM Reset mode, a duty-cycle truncation does not change the PWM base period. An interrupt (if enabled by register configuration) is generated when a duty-cycle truncation occurs.

[0093] The Duty-cycle Truncation mode can run in parallel with the PWM Reset mode.

In practice this is often done to provide cycle-by-cycle limitation to the electric-currents flowing through the hardware circuitry external to the CPU 302. Any duty-cycle truncation that occurs may have an effect on the natural period of the PWM output whose pulse was truncated, but the processes described in the above sections keep the two PWM outputs 180° out-of-phase with each other.

[0094] FIGs. 9A-9B are signal diagrams illustrating a trigger hold-off operation of the

PWM circuitry block 304 of FIG. 3 in accordance with some embodiments. By configuring appropriate control registers, a "blanking" period within a PWM period can be set up such that any trigger pulse that is selected to cause a PWM Reset or Duty-Cycle Truncation is ignored. Two blanking periods can be set-up within a PWM period: one starting with the asserting edge of the PWM pulse and the other starting with the de-asserting edge of the PWM pulse. This

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WEST\229565560.1 Attorney Docket No.: 380533-995170 operation is illustrated in two examples shown as FIG. 9A, illustrating the effect of trigger hold- off in duty cycle truncation, and 9B, illustrating the effect of trigger hold-off in a PWM reset.

[0095] The Trigger-Hold-Off feature is necessary to the PWM Reset Mode because it can be used to limit the lowest natural period allowed on the PWM output. This is important to many end applications of the PWM Reset mode.

[0096] A trigger pulse for PWM Reset mode is edge sensitive. If a trigger pulse asserts during a trigger hold-off period and remains asserted at the end of the trigger hold-off period, a reset does not occur. The PWM reset only occurs if the trigger pulse asserts outside of the trigger hold-off period.

[0097] FIG. 10 is a signal diagram illustrating a PWM period capture operation of the

PWM circuitry block 304 of FIG. 3 in accordance with some embodiments. The period capture operation, shown in FIG. 10, captures and stores, i.e. records, the length (i.e. time duration) of the last PWM period, or natural period as described in the PWM Reset section above, at the instant that a PWM reset occurs. If no PWM Reset trigger pulse comes in for an entire base- period, the base-period is captured or considered as the natural period.

[0098] FIG. 1 1 is a block diagram illustrating a power supply 1 101 coupled to a load device 1 103 (client device) in accordance with some embodiments. The power supply 1 101 includes an AC/DC converter 1 106 for receiving a voltage from a power source, such as an AC source 1 102 and converting the AC voltage to DC voltage for use by devices coupled to ports 1 1 14A-N, such as a device that includes client device 1 103. The power supply 1 101 also includes DC/DC converters 1 108A-N for each respective port 1 1 14 to service a correspondingly connected device such as client device 1 103. The DC/DC converter 1 108 supplies voltage to respectively connected devices such as client device 1 103 on power line 1 1 16. In some embodiments, the DC/DC converter 1 108 may supply different voltages from device to device or make adjustments to provide varying voltages to the same device depending on power requirements or changes to the power requirements. In some embodiments, the DC/DC converter 1 108 may provide a legacy fixed voltage to supply a fixed voltage to client device 1 103 when the client device 1 103 is a legacy device.

[0099] In some embodiments the AC/DC converter is connected to the DC/DC converters 1 108A-N via power conductor 1 1 17. In some embodiments, switches 1 150A-N are

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WEST\229565560.1 Attorney Docket No.: 380533-995170 coupled to the AC/DC converter 1 106 and respective power line 1 1 16 at each port 1 1 14A-N. Switches 1 150A-N allow for power signals to bypass the DC/DC converter 1 108 depending on the power needs of the connected client device 1 103. When the client device 1 103 is a high- power system, power from the AC/DC converter 1 106 is directly utilized by enabling the respective switch 1 150 and disabling the respective DC/DC converter 1 108 to output the higher power of the AC/DC converter 1 106 for the client device 1 103. When the client device 1 103 is a low-power system, the respective switch 1 150 is disabled and the respective DC/DC converter 1 108 is enabled for the normal operation of the DC/DC converter 1 108 converting a high DC power to a low DC power to service the lower powered client device 1 103. Thus, each of the ports 1 1 14A-N is enabled to service either a high or low power system. Separating the high- power pathway and the low-power pathway by a simple switch reduces power dissipation and allows for simplified circuitry, resulting in an overall low-cost, smaller-sized power supply 1 101.

[00100] In some embodiments, the power supply 1 101 includes a controller 1 104 for programming and regulating various circuitry in the power supply 1 101 and communicating with the one or more connected devices. Generally, these are controlled power sources that can provide adjustable output values, e.g., voltage or current, through the use of a feedback system via a communication line 1 1 12. The communication line 1 1 12 communicates to connected devices by sending and receiving power requirement information. The controller 1 104 sends and receives digital communication from devices such as client device 1 103 via the communication line 1 1 12. The controller 1 104 receives and processes digital messages from the client devices 1 103. The controller 1 104 is also coupled to the DC/DC converters 1 108 via control line 1 1 10 to configure the DC/DC converters 1 108 and make adjustments to the supplied power. The controller 1 104 is additionally coupled to switches 1 150A-N via control line 1 1 10 and to the AC/DC converter 1 106 via another control connection 1 105. Thus, the controller 1 104 enables or disables switches 1 150A-N by control signals 1 152A-N and the DC/DC converters 1 108A-N via the conductor line 1 1 10 depending on whether the client device 1 103 is a high or low power system. As previously described, the controller 1 104 may additionally have tunable control of voltage levels of the AC/DC converter 1 106 to match power requirements of high-power client device 1 103. The controller 1 104 may also enable or disable switches within the AC/DC converter 1 106, as described with respect to FIG. 5, to place the AC/DC converter 1 106 in a standby mode for additional power saving features. The controller 1 104 may include

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WEST\229565560.1 Attorney Docket No.: 380533-995170 microprocessors, memory, power supply hub and other components (not shown) for storing and processing values, feedback information and instructions to configure the power supply 1 101. In some embodiments, the processing of a digital message from a client device 1 103 includes error detection, inspecting the contents of the message, and based on the contents, execute further instructions. Based on the content of the messages, the controller 1 104 executes instructions to send responses to the client devices 1 103 via the communication line 1 1 12 and/or provide voltage or current values to program the DC/DC converters 1 108 via conductor line 1 1 10.

[00101] In some embodiments, the controller 1 104 includes a sense detection mode, which detects the connection of the client device 1 103 or whether the client device 1 103 is high or low powered. In some embodiments, the controller 1 104 includes a communicate mode during which data is transmitted and received on communication line 1 1 12, and subsequently on communication line 1 122 to and from the client device 1 103. In some embodiments, the controller 1 104 also includes a switch control mode to send control signals to enable or disable switches in AC/DC converter 1 106, switches 1 150A-N or the DC/DC converters 1 108A-N for enhanced power saving features and service both high and low powered client devices 1 103 as previously described.

[00102] In some embodiments, the controller 1 104 includes memory (not shown) to store a database of predefined power profiles. A power profile is a predefined set of data that specifies power requirements, or more particularly, a predefined combination of power requirement parameters. In some embodiments, a power profile includes one or more of the following: a constant voltage value, a constant current value, a wattage value, an upper limit current value, and a battery type. The power profiles may be organized as a lookup table in memory, with each power profile referenced by an identifier. A device such as client device 1 103 may communicate, in a digital message, the identifier of the desired profile to the controller 1 104. The controller 1 104 retrieves from memory the power profile corresponding to the identifier provided by the client device 1 103. Parameters in the retrieved power profile are used to configure the power supply 1 101.

[00103] The client device 1 103 may include a hub interface 1 130 having components to interface with the power supply 1 101 through Port 1 1 1 14A and device port 1 128. The client device 1 103 communicates power requirements via communication lines 1 122 to allow the

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WEST\229565560.1 Attorney Docket No.: 380533-995170 power supply 1 101 to establish whether the client device 1 103 requires high or low power and further adjust the appropriate power level. Once the power requirements of the client device 1 103 are determined, the proper power is configured on the power line 1 1 16 to fully power the client device 1 103. In some embodiments, the client device 1 103 includes a load sub-device 1 140, which may include a load processor, memory, power-saving circuitry and other components to collaborate with the power supply 1 101 and communicate various power needs of the client device 1 103.

[00104] FIG. 12 is a flow diagram illustrating a process of supplying power by a power supply to a connected device in accordance with some embodiments. The process includes a method for processing data on a multi-threaded processor. At step 1210, requests for processing data in a non-critical operations mode are continuously received. At step 1220, a request for a time-critical calculation is received. At step 1230, the request for the time-critical calculation is processed as it is received while simultaneously processing requests for processing data in a non- critical operations mode.

[00105] FIG. 13 is a flow diagram illustrating a process of generating mixed mode control signals in supplying power to a connected device in accordance with other embodiments. At step 1310, a first modulating signal is generated, and at step 1320, a second modulating signal is generated relative to the first modulating signal or a programmed initial offset. At step 1330, a present cycle of the first modulating signal is offset based on one or more preceding cycle(s) of the first modulating signal or a programmed initial offset. At step 1340, a next cycle of the second modulating signal is offset based on the one or more preceding cycle(s) of the first modulating signal. At step 1350, a next cycle of the first modulating signal is offset based on the preceding cycle of the second modulating signal, or an average calculated based on two or more preceding cycles of both modulating signals. At step 1360, a next cycle of the second modulating signal is offset based on the preceding cycle of the first modulating signal, or an average calculated based on two or more preceding cycles of both modulating signals. Steps 1350 and 1360 then repeat indefinitely.

[00106] FIG. 14 is a flow diagram illustrating a process of supplying power to a connected device in accordance with some other embodiments. The process includes a method of detecting a load to a power supply. At step 1410, a pulsed power signal is received. At step 1420, the

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WEST\229565560.1 Attorney Docket No.: 380533-995170 pulsed power signal is monitored for a predetermined time interval. At step 1430, a reflected pulse signal, may be detected during the predetermined time interval, wherein the reflected pulse signal is indicative of a connection status of the load device.

[00107] According to some embodiments, a microcontroller system comprises an input node coupled to receive power from a power source. A first signal block is coupled to the input node and configured to generate a first modulating signal output. At least a second signal block is coupled to the input node and configured to generate a second modulating signal output, the outputs of each of the first and second modulating signals being offset relative to a portion of the previous captured signal that generated the most recent output.

[00108] According to some other embodiments, a microcontroller apparatus in a power supply, comprises a communication interface including a sensing input. An auxiliary power source is coupled to the sensing input of the communication interface, the auxiliary power source being operable to generate pulsed power signals. A counter is coupled to the auxiliary power source and configured to count for a predetermined interval, the counter being operable to monitor the pulsed power signals during the predetermined interval, and detect a reflected pulse, wherein the presence of a reflected pulse is indicative of a connection status of a load device.

[00109] According to some other embodiments, a microcontroller system, comprises a databus and an analog-to-digital converter ("ADC") coupled to the databus. The ADC including a plurality of channels. A multi-threaded processor unit is coupled to the ADC and the databus, the processor unit is configured to process requests for time-critical calculations as they are received while simultaneously processing on-going non-critical operations.

[00110] FIG. 15 is a screen shot of the graphical user interface (GUI) of a portable software tool Greenscape. Greenscape provides a user-friendly GUI, enabling the user to adjust the parameters of the power supply and monitor the effects in real time without knowing details of the Green Power Processor's firmware or its debug interface. It stores the adjusted parameters on the local file system and/or in the non-volatile memory of the power supply.

[00111] The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and

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WEST\229565560.1 Attorney Docket No.: 380533-995170 described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.

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WEST\229565560.1

Claims

Attorney Docket No.: 380533-995170

We Claim;

1. A microcontroller system comprising:

a multi-threaded processor;

a memory sub-system connected with the processor; and

one or more of a communication component, a clock/timer component, a fault component, a comparator component, an analog-to-digital converter (ADC) interfaced with the processor via a parallel data bus, a digital-to-analog converter (DAC), and/or a pulse-width modulation (PWM) component connected with the processor.

2. The system of claim 1 further comprising one or more of a rectifier circuit, an auxiliary power supply, a PFC, a Down Converter, a connector and / or a communication link.

3. The system of claim 1 further comprising a hardware burst mode control engine that minimizes overhead during low load conditions.

4. The system of claim 1 wherein the data bus is configured to be accessed by either hardware thread via a parallel ADC data port of the ADC connected to the data bus.

5. The system of claim 1 wherein the ADC includes an ADC controller configured to determine which of the ADC input channels will automatically send its analog-to-digital conversion result through the data bus as soon as a conversion completes.

6. The system of claim 5 further configured to do one or both of retrieve, via software of the processor, each conversion result by reading the ADC data port connected to the data bus, and/or return a read only if new data (ADC conversion result) is available to be fetched at the port, wherein, when a first hardware thread of the processor is dedicated to reading and processing ADC conversion results, software execution is halted on a second thread that attempts to read the port if there is no new data arriving at the port.

7. The system of claim 6 wherein, as soon as a piece of data arrives at the port, the software execution immediately resumes.

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WEST\229565560.1 Attorney Docket No.: 380533-995170

8. The system of claim 6 or claim 7 wherein no interrupts are utilized to inform the processor of time-critical events, and zero overhead in saving contexts is provided.

9. The system of claim 6 wherein, while the software execution on a hardware thread is halted while waiting for data, one or more other hardware threads continue to run and execute ongoing procedures.

10. The system of any of claims 6 through claim 9 wherein interference is eliminated between ongoing (background/house-keeping) tasks, and intermittent, high frequency real-time critical handlers.

11. The system of claim 5 wherein the system is configured to perform software branching while ADC conversion is taking place.

12. The system of claim 1 1 wherein the system is configured to:

deliver, as soon as a sample (snap shot) is taken on an input ADC channel of interested, a user-preconfigured memory address corresponding to the location of the software algorithm through the data bus to the port;

execute the software branching as soon as this memory address data is read through the port; and/or

return, via a next read on the port, an actual ADC conversion result of the channel of interest.

13. The system of any claim herein wherein, as a function of a CPU program counter being set to a correct location, the system can immediately begin processing of data.

14. The system of claim 1 further comprising a pulse-width modulation (PWM) module that is configured to provide pulsed power signals configured to support a number of operating modes.

15. The system of claim 14 wherein the PWM module is configured to operate in an

independent mode, where each output waveform is configured independently.

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WEST\229565560.1 Attorney Docket No.: 380533-995170

16. The system of claim 14 wherein the PWM module is configured to operate in a

complementary mode, wherein two output waveforms are complements of each other.

17. The system of claim 14 wherein the PWM module is configured to operate in 180° synchronization mode, wherein two outputs with independent and varying periods and duty- cycles are aligned 180 degrees out-of-phase.

18. A power adapter system comprising:

a microcontroller including a processor as well as a memory sub-system and a clock/timer component connected with the processor; and

an auxiliary power supply component connected with the microcontroller;

wherein the clock/timer component includes a kick timer that monitors changes in the auxiliary power supply.

19. The system of claim 18 wherein the system is configured to provide a load detection sensing feature, including a digital input that works with the kick timer to detect presence of a load to a power supply in which the processor resides.

20. The system of claim 18 configured such that the kick timer monitors pulse signals to detect the presence or absence of a load device, and, if a load device is attached, the kick timer recognizes the load by detecting a reflection in the pulse signal.

21. The system of claim 18 wherein the kick timer is configured to increment at a fixed interval and/or configured with timing functionality including a feature to timeout at a predetermined time and/or to prevent the kick timer from timing out, receive a kick in the form of a pulse.

22. A method of synchronizing 2 PWM output signals for power management, the method comprising:

performing a first synchronization process including following a pulse on a first PWM output, initiating a pulse on a second PWM output after the latest calculated minimum offset has

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WEST\229565560.1 Attorney Docket No.: 380533-995170 elapsed and at least a natural period since a last pulse on this output has expired, wherein the natural period is defined as the PWM period that would have resulted from a PWM Reset operation if there is no minimum offset taking effect;

performing a second synchronization process concurrently with the first synchronization process;

wherein PWM pulses being output are forced to strictly alternate between the two PWM outputs, even if two PWM resets occur on one PWM output before the next pulse on the other output;

wherein 2 PWM outputs are automatically synchronized such that they are 180° out-of- phase with each other.

23. The method of claim 22 wherein a minimum offset from a pulse on one PWM output to the next pulse on the alternate PWM output is calculated as half of the previous captured/natural period length on the PWM output that generated the most recent pulse.

24. The method of claim 22 wherein the 2 PWM outputs are enable one after another, and wherein:

given a condition that at least one natural period on the first enabled output has elapsed before the second output is enabled, a known minimum offset is applied between the latest pulse of the first enabled output and the first pulse of the later enabled output; and

if the condition does not exist, an initial-offset is configured via the appropriate control register which forces the first pulse on the later enabled output to occur no earlier than initial- offset from the assertion of the first pulse on the first-enabled output.

25. The method of claim 24 wherein the second pulse on the first enabled output is allowed to occur no earlier than two times the initial-offset, regardless of what first natural period of the first enabled output is.

26. The method of claim 24 wherein, if the initial offset is configured as zero, then the first pulse on the later enabled PWM output can assert anywhere within the first natural period of the first enabled output.

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WEST\229565560.1 Attorney Docket No.: 380533-995170

27. The method of claim 22 wherein the 2 PWM outputs are enable simultaneously, and wherein:

if initial-offset is not zero, the first pulse of one of the outputs (PWM1) will be delayed by the initial offset, and the second pulse on the output whose first pulse is not delayed (PWMO) is allowed to occur no earlier than two times the initial-offset, regardless of what its first natural period is; and

if initial-offset is zero, then the first pulses of both PWM outputs will begin simultaneously but the second pulse of one output will not be allowed to occur until one natural period of the other output has elapsed, thereby providing a known minimum offset.

28. The method of claim 25 wherein, if the configured initial-offset is greater than the first natural period of the PWM output whose first pulse is not offset, half of this natural period is used as the offset for the first pulse of the other PWM output and the initial-offset is ignored.

29. A method of performing pulse-width modulation/compensation synchronizing 2 PWM output signals for power management, the method comprising:

incrementing or decrementing a pulse-width of one PWM output based on a comparison between the latest period-captures (or capture averages if the averaging feature is enabled) for each PWM output;

wherein the pulse-width changes in the direction to balance the natural periods of the two PWM outputs, when the resulting natural period is longer for greater the pulse-width; and

wherein the pulse-width of the compensating PWM output (PWM1) increases if the captured/natural period of the compensating PWM output is shorter than the other output (PWMO), and decreases if the captured/natural period of the compensating PWM output is longer than the other output.

30. The method of claim 29 wherein the step size is configurable via control registers.

31. The method of claim 29 wherein only the last single captured/natural periods from the two PWM output are compared.

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WEST\229565560.1 Attorney Docket No.: 380533-995170

32. The method of claim 31 or claim 29 wherein capture-averaging is utilized such that the comparison is made based on a running average of multiple most recent natural periods on the two PWM outputs.

33. A method of processing carry-over information in association with pulse-width

compensation in synchronizing 2 PWM output signals for power management, the method comprising:

calculating/determining, via a digital feedback loop, a new PWM pulse-width update at fixed/variable intervals;

providing a primary adjustment to the pulse-widths of both PWM outputs as a function of the new PWM pulse-width update; and

automatically adding, when a primary adjustment occurs, the currently used

compensation amount to the compensating PWM output.

34. The method of claim 33 wherein the primary adjustment is provided via a software write to a pulse-width control register.

35. The method of claim 33 wherein the primary adjustment is provided via a digital circuitry write to a pulse-width control register.

36. The system of claim 17 wherein the 180° Synchronization mode is configured to utilize two pairs of Complementary PWM outputs.

37. A method of performing power adaption/compensation associated with a microcontroller including 2 pulse-width modulation (PWM) outputs, the method comprising:

entering a pulse-width modulation (PWM) Reset mode; and

implementing a duty-cycle Truncation mode in parallel with the PWM Reset mode.

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WEST\229565560.1 Attorney Docket No.: 380533-995170

38. The method of claim 37 further comprising:

providing cycle -by-cycle limitation to the electric-currents flowing through the hardware circuitry external to a processor.

39. The method of claim 37 or claim 38 further comprising performing a duty-cycle truncation operation that maintains the 2 PWM outputs 180° out-of-phase with each other.

40. A microcontroller system comprising:

an input node coupled to receive power from a power source;

a first signal block coupled to the input node and configured to generate a first modulating signal output; and

at least a second signal block coupled to the input node and configured to generate a second modulating signal output.

41. The system of claim 40 wherein the outputs of each of the first and second modulating signals being offset relative to a portion of the previous captured signal that generated the most recent output.

42. A microcontroller apparatus in a power supply, comprising:

a communication interface including a sensing input;

an auxiliary power source coupled to the sensing input of the communication interface, the auxiliary power source being operable to generate pulsed power signals; and

a counter coupled to the auxiliary power source and configured to count for a

predetermined interval.

43. The apparatus of claim 42 wherein the counter being operable to monitor the pulsed power signals during the predetermined interval, and detect a reflected pulse, wherein the presence of a reflected pulse is indicative of a connection status of a load device.

A microcontroller system, comprising:

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WEST\229565560.1 Attorney Docket No.: 380533-995170 a databus;

an analog-to-digital converter ("ADC") coupled to the databus, the ADC including a plurality of channels; and

a multi-threaded processor unit coupled to the ADC and the databus, the processor unit configured to perform a power conversion application during which the processor processes requests for time-critical calculations as they are received while simultaneously processing ongoing non-critical operations.

45. A method for processing data on a multi-threaded processor in performance of a power conversion application, the method comprising:

continuously receiving requests for processing data in a non-critical operations mode;

receiving a request for a time-critical calculation; and

performing a power conversion process, in which the request for the time-critical calculation is processed as it is received while simultaneously processing requests for processing data in a non-critical operations mode.

46. The method of claim 45 wherein the method involves a 180° synchronization mode, wherein two outputs with independent and varying periods and duty-cycles are aligned 180 degrees out-of-phase.

47. The method of claim 45 further comprising processing carry-over information in association with pulse-width compensation in synchronizing 2 PWM output signals for power management.

48. The method of claim 45 further comprising providing pulsed power signals, via a pulse- width modulation (PWM) module, to support a number of operating modes.

49. The method of claim 45 wherein the method involves one or more of the following modes: independent mode, where each output waveform is configured independently;

a complementary mode, wherein two output waveforms are complements of each other; and / or

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WEST\229565560.1 Attorney Docket No.: 380533-995170 a 180° synchronization mode, wherein two outputs with independent and varying periods and duty-cycles are aligned 180 degrees out-of-phase.

50. A method of supplying power to a connected device via generation of mixed-mode control signals, the method comprising:

generating a first modulating signal;

generating a second modulating signal relative to the first modulating signal or programmed initial offset;

offsetting a present cycle of the first modulating signal based on one or more preceding cycles of the first modulating signal or a programmed initial offset; and

offsetting another cycle of the second modulating signal based on the one or more preceding cycles of the first modulating signal;

offsetting another cycle of the first modulating signal based on the one or more preceding cycles of the second modulating signal, or an average calculated based on two or more preceding cycles of both modulating signals;

offsetting another cycle of the second modulating signal based on the one or more preceding cycles of the first modulating signal or an average calculated based on two or more preceding cycles of both modulating signals.

51. The method of claim 50, wherein the another cycle is a next cycle, and wherein each of the first and second modulating signals is offset relative to a portion of the previous captured signal that generated the most recent output.

52. A method for generating mixed-mode control signals, comprising:

generating a first modulating signal;

offsetting a next cycle of the second modulating signal based on the one or more preceding cycles of the first modulating signal;

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WEST\229565560.1 Attorney Docket No.: 380533-995170 offsetting a next cycle of the first modulating signal based on the one or more preceding cycles of the second modulating signal, or an average calculated based on two or more preceding cycles of both modulating signals;

offsetting a next cycle of the second modulating signal based on the one or more preceding cycles of the first modulating signal or an average calculated based on two or more preceding cycles of both modulating signals;

wherein each of the first and second modulating signals is offset relative to a portion of the previous captured signal that generated the most recent output.

53. A method of detecting a load to a power supply, comprising:

receiving a pulsed power signal; and

monitoring the pulsed power signal for a predetermined time interval to detect a reflected pulse signal, wherein the reflected pulse signal is indicative of a connection status of the load device.

54. A method of detecting a load to a power supply, comprising:

receiving a pulsed power signal; and

monitoring the pulsed power signal for a predetermined time interval; and detecting a reflected pulse signal from a load device.

55. The method of claim 54 wherein the reflected pulse signal is processed to determine information regarding the load device.

56. The method of claim 55 wherein the reflected pulse signal is indicative of a connection status of the load device.

57. A power supply system comprising:

an AC/DC converter in communication with at least one port;

one or more DC/DC converters in communication with at least one port; and

a controller configured to receive and process digital messages from the client devices, wherein the controller is further configured to vary voltages to the at least one port.

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WEST\229565560.1 Attorney Docket No.: 380533-995170

57. The power supply system of claim 57 wherein the controller is configured to vary the voltage supplied to the at least one port from the voltage supplied to at least one other port.

57. The power supply system of claim 57 wherein the controller is configured to vary the voltage provided to the at least one port.

58. The power supply system of claim 57 wherein,

the AC/DC converter is in communication with the DC/DC converters via a power conductor;

wherein the communication includes switches to bypass the DC/DC converters.

59. A multi-port power hub comprising a green power processor, a power factor correction, a power converter, at least one connector, and

at least one variable DC/DC converter, wherein the green power processor is in communication with the at least one connector via at least one DC/DC converter; and wherein the green power processor is in communication with the connector via a greenwire.

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