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WO2012120653A1 - Procédé de production pour dispositif semi-conducteur et dispositif semi-conducteur - Google Patents

Procédé de production pour dispositif semi-conducteur et dispositif semi-conducteur Download PDF

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Publication number
WO2012120653A1
WO2012120653A1 PCT/JP2011/055408 JP2011055408W WO2012120653A1 WO 2012120653 A1 WO2012120653 A1 WO 2012120653A1 JP 2011055408 W JP2011055408 W JP 2011055408W WO 2012120653 A1 WO2012120653 A1 WO 2012120653A1
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Prior art keywords
semiconductor
layer
region
insulating layer
forming
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Ceased
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PCT/JP2011/055408
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English (en)
Japanese (ja)
Inventor
舛岡　富士雄
原田　望
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Unisantis Electronics Singapore Pte Ltd
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Unisantis Electronics Singapore Pte Ltd
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Priority to PCT/JP2011/055408 priority Critical patent/WO2012120653A1/fr
Priority to CN2012800004124A priority patent/CN102792452A/zh
Priority to JP2012521405A priority patent/JP5114608B2/ja
Priority to PCT/JP2012/052777 priority patent/WO2012120951A1/fr
Priority to KR1020127015784A priority patent/KR101350577B1/ko
Priority to TW101107287A priority patent/TW201242003A/zh
Publication of WO2012120653A1 publication Critical patent/WO2012120653A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0195—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/026—Wafer-level processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8033—Photosensitive area

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure, and the semiconductor device.
  • Solid-state imaging devices such as CCD and CMOS type are widely used for video cameras, stale cameras and the like. Further, there is a demand for improved performance such as higher resolution, higher speed operation, and higher sensitivity of the solid-state imaging device.
  • a solid-state imaging device in which one pixel is configured in one columnar semiconductor 110 is known (see, for example, Patent Document 1).
  • an N + type silicon layer 51 that functions as a signal line of a solid-state imaging device is formed on a semiconductor substrate.
  • the columnar semiconductor 110 is connected to the N + type silicon layer 51.
  • the columnar semiconductor 110 is formed with a MOS transistor for removing accumulated charges, which includes a P-type silicon layer 52, insulating films 53a and 53b, and gate conductor layers 54a and 54b.
  • the columnar semiconductor 110 is formed with a photodiode that is connected to the MOS transistor and accumulates charges generated by irradiation with light (electromagnetic energy wave).
  • This photodiode is composed of a P-type silicon layer 52 and N-type silicon layers 58a and 58b.
  • a P + type silicon layer 56 and an N + type silicon layer formed on the P type semiconductor 52 surrounded by the photodiode as a channel, the photodiode as a gate, and the photodiode are connected to the pixel selection lines 57a and 57b.
  • Junction transistors are formed using the P-type silicon layer 52 in the vicinity of 51 as a source and a drain, respectively.
  • the basic operation of this solid-state imaging device includes a signal charge accumulation operation in which signal charges (electrons in this case) generated by light irradiation are accumulated in a photodiode, and a P-type silicon layer 52 and P + in the vicinity of the N + -type silicon layer 51.
  • a signal read operation for modulating the source / drain current flowing between the silicon layer 56 and the gate voltage by the photodiode voltage corresponding to the above-mentioned accumulated signal charge and reading this as a signal current, and completion of this signal read operation Thereafter, the signal charge accumulated in the photodiode is reset to remove the N + -type silicon layer 51 by applying an ON voltage to the gate conductor layers 54a and 54b of the MOS transistor.
  • the pixels shown in FIG. 14 are two-dimensionally arranged in the photosensitive area.
  • the signal reading operation is performed by transmitting a pixel signal (signal current) to an output circuit provided around the photosensitive region via the N + type silicon layer 51.
  • the reset operation is also performed through electrical transmission between the pixel and the peripheral circuit of the photosensitive region.
  • the bonding metal layer 59 formed on the silicon substrate 60 Possible structures are possible. As a result, the electric resistance of the signal line is almost determined by the metal layer 59, so that the high-speed operation of the signal reading operation described above is realized. However, it is difficult to form the metal layer 59 bonded to the N + type silicon layer 51 from the viewpoint of the affinity of bonding between the metal material and the silicon material.
  • the following method can be considered to form the metal layer 59 on the silicon substrate 60. That is, as shown in FIG. 15B, a silicon oxide layer 62 is formed on the semiconductor substrate 61, and a metal layer 59 is formed on the silicon oxide layer 62. Then, the semiconductor substrate 61 on which the metal layer 59 is formed and the semiconductor substrate 64 are bonded. Thereafter, pixels are formed in the portion of the semiconductor substrate 64 indicated by the broken line in FIG. 15B.
  • a dot-dash line D-D ′ shown in FIG. 15B shows a state in which the semiconductor substrate 64 is formed to a predetermined height by polishing, etching, or other separation methods of the semiconductor substrate 64.
  • the side surface of a columnar semiconductor having a columnar structure is used as a channel region, and a vertical MOS transistor having a structure in which a gate electrode surrounds the channel region is an SGT (Surrounding Gate Transistor).
  • SGT Square Gate Transistor
  • a planar silicon film 67 is formed on the buried oxide film substrate 66, and a columnar structure is formed by the planar silicon film 67 and the PMOS columnar silicon layer 68. .
  • a P + -type silicon diffusion layer 69 that functions as a drain is formed in the planar silicon film 67.
  • a P + -type silicon diffusion layer 70 functioning as a source is formed on the PMOS columnar silicon layer 68, and a gate insulating layer 71 is formed on the outer periphery of the PMOS columnar silicon layer 68.
  • a gate electrode 72 is formed on the outer periphery of the gate insulating layer 71.
  • a silicon nitride (SiN) film 73 and a silicon oxide (SiO 2 ) film 74 are formed so as to surround the gate electrode 72, the P + -type silicon diffusion layer 70, and the P + -type silicon diffusion layer 69.
  • a contact hole 75 is formed in the silicon oxide layer 74, and the P + -type silicon diffusion layer 70 is connected to the source metal wiring 76 through the contact hole 75.
  • one MOS transistor is formed in a columnar structure.
  • the P + -type silicon diffusion layer 69 shown in FIG. 16 is connected to a metal wiring (not shown) at a predetermined portion where the planar silicon film 67 extends on the same plane.
  • the connection between the P + -type silicon diffusion layer 69 and the metal wiring is as in the P + -type silicon diffusion layer 70. It is required to be performed at a short distance.
  • a pixel signal (signal current) is provided around the photosensitive region and transmitted to an external circuit via the N + type silicon layer 51 functioning as a signal line. Is done.
  • the reset operation is also performed through electrical transmission between the pixel and an external circuit in the photosensitive area. The responsiveness of this electrical transmission is greatly influenced by the electrical resistance and parasitic capacitance of the wiring connecting the pixel and the peripheral circuit. In order to increase the number of pixels of the solid-state imaging device or the number of readout screens per unit time, it is necessary to reduce the electrical resistance of such wiring.
  • such an electric resistance is substantially determined by the electric resistance of the N + type silicon layer 51.
  • N + -type silicon layer 51 is formed a donor impurity in silicon (Si) semiconductor, such as phosphorus (P), arsenic (As) by ion doping (ion implantation), electrical of the N + -type silicon layer 51
  • Si silicon
  • P phosphorus
  • As arsenic
  • ion doping ion implantation
  • the resistance value cannot be made smaller than the electrical resistance value of a metal used in a normal semiconductor device such as aluminum (Al), copper (Cu), tungsten (W), nickel (Ni).
  • the solid-state imaging device shown in FIG. 14 has a problem inferior in high-speed operation characteristics as compared with a solid-state imaging device that performs electrical connection between a pixel and a peripheral circuit by a metal wiring.
  • the P + -type silicon diffusion layer 69 is connected to the metal wiring at the portion where the planar silicon film 67 is extended.
  • Such means by connecting the P + -type silicon diffusion layer 69 and the metal wiring cannot be connected to the metal wiring at a short distance as in the P + -type silicon diffusion layer 70, so that the metal wiring and the SGT channel are not connected.
  • a considerable electrical resistance is present up to the end of the closest P + -type silicon diffusion layer 69. For this reason, in the semiconductor device having SGT, it is necessary to reduce this electric resistance in order to realize further high-speed signal reading operation.
  • the present invention has been made in view of the above-described circumstances, and an object thereof is to provide a semiconductor device capable of realizing high integration and high speed operation.
  • a method of manufacturing a semiconductor device includes: A first insulating layer forming step of forming a first insulating layer on the semiconductor substrate; An insulating layer removing step of removing a predetermined portion of the first insulating layer to form an insulating layer removal region; A first semiconductor layer forming step of forming a first semiconductor layer containing a donor impurity or an acceptor impurity on the semiconductor substrate so as to cover at least the insulating layer removal region; A conductive layer forming step of forming a conductive layer on the first semiconductor layer; A molding step of molding the conductive layer and the first semiconductor layer into a predetermined shape; A second insulating layer forming step of forming a second insulating layer so as to cover the conductive layer and the first semiconductor layer formed in the predetermined shape; A planarization step of planarizing the surface of the second insulating layer; An adhesion step of adhering a substrate to the flattened surface of the second insulating layer;
  • the circuit element forming step includes Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer; Forming a fourth semiconductor region having the same conductivity type as the first semiconductor region in a portion above the gate conductor layer and in a surface layer portion of the columnar semiconductor;
  • the columnar semiconductor includes a step of forming a third semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the third insulating layer.
  • the circuit element forming step includes Forming a third insulating layer on the outer periphery of the columnar semiconductor and forming a gate conductor layer on the outer periphery of the third insulating layer; And forming a fifth semiconductor region having the same conductivity type as that of the first semiconductor region at a position above the third insulating layer in the columnar semiconductor.
  • the circuit element forming step includes Preferably, the method includes a step of forming a sixth semiconductor region having a conductivity type opposite to that of the first semiconductor region in an upper portion of the columnar semiconductor.
  • the first semiconductor layer forming step includes a step of forming a second semiconductor layer functioning as an electric resistance in the same layer as the first semiconductor layer.
  • the first semiconductor layer forming step includes a step of forming an insulating film functioning as a capacitor insulating film in a predetermined region on the first semiconductor layer functioning as a capacitor electrode;
  • the conductive layer forming step preferably includes a step of forming a conductive layer functioning as a capacitor electrode together with the first semiconductor layer on the insulating film.
  • the first insulating layer forming step forms a fourth insulating layer together with the first insulating layer on the semiconductor substrate, and has a thickness larger than that of the fourth insulating layer in a preset capacitance forming region.
  • Forming a thin fifth insulating layer functioning as a capacitive insulating film includes a step of forming a conductive layer functioning as a capacitor electrode on the fifth insulating layer,
  • the insulating layer removing step preferably includes a capacitor forming step of forming an impurity layer having a donor impurity or an acceptor impurity in the capacitor forming region and functioning as a capacitor electrode.
  • a mask alignment mark formation region setting step for setting a mask alignment mark formation region on the semiconductor substrate; Forming a mask alignment hole in the mask alignment mark formation region to expose at least one of the insulating layer removal region, the first insulating layer, and the conductive layer; A mask alignment mark forming step of forming a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer, and the conductive layer through the mask alignment hole; It is preferable that the method further includes a mask alignment step of performing mask alignment of the photomask with the mask alignment mark as a reference.
  • a mask alignment mark comprising at least one of the insulating layer removal region, the first insulating layer, and the conductive layer is formed through the transparent insulator,
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
  • the columnar semiconductor is A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor;
  • a diode that accumulates signal charges generated by irradiation of electromagnetic energy waves from the second semiconductor region and the fourth semiconductor region is formed, The diode functions as a gate, one of the first semiconductor region and the third semiconductor region functions as a source, the other functions as a drain, and a channel formed in the second semiconductor region.
  • a junction transistor is formed that is capable of taking out a current that flows and changes in accordance with the amount of signal charge accumulated in the diode by a signal taking-out means,
  • the gate conductor layer functions as a gate, and a voltage is applied to the gate conductor layer by a MOS transistor in which one of the first semiconductor region and the fourth semiconductor region functions as a source and the other functions as a drain.
  • signal charge removing means for removing the signal charge accumulated in the diode in the first semiconductor region is formed.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
  • the columnar semiconductor is A second semiconductor region formed on the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region or an intrinsic semiconductor;
  • the gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain. To do.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention,
  • the columnar semiconductor is Between the first semiconductor region and the sixth semiconductor region, a second semiconductor region made of a conductive type or a specific semiconductor opposite to the first semiconductor region is provided, A diode is formed from the second semiconductor region and the sixth semiconductor region.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer;
  • the plurality of columnar semiconductors include a plurality of first columnar semiconductors in which the first semiconductor region is doped with an acceptor impurity, and a plurality of second columnar semiconductors in which the first semiconductor region is doped with a donor impurity. It consists of a semiconductor.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer; In the plurality of columnar semiconductors, both or one of the plurality of first semiconductor regions and the plurality of conductive layers are connected to each other.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer; Each of the columnar semiconductors is A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor; A fifth semiconductor region formed on the second semiconductor region; A third insulating layer formed on the outer periphery of the second semiconductor region; A gate conductor layer formed on the outer periphery of the third insulating layer, The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
  • the first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer formed so as to be connected is a contact formed on an insulating layer. It is connected to a wiring layer for connecting to an external circuit through a hole.
  • a semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first aspect of the present invention, A plurality of the columnar semiconductors are formed on the first semiconductor layer; Each of the columnar semiconductors is A second semiconductor region made of a semiconductor having a conductivity type opposite to that of the first semiconductor region formed on the first semiconductor region or an intrinsic semiconductor; A fifth semiconductor region formed on the second semiconductor region; A third insulating layer formed on the outer periphery of the second semiconductor region; A gate conductor layer formed on the outer periphery of the third insulating layer, The gate conductor layer functions as a gate, and a MOS transistor is formed in which one of the first semiconductor region and the fifth semiconductor region functions as a source and the other functions as a drain.
  • the first semiconductor layer is formed so as to be continuously connected over the plurality of columnar semiconductors, and the first semiconductor layer is connected to a predetermined hole via a contact hole formed in the insulating layer. It is connected to a wiring layer for connecting to the gate of the transistor.
  • FIG. 20 is a circuit plan view for explaining a two-stage CMOS inverter circuit according to a tenth embodiment.
  • (First embodiment) 1A to 1L show a method for manufacturing a solid-state imaging device according to the first embodiment of the present invention.
  • high-concentration hydrogen ions H +
  • a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed (see Non-Patent Document 2).
  • a first silicon oxide layer 3 that is an insulating film is formed on the first semiconductor substrate 1 by thermal oxidation or CVD (Chemical Vapor Deposition).
  • the first semiconductor substrate 1 may be a unique semiconductor (i-type silicon) that does not substantially contain impurities, instead of P-type silicon.
  • the hole 4 is formed by removing silicon oxide (SiO 2 ) corresponding to the portion where the signal line drain of the solid-state imaging device is formed in the first silicon oxide layer 3. To do.
  • the region (hole 4) from which the silicon oxide has been removed becomes the silicon oxide layer removal region 48 (see FIGS. 11A and 13A).
  • a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3 and the first semiconductor substrate 1 by the CVD method so as to cover the hole 4.
  • the polycrystalline silicon layer 5 is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As), thereby the first semiconductor substrate 1 and the first silicon oxide.
  • a donor impurity such as phosphorus (P) or arsenic (As)
  • P phosphorus
  • As arsenic
  • tungsten (W), tungsten silicide (WSi), nickel (Ni), nickel silicide (NiSi) is deposited on the N + polycrystalline silicon layer 5a by vapor deposition or CVD. Or a metal layer 7 formed by laminating a plurality of these layers.
  • N + polysilicon layer 5a and the metal layer 7 are part that embeds the hole 4 remaining, N + polycrystalline silicon layer
  • the 5a and the metal layer 7 are formed into a predetermined shape.
  • the source or drain of the junction transistor in the pixel of the solid-state imaging device is formed.
  • a second silicon oxide layer 8 that is an insulating film is formed by a CVD method so as to cover the N + polycrystalline silicon layer 5a, the metal layer 7, and the first silicon oxide layer 3. . Then, the surface of the second silicon oxide layer 8 is planarized by CMP (Chemical Mechanical Polishing).
  • a second semiconductor substrate 9 made of silicon (Si) and having a planarized surface is prepared, and the planarized surface of the second semiconductor substrate 9 and the second silicon oxide are prepared.
  • the planarized surfaces of the layer 8 are bonded together by pressure bonding. In this bonding process, the difference in thermal expansion coefficient between the silicon layer in the second semiconductor substrate 9 and the silicon layer in the second silicon oxide layer 8 are bonded to each other. Due to the difference, it is possible to obtain a laminated structure in which warpage, cracking and peeling are unlikely to occur.
  • the N + polycrystalline silicon layer 5a corresponds to the N + type silicon layer 51 shown in FIG. 14, and in this embodiment, the N + polycrystalline silicon layer 5a includes all of its formation regions.
  • the metal layer 7 is joined over the entire area.
  • the silicon layer in the region other than the silicon layer in the region directly above so that the silicon layer in the region immediately above the N + polycrystalline silicon layer 5 a remains. Are removed by etching. Thereby, a silicon (Si) pillar 1a having a pillar structure is formed.
  • the silicon pillar 1a becomes a P-type silicon layer 30 shown in FIGS. 1K, 1L and the like.
  • heat treatment is performed to thermally diffuse the donor impurity from the N + polycrystalline silicon layer 5a to the silicon pillar 1a, thereby forming the N + diffusion layer 6a in the lower part of the silicon pillar 1a.
  • thermal oxidation is performed to form third silicon oxide layers 10a and 10b that are insulators on the outer periphery of the silicon pillar 1a.
  • gate conductor layers 11a and 11b are formed on the outer peripheral portions of the third silicon oxide layers 10a and 10b by vapor deposition or CVD.
  • an N-type is formed by ion-doping a donor impurity such as phosphorus (P) or arsenic (As) in the upper portion of the gate conductor layers 11a and 11b and the surface layer portion of the silicon pillar 1a.
  • Silicon layers 12a and 12b are formed.
  • the N-type silicon layers 12a and 12b and the silicon pillar 1a (P-type silicon layer 30) form a photodiode as signal charge storage means for storing signal charges (electrons in this case) corresponding to incident light. Is done.
  • the signal charge is accumulated in the silicon pillar 1a (P-type silicon layer 30) between the N + diffusion layer 6a and the P + -type silicon layer 13a.
  • an upper portion of the third silicon oxide layers 10a and 10b is ion-doped with an acceptor impurity such as boron (B) to thereby form a P + -type silicon layer 13a.
  • an acceptor impurity such as boron (B)
  • a third oxide which is an insulator is formed by thermal oxidation on the outer periphery of the silicon pillar 1b constituting another pixel and adjacent to the silicon pillar 1a constituting the pixel of the solid-state imaging device. Silicon layers 10c and 10d are formed.
  • the silicon pillar 1b is formed by the steps shown in FIGS. 1A to 1K, similarly to the silicon pillar 1a.
  • gate conductor layers 11c and 11d are formed on the outer periphery of the third silicon oxide layers 10c and 10d by vapor deposition or CVD.
  • the upper portion of the gate conductor layers 11c and 11d and the surface layer portion of the silicon pillar 1a are ion-doped with a donor impurity such as phosphorus (P) or arsenic (As).
  • Silicon layers 12c and 12d are formed.
  • the N-type silicon layers 12c and 12d and the silicon pillar 1b form a photodiode as signal charge storage means for storing signal charges (electrons in this case) corresponding to incident light.
  • the signal charge is accumulated in the silicon pillar 1b (P-type silicon layer 30) between the N + diffusion layer 6ab and the P + -type silicon layer 13b.
  • the N + diffusion layer 6a in the silicon pillar 1a is thermally diffused from the N + polycrystalline silicon layer 5a to the silicon pillar 1a by heat treatment. Formed.
  • the N + diffusion layer 6a is not limited to this, and the N + diffusion layer 6a is formed from the N + polycrystalline silicon layer 5a to the first semiconductor substrate by heat treatment at an arbitrary stage after the N + polycrystalline silicon layer 5a shown in FIG. 1C is formed. It can also be formed by diffusing donor impurities in 1. That is, after the step of forming the N + polycrystalline silicon layer 5a shown in FIG.
  • the impurities are diffused from the N + polycrystalline silicon layer 5a including the donor impurity, thereby the N + diffusion layer 6a is formed in the silicon pillar 1a.
  • the N + diffusion layer 6a may be formed by performing heat treatment on the silicon pillar 1a (P-type silicon layer 30) in the stage shown in FIG. 1K. Further, the heat treatment for forming such an N + diffusion layer 6a may be performed only once or may be performed in a plurality of times.
  • the solid-state imaging device is formed by the processes shown in FIGS. 1A to 1L. In addition, pixels of the solid-state imaging device are formed on each of the silicon pillars 1a and 1b.
  • N + polycrystalline silicon layer 5a and metal layer 7 formed below silicon pillars 1a and 1b and joined to each other constitute a signal line of the solid-state imaging device.
  • the N + diffusion layers 6a and 6ab in the two silicon pillars 1a and 1b are electrically connected to each other.
  • junction transistors are formed in the silicon pillars 1a and 1b.
  • a photodiode constituted by N-type silicon layers 12a and 12b (12c and 12d) and a silicon pillar 1a (P-type silicon layer 30) is a gate
  • P + -type silicon layers 13a and 13b are drains
  • N + The diffusion layers 6a and 6ab function as sources.
  • the junction transistor channel is formed in the silicon pillars 1a and 1b.
  • an external circuit serving as a signal extraction unit that flows as channels through the channels in the silicon pillars 1a and 1b by the junction transistor and extracts a current that changes according to the amount of signal charge accumulated in the photodiode as an electric signal. (Not shown) is provided.
  • the silicon pillars 1a and 1b shown in FIG. 1L are formed on the silicon pillars 1a and 1b (P-type silicon layer 30) between the N + diffusion layers 6a and 6ab and the P + -type silicon layers 13a and 13b by the photodiode.
  • MOS transistors are formed as signal charge removing means for removing the signal charges accumulated in the N + diffusion layers 6a and 6ab.
  • gate conductor layers 11a, 11b, 11c formed on the outer peripheral surfaces of the third silicon oxide layers 10a, 10b, 10c, 10d so as to surround the silicon pillars 1a, 1b (P-type silicon layer 30).
  • 11d functions as a gate
  • N + diffusion layers 6a and 6ab function as a drain
  • N-type silicon layers 12a, 12b, 12c, and 12d function as a source, respectively.
  • the channel of this MOS transistor is formed in the silicon pillars 1a and 1b.
  • the silicon layer of the second semiconductor substrate 9 and the second silicon oxide layer 8 on the first semiconductor substrate 1 are bonded to each other on the planarized surfaces. Is done.
  • the first semiconductor substrate 1 (second silicon oxide layer 8) and the second semiconductor substrate 9 are bonded to each other over the entire surfaces of the first semiconductor substrate 1 and the second semiconductor substrate 9. Since this is performed between the Si (silicon) surface and the SiO 2 (silicon oxide) surface having a high affinity, it is possible to obtain a laminated structure in which warpage, cracking, and peeling are unlikely to occur.
  • the metal layer 7 is bonded to the N + polycrystalline silicon layer 5a constituting the signal line in the pixel of the solid-state imaging device, the electrical resistance between the pixel and the peripheral circuit of the pixel Can be lowered.
  • the solid-state imaging device can be operated at a higher speed even when the number of pixels is increased or the number of readout screens per unit time is increased as compared with the conventional solid-state imaging device.
  • a PN junction (photodiode) composed of a P-type silicon layer 30 and N-type silicon layers 12a and 12b, and a P-type silicon layer 30 and N + diffusion are used.
  • the PN junction composed of the layer 6a is formed in the silicon pillar 1a made of single crystal silicon. Since the PN junction is thus formed in single crystal silicon, a pixel of a solid-state imaging device with low leakage current is configured.
  • the silicon pillar 1a which is a photoelectric conversion region and is reflected by the metal layer 7.
  • the optical path length in the silicon pillar 1a increases, and the sensitivity of the solid-state imaging device is improved.
  • the solid-state imaging device can be easily manufactured while obtaining the same sensitivity as that of the conventional example. An effect is also obtained.
  • N + polycrystal is formed by CVD so as to fill (cover) the hole 4 on the first silicon oxide layer 3 and the first semiconductor substrate 1.
  • a polycrystalline silicon layer 5 to be a silicon layer 5a was formed.
  • a single crystalline silicon layer may be formed by epitaxial growth.
  • a single crystal silicon layer can be formed also on the first silicon oxide layer 3, and thereafter, a solid-state imaging device is formed in the same manner as the steps shown in FIGS. 1C to 1K. Can do.
  • the first semiconductor substrate 1 is thinned to a predetermined thickness by removing the lower part of the first semiconductor substrate 1 by using a heat treatment at 400 to 600 ° C. with the separation layer 2 as a boundary. did.
  • the first semiconductor substrate 1 is not limited to this, but the first semiconductor substrate 1 is formed of a P + -type substrate and a P-type silicon layer formed by epitaxial growth on the P + -type substrate. Can also be performed by etching and CMP.
  • the gate insulating layers 15a and 15b are formed on the outer periphery of the silicon pillar 1a by the oxidation method or the CVD method, and the gate insulating layers 15a and 15b are formed.
  • Gate conductor layers 16a and 16b functioning as gates of SGTs (MOS transistors) are formed on the outer periphery of the gate electrode.
  • an upper portion of the gate conductor layers 16a and 16b is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As), thereby functioning as an NGT functioning as a source of SGT (MOS transistor).
  • a donor impurity such as phosphorus (P) or arsenic (As)
  • P phosphorus
  • As arsenic
  • a + type silicon layer 17a is formed.
  • a metal wiring layer 18a is formed on the N + type silicon layer 17a by vapor deposition and pattern etching.
  • an SGT specifically, an N-channel SGT is formed on the second semiconductor substrate 9.
  • the N + polycrystalline silicon layer 55a functioning as the drain of the N channel type SGT may function as a source in the N channel type SGT
  • the N + type silicon layer 17a functioning as the source may be the N channel type SGT. , It may function as a drain.
  • the metal layer 7 is bonded to the entire back surface of the N + polycrystalline silicon layer 55a that functions as a drain. With this configuration, the electrical resistance from the metal layer 7 to the N + diffusion layer 6a is reduced, so that an SGT with high speed operation is obtained.
  • an N channel type SGT formation region 1n is an N channel type SGT
  • a P channel type SGT formation region 1p is a P channel type.
  • Each SGT is formed.
  • the N-channel SGT in the N-channel SGT formation region 1n is formed in the same manner as the steps shown in FIGS. 1A to 1J of the first embodiment and FIG. 2 of the second embodiment.
  • the P-channel SGT in the P-channel SGT formation region 1p is formed in substantially the same manner as the steps shown in FIGS. 1A to 1J of the first embodiment and FIG. 2 of the second embodiment.
  • the step corresponding to FIG. 1C instead of forming the N + polycrystalline silicon layer 55a that functions as the drain of the N channel type SGT, boron (B ) Or the like is ion-doped to form a P + polycrystalline silicon layer 55b that functions as a source of the P-channel SGT.
  • an N channel type SGT constituted by the silicon pillar 1a and a silicon pillar 1b are formed.
  • a P channel type SGT is formed.
  • the N-type silicon layer 30a is formed by ion doping a P-channel SGT silicon pillar 1b (P-type silicon) with a donor impurity such as phosphorus (P) or arsenic (As).
  • the gate insulating layers 15a, 15b, 15c, and 15d are formed on the outer peripheral portions of the silicon pillars 1a and 1b by thermal oxidation or CVD, and the gate insulating layers 15a, 15b, and 15c are formed. , 15d, gate conductor layers 16a, 16b, 16c, 16d are formed by CVD (see FIG. 3B).
  • donor impurities and acceptor impurities are ion-doped in the upper portions of the gate conductor layers 16a, 16b, 16c, and 16d, respectively.
  • An N + type silicon layer 17a that functions as a source and a P + type silicon layer 17b that functions as a source of a P-channel type SGT are formed.
  • the N channel type SGT and the P channel type SGT are formed on the second semiconductor substrate 9.
  • any one of the N + polycrystalline silicon layer 55a and the N + diffusion layer 6a in the silicon pillar 1a in the N channel type SGT and the N + type silicon layer 17a is a drain, and the other is Act as a source.
  • any one of the P + polycrystalline silicon layer 55b and the P + diffusion layer 6b and the P + type silicon layer 17b in the silicon pillar 1b in the P channel type SGT is a drain, the other functions as a source.
  • the N-channel SGT and the P-channel SGT can be easily formed on the second semiconductor substrate 9.
  • the P-channel SGT silicon pillar 1b (P-type silicon) is formed with phosphorus (P), arsenic (As), or the like.
  • the N-type silicon layer 30a was formed by ion doping of the donor impurities.
  • the first semiconductor substrate 1 in FIG. 1A is replaced with i-type silicon, which is a unique semiconductor, instead of P-type silicon. In the process corresponding to FIG.
  • the silicon pillar 1a in the type SGT is ion-doped with an acceptor impurity such as boron (B) to form a P-type silicon layer 30, and the silicon pillar 1a in the P-channel type SGT has phosphorus (P) or arsenic (As). It is also possible to form the N-type silicon layer 30a by ion doping with a donor impurity such as
  • an N channel type SGT and a P channel type SGT are formed on the second semiconductor substrate 9, which is the same semiconductor substrate, in substantially the same manner as in the first and third embodiments (FIGS. 1A to 1D). 1J, see FIGS. 3A and 3B).
  • N + polycrystalline silicon layers 55a functioning as sources and P + many functioning as drains.
  • the crystalline silicon layers 55b are electrically connected to each other by the metal layers 7aa and 7bb, the first connection metal layer 7a, and the second connection metal layer 7b.
  • the metal layer 7 is formed by vapor deposition and etching so as to cover the silicon layers to be the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b. . Then, the metal layer 7, the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b are formed into a predetermined shape by etching. Thereby, as shown in FIG. 4, an N + polycrystalline silicon layer 55a, a P + polycrystalline silicon layer 55b, metal layers 7aa and 7bb, and a first connection metal layer 7a are formed.
  • a silicon oxide layer 20 is formed on the first connection metal layer 7a, and a contact hole 21c is formed in the silicon oxide layer 20.
  • the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b and the external metal wiring layer 22c formed on the silicon oxide layer 20 through the contact hole 21c and the first connection metal layer 7a.
  • a second connection metal layer 7b is formed in a portion extending from the first connection metal layer 7a, and the second connection metal layer 7b is used to electrically connect from a predetermined location through a contact hole (not shown). Take out the contact.
  • metal layers 7aa and 7bb are bonded to the entire back surfaces of N + polycrystalline silicon layers 55a and 55b that function as drains of the N-channel SGT, respectively.
  • the N + diffusion layers 6a and 6b and the plurality of metal layers 7aa and 7bb which are one of the plurality of metal layers 7aa and 7bb are connected to each other.
  • both of the N + diffusion layers 6a and 6b and the plurality of metal layers 7aa and 7bb may be connected to each other.
  • the N + polycrystalline silicon layer 55a functions as an N-channel SGT source
  • the P + polycrystalline silicon layer 55b functions as a P-channel SGT drain.
  • the present invention is not limited to this, and the N + polycrystalline silicon layer 55a can also function as an N-channel SGT drain and the P + polycrystalline silicon layer 55b can function as a P-channel SGT source. Further, both the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b may function as a source or a drain.
  • the source and drain constituted by the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b are arranged on the upper surface of the silicon oxide layer 20.
  • the metal wiring layers 22a, 22b, and 22c are electrically connected to each other by the first connection metal layer 7a without being connected after being drawn out through a contact hole or the like. Thereby, the integration degree of the circuit element which has SGT can be raised.
  • the semiconductor device manufacturing method according to the present embodiment can be applied to a solid-state imaging device manufacturing method.
  • the drains of the pixels are connected to each other by the first connection metal layer 7a. Connect with.
  • the drain and source of each pixel need not be connected to each other after being connected to another metal wiring in the upper layer portion via a contact hole or the like. For this reason, further high integration of the pixels of the solid-state imaging device is realized.
  • FIGS. 5A to 5C a method for forming an electrical resistance in a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 5A to 5C.
  • the manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
  • an electrical resistance which is a circuit element of the semiconductor device is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
  • a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
  • a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
  • a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3, and in the process shown in FIG. 1C, phosphorus (P) or The N + polycrystalline silicon layer 5a is formed by ion doping with a donor impurity such as arsenic (As).
  • a donor impurity such as arsenic (As).
  • N + polycrystalline silicon layers 23a and 23b are formed by ion doping with a donor impurity such as) at a predetermined concentration.
  • the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 in which the donor impurity is not ion-doped reduce the electric resistance value in a predetermined region (polycrystalline silicon layer 23) of the polycrystalline silicon layer 5 and A resistance is formed.
  • the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 are formed from the polycrystalline silicon layer 5 (see FIG. 1B) in the same manner as the N + polycrystalline silicon layer 5a (see FIG. 1C). Therefore, it is located in the same layer as the N + polycrystalline silicon layer 5a.
  • metal wiring layers 24a and 24b located in the same layer as the metal layer 7 are formed in the same manner as the metal layer 7 on the N + polycrystalline silicon layers 23a and 23b.
  • a predetermined region of the polycrystalline silicon layer 5 is ion-doped with a donor impurity having a predetermined concentration, so that N + polycrystalline silicon layers 23a and 23b having a predetermined electric resistance value, polycrystalline silicon Layer 23 is formed.
  • the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23 are formed in the same layer as the N + polycrystalline silicon layer 5a.
  • the polycrystalline silicon layer 25 is formed in the step shown in FIG. 1B and formed into a predetermined shape by etching
  • the polycrystalline silicon layer is formed by vapor deposition or CVD.
  • Metal wiring layers 26 a and 26 b connected to the layer 25 are formed. In this way, electrical resistance in the semiconductor device is also formed by the polycrystalline silicon layer 25.
  • the second silicon oxide layer 8 is formed on the second semiconductor substrate 9, and the N + is formed on the second silicon oxide layer 8 by the method described above.
  • Polycrystalline silicon layers 23a and 23b and a polycrystalline silicon layer 23 are formed.
  • the first silicon oxide layer 3 is formed on the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23, and the silicon oxide layer 20 (see FIG. 4) is formed on the first silicon oxide layer 3. It is also possible to do.
  • the electrical resistance shown in FIG. 5A is formed from the N + polycrystalline silicon layers 23a and 23b and the polycrystalline silicon layer 23.
  • a circuit element or metal wiring having SGT is formed on the first silicon oxide layer 3. Further, in the modification shown in FIG. 5C, the polycrystalline silicon layer 23 constituting the electric resistance is formed below the first silicon oxide layer 3 which is an insulator.
  • the upper and lower sides of the SiO 2 layer (first silicon oxide layer 3) are shown in FIG. 4 so as to overlap with the polycrystalline silicon layer 23 constituting the electric resistance.
  • the metal wiring layers 22a, 22b and 22c of the circuit element can be formed. Thereby, further high integration of the semiconductor device (circuit element) having electric resistance is realized.
  • FIGS. 6A to 6C a method of forming a capacitor in a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 6A to 6C.
  • the manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
  • a capacitor which is a circuit element of a semiconductor device, is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
  • a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
  • a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
  • a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3, and in the process shown in FIG. 1C, phosphorus (P) or The N + polycrystalline silicon layer 5a is formed by ion doping with a donor impurity such as arsenic (As).
  • a donor impurity such as arsenic (As).
  • capacitive silicon oxide layer 27 is formed on the surface layer portion of N + polycrystalline silicon layer 5a by thermal oxidation or CVD.
  • the capacitor silicon oxide layer 27 functioning as a capacitor insulating film is formed into a predetermined shape in the capacitor region where the capacitor is formed by etching using a mask.
  • a metal layer 28 that functions as a capacitor electrode is formed on the capacitor silicon oxide layer 27 formed in a predetermined shape by vapor deposition or CVD.
  • the metal layer 28 is formed in the same layer as the metal layer 7 of the first embodiment.
  • a laminated structure as shown in FIG. 6C is formed. That is, a second silicon oxide layer 8 is formed on the second semiconductor substrate 9, and inside the second silicon oxide layer 8, a metal layer 28 functioning as a capacitor electrode is formed in a capacitor region where a capacitor is formed, and A capacitive silicon oxide layer 27 that is stacked on the metal layer 28 and functions as a capacitive insulating film is disposed. Then, the N + polycrystalline silicon layer 5a, the first silicon oxide layer 3 and the silicon oxide layer 29 (silicon oxide layer 20) are stacked in this order on the capacitive silicon oxide layer 27 and the second silicon oxide layer 8. Is obtained. In this structure, the metal layer 28 and the N + polycrystalline silicon layer 5a function as a capacitor electrode, and a capacitor in which the capacitor silicon oxide layer 27 functions as a capacitor insulating film is formed.
  • the process of forming the insulating layer 27 on the surface layer of the N + polycrystalline silicon layer 5a (see FIG. 6A).
  • a step of forming the capacitive silicon oxide layer 27 and the metal layer 28 see FIG. 6B.
  • a method of forming a capacitor in a semiconductor device according to a seventh embodiment of the present invention will be described.
  • the manufacturing process of the semiconductor device according to the present embodiment is the same as that of the first embodiment, except as described below.
  • a capacitor which is a circuit element of a semiconductor device, is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
  • a separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
  • a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
  • the capacitance forming region 100 shown in FIG. 7A is set on the first silicon oxide layer 3, and the capacitance forming region 100 in this capacitance forming region 100 is set.
  • a concave silicon oxide layer removal region is formed. That is, in the step shown in FIG. 1B, as shown in FIG. 7A, the silicon oxide layers 101a and 101b are left around the silicon oxide layer removal region, and the silicon oxide layer removal region has a silicon oxide layer.
  • a silicon oxide layer 103 having a thickness smaller than those of 101a and 101b is left.
  • acceptor impurities such as boron (B) are ion-doped or thermally diffused, whereby the surface layer of the first semiconductor substrate 1 in the capacitor formation region 100 through the silicon oxide layer 103.
  • the P + diffusion layer 102 is formed.
  • a polycrystalline silicon layer 5 is formed on the first silicon oxide layer 3 so as to embed a silicon oxide layer removal region.
  • the polysilicon layer 5 is ion-doped with a donor impurity such as phosphorus (P) or arsenic (As) to form an N + polycrystalline silicon layer 104 (see FIG. 1C). (See FIG. 7A).
  • a donor impurity such as phosphorus (P) or arsenic (As)
  • a metal layer 105 is formed on the N + polycrystalline silicon layer 104 by vapor deposition or CVD (see FIG. 7A).
  • the metal layer 105 is formed in the same layer as the metal layer 7 in the first embodiment.
  • the N + polycrystalline silicon layer 104 and the N + polycrystalline silicon layer 104 are formed and function as a capacitor electrode.
  • the metal layer 105 to be formed is formed into a predetermined shape.
  • the P + diffusion layer 102 is left in the silicon pillar 1a, and the P + diffusion layer 102 and the oxidation layer are oxidized.
  • a silicon oxide layer 107 is formed so as to cover the silicon layers 101a and 101b.
  • a contact hole 108 is formed in the silicon oxide layer 107, and the metal wiring layer 109 and the P + diffusion layer 102 on the silicon oxide layer 107 are electrically connected via the contact hole 108. Connect to.
  • the N + polycrystalline silicon layer 104, the metal layer 105, and the P + diffusion layer 102 function as a capacitor electrode in the capacitor formation region 100 (see FIG. 7A).
  • a capacitor is formed in which the silicon oxide layer 103 between 101a and 101b functions as a capacitor insulating film.
  • the P + diffusion layer 102 is formed by ion doping or thermal diffusion of acceptor impurities such as boron (B) into the first semiconductor substrate 1 using the silicon oxide layers 101a and 101b as a mask.
  • acceptor impurities such as boron (B)
  • the P + diffusion layer 102 performs ion doping with a high acceleration voltage on the first silicon oxide layer 3 (see FIG. 1A) having a uniform thickness before the silicon oxide layers 101a and 101b are formed. Thus, it can be formed in a predetermined region other than the capacitance forming region 100.
  • the contact hole 108 enables connection between capacitors and extraction of an electric signal to an external circuit from an arbitrary location of the semiconductor device. As a result, further integration of circuit elements can be realized.
  • FIGS. 8A to 8C a method for forming a diode in a semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIGS. 8A to 8C.
  • the manufacturing process of the semiconductor device according to the present embodiment and the modification thereof is the same as that of the first embodiment except for the case specifically described below.
  • a diode which is a circuit element of a semiconductor device is formed by using the polycrystalline silicon layer 5 formed on the first semiconductor substrate 1 shown in FIG. 1B.
  • the second silicon oxide layer 8 is formed on the second semiconductor substrate 9 as shown in FIG. 8A through the steps shown in FIGS. 1A to 1I of the first embodiment.
  • the metal layer 7, the N + polycrystalline silicon layer 5a, and the silicon pillar 1a are formed in this order from below.
  • a first silicon oxide layer 3 is formed around the N + polycrystalline silicon layer 5a.
  • an ion impurity is doped with an acceptor impurity such as boron (B) to thereby form a P-type silicon layer shown in FIG. 8B. 30 is formed.
  • acceptor impurity such as boron (B)
  • N + diffusion layer 6a is formed.
  • ion implantation of acceptor impurities such as boron (B) is formed on the upper portion of the P-type silicon layer 30 (silicon pillar 1 a), thereby forming a P + -type silicon layer 31.
  • the metal layer 32 is formed on the P + type silicon layer 31 by vapor deposition and etching.
  • a silicon oxide layer 33 is formed so as to cover the P-type silicon layer 30 and the metal layer 32.
  • contact holes 34, The metal wiring layer 35 is formed in this order. Thereby, the metal wiring layer 35 and the metal layer 32 are electrically connected via the contact hole 34.
  • a pn junction diode is formed by the P + type silicon layer 31 and the P type silicon layer 30.
  • a diode circuit element
  • a semiconductor device such as SGT
  • FIG. 8C shows a modification of this embodiment in which a PIN photodiode is formed on the silicon pillar 1a.
  • an i-type silicon layer 30b which is a unique semiconductor, is formed on the silicon pillar 1a shown in the eighth embodiment instead of the P-type silicon layer 30.
  • a P + type silicon layer 31 is formed on the i type silicon layer 30b.
  • a PIN photodiode is formed by the i-type silicon layer 30 b and the P + -type silicon layer 31.
  • the depletion layer is formed in the entire i-type silicon layer 30b or in a wide area, so that a wide photoelectric conversion area can be secured and the thickness of the capacitance formation area can be increased. Since the thickness of the corresponding depletion layer is increased, the capacity can be reduced.
  • the PIN photodiode is formed as an optical connection light receiving element on the same semiconductor substrate as the circuit element of the semiconductor device.
  • the PIN photodiode of this modification functions as an optical switch, there is no RC delay due to the resistance / capacitance of the input circuit wiring, and the speed of the circuit input section and the speed of the entire circuit can be increased.
  • a PIN photodiode (circuit element) can be formed on the same semiconductor substrate together with a pixel of a solid-state imaging device, a semiconductor device such as SGT, and the manufacturing process can be simplified. become.
  • FIG. 9A shows a CMOS inverter circuit used in this embodiment.
  • a P-channel MOS transistor 37a and an N-channel MOS transistor 37b are connected in series.
  • the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b are connected through a gate connection wiring 38, and the gate connection wiring 38 is connected to the input terminal wiring Vi.
  • the source of the P-channel MOS transistor 37a is connected to the power supply terminal wiring Vdd.
  • the drain of the P-channel MOS transistor 37a and the drain of the N-channel transistor 37b are connected to the output terminal wiring Vo via the drain connection wiring 39, and the source of the N-channel MOS transistor 37b is at the ground potential. It is connected to the ground terminal wiring Vss.
  • FIG. 9B shows a plan layout of this CMOS inverter circuit. As shown in FIG. 9B, the contact hole 41c, the silicon pillar 40a, the contact hole 41a, the contact hole 41b, and the contact hole 41d are arranged in a straight line.
  • the input terminal wiring Vi is for inputting an electric signal (gate voltage) from the contact hole 41c.
  • the power supply terminal wiring Vdd is for supplying a power supply voltage from the contact hole 41a.
  • the ground terminal wiring Vss is for connecting to the ground via the contact hole 41b.
  • the output terminal wiring Vo is for outputting an electrical signal from the contact hole 41d.
  • the contact hole 41c is formed on the gate connection wiring 38 that connects the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b.
  • the silicon pillar 40a constitutes a P channel type MOS transistor 37a.
  • the contact hole 41a is formed on the silicon pillar 40a.
  • the silicon pillar 40b constitutes an N channel type MOS transistor 37b.
  • the contact hole 41b is formed on the silicon pillar 40b.
  • the contact hole 41d is formed on a drain connection wiring 39 that connects the drain of the P-channel MOS transistor 37a and the drain of the N-channel MOS transistor 37b to each other.
  • the input terminal wiring Vi, the power supply terminal wiring Vdd, the ground terminal wiring Vss, and the output terminal wiring Vo are arranged so as to extend in the row direction orthogonal to the column direction of the contact holes 41b and 41d, respectively. (See FIG. 9A).
  • FIG. 9C is a sectional structural view taken along line B-B ′ of FIG. 9B.
  • a method of forming the above-described CMOS inverter circuit will be described with reference to FIG. 9C.
  • the process of forming the CMOS inverter circuit is the same as that of the first embodiment, except as specifically described below.
  • the CMOS inverter circuit having the P-channel MOS transistor 37a and the N-channel MOS transistor 37b shown in FIG. 9C is the same as the N-channel MOS transistor and the P-channel type in the CMOS inverter circuit shown in FIG. 3B.
  • the left and right positional relationship with the MOS transistor is switched, it is formed in the same manner as the third embodiment shown in FIGS. 3A and 3B.
  • the description of the parts indicated by the same or corresponding symbols as those of the above embodiment will be omitted.
  • a drain connection wiring 39 is formed below the P + polycrystalline silicon layer 55b functioning as the drain in the P-channel MOS transistor 37a and the N + polycrystalline silicon layer 55a functioning as the drain in the N-channel MOS transistor 37b.
  • a drain connection wiring 39 is formed.
  • a drain connection wiring 39 is bonded to the lower surfaces of the N + polycrystalline silicon layer 55a and the P + polycrystalline silicon layer 55b.
  • the N + polycrystalline silicon layer 55 a and the P + polycrystalline silicon layer 55 b are connected via the drain connection wiring 39.
  • the drain connection wiring 39 is formed on the insulating layer 43 b and is connected to the output terminal wiring layer Vo through a contact hole 41 d penetrating the silicon oxide layer 45.
  • the gate conductor layers 16ba and 16bb of the P-channel MOS transistor 37a and the gate conductor layers 16aa and 16ab of the N-channel MOS transistor 37b are connected through a gate connection wiring 38 formed on the insulating layer 43a. ing.
  • the metal wiring layer 18a and the drain connection wiring 39 formed above are input terminal wirings formed on the silicon oxide layer 45 through contact holes 41c, 41a, 41b and 41d penetrating the silicon oxide layer 45, respectively.
  • the layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vo are connected.
  • the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vo are wired in parallel to each other (see FIG. 9C).
  • the P + polycrystalline silicon layer 55b functioning as a drain in the P-channel MOS transistor 37a and the N + polycrystalline silicon layer 55a functioning as a drain in the N-channel MOS transistor 37b are close to each other.
  • the drain connection wiring 39 having a low electric resistance is electrically connected.
  • FIG. 10A shows a CMOS inverter circuit having a two-stage structure used in this embodiment.
  • P-channel MOS transistors 37a and 37c and N-channel MOS transistors 37b and 37d are connected in series at the first and second stages, respectively.
  • the gates of the first-stage P-channel MOS transistor 37a and N-channel MOS transistor 37b are connected to the input terminal wiring Vi through the gate connection wiring 38a.
  • the gates of the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37d are connected to the first-stage output terminal wiring Vo through the gate connection wiring 38b.
  • the drains of the first-stage and second-stage P-channel MOS transistors 37a and 37c are connected to the power supply terminal wiring Vdd.
  • the sources of the first-stage and second-stage P-channel MOS transistors 37b and 37d are connected to the ground terminal wiring Vss.
  • the drain of the P-channel MOS transistor 37a and the drain of the N-channel transistor 37b are connected to the first-stage output terminal wiring Vo via the drain connection wiring 39a.
  • the drain of the P-channel transistor 37c and the drain of the N-channel transistor 37d are connected to the output terminal wiring Vout via the drain connection wiring 39b.
  • FIG. 10B shows a plan layout of this CMOS inverter circuit.
  • a contact hole 41c is formed on the gate connection wiring 38a formed on the silicon pillar 40a constituting the first-stage P-channel MOS transistor 37a and the silicon pillar 40b constituting the N-channel MOS transistor 37b.
  • the contact hole 41c is connected to the input terminal wiring Vi.
  • the gate connection wiring 38a connects the gates of the P-channel MOS transistor 37a and the N-channel MOS transistor 37b.
  • the drain of the P-channel MOS transistor 37a and the drain of the N-channel MOS transistor 37b are connected via the first-stage drain connection wiring 39a.
  • a contact hole 41e is formed on the gate connection wiring 38b formed in the silicon pillar 40c constituting the second-stage P-channel MOS transistor 37c and the silicon pillar 40d constituting the N-channel MOS transistor 37d. It is connected to the first-stage output terminal wiring Vo (see FIG. 10A).
  • the first-stage drain connection wiring 39a is connected to the gate connection wiring 38b through the contact hole 41e (see FIG. 10C).
  • the gate connection wiring 38b connects the gates of the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37d.
  • Contact holes 41a and 41c are formed on the silicon pillars 40a and 40c of the first-stage and second-stage P-channel MOS transistors 37a and 37c, respectively.
  • the contact holes 41a and 41c are both connected to the power supply terminal wiring layer Vdd.
  • Contact holes 41b and 41d are formed on the silicon pillars 40b and 40d of the first-stage and second-stage P-channel MOS transistors 37b and 37d, respectively, and both of the contact holes 41b and 41d are connected to the ground terminal wiring layer Vss. Has been.
  • a contact hole 41f is formed on the second-stage drain connection wiring 39b, and the contact hole 41f is connected to the output terminal wiring layer Vout.
  • the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other.
  • FIG. 10C is a cross-sectional structural view taken along the line C-C ′ of FIG. 10B.
  • the above-described two-stage CMOS inverter circuit will be described with reference to FIG. 10C.
  • the two-stage CMOS inverter circuit is formed in the same manner as in the first embodiment.
  • CMOS inverter circuit having the P-channel MOS transistor 37a and the N-channel MOS transistor 37b shown in FIG. 10C is the same as the CMOS inverter circuit shown in FIG. 3B in terms of the left and right sides of the N-channel MOS transistor and the P-channel MOS transistor. However, they are formed in the same manner as the third embodiment shown in FIGS. 3A and 3B.
  • the conductor layers 16aa and 16ab are connected via the gate connection wiring 38a.
  • a contact hole 41b connected to the metal wiring layer 18a on the N-channel MOS transistor 37b is formed in the silicon oxide layer 45 formed on the gate connection wiring 38a.
  • the contact hole 41b is connected to the ground terminal wiring Vss of the N channel type MOS transistor 37b.
  • a silicon oxide layer 43 is formed between the first silicon oxide layer 3 and the gate connection wiring 38a.
  • the N + polycrystalline silicon layer 55a functioning as the drain is electrically connected to each other through the metal wiring layer 42 which is the first-stage drain connection wiring 39a.
  • the metal wiring layer 42 is connected via a gate connection wiring 38b that connects the gates of the second-stage P-channel MOS transistor 37c and the N-channel MOS transistor 37d, and a contact hole 41e formed in the silicon oxide layer 45. Are connected (see FIGS. 10A and 10B).
  • a contact hole 41a is formed on the silicon pillar 40a of the first-stage P-channel MOS transistor 37a, and the contact hole 41a is connected to the power supply terminal wiring layer Vdd.
  • a contact hole 41b is formed on the silicon pillar 40b of the first-stage N-channel MOS transistor 37b, and the contact hole 41b is connected to the ground terminal wiring layer Vss.
  • a contact hole 41f is formed on the second-stage drain connection wiring 39b, and the output terminal wiring layer Vout is connected to the contact hole 41f on the silicon oxide layer 45 (see FIGS. 10A and 10B). Further, the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout are wired in parallel to each other (see FIG. 10B).
  • the metal wiring layer 42 functioning as the drain connection wiring 39a of the first-stage P-channel MOS transistor 37a and N-channel MOS transistor 37b is replaced with the second-stage P-channel MOS transistor 37c and N-channel MOS transistor 37c.
  • the channel type MOS transistor 37d is directly connected to the gate connection wiring 38b via the contact hole 41e.
  • the metal wiring layer 42 (39a) is connected to the input terminal wiring layer Vi, the power supply terminal wiring layer Vdd, the ground terminal wiring layer Vss, and the output terminal wiring layer Vout through the contact holes formed in the silicon oxide layer 45 (FIG. 10B), it is not necessary to pull up to the same layer as that, so that high integration of circuit elements is realized.
  • FIGS. 11A and 11B a method for forming a mask alignment mark on a semiconductor substrate according to an eleventh embodiment of the present invention will be described with reference to FIGS. 11A and 11B.
  • the process shown in FIG. 11A corresponds to the process shown in FIG. 1H in the first embodiment.
  • the other steps are the same as those in the first embodiment except for the case specifically described below.
  • a second silicon oxide layer 8 is formed on the second semiconductor substrate 9.
  • the first silicon oxide layer 3 and the first semiconductor substrate 1 are formed in this order.
  • a mask alignment mark formation region 47a for mask alignment and a circuit formation region 47b for forming a circuit are set at predetermined positions on the first semiconductor substrate 1.
  • a silicon oxide layer removal region 48 is formed in the first silicon oxide layer 3 (see FIG. 1B). At the center of the silicon oxide layer removal region 48, a mark metal layer 49a and a mark polycrystalline silicon layer 49b are formed in a laminated state.
  • the silicon oxide layer removal region 48 is formed simultaneously with the hole 4 in which the source or drain of the junction transistor in the pixel of the solid-state imaging device is formed.
  • a metal layer 7 and an N + polycrystalline silicon layer 5a are formed in a laminated state in the center of the circuit formation region 47b (see FIG. 1H).
  • a mask alignment hole 50 is formed at a predetermined position as shown in FIG. 11B.
  • the mark metal layer 49 a, the mark polycrystalline silicon layer 49 b, and the silicon oxide layer removal region 48 are exposed through the mask alignment hole 50.
  • the mask alignment of the photomask is performed using any one of the mark metal layer 49a, the mark polycrystalline silicon layer 49b, and the silicon oxide layer removal region 48 in the mask alignment hole 50 as a reference mask alignment mark. Do.
  • a photomask is overlaid on the region where the photoresist is formed, and light is irradiated to transfer the circuit.
  • the first semiconductor substrate 1 is covered with a photoresist, and the mark metal layer 49a and the mark polycrystalline silicon layer located below the first semiconductor substrate 1 are covered.
  • Mask alignment is performed using either of 49b and the silicon oxide layer removal region 48 as a mark.
  • the first semiconductor substrate 1 is made of silicon and absorbs blue light and ultraviolet light. Therefore, red wavelength light or infrared light having high transmittance is used for mask alignment. For this reason, the resolution of the mark image is lowered and the mask alignment accuracy is lowered.
  • the mask alignment mark formation region 47a does not include a silicon layer that absorbs a large amount of blue light and ultraviolet light, so the mark metal layer 49a, the mark polycrystalline silicon layer 49b, the oxidation layer A photoresist can be formed directly on the silicon layer removal region 48. For this reason, a high-resolution mark image is obtained, and the mask alignment accuracy is improved.
  • the photoresist is directly formed on the silicon oxide layer removal region 48, the alignment accuracy between the N + polycrystalline silicon layer 5a and the silicon pillar 1a shown in FIG. .
  • a transparent insulating layer 50a that transmits blue light or ultraviolet light is embedded in the mask alignment hole 50 shown in FIG. 11B.
  • An SiO 2 film is used for the transparent insulating layer 50a. Thereafter, the SiO 2 film and the surface of the first semiconductor substrate 1 are planarized by CMP. The step of filling the mask alignment hole 50 with the SiO 2 film is performed before the silicon pillar 1a on which the junction transistor is formed is formed with reference to FIG. 1I.
  • the transparent insulating layer 50a in the mask alignment hole 50 can make the photoresist covering the mask alignment mark formation region 47a and the circuit formation region 47b thin and uniform. Compared with the embodiment, the mask alignment accuracy is further improved.
  • FIG. 13A corresponds to the step shown in FIG. 1B in the first embodiment.
  • the other steps are the same as those in the first embodiment except for the case specifically described below.
  • the separation layer 2 for separating the first semiconductor substrate 1 into two upper and lower portions is formed at a predetermined depth of the first semiconductor substrate 1.
  • a first silicon oxide layer 3 as an insulator is formed on the first semiconductor substrate 1.
  • holes 4 are formed in the first silicon oxide layer 3 by removing silicon oxide (SiO 2 ) in a predetermined region.
  • polycrystalline silicon is formed on the first silicon oxide layer 3 and the first semiconductor substrate 1 by the CVD method so as to fill the hole 4 (silicon oxide layer removal region 48).
  • Layer 111 is formed. This polycrystalline silicon layer 111 is not doped with donor impurities or acceptor impurities.
  • an N + polycrystalline silicon layer 106 doped with donor impurities is formed on the polycrystalline silicon layer 111 by CVD and ion doping of donor impurities.
  • a metal layer 7 is formed on the N + polycrystalline silicon layer 106 in the same manner as the step shown in FIG. 1D. Further, a semiconductor device is formed in the same manner as the steps shown in FIGS. 1E to 1L.
  • the polycrystalline silicon layer 111 which is not doped with impurities is formed between the first semiconductor substrate 1 and the N + polycrystalline silicon layer 106. Due to the presence of the polycrystalline silicon layer 111, the diffusion depth of the donor impurity to the silicon pillar 1a when the N + polycrystalline silicon layer 106 is used as a diffusion source by the heat treatment in the step shown in FIG. 1J can be adjusted. it can.
  • the donor impurity is diffused from the N + polycrystalline silicon layer 106 by heat treatment, so that the polycrystalline silicon layer 111 becomes an N + polycrystalline silicon layer. Then, by diffusing donor impurities by heat treatment of N + polysilicon layer 111 in the silicon pillar 1a to form the N + diffusion layer 6a.
  • the polycrystalline silicon layer 111 not doped with donor impurities by heat treatment into an N + polycrystalline silicon layer, the diffusion performance of donor impurities from the N + polycrystalline silicon layer 106 to the outside is reduced.
  • N 2 is changed depending on the heat treatment conditions (temperature, time) after bonding the second semiconductor substrate 9 and the second silicon oxide layer 8 on the first semiconductor substrate 1.
  • the + diffusion layer 6a is assumed to diffuse beyond a desired depth, this is effective for suppressing the diffusion depth.
  • a P + polycrystalline silicon layer can be used in place of the N + polycrystalline silicon layer 106. Even if the polycrystalline silicon layer 111 that is not doped with donor impurities or acceptor impurities contains a small amount of impurities even if they are not actively doped, the effect of this embodiment is not affected.
  • the first silicon oxide layer 3 is formed by thermal oxidation, anodization, CVD (Chemical Vapor Deposition), or the like. Formed.
  • CVD Chemical Vapor Deposition
  • the present invention is not limited to this, and a multilayer structure with another insulating film such as a silicon nitride (SiN) film may be used.
  • the present invention is not limited to the embodiments described in the first to twelfth embodiments described above, and various modifications can be made.
  • the first semiconductor substrate 1 is P-type conductivity.
  • the first semiconductor substrate 1 is not limited to this, and may be i-type (intrinsic type) which is a unique semiconductor. Further, depending on the circuit element formed on the first semiconductor substrate 1, an N-type conductivity type may be used.
  • the channel of the P-channel MOS transistor is formed in the N-type silicon layer 30a, and the channel of the N-channel MOS transistor is the P-type silicon layer.
  • the channel of the N-channel MOS transistor may be formed on i-type silicon which is a unique semiconductor.
  • the N + polycrystalline silicon layer 5a, the metal layer 7, and the N + diffusion layer 6a are used as individual material layers.
  • the metal layer 7 is reacted with the metal material (Ni, W, etc.) of the metal layer 7 and a part of the N + polycrystalline silicon layer 5a or the N + diffusion layer 6a. 7.
  • All or part of the N + polycrystalline silicon layer 5a or the N + diffusion layer 6a may be changed to a silicide layer (NiSi, WSi, etc.).
  • the temperature is 400 to 600 ° C.
  • the first semiconductor substrate 1 was separated into a top and bottom by heat treatment, and the first semiconductor substrate 1 was thinned to a predetermined thickness.
  • a method of forming a porous layer in the separation layer 2 shown in Non-Patent Document 3 may be employed to reduce the thickness of the first semiconductor substrate 1 to a predetermined thickness.
  • a method of separating the first semiconductor substrate 1 vertically can be employed.
  • the second semiconductor substrate 9 may be a semiconductor different from silicon, for example, a compound semiconductor such as silicon carbide (SiC), an insulator, or an organic resin body. Also with this configuration, the circuit elements formed on the first semiconductor substrate 1 can be held.
  • the second silicon oxide layer 8 and the silicon oxide layers 20, 29, 45 may have a multilayer structure with other insulating films such as a silicon nitride (SiN) film.
  • SiN silicon nitride
  • the N + polycrystalline silicon layers 5a and 55a and the P + polycrystalline silicon layer 55b were formed by ion doping.
  • the present invention is not limited to this, and it may be formed by thermal diffusion of impurities or a doped polycrystalline silicon layer mixed with impurities.
  • the polycrystalline silicon layer 5 was formed by a CVD method.
  • the present invention is not limited to this, and the polycrystalline silicon layer 5 may be formed by epitaxial growth.
  • a single crystal silicon layer is grown on the first semiconductor substrate 1, and a polycrystalline silicon layer is formed on the first silicon oxide layer 3 depending on the growth conditions.
  • the single crystal silicon layer becomes a diffusion source to the silicon pillar 1a of the donor or acceptor.
  • the silicon layer can be prevented from being formed on the first silicon oxide layer 3 depending on the growth conditions (temperature, etc.) of the single crystal silicon layer.
  • the second semiconductor substrate 9 made of silicon and the second silicon oxide layer 8 flattened by CMP are bonded together, and an oxide layer is formed on the surface of the second semiconductor substrate 9 by oxidation or CVD.
  • the second semiconductor substrate 9 and the second silicon oxide layer 8 can be bonded after the insulating layer is formed.
  • the drain connection wiring 39 and the output terminal wiring Vo are connected via the contact hole 41d.
  • the drain connection wiring 39 and the output terminal wiring Vo can be connected so that the bottom of the contact hole 41 d is in contact with the N + polycrystalline silicon layer 55 a on the drain connection wiring 39. Also with this configuration, the electrical resistance of the N + polycrystalline silicon layer 55a is sufficiently small, so that high-speed operation of the circuit element is realized.
  • the metal wiring layer 42 (39a) functioning as the drain connection wiring and the second-stage gate connection wiring 38b are connected via the contact hole 41e.
  • the connection is not limited to this, and the contact hole 41 e can be connected so that the bottom thereof is in contact with the N + polycrystalline silicon layer 55 a on the metal wiring layer 42. Also with this configuration, the electrical resistance of the N + polycrystalline silicon layer 55a is sufficiently small, so that high-speed operation of the circuit element is realized.
  • gate conductor layers 11a, 11b, 11c, 11d, 16a, 16b, 16c, 16d, and gate connection wirings 38, 38a, as shown in FIG. 10C, as shown in FIG. 1L, FIG. 2, and FIG. 38b was formed by a vapor deposition method or a CVD method.
  • the present invention is not limited to this, and a single layer or a plurality of different types of metal layers, a polycrystalline silicon layer doped with impurities, or a multilayer configuration of the polycrystalline silicon layer and the metal layer may be used.
  • the gate connection wirings 38, 38a, and 38b may use different materials for the N channel type and the P channel type.
  • the two-stage CMOS inverter circuit shown in FIGS. 10B and 10C can be configured as follows. That is, the P + -type silicon layer 17b and the N + -type silicon layer 17a in the upper part of the silicon pillar 40a of the P-channel MOS transistor 37a and the silicon pillar 40b of the N-channel MOS transistor 37b are formed in the silicon oxide layer 45. It is connected to the first-stage output terminal wiring layer Vout through the formed contact holes 41a and 41b.
  • the metal layer 46b connected to the P + polycrystalline silicon layer 55b and the P + diffusion layer 6b below the silicon pillar 40a of the P channel MOS transistor 37a is used as a power supply terminal wiring layer Vdd, and N channel
  • the metal layer 46a connected to the N + polycrystalline silicon layer 55a and the N + diffusion layer 6a below the silicon pillar 40b of the type MOS transistor 37b is defined as a ground terminal wiring layer Vss. Also in this structure, the same effect as the structure shown in FIG. 10C can be obtained.
  • arsenic is formed after the gate conductor layers 11a and 11b are formed in order to perform self-alignment between the gate conductor layers 11a and 11b and the N + diffusion layer 6a serving as a signal line.
  • the N + -type silicon layer may be formed in the silicon pillar 1a between the gate conductor layers 11a and 11b and the N + diffusion layer 6a by using the ion doping or the deposited As-doped silicon oxide layer as a diffusion source.
  • the first semiconductor substrate 1 is etched to the surface of the first silicon oxide layer 3 to form the silicon pillar 1a. It may be stopped before reaching the surface of the layer 3.
  • an N + type silicon layer may be formed by doping a remaining silicon layer without being etched with a donor impurity.
  • arsenic (As) ion doping or deposition As doping is performed in order to perform self-alignment between the gate conductor layers 16a and 16b and the N + diffusion layer 6a serving as the source or drain.
  • An N + type silicon layer may be formed in the silicon pillar 1a between the gate conductor layers 16a and 16b and the N + diffusion layer 6a using the silicon oxide layer as a diffusion source.
  • the third silicon oxide layer 10a on the outer peripheral portion of the N-type silicon layers 12a and 12b constituting the photodiode, A conductor layer that reflects light through 10b may be formed. This prevents color mixing. Further, by forming a P + -type silicon layer connected to the P + -type silicon layer 13 a in the silicon pillar 1 a on the outer periphery of the N-type silicon layers 12 a and 12 b, it is possible to realize a low afterimage and low noise. Good. As described above, a structure in which the function of the solid-state imaging device is further enhanced can be appropriately formed in the silicon pillar 1a.
  • the present invention can be applied to a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure.

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

L'invention concerne un procédé de production pour un dispositif semi-conducteur comportant : une étape dans laquelle une couche conductrice (7) et une première couche semi-conductrice (5a), comprenant des impuretés de donneurs ou des impuretés d'accepteurs sont formées sur un premier substrat semi-conducteur ; une étape dans laquelle une seconde couche isolante (8) est formée de manière à recouvrir la première couche semi-conductrice (5a) ; une étape dans laquelle l'épaisseur du premier substrat semi-conducteur (9) est réduite à une épaisseur prédéfinie ; une étape dans laquelle un semi-conducteur en colonne (1a) ayant une structure de colonne est formé à partir du premier substrat semi-conducteur sur la première couche semi-conductrice (5a) ; une étape dans laquelle une première aire semi-conductrice (6a) est formée sur le semi-conducteur en colonne (1a) en dispersant des impuretés de la première couche semi-conductrice (5a) ; et une étape dans laquelle des pixels pour un dispositif d'imagerie à l'état solide sont formés au moyen du semi-conducteur en colonne (1a) après que les impuretés ont été dispersées.
PCT/JP2011/055408 2011-03-08 2011-03-08 Procédé de production pour dispositif semi-conducteur et dispositif semi-conducteur Ceased WO2012120653A1 (fr)

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CN2012800004124A CN102792452A (zh) 2011-03-08 2012-02-07 半导体器件的制造方法及半导体器件
JP2012521405A JP5114608B2 (ja) 2011-03-08 2012-02-07 半導体装置の製造方法、及び、半導体装置
PCT/JP2012/052777 WO2012120951A1 (fr) 2011-03-08 2012-02-07 Procédé de production pour dispositif semi-conducteur et dispositif semi-conducteur
KR1020127015784A KR101350577B1 (ko) 2011-03-08 2012-02-07 반도체 장치의 제조 방법 및 반도체 장치
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