WO2012106876A1 - 计算机系统中子网管理方法、总线适配器及计算机系统 - Google Patents
计算机系统中子网管理方法、总线适配器及计算机系统 Download PDFInfo
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- WO2012106876A1 WO2012106876A1 PCT/CN2011/076983 CN2011076983W WO2012106876A1 WO 2012106876 A1 WO2012106876 A1 WO 2012106876A1 CN 2011076983 W CN2011076983 W CN 2011076983W WO 2012106876 A1 WO2012106876 A1 WO 2012106876A1
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- subnet
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- the embodiments of the present invention relate to the field of communications, and in particular, to a method, a bus adapter, and a computer system for managing a subnet through a bus adapter in a computer system.
- the computer system includes a server such as a minicomputer or a mainframe.
- a server such as a minicomputer or a mainframe.
- the following is a description of a method for managing a subnet in a computer system by taking a minicomputer and a mainframe as examples.
- a subnet management method in a minicomputer is described by taking a minicomputer having 32 central processing units as an example.
- the minicomputer has 16 subnet nodes, each subnet node.
- the PCIE bus connects each subnet node to form a subnet through an IB (infmiband) switch.
- Each subnet node includes a node controller chip (NCC) and two central processing units. (CPU, Central Processing Unit), 16 subnet nodes compete for a primary subnet node and an alternate primary subnet node, and the node control chip on the primary subnet node is responsible for subnet management.
- NCC node controller chip
- 16 subnet nodes compete for a primary subnet node and an alternate primary subnet node
- the node control chip on the primary subnet node is responsible for subnet management.
- the management method of the subnet in the mainframe is also the same as the management method of the subnet to the subnet.
- the nodes compete with each other to compete for a primary subnet node and an alternate primary subnet node.
- the control chip is responsible for the management of the subnet.
- This subnet management method will reduce the overall service capability of various computer systems due to the bandwidth of the node control chip being occupied by subnet-managed transactions.
- Embodiments of the present invention provide a subnet management method, a bus adapter, and a computer system in a computer system, which can translate the bandwidth of a subnet node control chip in a computer system, thereby improving the overall performance of the computer system.
- a subnet management method in a computer system comprising:
- Each subnet node in the subnet is assigned a network address by a bus adapter, the subnet node comprising a node control chip and at least one central processor, wherein each subnet node is connected to the PCIE bus through a bridge, the bus The adapter is plugged into the slot of the PCIE bus;
- a computer system comprising a PCIE bus, a bus adapter and a plurality of subnet nodes, each of the subnet nodes comprising a node control chip and at least one central processor, wherein each subnet node passes through a bridge and a PCIE Connected to the bus, the bus adapter is plugged into a slot of the PCIE bus, and the bus adapter includes:
- An address allocation unit configured to allocate a network address for each subnet node in the subnet
- a storage unit configured to store, after the address allocation unit allocates a network address for each subnet node in the subnet, a network address of each subnet node to implement communication between the subnet nodes.
- a bus adapter comprising:
- An address allocation unit configured to allocate a network address for each subnet node in the subnet
- a storage unit configured to store, after the address allocation unit allocates a network address for each subnet node in the subnet, a network address of each subnet node to implement communication between the subnet nodes.
- the embodiments of the present invention have the following advantages:
- a bus adapter having a subnet management function is added to the computer system, and the subnet is managed by inserting the bus adapter into the slot of the PCIE bus, and the prior art has more
- the subnet node performs the competition, and the subnet management method in the computer system provided by the embodiment of the present invention is controlled by the node control chip management subnet in the main subnet node that is out of competition, and the subnet is managed by the bus adapter.
- the bandwidth of the node control chip is put on, which improves the overall performance of the computer system.
- FIG. 1 is a schematic diagram of an embodiment of a subnet management method according to an embodiment of the present invention
- FIG. 2 is a schematic diagram of another embodiment of a subnet management method according to an embodiment of the present invention.
- FIG. 3 is a schematic diagram of an embodiment of a computer system of the present invention.
- FIG. 4 is a schematic diagram of another embodiment of a computer system of the present invention.
- FIG. 5 is a schematic diagram of an embodiment of a bus adapter according to the present invention.
- FIG. 6 is a schematic diagram of another embodiment of a bus adapter of the present invention.
- the embodiment of the invention provides a method for managing a subnet in a computer system, a bus adapter and a computer system.
- the embodiment of the invention manages a subnet in a computer system through a bus adapter, The bandwidth of the node control chip in the computer system is released, and the overall performance of the computer system is improved.
- an embodiment of a method for managing a subnet in a computer system of the present invention includes:
- the computer system includes a plurality of subnet nodes, each subnet node includes a node control chip and at least one central processor, and each subnet node is connected to the PCIE bus through a bridge, and the PCIE bus passes each sub through an IB (infiniband) switch.
- the network nodes are connected to form a subnet, and the computer system further includes a master board management server and a slave board management server, the master board management server, and the slave board management server through the PCIE bus connection in the subnet, the bus adapter Plug in the slot of the PCIE bus to assign a network address to each subnet node in the subnet;
- the bus adapter detects the subnet node one by one. After detecting the existence of the subnet node, the network address is assigned to the subnet node, and the network address allocated by the bus adapter for each subnet node is different;
- bus adapters There are two bus adapters provided in this embodiment, which are a main bus adapter and a backup bus adapter respectively, and the main bus adapter is monitored by the standby bus adapter.
- the standby bus adapter replaces the The main bus adapter is described, and the network address assigned to each subnet node by the main bus adapter is backed up by the standby bus adapter, so that after the main bus adapter is abnormal, the standby bus adapter can immediately enter the working state.
- the main bus adapter and the backup bus adapter may be specifically inserted in the slot of the PCIE bus connected to the subnet node, or the main bus adapter may be plugged into the slot of the PCIE bus of the main onboard management server, and the bus adapter is plugged in From the slot of the PCIE bus on the board management server.
- the bus adapter assigns a network address to each subnet node
- the network address of each subnet node is stored in the bus adapter, so that when the nodes communicate, the source node goes to the bus adapter to query the network address of the destination node.
- the subnet is managed by a bus adapter inserted in a slot of the PCIE bus.
- the bus adapter allocates a network address for each subnet node
- the network address of each subnet node is stored in the bus adapter, so that Nodes communicate with each other.
- the computer system uses a bus adapter to manage the subnet, so that multiple subnet nodes in the computer system do not need to compete again, and the control chip on the subnet node is not needed to manage the subnet transaction, and the master technology is adopted in the prior art.
- Network node control core Compared with the slice management subnet transaction, the bandwidth of the primary subnet node is translated, which improves the overall performance of the computer system.
- the foregoing embodiment is described by taking two bus adapters as an example.
- a bus adapter can also perform subnet management work, but the stability is slightly worse than when there are two bus adapters.
- there is no alternative bus adapter In the event of a bus adapter failure, there is no alternative bus adapter, and only maintenance can be stopped.
- another embodiment of the present invention further includes:
- the bus adapter periodically detects whether the communication of each subnet node is abnormal. If the subnet node communication abnormality is detected, step 202 is performed.
- the subnet node For a subnet node with abnormal communication, the subnet node is faulty or has been removed.
- the bus adapter checks the problem node and deletes the network address of the node to prevent other subnet nodes from continuing to communicate with the subnet node. Communication confusion occurs in the network.
- the network address of the subnet node is deleted in time to prevent other subnet nodes from continuing to communicate with the abnormal subnet node, resulting in too many subnets. Packets sent to the abnormal node cannot be processed, causing subnet communication confusion.
- an embodiment of the computer system of the present invention includes:
- the computer system includes a plurality of sub-network nodes, each sub-node node includes a node control chip and two central processing units, and each sub-network node is connected to the PCIE bus through a bridge chip, and the PCIE bus passes each sub-ion through an IB (infiniband) switch.
- each sub-node node includes a node control chip and two central processing units
- each sub-network node is connected to the PCIE bus through a bridge chip, and the PCIE bus passes each sub-ion through an IB (infiniband) switch.
- IB infiniband
- the network nodes are connected to form a subnet
- the computer system further includes a primary onboard management server and a secondary onboard management server, the primary onboard management server, and the onboard management server connected to the subnet through the PCIE bus
- the computer system further includes a main bus adapter and a backup bus adapter, wherein the bus adapter and the backup bus adapter are respectively inserted in the slots of the PCIE bus connected to the subnet node; in this embodiment, the main bus adapter includes:
- An address allocation unit configured to allocate a network address for each subnet node in the subnet
- a storage unit configured to store, after the address allocation unit allocates a network address for each subnet node in the subnet, a network address of each subnet node to implement communication between the subnet nodes; a timing detecting unit, configured to periodically detect whether the communication of each subnet node is abnormal; and a deleting unit, configured to delete the communication stored in the bus adapter when the timing detecting unit detects a subnet node communication abnormality The network address of the abnormal subnet node;
- the standby bus adapter includes:
- a monitoring unit configured to monitor the main bus adapter, and replace the main bus adapter with the standby bus adapter when an abnormality occurs in the main bus adapter
- a backup unit for backing up the network address assigned by the main bus adapter to each subnet node; in fact, both the main bus adapter and the standby bus adapter include the above units, but there is such a distinction here because of different operations performed.
- the two bus adapters are respectively connected to the subnets of the PCIE bus connected to the subnet node, and the subnets are managed in the main subnet node managed by the nodes in the prior art.
- the bandwidth of the control chip of the primary subnet node and the auxiliary subnet node is translated, and the performance of the computer system is improved.
- the bus adapter is not limited to two, and there may be only one.
- the bus adapter performs the operation of the main bus adapter.
- FIG. 4 another embodiment of the computer system of the present invention includes:
- the computer system includes a plurality of sub-network nodes, each sub-node node includes a node control chip and two central processing units, and each sub-network node is connected to the PCIE bus through a bridge chip, and the PCIE bus passes each sub-ion through an IB (infmiband) switch.
- each sub-node node includes a node control chip and two central processing units
- each sub-network node is connected to the PCIE bus through a bridge chip, and the PCIE bus passes each sub-ion through an IB (infmiband) switch.
- IB infmiband
- the network nodes are connected to form a subnet
- the computer system further includes a primary onboard management server and a secondary onboard management server, the primary onboard management server, and the onboard management server connected to the subnet through the PCIE bus
- the computer system includes a bus adapter and a backup bus adapter, the bus adapter being plugged into a slot of a PCIE bus of the main board management server, the spare bus adapter being plugged into a slot of the PCIE bus from the board management server,
- the functions of the main bus adapter and the standby bus adapter are the same as those of the above embodiment, and will not be further described herein.
- two bus adapters are respectively inserted in the slots of the PCIE bus of the main board management server and the subnets are managed from the slots of the PCIE bus in the board management server, and the nodes in the prior art are actually connected.
- the main subnet node that is contending for the management of the subnet in the computer system is compared
- the bandwidth of the control chip of the primary subnet node and the secondary subnet node is increased, which improves the computer system's '.
- the bus adapter when there is only one bus adapter, the bus adapter is plugged into the slot of the PCIe bus of the main onboard management server to perform the operation of the primary bus adapter.
- a first embodiment of the bus adapter of the present invention includes: an address allocation unit 301 and a storage unit 302.
- the address allocation unit 301 is configured to allocate a network address for each subnet node in the subnet.
- the storage unit 302 is configured to store each sub-address after the address allocation unit allocates a network address for each sub-network node in the subnet. The network address of the network node to implement communication between the sub-network nodes.
- the storage unit 302 stores the network address after each of the subnet nodes in the subnet is allocated by the address allocating unit 301.
- the network address of each subnet node to implement communication between the subnet nodes.
- the bus adapter provided by the embodiment of the invention can manage the subnet in the computer system, and the bandwidth of the main subnet node is translated and the performance of the computer system is improved compared with the prior art control of the subnet transaction by the main subnet node control chip. .
- a further embodiment of the bus adapter provided by the present invention comprises: an address allocation unit 401, a storage unit 402, a timing detection unit 403 and a deletion unit 404, on the basis of an embodiment of the bus adapter.
- the address allocation unit 401 and the storage unit 402 are the same as the above-mentioned embodiments, and will not be described in detail.
- the timing detection unit 403 is configured to periodically detect whether the communication of each subnet node is abnormal.
- the deleting unit 404 is configured to detect the timing. When the unit 403 detects that the subnet node communication is abnormal, the network address of the communication abnormal subnet node stored in the bus adapter is deleted.
- the storage unit 402 stores the network address of each subnet node, and the timing detecting unit 403 periodically detects each subnet node, when the timing detecting unit detects
- the deleting unit 404 deletes the network address of the abnormal node stored in the storage unit 402. The other subnet nodes are prevented from continuing to communicate with the abnormal subnet node, and the packets in the subnet that are too sent to the abnormal node cannot be processed, causing the subnet communication to be confused.
- the related hardware can be instructed by a program, and the program can be stored in a computer readable storage medium.
- the storage medium mentioned above can be a read only memory, a magnetic disk or an optical disk.
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Abstract
一种计算机系统中子网管理方法，通过总线适配器为子网中的每个子网节点分配网络地址，所述每个子网节点包括节点控制芯片和至少一个中央处理器，所述每个子网节点通过桥片与PCIE总线相连，所述总线适配器插接在PCIE总线的槽口内，通过所述总线适配器存储每个子网节点的网络地址，以实现所述子网节点间通信。本发明还提供了相应的计算机系统及总线适配器。
Description
计算机系统中子网管理方法、 总线适配器及计算机系统 技术领域
本发明实施例涉及通信领域，尤其涉及一种计算机系统中通过总线适配器 对子网管理的方法、 总线适配器及计算机系统。
背景技术
计算机系统中包括小型机、 大型机等服务器， 下面以小型机和大型机为例 对计算机系统中子网的管理方法进行说明。
目前的小型机中子网的管理方法， 以有 32颗中央处理器的小型机为例对 小型机中的子网管理方法进行说明， 所述小型机内有 16个子网节点， 每个子 网节点均有 PCIE总线和桥片， 所述 PCIE 总线通过 IB ( infmiband )交换机将 每个子网节点连接起来构成子网，每个子网节点包括一个节点控制芯片（ NCC, Node Controller Chip )和两个中央处理器（CPU, Central Processing Unit ), 16 个子网节点通过竟争选出一个主子网节点和一个备用主子网节点，主子网节点 上的节点控制芯片负责子网的管理。大型机中子网的管理方法也和小型机对子 网的管理方法相同，都是通过节点间互相竟争， 竟争选出一个主子网节点和一 个备用主子网节点， 主子网节点上的节点控制芯片负责子网的管理。
这种子网管理方法均会由于节点控制芯片的带宽被子网管理的事务占用， 而导致各类计算机系统的整体业务能力降低。 发明内容
本发明实施例提供了计算机系统中子网管理方法，总线适配器及计算机系 统， 可以译放计算机系统中子网节点控制芯片的带宽，从而提高计算机系统的 整体性能。
计算机系统中子网管理方法， 其特征在于， 包括：
通过总线适配器为子网中的每个子网节点分配网络地址 ,所述每个子网节 点包括节点控制芯片和至少一个中央处理器， 所述每个子网节点通过桥片与 PCIE 总线相连， 所述总线适配器插接在 PCIE 总线的槽口内；
通过所述总线适配器存储每个子网节点的网络地址 ,以实现所述子网节点
间通信。
一种计算机系统， 所述的计算机系统包括 PCIE 总线， 总线适配器和多个 子网节点， 所述每个子网节点包括节点控制芯片和至少一个中央处理器， 所述 每个子网节点通过桥片与 PCIE 总线相连， 所述总线适配器插接在 PCIE 总线 的槽口内， 所述总线适配器包括：
地址分配单元， 用于为子网中的每个子网节点分配网络地址；
存储单元，用于在所述地址分配单元为子网中的每个子网节点分配网路地 址后， 存储每个子网节点的网络地址， 以实现所述子网节点间通信。
一种总线适配器， 其特征在于， 包括：
地址分配单元， 用于为子网中的每个子网节点分配网络地址；
存储单元，用于在所述地址分配单元为子网中的每个子网节点分配网路地 址后， 存储每个子网节点的网络地址， 以实现所述子网节点间通信。
从以上技术方案可以看出， 本发明实施例具有以下优点：
本发明实施例中， 在计算机系统中增加具有子网管理功能的总线适配器， 通过将总线适配器插接在 PCIE总线的槽口内对子网进行管理， 与现有技术中 的，计算机系统中的多个子网节点进行竟争， 由竟争出的主子网节点中的节点 控制芯片管理子网相比， 本发明实施例提供的计算机系统中的子网的管理方 法， 通过总线适配器管理子网， 译放了节点控制芯片的带宽， 提高了计算机系 统的整体性能。
附图说明
图 1为本发明实施例中子网管理方法一实施例示意图；
图 2为本发明实施例中子网管理方法另一实施例示意图；
图 3为本发明计算机系统的一实施例示意图；
图 4为本发明计算机系统的另一实施例示意图；
图 5为本发明总线适配器的一实施例示意图；
图 6为本发明总线适配器的另一实施例示意图。
具体实施方式
本发明实施例提供了一种计算机系统中子网的管理方法，总线适配器和计 算机系统， 本发明实施例通过总线适配器对计算机系统中的子网进行管理，释
放了计算机系统中节点控制芯片的带宽， 提高了计算机系统的整体性能。 请参阅图 1 , 本发明计算机系统中子网的管理方法的一实施例包括：
101、 通过总线适配器为子网中的每个子网节点分配网络地址。
计算机系统中包含多个子网节点，每个子网节点包括一个节点控制芯片和 至少一个中央处理器，每个子网节点通过桥片与 PCIE 总线相连，所述 PCIE 总 线通过 IB ( infiniband ) 交换机将每个子网节点连接起来构成子网， 所述计算 机系统还包括主在板管理服务器和从在板管理服务器，所述主在板管理服务器 和从在板管理服务器通过 PCIE 总线连接在子网中， 总线适配器插接在 PCIE 总线的槽口内， 为子网中的每个子网节点分配网络地址；
总线适配器逐个子网节点检测，检测到子网节点存在后， 为子网节点分配 网络地址， 总线适配器为每个子网节点分配的网络地址各不相同；
本实施例中提供的总线适配器有两个，分别为主总线适配器和备总线适配 器，通过所述备总线适配器监视所述主总线适配器， 当所述主总线适配器出现 异常时，备总线适配器替代所述主总线适配器， 并且通过所述备总线适配器备 份所述主总线适配器给每个子网节点分配的网络地址，以便主总线适配器发生 异常后， 备总线适配器可以立即进入工作状态。
主总线适配器和备总线适配器具体可以插接在连接子网节点的 PCIE 总 线的槽口内，也可以是主总线适配器插接在主在板管理服务器的 PCIE 总线的 槽口内， 备总线适配器插接在从在板管理服务器的 PCIE 总线的槽口内。
102、 通过所述总线适配器存储每个子网节点的网络地址， 以实现所述子 网节点间通信。
总线适配器为每个子网节点分配网络地址后，要将每个子网节点的网络地 址存储在总线适配器内， 以便节点间通信时， 源节点去总线适配器内查询目的 节点的网络地址。
本发明实施例中通过总线适配器插接在 PCIE 总线的槽口内对子网进行 管理， 总线适配器在为每个子网节点分配网络地址后，将每个子网节点的网络 地址存储在总线适配器内， 以便节点间互相通信。计算机系统中采用总线适配 器来管理子网，使计算机系统中的多个子网节点不需要再进行竟争，也不需要 子网节点上的控制芯片来管理子网事务，与现有技术中通过主子网节点控制芯
片管理子网事务相比，译放了主子网节点的带宽，提高了计算机系统的整体性 能。
可选地， 上述实施例是以有两个总线适配器为例进行的说明， 实际上， 也 可以只有一个总线适配器，该总线适配器插接在连接连接子网节点的 PCIE 总 线的槽口内或插接在主在板管理服务器的 PCIE 总线的槽口内。一个总线适配 器也可以执行子网管理工作， 只是稳定性比有两个总线适配器的情况稍差，在 总线适配器出现故障时， 没有可以替代的总线适配器， 只能停机维修。
参阅图 2,可选地，在第一实施例的基石出上，本发明的另一实施例还包括：
201、 通过所述总线适配器定时检测所述每个子网节点通信是否异常， 若 检测到子网节点通信异常， 执行步骤 202。
202、 通过所述总线适配器删除存储在所述总线适配器内的所述通信异常 子网节点的网络地址。
对于通信异常的子网节点，说明该子网节点出现故障或已被拔除， 总线适 配器检查出问题节点，删除该节点的网络地址， 可避免其他子网节点继续与该 子网节点通信， 导致子网中出现通信混乱。
本发明实施例中，对于子网中出现异常的子网节点，及时删除该子网节点 的网络地址，避免其他子网节点继续与该异常的子网节点通信， 导致子网中有 太多的发给异常节点的数据包不能被处理， 造成子网通信混乱。
参阅图 3 , 本发明计算机系统的一实施例包括：
计算机系统中包含多个子网节点 ,每个子网节点包括一个节点控制芯片和 两个中央处理器， 每个子网节点通过桥片与 PCIE 总线相连， 所述 PCIE 总线 通过 IB ( infiniband ) 交换机将每个子网节点连接起来构成子网， 所述计算机 系统还包括主在板管理服务器和从在板管理服务器，所述主在板管理服务器和 从在板管理服务器通过 PCIE 总线连接在子网中，所述计算机系统中还包括主 总线适配器和备总线适配器，所述总线适配器和备总线适配器分别插接在连接 子网节点的 PCIE 总线的槽口内； 在本实施例中， 主总线适配器包括：
地址分配单元， 用于为子网中的每个子网节点分配网络地址；
存储单元，用于在所述地址分配单元为子网中的每个子网节点分配网路地 址后， 存储每个子网节点的网络地址， 以实现所述子网节点间通信；
定时检测单元， 用于定时检测所述每个子网节点通信是否异常； 删除单元， 用于在所述定时检测单元检测到子网节点通信异常时，删除存 储在所述总线适配器内的所述通信异常子网节点的网络地址；
在本实施例中， 备总线适配器包括：
监视单元，用于监视所述主总线适配器，当所述主总线适配器出现异常时， 使所述备总线适配器替代所述主总线适配器；
备份单元， 用于备份所述主总线适配器给每个子网节点分配的网络地址； 实际上， 主总线适配器和备总线适配器都包括以上单元， 只是因执行的操 作不同， 在这里有这样的区分。
本发明实施例中两个总线适配器分别插接在连接子网节点的 PCIE 总线 的槽口内对子网进行管理，与现有技术中通过节点竟争选出的主子网节点管理 计算机系统中的子网相比，译放了主子网节点和辅助子网节点的控制芯片的带 宽， 提高了计算机系统的性能。
可选地， 总线适配器不限于两个， 可以只有一个， 当只有一个总线适配器 时， 该总线适配器执行主总线适配器的操作， 当然， 也可以有两个以上的总线 适配器， 但每增加一个适配器， 相应的软件编辑难度就会增加， 因此实际应用 中， 以两个总线适配器为宜。
参阅图 4, 本发明计算机系统的另一实施例包括：
计算机系统中包含多个子网节点，每个子网节点包括一个节点控制芯片和 两个中央处理器， 每个子网节点通过桥片与 PCIE 总线相连， 所述 PCIE 总线 通过 IB ( infmiband ) 交换机将每个子网节点连接起来构成子网， 所述计算机 系统还包括主在板管理服务器和从在板管理服务器，所述主在板管理服务器和 从在板管理服务器通过 PCIE 总线连接在子网中，所述计算机系统中包括总线 适配器和备总线适配器，所述总线适配器插接在主在板管理服务器的 PCIE 总 线的槽口内 ,所述备总线适配器插接在从在板管理服务器的 PCIE 总线的槽口 内，主总线适配器和备总线适配器的功能与上述实施例相同，在此不再做贅述。
本发明实施例中两个总线适配器分别插接在主在板管理服务器的 PCIE 总线的槽口内和从在板管理服务器的 PCIE 总线的槽口内对子网进行管理，与 现有技术中通过节点竟争选出的主子网节点管理计算机系统中的子网相比，释
放了主子网节点和辅助子网节点的控制芯片的带宽， 提高了计算机系统的 'ί 能。
可选地， 当只有一个总线适配器时， 该总线适配器插接在主在板管理服务 器的 PCIE 总线的槽口内， 执行主总线适配器的操作。
下面介绍本发明的总线适配器， 请参阅图 5 , 本发明总线适配器的第一实 施例包括： 地址分配单元 301和存储单元 302。
地址分配单元 301 , 用于为子网中的每个子网节点分配网络地址； 存储单元 302, 用于在所述地址分配单元为子网中的每个子网节点分配网 路地址后， 存储每个子网节点的网络地址， 以实现所述子网节点间通信。
本发明实施例中，地址分配单元 301为子网中的每个子网节点分配网络地 址后，存储单元 302在所述地址分配单元 301为子网中的每个子网节点分配网 路地址后， 存储每个子网节点的网络地址， 以实现所述子网节点间通信。 本发 明实施例提供的总线适配器可管理计算机系统中的子网，与现有技术中通过主 子网节点控制芯片管理子网事务相比，译放了主子网节点的带宽，提高了计算 机系统的性能。
参阅图 4, 在总线适配器的一实施例的基石出上， 本发明提供的总线适配器 的第另一实施例包括： 地址分配单元 401、 存储单元 402、 定时检测单元 403 和删除单元 404。
地址分配单元 401和存储单元 402与上述实施例相同 , 不再做详细贅述； 定时检测单元 403 , 用于定时检测所述每个子网节点通信是否异常； 删除单元 404,用于在所述定时检测单元 403检测到子网节点通信异常时， 删除存储在所述总线适配器内的所述通信异常子网节点的网络地址。
本发明实施例中， 在地址分配单元 401给每个子网节点分配网络地址后， 存储单元 402存储每个子网节点的网络地址，定时检测单元 403定时检测每个 子网节点， 当定时检测单元检测出子网节点通信异常时，删除单元 404删除所 述存储单元 402中存储的异常节点的网络地址。避免其他子网节点继续与该异 常的子网节点通信， 导致子网中有太过的发给异常节点的数据包不能被处理， 造成子网通信混乱。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分步骤
是可以通过程序来指令相关的硬件完成，该程序可以存储于一种计算机可读存 储介质中， 上述提到的存储介质可以是只读存储器， 磁盘或光盘等。
以上对本发明所提供的计算机系统中子网的管理方法、总线适配器及计算 机系统进行了详细介绍，对于本领域的一般技术人员，依据本发明实施例的思 想， 在具体实施方式及应用范围上均会有改变之处， 因此， 本说明书内容不应 理解为对本发明的限制。
Claims
1、 计算机系统中子网管理方法， 其特征在于， 包括：
通过总线适配器为子网中的每个子网节点分配网络地址，所述每个子网节 点包括节点控制芯片和至少一个中央处理器， 所述每个子网节点通过桥片与 PCIE 总线相连， 所述总线适配器插接在 PCIE 总线的槽口内；
通过所述总线适配器存储每个子网节点的网络地址，以实现所述子网节点 间通信。
2、 根据权利要求 1所述的计算机系统中子网管理方法， 其特征在于， 包 括：
通过所述总线适配器定时检测所述每个子网节点通信是否异常；
若检测到子网节点通信异常，通过所述总线适配器删除存储在所述总线适 配器内的所述通信异常子网节点的网络地址。
3、根据权利要求 1或 2所述的计算机系统中子网管理方法， 其特征在于， 所述总线适配器插接在连接子网节点的 PCIE 总线的槽口内。
4、根据权利要求 1或 2所述的计算机系统中子网管理方法， 其特征在于， 所述计算机系统还包括主在板管理服务器， 所述主在板管理服务器通过 PCIE 总线连接在子网中，所述总线适配器插接在所述主在板管理服务器的 PCIE 总 线的槽口内。
5、根据权利要求 1或 2所述的计算机系统中子网管理方法， 其特征在于， 所述总线适配器包括主总线适配器和备主线适配器；
通过所述备总线适配器监视所述主总线适配器，当所述主总线适配器出现 异常时， 备总线适配器替代所述主总线适配器；
通过所述备总线适配器备份所述主总线适配器给每个子网节点分配的网 络地址。
6、 根据权利要求 5所述的计算机系统中子网管理方法， 其特征在于， 所 述计算机系统还包括主在板管理服务器和从在板管理服务器，所述主在板管理 服务器和从在板管理服务器通过 PCIE 总线连接在子网中，所述主总线适配器 插接在主在板管理服务器的 PCIE 总线的槽口内，所述从总线适配器插接在从 在板管理服务器的 PCIE 总线的槽口内。
7、 一种计算机系统， 其特征在于， 所述的计算机系统包括 PCIE 总线， 总线适配器和多个子网节点，所述每个子网节点包括节点控制芯片和至少一个 中央处理器， 所述每个子网节点通过桥片与 PCIE 总线相连， 所述总线适配器 插接在 PCIE 总线的槽口内， 所述总线适配器包括：
地址分配单元， 用于为子网中的每个子网节点分配网络地址；
存储单元，用于在所述地址分配单元为子网中的每个子网节点分配网路地 址后， 存储每个子网节点的网络地址， 以实现所述子网节点间通信。
8、 根据权利要求 7所述的计算机系统， 其特征在于， 所述的总线适配器 还包括
定时检测单元， 用于定时检测所述每个子网节点通信是否异常；
删除单元， 用于在所述定时检测单元检测到子网节点通信异常时， 删除存 储在所述总线适配器内的所述通信异常子网节点的网络地址。
9、 根据权利要求 7或 8所述的计算机系统， 其特征在于， 所述总线适配 器插接在连接子网节点的 PCIE 总线的槽口内。
10、根据权利要求 7或 8所述的计算机系统， 其特征在于， 所述计算机系 统还包括主在板管理服务器，所述主在板管理服务器通过 PCIE 总线连接在子 网中 , 所述总线适配器插接在所述主在板管理服务器的 PCIE 总线的槽口内。
11、 根据权利要求 7或 8所述的计算机系统， 其特征在于， 所述总线适配 器包括主总线适配器和备主线适配器， 所述备总线适配器还包括：
监视单元，用于监视所述主总线适配器，当所述主总线适配器出现异常时， 使所述备总线适配器替代所述主总线适配器；
备份单元， 用于备份所述主总线适配器给每个子网节点分配的网络地址。
12、 根据权利要求 11所述的计算机系统， 其特征在于， 所述主总线适配 器和备总线适配器分别插接在连接子网节点的 PCIE 总线的槽口内。
13、 根据权利要求 11所述的计算机系统， 其特征在于， 所述计算机系统 还包括主在板管理服务器和从在板管理服务器，所述主在板管理服务器和从在 板管理服务器通过 PCIE 总线连接在子网中，所述主总线适配器插接在主在板 管理服务器的 PCIE 总线的槽口内 ,所述从总线适配器插接在从在板管理服务 器的 PCIE 总线的槽口内。
14、 一种总线适配器， 其特征在于， 包括：
地址分配单元， 用于为子网中的每个子网节点分配网络地址；
存储单元，用于在所述地址分配单元为子网中的每个子网节点分配网路地 址后， 存储每个子网节点的网络地址， 以实现所述子网节点间通信。
15、 根据权利要求 14所述的总线适配器， 其特征在于， 还包括： 定时检测单元， 用于定时检测所述每个子网节点通信是否异常； 删除单元， 用于在所述定时检测单元检测到子网节点通信异常时，删除存 储在所述总线适配器内的所述通信异常子网节点的网络地址。
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10360205B2 (en) | 2015-09-23 | 2019-07-23 | International Business Machines Corporation | Cooperative MKEY locking for managing infiniband networks |
| US10432470B2 (en) * | 2015-09-23 | 2019-10-01 | International Business Machines Corporation | Distributed subnet manager for InfiniBand networks |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410804A (zh) * | 2006-04-18 | 2009-04-15 | 国际商业机器公司 | 管理多个接口的方法和数据处理系统 |
| EP2112589A2 (en) * | 2008-04-07 | 2009-10-28 | Hitachi Ltd. | Method and apparatus for HBA migration |
| CN101604301A (zh) * | 2008-05-22 | 2009-12-16 | 凹凸电子（武汉）有限公司 | 使用绑定选择在pci配置空间中转换的适配器 |
| CN101997918A (zh) * | 2010-11-11 | 2011-03-30 | 清华大学 | 异构san环境中的海量存储资源按需分配的实现方法 |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583996A (en) * | 1993-03-16 | 1996-12-10 | Bell Communications Research, Inc. | Method and system for shortcut routing over public data networks |
| US7281036B1 (en) * | 1999-04-19 | 2007-10-09 | Cisco Technology, Inc. | Method and apparatus for automatic network address assignment |
| US6889380B1 (en) * | 2000-06-30 | 2005-05-03 | Intel Corporation | Delaying loading of host-side drivers for cluster resources to avoid communication failures |
| US7111100B2 (en) * | 2002-04-26 | 2006-09-19 | The Boeing Company | Systems and methods for assigning an address to a network device added to an existing network |
| US7243160B2 (en) * | 2001-05-10 | 2007-07-10 | Intel Corporation | Method for determining multiple paths between ports in a switched fabric |
| US7318095B2 (en) * | 2001-11-21 | 2008-01-08 | Clearcube Technology, Inc. | Data fail-over for a multi-computer system |
| US7653746B2 (en) * | 2002-08-02 | 2010-01-26 | University Of Southern California | Routable network subnet relocation systems and methods |
| JP3848235B2 (ja) * | 2002-10-04 | 2006-11-22 | ソニー株式会社 | 通信処理装置、通信処理システム、および方法、並びにコンピュータ・プログラム |
| US20050066035A1 (en) * | 2003-09-19 | 2005-03-24 | Williams Aidan Michael | Method and apparatus for connecting privately addressed networks |
| US7620695B2 (en) * | 2003-12-02 | 2009-11-17 | International Business Machines Corporation | Storing fibre channel information on an Infiniband administration data base |
| US7206973B2 (en) * | 2003-12-11 | 2007-04-17 | Lsi Logic Corporation | PCI validation |
| JP4619940B2 (ja) * | 2005-12-21 | 2011-01-26 | 富士通株式会社 | ネットワーク障害箇所検出装置及びネットワーク障害箇所検出方法 |
| JP4747118B2 (ja) * | 2007-03-05 | 2011-08-17 | 富士通株式会社 | ルータ、通信保証方法および通信保証プログラム |
| CN101277195B (zh) * | 2007-03-30 | 2011-12-07 | 杭州华三通信技术有限公司 | 一种交换网通信系统、实现方法及交换装置 |
| US8345052B1 (en) * | 2007-11-08 | 2013-01-01 | Nvidia Corporation | Method and system for using a GPU frame buffer in a multi-GPU system as cache memory |
| US7565470B2 (en) * | 2007-12-04 | 2009-07-21 | Holylite Microelectronics Corp. | Serial bus device with address assignment by master device |
| JP5139851B2 (ja) * | 2008-03-14 | 2013-02-06 | キヤノン株式会社 | 通信装置及びそのネットワーク構築方法 |
| JP5272265B2 (ja) * | 2008-09-29 | 2013-08-28 | 株式会社日立製作所 | Ｐｃｉデバイス共有方法 |
| US7778191B2 (en) * | 2008-12-12 | 2010-08-17 | Mitel Networks Corporation | System and method for fast detection of communication path failures |
| US8224946B2 (en) * | 2009-04-24 | 2012-07-17 | Rockstar Bidco, LP | Method and apparatus for accommodating duplicate MAC addresses |
| EP2326129B1 (en) * | 2009-11-20 | 2016-07-13 | Alcatel Lucent | Allocating an IP subnet address in a local network comprising a plurality of devices and connected to the internet |
| US9195623B2 (en) * | 2010-06-23 | 2015-11-24 | International Business Machines Corporation | Multiple address spaces per adapter with address translation |
-
2011
- 2011-07-08 WO PCT/CN2011/076983 patent/WO2012106876A1/zh not_active Ceased
- 2011-07-08 CN CN201180001241.2A patent/CN102301650B/zh active Active
-
2012
- 2012-07-06 US US13/543,531 patent/US20130013830A1/en not_active Abandoned
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410804A (zh) * | 2006-04-18 | 2009-04-15 | 国际商业机器公司 | 管理多个接口的方法和数据处理系统 |
| EP2112589A2 (en) * | 2008-04-07 | 2009-10-28 | Hitachi Ltd. | Method and apparatus for HBA migration |
| CN101604301A (zh) * | 2008-05-22 | 2009-12-16 | 凹凸电子（武汉）有限公司 | 使用绑定选择在pci配置空间中转换的适配器 |
| CN101997918A (zh) * | 2010-11-11 | 2011-03-30 | 清华大学 | 异构san环境中的海量存储资源按需分配的实现方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102301650A (zh) | 2011-12-28 |
| CN102301650B (zh) | 2014-07-09 |
| US20130013830A1 (en) | 2013-01-10 |
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