WO2012174933A1 - Rs encoder and encoding method thereof - Google Patents

Abstract

An RS encoder and encoding method thereof, the encoding method comprising: the RS encoder divides input data into predetermined number of parallel path data; the RS encoder simultaneously performs multi-codeword parallel encoding processing on the predetermined number of path data. The encoding method and the RS encoder solve such problems as low encoding efficiency and low data throughput rate that limit the transmission rate of the overall system; the present invention effectively improves the encoding efficiency and the data throughput rate and greatly improves the transmission rate of the overall system.

Description

TECHNICAL FIELD The present invention relates to the field of communications, and in particular to an encoding method and an RS encoder for a Reed-Solomon (RS) encoder. BACKGROUND OF THE INVENTION With the rapid growth of IP services, optical communications are faced with higher transmission rates and reliability requirements. In terms of reliability, Forward Error Correction (FEC) technology is usually used to improve the reliability of channel transmission, and RS code is used as a kind of multi-digit Boss Chad with strong error correction capability. Bose Chaudhuri Hocquenghem (BCH), which has excellent performance and high throughput, is widely used in many fields such as optical transmission and digital broadcasting. In the prior art, RS coding is usually applied by serial coding, that is, one codeword followed by one codeword serial processing, and each clock can only process one codeword, as shown in FIG. In this way, not only the coding efficiency is not high, but also the throughput of the data is not large, which is not conducive to the improvement of the transmission rate of the entire system. In view of the above problems in the related art, an effective solution has not yet been proposed. SUMMARY OF THE INVENTION A primary object of the present invention is to provide an encoding method of an RS encoder and an RS encoder to solve at least one of the above problems. According to an aspect of the present invention, an encoding method of an RS encoder is provided, including: an RS encoder dividing input data into parallel predetermined number of channels of data; and an RS encoder simultaneously performing multi-codeword parallelism on a predetermined number of channels of data Encoding processing. After the RS encoder encodes the predetermined number of road data at the same time, the method further includes: the RS encoder determines the input control signal enable state, and if enabled, inserts the encoded data into the designated position of the pre-coded data stream. Output, otherwise, the input data is output directly. Before the RS encoder determines the input control signal enable state, the RS encoder further includes: the RS encoder serially processes the parallel predetermined predetermined number of data in the predetermined number of codewords. Before the RS encoder divides the input data into parallel predetermined number of road data, the method further includes: the RS encoder performs a zero-padding operation on the input data at a specified position of the data stream. After the RS encoder serially processes the parallel predetermined number of channels of data, the method further includes: the RS encoder performs de-zero processing on the data obtained after the serial processing. The above method further includes: the RS encoder calculates the content of the specified location by the following formula:

Σ^ Θ ^ © ^ ), = 0,1...,∞- 1 (∑ g _l5 - _l ® (" © c ₁₅ — , )) Θ c _} _ _m = m,m + - - -,\ 5 wherein, the phase result of the j-th multi-codeword parallel coding of one of the predetermined number of road data is represented (j is a value of 0 to 15 closed interval), and g represents a generator polynomial of the RS pattern The calculation factor, m is the number of codewords encoded in parallel, the i-th element of the j-th row of the matrix calculation factor representing the multi-codeword parallel coding process, representing the input m codewords to be encoded, ® is a finite field multiplier According to another aspect of the present invention, an RS encoder is further provided, comprising: a dividing module configured to divide input data into parallel predetermined number of road data; and an encoding module configured to simultaneously The multi-codeword parallel encoding process is performed on the predetermined number of road data. The letter book encoder further includes: a judging module configured to determine an enable state of the input control signal; and an output module configured to be in a case where the output result of the judging module is YES , insert the encoded data into the pre-encoding data stream The output is output after the position is determined; and the input data is directly output when the output result of the determination module is negative. The encoder further includes: a serial processing module, connected to the coding module, configured to determine whether the The encoded data is serially processed by a predetermined number of codewords in a predetermined number of codewords before being inserted into a predetermined position of the pre-encoding data stream. The encoder further includes: a zero-padding module, Connected to the partitioning module, configured to perform zero-padding operation on the input data at a specified position of the data stream before dividing the input data into a parallel predetermined number of road data. The encoder further includes: a zero-removing module, and the connection is judged Between the module and the serial processing module, after the serial processing of the predetermined number of parallel data is performed, the data obtained after the serial processing is subjected to de-zero processing. The invention adopts the technical means of parallel coding in the RS coding, and solves the problems in the related art that the coding efficiency is not high, the data throughput rate is not large, and the transmission rate of the whole system is not improved, thereby achieving an effective improvement. The efficiency of coding and data throughput are also good, and the transmission rate of the whole system is also promoted. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In the drawings: FIG. 1 is a schematic structural diagram of an RS serial encoder according to the related art; FIG. 2 is a flowchart of an encoding method of an RS encoder according to an embodiment of the present invention; FIG. 3 is an RS encoding according to an embodiment of the present invention. FIG. 4 is a schematic structural diagram of an RS encoder according to a preferred embodiment of the present invention; FIG. 5 is a schematic structural diagram of an RS encoder according to an embodiment of the present invention; FIG. 6 is an RS encoding based on the example shown in FIG. FIG. 7 is a schematic diagram of a zero-padding and data splicing according to an example of the present invention; FIG. 8 is a schematic diagram of a 16-code block interleaving structure according to an embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. 2 is a flow chart of an encoding method of an RS encoder according to an embodiment of the present invention. As shown in FIG. 2, the method includes: Step S202: The RS encoder divides the input data into parallel predetermined number of road data. In a specific implementation, the input data may be zero-padded, and then interleaved by a predetermined number of codewords, such as a single or a plurality of codewords, to output a predetermined number of road data in parallel. Step S204, the RS encoder simultaneously performs multi-codeword parallel encoding processing on the predetermined number of road data. It should be noted that the above-described multi-codeword parallel encoding process is directed to serial processing in accordance with a single codeword in the related art. In the above embodiment, since the RS encoder adopts a technique of parallel encoding processing in encoding, the encoding efficiency and the data throughput rate are improved as compared with the serial encoding in the related art, and the transmission rate of the entire system is also good. The promotion effect. In a specific application process, the foregoing method may further include the following process: the RS encoder determines the input control signal enable state, and if enabled, inserts the encoded data into a specified position of the pre-encoding data stream, and outputs , directly output the input data. The above processing may be performed after the RS encoder simultaneously performs multi-codeword parallel encoding processing on a predetermined number of road data. Through the above processing, after the input data is encoded by the RS encoder, the specific content of the output data is specified. In a specific application process, the foregoing method may further include the following process: the RS encoder serially processes the parallel predetermined number of road data after the encoding process in a predetermined number of codewords, that is, restores the parallel data to a string. Row. The above processing may be performed before the RS encoder determines that the input control signal is enabled. In a specific implementation, the de-interleave processing may be performed on the encoded data according to the foregoing (corresponding to the interleaving process in the specific implementation process of step S202), and the plurality of codewords in a single or multiple units are used as a unit, and the parallel The predetermined number of road coded data is serially output (processed). In a specific application process, the above method may further include the following process: The RS encoder performs a zero-padding operation on the input data at a specified position of the data stream. The number of zero padding is determined according to the predetermined number of road data and the number of code words processed by the parallel encoding. For details, refer to Table 2 below. The above processing may be performed before the RS encoder divides the input data into parallel predetermined number of road data. The input data is constructed into integer beat data for processing by the zero-padding operation. In a specific application process, the foregoing method may further include: the RS encoder performs de-zero processing on the data obtained after the serial processing. The above processing may be performed after the RS encoder performs serial processing on a predetermined number of parallel data in parallel. Through the above processing, the input data described in the above step S202 can be restored, that is, the valid information in the data stream is restored. In the specific application process, the above method further includes: the RS encoder calculates the specified position by the following formula

f _{j gl5} _ _{] 1} ® (a ₁ ® c _l5 _ ₁ ) = 0,l ...,m - l

Content: _C] = _η _ '-°

(∑ ₅ - w ® © As-! )) © = m, m + !,■■■, 15 Wherein, the phase result of the j-th multi-codeword parallel coding of one of the predetermined number of road data is represented (j is a value of 0 to 15 closed interval), and g represents a calculation obtained by the generator polynomial of the RS pattern Factor (calculation factor g is obtained according to the generator polynomial of the specific RS pattern, which can be queried in the related art, and will not be described here), m is the number of parallel coded codewords, indicating multi-codeword parallel coding processing The i-th element of the j-th row of the matrix calculation factor represents the input m codewords to be encoded, ® is a finite field multiplier, and ® is a finite field adder. Among them, C has the same meaning as c. In order to better understand the above embodiments, the following detailed description will be made in conjunction with the accompanying drawings and specific examples. Example 1 In this example, the optical channel transport unit (OTU) frame format specified in the G709 protocol is taken as an example. The RS serial coding method shown in FIG. 1 can only process one codeword per clock. The encoder using the parallel coding method of the present example can process at least two codewords per clock, and the coding efficiency is improved by at least one time. Taking the above OTU frame format as an example, the related art RS serial coding is at 400 MHz. The data throughput rate under the clock is 3.2 Gbps, and the parallel encoder with this example has a data throughput rate of at least 102 Gbps, and the data throughput rate is greatly improved, which is beneficial to the improvement of the optical communication transmission rate. In this example, the RS code encoder includes: a zero padding unit, a data interleaving unit, a parallel encoding unit, a data deinterleaving unit, a zeroing unit, and a data splicing unit. Wherein, the zero-padding unit is set to perform zero-padding operation on the input data, and is configured to be processed into integer beat data; the data interleaving unit is set to perform data interleaving according to a single codeword as a unit of zero-padded data, in parallel Output n-channel data; the data de-interleaving unit is configured to de-interleave the encoded data, serially output the n-coded data input in parallel according to a single codeword; the zero-removing unit is set to solve the data The data from the interleaving unit is subjected to de-zero processing to remove the zero inserted before encoding; the data splicing unit is configured to determine whether to insert the encoded data into the specified position of the pre-encoding stream according to the state of the input control signal, Output the complete encoding result. The parallel coding method adopted by the parallel coding unit is derived according to the serial RS encoder shown in FIG. 1, and the derivation steps are as follows: (1) Based on the serial encoder of Figure 1, for the RS(n,k) code, the contents of CO, Cl, ..., Cn-k-1 in the t clock cycle remainder register are: C0 (t), Cl1,..., Cn-k-11; When t+1, the input information bit is a(t+l), then the content in the remainder register of t+1 clock cycle is updated according to the connection relationship of the feedback circuit for:

C„_ _k _,(t + l) = C, r(K)+ +i))

C _n _ _k _ ₂ (t ₊ l) = C, W+g„- _{t 2} ·υ + +ι))

Q (t + l) = C ₀ (t) + _gl · (C _n _ _k _ _x (t) + a(t + 1))

C ₀ (t +

(2) Write the formula 1 as a matrix expression. To simplify the expression and facilitate the calculation, set the parameters C(t+1), C(t), A(t+1) and G. Then the formula 1 can be simplified as:

C(t + l) = G-(C(t) + ^(t + l)) 2

(3) The relationship between the information C(t+m), the input information A(t+m), and the pre-state information C(t) after the state of t+m can be derived from the analogy of the equation 2, thereby further Iterate out the following expression:

这意味着可以在时钟 T时刻同时输入 m个信息 （m为 1到 16之间的任意一个值 均可）， 那么 k/m个时钟周期之后， 系统编码所需要的校验位就是寄存器的内容。 上述实例中的 RS编码器， 与相关技术中的串行编码方案相比， 节省了编码时间， 编码效率提升了至少一倍， 数据吞吐率也提高了数倍， 对整个系统的传输速率有良好 的促进效果。 若对码字采用并行的编码方法， 如每个时钟周期并行处理 2个、 3个、 4个或者更 多的码字， 这样不仅编码器的编码效率有很大的提升， 而且系统设备的整体数据吞吐 率也有很大提高。 图 3为根据本发明实施例的 RS编码器的结构框图。 如图 3所示， 该编码器包括: 划分模块 30，连接至编码模块 32， 设置为将输入的数据划分成并行的预定数目路 数据； 编码模块 32， 设置为同时对预定数目路数据进行多码字并行编码处理。 在优选实施过程中， 如图 4所示， 上述编码器还可以包括： 判断模块 34， 与输出 模块 36相连， 设置为判断输入的控制信号的使能状态； 输出模块 36， 设置为在判断 模块的输出结果为是的情况下， 将编码后的数据插入到编码前数据流的指定位置后输 出； 以及在在判断模块的输出结果为否的情况下， 直接将输入的数据输出。 在优选实施过程中， 如图 4所示， 上述编码器还可以包括： 串行处理模块 38， 与 编码模块 32相连， 设置为在判断模块 34判断是否将编码后的数据插入到编码前数据 流的指定位置之前， 以预定数量个码字为单位， 将编码处理后的并行的预定数目路数 据进行串行处理。 在优选实施过程中， 如图 4所示， 上述编码器还可以包括： 补零模块 40， 与划分 模块 30相连， 设置为在将输入的数据划分成并行的预定数目路数据之前，对输入的数 据在数据流的指定位置进行补零操作。 在优选实施过程中， 如图 4所示， 上述编码器还可以包括： 去零模块 42， 连接在 判断模块 34和串行处理模块 38之间， 设置为在对将并行的预定数目路数据进行串行 处理之后， 对串行处理后得到的数据进行去零处理。 为了更好地理解上述实施例， 以下结合具体实例和相关附图具体说明。 实例 2 本实例以 G709 协议中 Annex A 中规定的光信道传输单元 （Optical Channel Transport Unit, 简称为 OTU) 帧格式和 RS (255， 239) 为例来说明。 如图 5所示， RS码编码器包括以下处理单元： 补零单元 50 (相当于补零模块 40)、 数据交织单元 52 (相当于划分模块 30)， 并行编码单元 54 (相当于编码模块 32)、 数据解交织单元 56 (相当于串行处理模块 38)、 去零单元 58 (相当于去零模块 42)和数据拼接单元 60 (相当于判断模块 34和输出模块 36)。本实例以每拍并行处理 2个码字为例来详细说 明， 图 6中标注了数据流经过 RS码编码器时， 上述各个处理单元的位宽情况。 其中， 补零单元 50，设置为对输入的数据进行补零的操作，构造成整数拍数据进行处理; 如图 7所示， 图 7中的数字均代表时钟节拍数， 帧结构 1个子行 4080字节， 其中校验 字为 256字节。 每一路子编码单元的校验信息为 16字节， 每一个时钟周期数据为 256 位， 则每个子行占据 120周期的净荷数据 （含 128位补零） 和 8个周期的校验数据。 分别在第 0、 128、 256、 384周期时补零 128位， 和有效数据一起送入后级处理单元。 补零后的数据在校验数据对应的周期处可置 0， 为后续数据拼接模块插入校验数据。 数据交织单元 52， 设置为对补零后的数据， 按单个码字为单元进行交织处理， 并 行输出 n ( n为正整数） 路数据； 如图 8所示， 编码前， 将信息位依次交替的送入 16 个子编码单元， 当完成编码后， 按列优先依次顺序读出。 假定输入的 256bit数据写成 单个码字的形式为 B0,B1, ... ,B31。数据交织单元的功能是将输入的 256bit数据分成 16 路分别进入 16个 RS子编码单元， 即 B0， B16送入子编码单元 sub_0; B1,B17送入子 编码单元 sub_l B15， B31送入子编码单元 sub_15。 并行编码单元 54 实现对输入的交织数据进行并行编码， 其具体实现包括如下步 骤： （1)根据码生成多项式计算矩阵系数 G2; (2)根据矩阵系数和输入的信息得出并行 编码表达式。 步骤 (1)中， 可先根据具体 RS码型列出其生成多项式， 再由生成多项式产生生成 矩阵， 并行编码单元 54中每拍并行编码的码字个数 m， 即是矩阵因子 g的乘方次数。 具体地， 如表 1所示， 即是根据 RS (255， 239) 码生成多项式计算得出的有限域 RS 并行编码的矩阵系数 G²;

This means that m information can be input simultaneously at clock T (m can be any value between 1 and 16), then after k/m clock cycles, the check digit required for system coding is the contents of the register. . Compared with the serial coding scheme in the related art, the RS encoder in the above example saves coding time, improves coding efficiency by at least one time, increases data throughput rate by several times, and has good transmission rate for the entire system. The promotion effect. If parallel coding is applied to the codeword, such as processing 2, 3, 4 or more codewords in parallel for each clock cycle, not only the coding efficiency of the encoder is greatly improved, but also the overall system equipment. The data throughput rate has also been greatly improved. FIG. 3 is a structural block diagram of an RS encoder according to an embodiment of the present invention. As shown in FIG. 3, the encoder includes: a dividing module 30 connected to the encoding module 32, configured to divide the input data into parallel predetermined number of road data; The encoding module 32 is configured to perform multi-codeword parallel encoding processing on the predetermined number of road data at the same time. In the preferred implementation process, as shown in FIG. 4, the encoder may further include: a determining module 34 connected to the output module 36, configured to determine an enabled state of the input control signal; and an output module 36 configured to be in the determining module When the output result is YES, the encoded data is inserted into a specified position of the pre-encoding data stream and output; and when the output result of the judging module is NO, the input data is directly output. In a preferred implementation process, as shown in FIG. 4, the encoder may further include: a serial processing module 38 coupled to the encoding module 32, configured to determine, at the determining module 34, whether to insert the encoded data into the pre-encoding data stream. Before the designated position, the encoded predetermined parallel number of road data is serially processed in units of a predetermined number of code words. In a preferred implementation process, as shown in FIG. 4, the encoder may further include: a zero padding module 40, connected to the dividing module 30, configured to input the input data before being divided into parallel predetermined numbers of road data. The data is zero-filled at a specified location in the data stream. In a preferred implementation, as shown in FIG. 4, the encoder may further include: a zeroing module 42 connected between the judging module 34 and the serial processing module 38, and configured to perform a predetermined number of data to be paralleled. After the serial processing, the data obtained after the serial processing is subjected to de-zero processing. In order to better understand the above embodiments, the following detailed description will be specifically made with reference to specific examples and related drawings. Example 2 This example uses the optical channel transport unit (OTU) frame format and RS (255, 239) specified in Annex A of the G709 protocol as an example. As shown in FIG. 5, the RS code encoder includes the following processing units: a zero padding unit 50 (corresponding to the zero padding module 40), a data interleaving unit 52 (corresponding to the dividing module 30), and a parallel encoding unit 54 (corresponding to the encoding module 32). The data deinterleaving unit 56 (corresponding to the serial processing module 38), the zeroing unit 58 (corresponding to the zeroing module 42), and the data splicing unit 60 (corresponding to the judging module 34 and the output module 36). This example is described in detail by taking two codewords in parallel for each beat as an example. Figure 6 shows the bit width of each of the above processing units when the data stream passes through the RS code encoder. The zero-padding unit 50 is set to perform zero-padding operation on the input data, and is configured to be processed into integer beat data. As shown in FIG. 7, the numbers in FIG. 7 represent the number of clock beats, and the frame structure is 1 sub-line 4080. Byte, where the check word is 256 bytes. The parity information of each sub-coding unit is 16 bytes, and each clock cycle data is 256 bits. Then each sub-row occupies 120 cycles of payload data (including 128 bits of zero padding) and 8 cycles of parity data. 128 bits are padded at the 0th, 128th, 256th, and 384th cycles, respectively, and sent to the subsequent processing unit along with the valid data. The data after zero padding can be set to 0 at the period corresponding to the check data, and the check data is inserted for the subsequent data splicing module. The data interleaving unit 52 is configured to perform interleaving processing on the zero-padded data in units of a single codeword, and output n (n is a positive integer) channel data in parallel; as shown in FIG. 8, the information bits are sequentially alternated before encoding. The 16 sub-coding units are fed, and when the encoding is completed, the columns are sequentially read in order of priority. It is assumed that the input 256-bit data is written in the form of a single codeword as B0, B1, ..., B31. The function of the data interleaving unit is to divide the input 256-bit data into 16 channels and enter 16 RS sub-coding units respectively, that is, B0 and B16 are sent to the sub-encoding unit sub_0; B1 and B17 are sent to the sub-encoding unit sub_l B15, and B31 sends the sub-encoding. Unit sub_15. The parallel encoding unit 54 implements parallel encoding of the input interleaved data, and the specific implementation includes the following steps: (1) calculating the matrix coefficient G2 according to the code generation polynomial; (2) obtaining the parallel encoding expression according to the matrix coefficient and the input information. In step (1), the generator polynomial may be listed according to the specific RS pattern, and then the generator matrix is used to generate the generator matrix. The number of codewords encoded in parallel by each beat in the parallel coding unit 54 is the multiplication of the matrix factor g. Number of squares. Specifically, as shown in Table 1, the matrix coefficient G ² of the finite field RS parallel coding calculated according to the RS (255, 239) code generation polynomial;

Table 1

步骤 (2)中， 设并行输入的 2 个信息码字为： a0,al， t 时刻寄存器内容为 C(t)=[cl5,cl4,cl3,...,cl,cO]^T, t+1时刻寄存器内容为 C(t+l)=[C15,C14,C13，...,C1,C0]^T， 将的步骤 (1)计算得出的矩阵系数 G²代入公式③中， 即可得出 G²并行编码表达式， 如 下所示：

In step (2), it is assumed that the two information code words input in parallel are: a0, al, t The time register contents are C(t)=[cl5,cl4,cl3,...,cl,cO] ^T , t+ The time register content is C(t+l)=[C15,C14,C13,...,C1,C0] ^T , and the matrix coefficient G ² calculated in step (1) is substituted into formula 3, Get the G ² parallel encoding expression as follows:

2 ₁₅ = 0,1

 !=0

! ® (a _t c ₁₅ —! )) c _ ₂ , = 2,3,4,5,· -·,15

4 In the above formula 4, it is the i-th element of the jth row of the matrix G ² , the ® is a finite field multiplier, and @ is a finite field adder. Thus, after 120 clock cycles, the contents of the register C15, C14, C13, ..., C1, C0 are the parity bits obtained by the RS code encoding. After zero padding, the input information is [a0,al,..., _a 239]. After passing through the RS encoder, the last output codeword of the RS code is [a0,al,...,a239,C15,C14,C13 ,...,Cl,C0]. The data deinterleaving unit 56 is configured to perform deinterleaving processing on the encoded data, and serially output n pieces of encoded data input in parallel in units of a single codeword; the process of deinterleaving is opposite to the interleaving process. It is assumed that the 16-bit data output by sub_0 is written in byte form as A0, A1, sub_l output 16-bit data is A2, A3, and so on, and the 16-bit data output by sub_15 is A30, A31. Then, after deinterleaving, the output sequences are sequentially: A0, A2, A4, ... A30, Al, A3, A5, ... A31. The de-zeroing unit 58 is configured to perform de-zero processing on the data from the data deinterleaving unit 56, and remove the zero inserted before the encoding; as shown in FIG. 7, respectively, before the 0th, 128th, 256th, and 384th cycles are removed, The 128-bit zero, the valid information data is restored to the state before zero-padding, and the gap generated during the zero-cut process is placed directly at the end of the data frame. The data splicing unit 60 is configured to determine whether to insert the encoded data into the specified position of the pre-encoding stream and output the complete encoding result according to the state of the input control signal. As shown in FIG. 8, if the code enable signal is valid, the deinterleaved coded data is filled in the check data portion (for example, 120 to 127 in the first row, 248 to 255 in the second row, etc.), The input information data is spliced in accordance with the frame format to be completely output; conversely, if the code enable signal is invalid, the verification data portion is filled with zeros, and the input information data is directly output according to the frame format. The above example is only a specific implementation description for a parallel encoder that processes two codewords in parallel in the optical transmission domain RS (255, 239) code. In particular, as shown in Equation 3, the parallel RS coding described in this example The device can process m codewords in parallel (the range of m ranges from 1 to 16). As shown in Table 2, the related information of the parallel RS encoder in different embodiments is listed, including the input data bit width, the number of parallel processed code words, Zero and zero Parallel encoding takes time and so on. Correspondingly, as more codewords are processed in parallel for each beat, the more complicated the calculation, the more complicated the implementation, but the shorter the encoding time consumed, the higher the encoding efficiency, and the trade-offs need to be based on actual conditions.

Table 2

From the above description, it can be seen that the present invention achieves the following technical effects: By the present invention, the technical means of parallel coding is adopted in the RS coding, and the related art is solved, the coding efficiency is not high, and the data throughput rate is not Large, is not conducive to the improvement of the transmission rate of the entire system, and thus achieves the effect of effectively improving the coding efficiency and data throughput rate, and at the same time, has a good promotion effect on the transmission rate of the entire system. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. Perform the steps shown or described, or separate them into individual integrated circuit modules, or Multiple of these modules or steps are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software. The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim 1. A Reed Solomon RS encoder encoding method, comprising:  The RS encoder divides the input data into parallel predetermined number of road data;  The RS encoder simultaneously performs multi-codeword parallel encoding processing on the predetermined number of road data. The method according to claim 1, wherein, after the RS encoder performs the multi-codeword parallel encoding process on the predetermined number of road data, the method further includes:  The RS encoder determines the input control signal enable state. If enabled, the encoded data is inserted into a specified position of the pre-encoded data stream and output. Otherwise, the input data is directly output. The method according to claim 2, wherein before the RS encoder determines the input control signal enable state, the method further includes:  The RS encoder serially processes the predetermined number of parallel data in parallel after the encoding process in units of a predetermined number of codewords. The method according to any one of claims 1 to 3, wherein, before the RS encoder divides the input data into parallel predetermined number of road data, the method further includes:  The RS encoder performs a zero-padding operation on the input data at a specified position of the data stream. The method according to claim 4, wherein after the RS encoder serially processes the parallel predetermined number of data, the method further includes:  The RS encoder performs de-zero processing on the data obtained after the serial processing. The method according to claim 4, further comprising: the RS encoder calculating the content of the specified location by using the following formula: Σ^ Θ ^ © ^ ), = 0,1...,∞-1  c,. = (∑ g _l5 - _l ® (" © c ₁₅ — , )) Θ c _} _ _m = m, m + - - -, \5 where represents the jth of one of the predetermined number of way data The phased result of multi-codeword parallel coding (j is a value of 0 to 15 closed interval), g represents the generator polynomial of the RS pattern The calculated factor, m is the number of codewords encoded in parallel, representing the input m codewords to be encoded, representing the i-th element of the j-th row of the matrix calculation factor of the multi-codeword parallel coding process, 2 is limited The domain multiplier, Θ is a finite field adder. 7. An RS encoder, including:  The dividing module is configured to divide the input data into parallel predetermined number of road data; and the encoding module is configured to perform multi-codeword parallel encoding processing on the predetermined number of road data at the same time. The encoder according to claim 7, further comprising: a determining module, configured to determine an enabled state of the input control signal;  The output module is configured to, after the output result of the determining module is YES, insert the encoded data into a specified position of the pre-encoding data stream, and output the result; and if the output result of the determining module is negative Next, the input data is directly output. 9. The encoder according to claim 8, further comprising: a serial processing module, coupled to the encoding module, configured to determine, at the determining module, whether to insert the encoded data into the pre-encoding data stream Before the designated position, the predetermined number of parallel data in parallel after the encoding process is serially processed in units of a predetermined number of code words. The encoder according to any one of claims 7 to 9, further comprising:  A zero padding module is coupled to the partitioning module and configured to perform a zero padding operation on the input data at a specified position of the data stream before dividing the input data into a parallel predetermined number of road data. The encoder according to claim 10, further comprising: a zeroing module connected between the judging module and the serial processing module, configured to pair the parallel predetermined number of road data After the serial processing is performed, the data obtained after the serial processing is subjected to de-zero processing.