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WO2012169397A1 - Transistor à couche mince, son procédé de production, et élément d'affichage - Google Patents

Transistor à couche mince, son procédé de production, et élément d'affichage Download PDF

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Publication number
WO2012169397A1
WO2012169397A1 PCT/JP2012/063877 JP2012063877W WO2012169397A1 WO 2012169397 A1 WO2012169397 A1 WO 2012169397A1 JP 2012063877 W JP2012063877 W JP 2012063877W WO 2012169397 A1 WO2012169397 A1 WO 2012169397A1
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Prior art keywords
semiconductor layer
drain electrode
source electrode
electrode
tft
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English (en)
Japanese (ja)
Inventor
雅裕 冨田
北角　英人
一秀 冨安
加藤　純男
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to a thin film transistor, a manufacturing method thereof, and a display element, and more particularly to a thin film transistor having a semiconductor layer made of an oxide semiconductor, a manufacturing method thereof, and a display element.
  • a thin film transistor (hereinafter referred to as “TFT”) having a semiconductor layer made of an oxide semiconductor such as indium gallium zinc oxide (hereinafter referred to as “IGZO”) or zinc oxide (ZnO) is made of amorphous silicon.
  • TFT thin film transistor
  • IGZO indium gallium zinc oxide
  • ZnO zinc oxide
  • the semiconductor layer made of an oxide semiconductor is reduced when the entire substrate is heated in the subsequent manufacturing process. Specifically, the semiconductor layer is deprived of oxygen by the source electrode and the drain electrode and supplied with hydrogen from the source electrode and the drain electrode. Thus, immediately after the formation of the semiconductor layer, the entire semiconductor layer is a high resistance region.
  • the semiconductor layer that is in direct contact with the source electrode and the drain electrode and the semiconductor layer near the ends of those electrodes become a low resistance region, and the semiconductor layer sandwiched between the low resistance regions on both sides Is a region whose resistance value is between the low resistance region and the high resistance region (hereinafter referred to as “medium resistance region”).
  • the semiconductor layer operates as a resistance element.
  • Patent Document 1 discloses a TFT that can restore good transistor characteristics by easily supplying oxygen from the outside to a semiconductor layer made of an oxide semiconductor. Specifically, after forming the source electrode and the drain electrode of the TFT, an opening for exposing the surface of the semiconductor layer is formed in the source electrode and the drain electrode. Next, oxygen is supplied to the semiconductor layer from the opening by performing oxygen annealing at a high temperature. As a result, the TFT recovers good transistor characteristics.
  • Patent Document 1 openings are formed in a source electrode and a drain electrode in order to supply oxygen to a semiconductor layer.
  • the contact area between the source and drain electrodes and the semiconductor layer is reduced by forming the opening, the contact resistance between the source and drain electrodes and the semiconductor layer is increased.
  • the transistor characteristics are adversely affected, such as a reduction in the on-current of the TFT.
  • an object of the present invention is to provide a thin film transistor capable of recovering good transistor characteristics while maintaining a low contact resistance between a source electrode and a drain electrode and a semiconductor layer made of an oxide semiconductor.
  • a first aspect of the present invention is a thin film transistor having a semiconductor layer formed on an insulating substrate and made of an oxide semiconductor, A gate electrode formed on the insulating substrate; A gate insulating film formed to cover the gate electrode and including at least a first silicon oxide film; A source electrode and a drain electrode formed on the gate insulating film at a predetermined distance so as to sandwich the gate electrode; The semiconductor layer formed on the gate insulating film sandwiched between the source electrode and the drain electrode, and having one end and the other end electrically connected to either the back surface or the surface of the source electrode and the drain electrode, respectively , A passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film; The semiconductor layer has a narrower width in a channel region sandwiched between the source electrode and the drain electrode than a width in a region in contact with the back surface or the front surface of the source electrode and the drain electrode, The channel region is sandwiched between the first silicon oxide film and the second silicon oxide film.
  • the channel region has a first cutout at least at one end in the width direction.
  • the channel region has the first notch at both ends in the width direction.
  • the channel region has at least one second cutout portion along a length direction of the channel region at a position spaced inward from an end portion in the width direction.
  • the gate insulating film further includes a first silicon nitride film formed on a lower surface of the first silicon oxide film
  • the passivation film further includes a second silicon nitride film formed on the surface of the second silicon oxide film.
  • the source electrode and the drain electrode are formed on the semiconductor layer so as to face each other with a predetermined distance therebetween,
  • the semiconductor layer is formed so that the one end is electrically connected to the back surface of the source electrode and the other end is electrically connected to the back surface of the drain electrode.
  • a seventh aspect of the present invention is the sixth aspect of the present invention, An etching stopper layer made of silicon oxide formed on the semiconductor layer sandwiched between the source electrode and the drain electrode; The channel region is sandwiched between two first regions each having a low resistance value formed along the ends of the source electrode and the drain electrode, and the two first regions. A second region having a resistance value higher than that of the first region, The etching stopper layer is formed so as to cover at least the second region.
  • the source electrode and the drain electrode are formed on the gate insulating film so as to face each other with a predetermined distance therebetween,
  • the semiconductor layer has one end covering the end of the source electrode and electrically connected to the surface of the source electrode, and the other end covering the end of the drain electrode and electrically connected to the surface of the source electrode. It is formed so that it may be connected to.
  • the oxide semiconductor constituting the semiconductor layer is amorphous.
  • a tenth aspect of the present invention is a method of manufacturing a thin film transistor having a semiconductor layer formed on an insulating substrate and made of an oxide semiconductor, Forming a gate electrode on the insulating substrate; Forming a gate insulating film including at least a first silicon oxide film so as to cover the gate electrode; Forming a source electrode and a drain electrode on the gate insulating film at a predetermined distance so as to sandwich the gate electrode; and Forming the semiconductor layer on the gate insulating film sandwiched between the source electrode and the drain electrode so that one end and the other end are electrically connected to the source electrode and the drain electrode, respectively; Forming a passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film; And a step of performing a heat treatment after the formation of the passivation film,
  • the step of forming the semiconductor layer includes a step of providing a notch in a channel region formed of the semiconductor layer sandwiched between the source electrode and the drain electrode using a
  • the step of performing the heat treatment is characterized in that the heat treatment is performed at a temperature of 200 to 400 ° C. for 1 to 2 hours in an atmosphere containing at least oxygen.
  • a twelfth aspect of the invention is an active matrix type display device for displaying an image, A plurality of pixel forming portions arranged in a matrix corresponding to a plurality of gate wirings, a plurality of source wirings intersecting with the plurality of gate wirings, and intersections of the plurality of gate wirings and the plurality of source wirings, respectively.
  • a display unit comprising The pixel formation portion includes a thin film transistor according to any one of the first to ninth aspects that is turned on or off according to a signal applied to a corresponding gate wiring.
  • the width of the semiconductor layer in the channel region is made smaller than the width of the semiconductor layer in the region in contact with the back surface or the surface of the source / drain electrode.
  • the semiconductor layer of the channel region whose side surface area is increased is sandwiched between the first silicon oxide film and the second silicon oxide film.
  • oxygen from the outside and oxygen contained in the first and second silicon oxide films are supplied to the channel region, so that the area of the low resistance region formed along the end portion of the source / drain electrode is reduced.
  • a channel region sandwiched between two low resistance regions becomes a high resistance region.
  • the width of the semiconductor layer in contact with the back surface or the front surface of the source / drain electrode is wider than the width of the semiconductor layer in the channel region, the contact resistance between the source / drain electrode and the semiconductor layer is kept low.
  • the on / off ratio of the thin film transistor can be increased while keeping the contact resistance low.
  • the channel region is provided with the first notch at one end in the width direction. For this reason, oxygen from the outside and oxygen contained in the first and second silicon oxide films are also supplied to the channel region from the side surface of the first notch. Accordingly, a high resistance region is formed in the channel region, so that the off-state current of the thin film transistor can be reduced.
  • the channel region is provided with first notches at both ends in the width direction. Oxygen from the outside and oxygen contained in the first and second silicon oxide films are supplied to the channel region from the side surfaces of the first notches on both sides. Accordingly, a high-resistance region having a high resistance value is formed by the channel region, so that the off-state current of the thin film transistor can be further reduced.
  • the channel region is provided with the second notch at a position away from the end in the width direction to the inside. Oxygen from the outside and oxygen contained in the first and second silicon oxide films are supplied to the channel region through the second notch.
  • the off-state current of the thin film transistor can be further reduced.
  • the larger the number of the second notches the more oxygen is supplied to the channel region, so that the off-state current of the thin film transistor can be further reduced.
  • the gate insulating film includes the first silicon nitride film
  • the withstand voltage of the gate insulating film can be ensured.
  • the passivation film includes the second silicon nitride film, moisture entering the thin film transistor from the outside is blocked, so that the reliability of the thin film transistor can be improved.
  • the on / off ratio can be increased.
  • the etching stopper layer protects the surface of the semiconductor layer from being etched when the source / drain electrodes are formed. Further, the etching stopper layer is made of silicon oxide and is formed so as to cover at least the second region of the channel region. Thus, oxygen from the outside and oxygen contained in the passivation film are supplied to the second region by heat treatment performed after the formation of the passivation film. Therefore, the resistance value of the second region can be further increased and the off-state current of the thin film transistor can be further reduced.
  • the ON / OFF ratio can be increased in the thin film transistor having the bottom contact structure.
  • oxygen supplied from the outside to the semiconductor layer by annealing in an atmosphere containing oxygen is more amorphous than in the case where the oxide semiconductor constituting the semiconductor layer is microcrystalline. More when it is quality. As a result, the area of the low resistance region formed in the channel region is further narrowed, and the channel region sandwiched between the two low resistance regions becomes a high resistance region having a higher resistance value. Therefore, the off current of the thin film transistor can be reduced.
  • a sufficient amount of oxygen is supplied also from the side surface of the semiconductor layer by performing a heat treatment at 200 to 400 ° C. for 1 to 2 hours in an atmosphere containing at least oxygen.
  • a high resistance region can be formed in the channel region of the thin film transistor.
  • the on / off ratio of the switching element can be increased by using the thin film transistor according to any one of the first to ninth inventions as the switching element of the pixel forming portion. .
  • the display quality of the display device can be improved.
  • FIGS. 4A to 4D are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG. (A) to (C) are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG.
  • (A) is a figure which shows the positional relationship of a foreign material and a channel area
  • (B) is a figure which shows the positional relationship of the foreign material and channel region at the time of providing a notch part in the both ends of a channel part. It is a figure which shows the influence of multiple reflection, and more specifically, (A) is a figure which shows the influence of multiple reflection when notch portions are not provided at both ends of the channel part, and (B) is the both ends of the channel part.
  • (A) is a top view which shows the structure of the bottom gate type TFT which concerns on the modification of this embodiment
  • (B) is a cross-sectional view of the TFT along the cutting line CC shown in (A)
  • (C) is a cross-sectional view of the TFT along the cutting line DD shown in (A).
  • (A) is a plane which shows the structure of the bottom gate type TFT which concerns on the 2nd Embodiment of this invention.
  • FIG. 1 is a cross-sectional view of the TFT along the cutting line EE shown in (A)
  • (C) is a cross-sectional view of the TFT along the cutting line FF shown in (A).
  • FIG. It is a figure which shows the structure of the top gate type TFT which concerns on the 3rd Embodiment of this invention, More specifically, (A) is a plane which shows the structure of the top gate type TFT which concerns on the 3rd Embodiment of this invention.
  • (B) is a cross-sectional view of the TFT along the cutting line GG shown in (A)
  • (C) is a cross-sectional view of the TFT along the cutting line HH shown in (A).
  • FIGS. 10A to 10D are process cross-sectional views illustrating respective manufacturing processes of the TFT shown in FIG.
  • FIGS. 10A to 10C are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG. It is a figure which shows the structure of the bottom gate type TFT which concerns on the 4th Embodiment of this invention, More specifically, (A) is a plane which shows the structure of the bottom gate type TFT which concerns on the 4th Embodiment of this invention. (B) is a cross-sectional view of the TFT along the cutting line JJ shown in (A), and (C) is a cross-sectional view of the TFT along the cutting line KK shown in (A).
  • FIGS. 14A to 14D are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG.
  • FIGS. 14A to 14C are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG.
  • It is a block diagram which shows the structure of the liquid crystal display device containing TFT shown in FIG.
  • FIG. 17 is a plan view showing a pattern arrangement in a pixel formation portion provided in the liquid crystal panel shown in FIG. 16.
  • FIG. 1 is a diagram showing a configuration of a bottom gate type TFT 100 according to the first embodiment of the present invention. More specifically, FIG. 1A shows a bottom gate type TFT according to the first embodiment of the present invention.
  • FIG. 1B is a plan view showing the structure of the TFT 100
  • FIG. 1B is a cross-sectional view of the TFT 100 along the cutting line AA shown in FIG. 1A
  • FIG. 2 is a cross-sectional view of the TFT 100 taken along a cutting line BB shown in FIG.
  • FIGS. 1A to 1C the structure of the TFT 100 will be described.
  • a gate electrode 20 is formed on a transparent insulating substrate 15 such as a glass substrate.
  • the gate electrode 20 may be made of any metal among, for example, titanium (Ti), molybdenum (Mo), aluminum (Al), tantalum (Ta), chromium (Cr), etc.
  • Ti titanium
  • Mo molybdenum
  • Al aluminum
  • Ta tantalum
  • Cr chromium
  • it may be constituted by a laminated metal film in which titanium, aluminum, and titanium are laminated in order from the surface side of 15.
  • a gate insulating film 30 is formed so as to cover the entire insulating substrate 15 including the gate electrode 20.
  • the gate insulating film 30 is formed by stacking a silicon oxide (SiO 2 ) film 32 (also referred to as “first silicon oxide film”) on a silicon nitride (SiNx) film 31 (also referred to as “first silicon nitride film”). It is comprised by the laminated insulating film.
  • the reason why the silicon nitride film 31 is included is to ensure the withstand voltage of the gate insulating film 30.
  • the reason why the silicon oxide film 32 is stacked on the silicon nitride film 31 is as follows. The first reason is to facilitate supply of oxygen from the silicon oxide film 32 to the semiconductor layer 40 described later. The second reason is that if the semiconductor layer 40 is formed on the surface of the silicon nitride film 31, a trap is formed at the interface and the reliability of the TFT 100 is likely to be lowered.
  • An island-shaped semiconductor layer 40 is formed at a position on the surface of the gate insulating film 30 corresponding to the gate electrode 20.
  • the semiconductor layer 40 is made of IGZO (indium gallium zinc oxide) containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O), and IGZO is an oxide semiconductor.
  • IGZO indium gallium zinc oxide
  • each end in the width direction of a region sandwiched between the source electrode 60a and the drain electrode 60b is cut out in a rectangular shape.
  • the width of the region 40a (hereinafter referred to as “channel region 40a”) sandwiched between the source electrode 60a and the drain electrode 60b of the semiconductor layer 40 is narrower than the width of the lower portion of the source electrode 60a and the drain electrode 60b. ing.
  • the channel region 40a sandwiched between the regions 41 from which the semiconductor layer 40 has been cut includes an end portion of the source electrode 60a and the drain electrode 60b.
  • Two low-resistance regions 40b (also referred to as “first regions”) reduced by the source electrode 60a and the drain electrode 60b are formed along the end portions of the first and second electrodes.
  • a high resistance region 40c (also referred to as “second region”) having a high resistance value is formed in the center of the channel region 40a sandwiched between the two low resistance regions 40b.
  • the film thickness of the semiconductor layer 40 is preferably about 40 to 50 nm. This is because the following problems occur. That is, when the film thickness of the semiconductor layer 40 is thinner than 40 ⁇ m, the transistor characteristics of the TFT 100 become unstable, and the threshold voltage shifts due to temperature and gate stress voltage. On the other hand, when the film thickness is thicker than 50 nm, the controllability by the gate voltage is deteriorated, resulting in a problem that the off-current is increased.
  • IGZO used as the semiconductor layer 40 of the TFT 100 contains indium, gallium, and zinc in the same ratio. However, they may be included in different proportions.
  • the IGZO constituting the semiconductor layer 40 is most preferably amorphous, but may be microcrystalline.
  • An oxide semiconductor that can be used as the semiconductor layer 40 of the TFT 100 is not limited to IGZO, and may be an In—Zn—O system, an In—Zn—Sn—O system, an In—Zn—Si—O system, or the like. Good. Specifically, IZO (indium zinc oxide), ITO (indium tin oxide), ZnO, SnO (tin oxide), WO (tungsten oxide), IO (indium oxide), or the like may be used.
  • the source electrode 60a and the drain electrode 60b are arranged on the upper surface of the semiconductor layer 40 so as to face each other with a predetermined distance.
  • the source electrode 60 a is formed so as to extend from the upper left surface of the semiconductor layer 40 to the left gate insulating film 30.
  • the drain electrode 60 b is formed so as to extend from the right upper surface of the semiconductor layer 40 to the right gate insulating film 30.
  • the low resistance region 40b of the channel region 40a is formed not only in the channel region 40a but also in the semiconductor layer 40e protruding in the width direction from the side surfaces of the source electrode 60a and the drain electrode 60b.
  • the semiconductor layer 40e protruding from the side surface is for securing an alignment margin when forming the source electrode 60a and the drain electrode 60b, and its width is 1/10 of the width of the source electrode 60a and the drain electrode 60b. It is as follows.
  • the low resistance region formed in the semiconductor layer 40e protruding from the side surface is not directly related to the present invention, the description thereof is omitted in this specification.
  • the source electrode 60a and the drain electrode 60b may be made of any metal among, for example, titanium, aluminum, tantalum, tungsten, molybdenum, gold (Au), and the like, and from the surface side of the insulating substrate 15.
  • titanium, aluminum, tantalum, tungsten, molybdenum, gold (Au), and the like may be comprised by the laminated metal film which laminated
  • the right end portion of the source electrode 60a is disposed above the left side portion of the gate electrode 20, and the left end portion of the drain electrode 60b is disposed above the right side portion of the gate electrode 20. For this reason, when a predetermined voltage is applied to the gate electrode 20, electrons are induced in each low resistance region 40 b of the semiconductor layer 40 by the electric field from the gate electrode 20, thereby forming a high concentration carrier layer. By forming the high concentration carrier layer, the source electrode 60a and the drain electrode 60b are ohmically connected to the two low resistance regions 40b, respectively.
  • a passivation film 90 is formed so as to cover the entire insulating substrate 15 including the source electrode 60a and the drain electrode 60b.
  • the passivation film 90 is made of silicon oxide having a thickness of 200 to 300 nm (also referred to as “second silicon oxide film”).
  • the passivation film 90 is a stacked insulating film in which a silicon oxide film (also referred to as “second silicon oxide film”) and a silicon nitride film (also referred to as “second silicon nitride film”) are sequentially stacked. May be. In this case, moisture entering from the outside is blocked by the silicon nitride film, so that each component of the TFT 100 can be prevented from being corroded by moisture. Thereby, the reliability of the TFT 100 can be ensured.
  • a region where two low resistance regions 40b and a high resistance region 40c sandwiched between them are combined, that is, a region sandwiched between the source electrode 60a and the drain electrode 60b is referred to as a channel region 40a.
  • a TFT in which a source electrode and a drain electrode covering a part of the upper surface of the semiconductor layer are sometimes referred to as a top contact TFT.
  • a TFT in which the surface of the channel region is not covered with an etching stopper layer is sometimes referred to as a channel-etched TFT. Therefore, the TFT 100 is a TFT with a top contact structure and a TFT with a channel etch structure.
  • FIGS. 2A to 2D and FIGS. 3A to 3C are process cross-sectional views showing each manufacturing process of the TFT 100.
  • FIG. 2A to 2D and FIGS. 3A to 3C are process cross-sectional views showing each manufacturing process of the TFT 100.
  • a metal film (not shown) to be the gate electrode 20 is formed on the insulating substrate 15 by a sputtering method so as to have a film thickness of 100 to 300 nm.
  • a resist pattern (not shown) is formed on the surface of the metal film using a photolithography method.
  • the metal film is etched by wet etching using the resist pattern as a mask to form the gate electrode 20. Thereafter, the resist pattern is peeled off.
  • the insulating substrate 15 including the gate electrode 20 is switched by using a plasma chemical vapor deposition method (Chemical Vapor Deposition: hereinafter referred to as “plasma CVD method”) to switch the source gas.
  • plasma CVD method Chemical Vapor Deposition: hereinafter referred to as “plasma CVD method”
  • a silicon nitride film 31 and a silicon oxide film 32 are successively formed so as to cover the whole, and a gate insulating film 30 is formed.
  • the thickness of the gate insulating film 30 is 300 to 400 nm.
  • the thickness of the silicon oxide film 32 is preferably about 50 to 60% of the thickness of the gate insulating film 30.
  • substrate temperature is set to 300 to 400 ° C.
  • the oxide semiconductor film 45 is formed over the gate insulating film 30 by a sputtering method.
  • the oxide semiconductor film 45 is made of, for example, IGZO containing indium, gallium, zinc, and oxygen.
  • the oxide semiconductor film 45 uses a target in which indium oxide (In 2 O 3 ), gallium oxide (Ga 2 O 3 ), and zinc oxide (ZnO) are mixed in an equimolar amount and sintered, and DC (Direct Current).
  • a film is formed by sputtering.
  • the thickness of the oxide semiconductor film 45 is 40 to 50 nm.
  • Sputtering is performed by introducing argon (Ar) gas having a flow rate of 100 to 300 sccm and oxygen (O 2 ) gas having a flow rate of 5 to 20 sccm into the chamber.
  • the substrate temperature at this time is set to 200 to 400.degree. Since the oxide semiconductor film 45 immediately after deposition contains a large amount of oxygen, the entire oxide semiconductor film 45 is a high resistance region. Note that the oxide semiconductor film 45 may be formed by a coating method instead of the sputtering method.
  • an amorphous IGZO film is formed by the above-described method, and then in an air atmosphere at 400 to 500 ° C. for about 1 to 2 hours. Annealing is performed.
  • RTA Rapid Thermal Anneal
  • RTA may be performed in an inert gas atmosphere such as nitrogen (N 2 ) instead of annealing in an air atmosphere. RTA is performed, for example, at 500 to 750 ° C. for about 1 to 10 minutes.
  • a resist pattern 48 is formed on the surface of the oxide semiconductor film 45.
  • the oxide semiconductor film 45 is etched by dry etching to form an island-shaped semiconductor layer 40.
  • the resist pattern 48 is peeled off.
  • notches are formed at both ends in the width direction of the channel region of the semiconductor layer 40. Note that in the process of forming the semiconductor layer 40 having the notch, it is only necessary to replace the mask with a changed pattern, and there is no need to change the process or add a new process.
  • a source metal film (not shown) is formed by sputtering.
  • the film thickness of the formed source metal film is 100 to 300 nm.
  • a resist pattern 68 separated left and right at a predetermined distance is formed on the source metal film above the gate electrode 20 by photolithography. Since the distance between the left and right ends of the resist pattern 68 is formed to be shorter than the length of the gate electrode 20, the resist pattern 68 covers the left and right ends of the gate electrode 20.
  • the source metal film is etched by dry etching to form a source electrode 60a and a drain electrode 60b.
  • the source electrode 60 a extends from the upper left surface of the semiconductor layer 40 to the left gate insulating film 30.
  • the drain electrode 60 b extends from the right upper surface of the semiconductor layer 40 to the right gate insulating film 30.
  • the resist pattern 68 is peeled off.
  • the etching stopper layer is not formed on the surface of the semiconductor layer 40, in order to suppress the etching of the surface of the semiconductor layer 40 as much as possible, an etching condition with a high selectivity between the source metal film and the semiconductor layer 40 is used. It is preferable to etch the source metal film.
  • a passivation film 90 made of silicon oxide is formed by plasma CVD so as to cover the entire insulating substrate 15 including the source electrode 60a and the drain electrode 60b.
  • the passivation film 90 is in contact with the semiconductor layer 40.
  • the passivation film 90 is preferably made of silicon oxide in order to supply oxygen to IGZO constituting the semiconductor layer 40, and the film thickness is preferably 200 to 300 nm.
  • the substrate temperature during film formation is 200 to 300.degree.
  • the low resistance region 40b is formed in the vicinity of the source electrode 60a and the drain electrode 60b of the semiconductor layer 40 along the end portions thereof. Further, oxygen is also released from the high resistance region sandwiched between the two low resistance regions 40b, and the middle resistance region 40d is formed.
  • annealing also referred to as “heat treatment” is performed in a dry air atmosphere at 200 to 400 ° C. for about 1 to 2 hours.
  • oxygen from the outside and oxygen from silicon oxide constituting the passivation film 90 are supplied to the semiconductor layer 40 in which oxygen is reduced.
  • the area of the low resistance region 40b formed at the time of forming the passivation film 90 is reduced, and oxygen is also supplied to the middle resistance region 40d to become the high resistance region 40c.
  • annealing may be performed not in a dry air atmosphere but in an oxygen atmosphere or an atmosphere containing oxygen.
  • the annealing of the passivation film 90 may be performed in an oxygen-free atmosphere, for example, a nitrogen atmosphere. Also in this case, a TFT having normal transistor characteristics is manufactured. This is presumably because oxygen was supplied from silicon oxide constituting the passivation film 90 or excessive oxygen was present in the channel region 40a.
  • the Oxidation of the oxide semiconductor in the channel region 40a proceeds by incorporating oxygen, and the area of the low-resistance region 40b becomes narrow, and the middle-resistance region 40d becomes a high-resistance region 40c having a higher resistance value. Accordingly, the off current of the TFT 100 becomes 1 ⁇ 10 ⁇ 10 to 10 ⁇ 11 A, and the TFT 100 sufficiently functions as a switching element of the liquid crystal display device.
  • the width of the source electrode 60a and the drain electrode 60b is made wider than the width of the channel region 40a of the semiconductor layer 40, and the surface of the semiconductor layer 40 is exposed to the source electrode 60a and the drain electrode 60b. There is no opening. Thereby, since the source electrode 60a and the drain electrode 60b are in electrical contact with the semiconductor layer 40 over the entire back surface, the contact resistance between the source electrode 60a and the drain electrode 60b and the semiconductor layer 40 can be kept low. As a result, a decrease in the on-current of the TFT 100 can be prevented, so that the on / off ratio can be increased.
  • the oxygen supplied to the semiconductor layer 40 from the outside by annealing in a dry air atmosphere is larger when the oxide semiconductor constituting the semiconductor layer 40 is amorphous than when it is microcrystalline. Accordingly, when the oxide semiconductor is amorphous, the channel region 40a is further oxidized and the area of the low-resistance region 40b is further narrowed and the medium-resistance region is smaller than when the oxide semiconductor is microcrystalline. 40d becomes a high resistance region 40c having a higher resistance value. This is considered to be because oxygen from the outside is hardly supplied to the channel region 40a because the film density of the oxide semiconductor made of microcrystals is high.
  • FIG. 4 is a diagram showing the positional relationship between the foreign matter 99 and the channel region 40a. More specifically, FIG. 4A shows the foreign matter 99 and the channel region when notch portions are not provided at both ends of the channel region 44a. 4B is a diagram showing the positional relationship between the foreign matter 99 and the channel region 40a when the notch portions 41 are provided at both ends of the channel region 40a.
  • etching gas for example, a fluorine-based gas such as methane tetrafluoride (CF 4 ), or boron trichloride (BCl 3 ) or Cl 2 (chlorine). Chlorine gas such as) is used.
  • a fluorine-based gas such as methane tetrafluoride (CF 4 ), or boron trichloride (BCl 3 ) or Cl 2 (chlorine).
  • CF 4 methane tetrafluoride
  • BCl 3 boron trichloride
  • Cl 2 Cl 2
  • These metal fluorides or metal chlorides adhering to the inner wall of the plasma CVD apparatus at the time of etching may be peeled off from the inner wall during the etching or after the etching is finished and fall onto the source metal film.
  • one end of the fallen foreign material 99 is in electrical contact with the low resistance region 44b of the semiconductor layer 44 adjacent to the source electrode 60a in the subsequent process, and the other end is In some cases, the low resistance region 40b of the semiconductor layer 44 adjacent to the drain electrode 60b is in electrical contact.
  • the source electrode 60a and the drain electrode 60b are short-circuited by being electrically connected via the two low-resistance regions 44b and the foreign matter 99.
  • the TFT 100 even if the foreign matter 99 made of metal chloride or metal fluoride falls at the same position as in FIG. A notch 41 is formed by etching when the layer 40 is formed. In this case, the position where the foreign material 99 has fallen is the cutout portion 41, and thus the low resistance region 40b is not formed. For this reason, the source electrode 60a and the drain electrode 60b are not short-circuited by the foreign matter 99. Thus, in the TFT 100, the possibility of a short circuit between the source electrode 60a and the drain electrode 60b due to the foreign matter 99 can be reduced.
  • FIG. 5 is a diagram showing the influence of multiple reflection. More specifically, FIG. 5A is a diagram showing the influence of multiple reflection when notches are not provided at both ends of the channel region 44a. FIG. 5B is a diagram showing the influence of multiple reflection when notches 41 are provided at both ends of the channel region 40a. As shown in FIG. 5A, the backlight light applied to the conventional TFT from the back surface side is directed toward the channel region 44a while being repeatedly reflected between the surface of the gate electrode 20 and the back surface of the drain electrode 60b. Go ahead.
  • the backlight light When the backlight light reaches the channel region 44a, it is absorbed by the semiconductor layer 44 in the channel region 44a and generates conduction electrons in the channel region 44a. As described above, in a TFT not provided with a notch, a current easily flows due to multiple reflection of backlight light.
  • the backlight light traveling while repeating multiple reflections between the surface of the gate electrode 20 and the back surface of the drain electrode 60b is The channel region 40a of the semiconductor layer 40 is reached.
  • the cutout portion 41 the backlight light passes through the cutout portion 41.
  • the backlight light is not absorbed by the channel region 40a, conduction electrons are not generated in the channel region 40a. For this reason, in TFT100, the electric current by the multiple reflection of backlight light can be suppressed.
  • FIG. 6 is a diagram showing the relationship between the channel length and the channel width at the time of designing to operate as the TFT 100.
  • FIG. 7 is an expected plan view showing the shape of the low resistance region, and more specifically, FIG. 7A is an expected plan view showing the shape of the low resistance region 44b in the case where the notch portion is not provided.
  • FIG. 7B is an expected plan view showing the shape of the low resistance region 40b when the notch 41 is provided.
  • the length of the low resistance region 40b in the channel direction formed in the channel region 40a is assumed to be constant regardless of the channel width. However, in practice, as shown in FIG. 6, when the channel width becomes narrower than 20 ⁇ m, the phenomenon that the channel length also becomes short accompanying it appears.
  • the length of the low resistance region 44b in the channel direction is not constant but varies irregularly according to the channel width.
  • the tip of the low resistance region 44b on the source electrode 60a side and the tip of the low resistance region 44b on the drain electrode 60b side overlap.
  • the source electrode 60a and the drain electrode 60b may be electrically connected (see FIG. 7A).
  • the TFT since the current cannot be controlled by the gate electrode 20, it always flows between the current source electrode 60a and the drain electrode 60b. In this case, the TFT operates not as a transistor but as a resistance element.
  • the notch 41 is provided in the channel region 40 a of the semiconductor layer 40, the low resistance region 40 b is not formed in the notch 41. Therefore, as shown in FIG. 7B, when a portion (a portion indicated by a dotted line) in which the length in the channel direction of the low resistance region 40b is increased is formed at the same position as FIG. It is possible to prevent the tip of the low resistance region 40b on the source electrode 60a side and the tip of the low resistance region 40b on the drain electrode 60b side from overlapping each other. In addition, it is expected that the irregular shape change of the low resistance region 40b is suppressed to some extent by providing the notch 41. From these things, it is presumed that the possibility that the tips of the low resistance regions 40b overlap each other is reduced. For this reason, it is estimated that the TFT 100 is less likely to operate as a resistance element.
  • FIG. 8 is a diagram illustrating a configuration of a bottom gate TFT 200 according to a modification of the present embodiment. More specifically, FIG. 8A illustrates a configuration of the bottom gate TFT 200 according to a modification of the present embodiment.
  • 8B is a cross-sectional view of the TFT 200 along the cutting line CC shown in FIG. 8A
  • FIG. 8C is a cross-sectional view shown in FIG. 8A.
  • FIG. 10 is a cross-sectional view of the TFT 200 along line DD.
  • the constituent elements of the TFT 200 the same constituent elements as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different constituent elements will be mainly described.
  • a notch 41 is provided only at one end of the channel region 40a.
  • the width of the channel region 40a is wider in the TFT 200 than in the TFT 100.
  • the same effects as the effects exhibited by the TFT 100 can be obtained.
  • the notch 41 of the TFT 200 is provided only on one side, the effect is half of the effect produced by the TFT 100.
  • FIG. 9 is a diagram showing a configuration of a bottom gate type TFT 300 according to the second embodiment of the present invention. More specifically, FIG. 9A shows a bottom gate type TFT according to the second embodiment of the present invention. 9B is a plan view showing the structure of the TFT 300, FIG. 9B is a cross-sectional view of the TFT 300 along the cutting line EE shown in FIG. 9A, and FIG. 9C is FIG. 2 is a cross-sectional view of the TFT 300 taken along a cutting line FF shown in FIG.
  • the constituent elements of the TFT 300 the same constituent elements as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different constituent elements will be mainly described.
  • the notches 41 are provided at both ends of the channel region 40a of the semiconductor layer 40, but also the channel region 40a.
  • a notch 42 (also referred to as “second notch”) is also provided at the center of the notch.
  • the notch 42 has a rectangular shape whose length in the channel direction is determined by the ends of the source electrode 60a and the drain electrode 60b. In the cutout portion 42, the semiconductor layer 40 is cut off, so that the surface of the silicon oxide film 32 underneath is exposed.
  • the mask used for forming the semiconductor layer 40 in the process shown in FIG. 2C among the manufacturing processes of the TFT 100 described in the first embodiment is replaced with a new notch 42. It is only necessary to replace the mask with the opening pattern to be added, and there is no need to change the process or add a new process.
  • the channel region 40a has a rectangular notch whose length in the channel direction is determined by the ends of the source electrode 60a and the drain electrode 60b not only at both ends but also in the center. A portion 42 is formed.
  • the TFT 300 has the same effect as that of the TFT 100. Specifically, by providing the notch portion 42, the area of the side surface of the semiconductor layer 40 is further increased. Therefore, oxygen from the outside and the silicon oxide film 32 are formed in the low resistance region 40b and the middle resistance region 40d. In addition, oxygen contained in the passivation film 90 is easily supplied.
  • the oxide semiconductor constituting the channel region 40a is further oxidized by taking in more oxygen, and the area of the low resistance region 40b is further narrowed.
  • the middle resistance region 40d becomes a high resistance region 40c having a higher resistance value. Therefore, the off current (leakage current) of the TFT 300 is 1 ⁇ 10 ⁇ 10 to 10 ⁇ 11 A, and the TFT 300 functions sufficiently as a switching element of the liquid crystal display device.
  • the source electrode 60a and the drain electrode 60b are short-circuited by foreign matters generated when the source electrode 60a and the drain electrode 60b are formed, or the backlight is subjected to multiple reflection between the surface of the gate electrode 20 and the surface of the drain electrode 60b. It is possible to further reduce the possibility that a current is generated due to this. Furthermore, since the low resistance region 40b on the source electrode 60a side and the low resistance region 40b on the drain electrode 60b side overlap, the possibility that the source electrode 60a and the drain electrode 60b are short-circuited can be further reduced.
  • the cutout portion 42 is formed at the center of the channel region 40a in the channel width direction.
  • one or a plurality of the cutout portions 42 may be formed at an arbitrary position in the channel region 40a.
  • one or a plurality of the notch portions 42 are formed at positions away from the end portions of the channel region 40a. May be.
  • FIG. 10 is a diagram illustrating a configuration of a top-gate thin film transistor 400 according to the third embodiment of the present invention. More specifically, FIG. 10A illustrates a top according to the third embodiment of the present invention.
  • FIG. 10B is a cross-sectional view of the TFT 400 taken along a cutting line GG shown in FIG. 10A
  • FIG. 10C is a plan view showing the structure of the gate type thin film transistor 400.
  • FIG. 11 is a cross-sectional view of the TFT 400 taken along a cutting line HH shown in FIG.
  • the same components as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different components will be mainly described.
  • the source electrode 70a and the drain electrode 70b are formed on the gate insulating film 30 including the silicon nitride film 31 and the silicon oxide film 32. Is formed.
  • a semiconductor layer 50 is formed on the surfaces of the source electrode 70a and the drain electrode 70b.
  • the semiconductor layer 50 is electrically connected to the source electrode 70a and the drain electrode 70b on the back surface thereof.
  • notches 51 hereinafter also referred to as “notches” or “first notches” are formed at both ends in the channel width direction.
  • the entire insulating substrate 15 including the semiconductor layer 50, the source electrode 70 a and the drain electrode 70 b is covered with a passivation film 90.
  • a region where two low resistance regions 50b and a high resistance region 50c sandwiched between them are combined, that is, a region sandwiched between the source electrode 60a and the drain electrode 60b is referred to as a channel region 50a.
  • FIG. 11A to FIG. 11D and FIG. 12A to FIG. 12C are process cross-sectional views showing each manufacturing process of the TFT 400.
  • FIGS. 11 (A) to 11 (D) and FIGS. 12 (A) to 11 (C) FIGS. 2 (A) to 2 (D) and FIGS. 3 (A) to 3
  • the same steps as those shown in (C) will be briefly described, and different steps will be mainly described.
  • membrane formed at each process, process conditions, etc. are the same as the case of 1st Embodiment, those description is abbreviate
  • the gate electrode 20 is formed on the insulating substrate 15.
  • a gate insulating film 30 including a silicon nitride film 31 and a silicon oxide film 32 is formed so as to cover the insulating substrate 15 including the gate electrode 20.
  • a source metal film 75 is formed on the gate insulating film 30 by a sputtering method.
  • a resist pattern 78 having an opening is formed over the gate electrode 20, the source metal film 75 is etched using the resist pattern 78 as a mask, and a source electrode 70a and a drain electrode 70b are formed. Form. Thereafter, the resist pattern 78 is peeled off.
  • oxidation is performed by sputtering so as to cover the entire insulating substrate 15 including the gate insulating film 30, the source electrode 70a, and the drain electrode 70b sandwiched between the source electrode 70a and the drain electrode 70b.
  • a physical semiconductor film 55 is formed.
  • a resist pattern 58 is formed on the oxide semiconductor film 55 above the gate electrode 20 using a mask in which a pattern for forming the channel region 50a is formed. Since the oxide semiconductor film 55 immediately after film formation contains a large amount of oxygen, the entire oxide semiconductor film 55 is a high resistance region.
  • the oxide semiconductor film 55 is etched using the resist pattern 58 as a mask to form the semiconductor layer 50. Thereafter, the resist pattern 58 is removed, and a passivation film 90 is formed so as to cover the entire insulating substrate 15 including the semiconductor layer 50, the source electrode 70a, and the drain electrode 70b.
  • the insulating substrate 15 is heated when the passivation film 90 is formed. For this reason, the source electrode 70 a and the drain electrode 70 b take oxygen from the semiconductor layer 50 and supply the hydrogen to the semiconductor layer 50, thereby reducing the semiconductor layer 50.
  • a low resistance region 50b (also referred to as “first region”) is formed in the semiconductor layer 50 close to the source electrode 70a and the drain electrode 70b. Further, oxygen is also released from the high resistance region sandwiched between the two low resistance regions 50b, and the middle resistance region 50d is formed.
  • oxygen from the outside and oxygen contained in the silicon oxide film 32 and the passivation film 90 are supplied to the channel region 50a of the semiconductor layer 50 by annealing in a dry air atmosphere. .
  • the area of the low resistance region 50b is reduced, and the resistance value of the middle resistance region 50d is increased to become the high resistance region 50c (also referred to as “second region”).
  • the area of the low-resistance region 50b of the channel region 50a is narrowed and the channel region sandwiched between the low-resistance regions 50b is the same as the effect exhibited by the TFT 100 according to the first embodiment.
  • a high resistance region 50c is formed in 50a. Further, it is possible to reduce the possibility that the source electrode 70a and the drain electrode 70b are short-circuited by a foreign substance, or that current is generated due to multiple reflection of backlight light. Furthermore, the possibility that the source electrode 70a and the drain electrode 70b are short-circuited by the overlap of the low resistance region 50b on the source electrode 70a side and the low resistance region 50b on the drain electrode 70b side can be reduced.
  • FIG. 13 is a diagram showing a configuration of a bottom gate type TFT 500 according to the fourth embodiment of the present invention. More specifically, FIG. 13A shows a bottom gate type TFT according to the fourth embodiment of the present invention.
  • FIG. 13B is a cross-sectional view of the TFT 500 taken along a cutting line JJ shown in FIG. 13A
  • FIG. 13C is a plan view showing the structure of the TFT 500.
  • FIG. 2 is a cross-sectional view of the TFT 500 along the cutting line KK shown in FIG.
  • the constituent elements of the TFT 500 the same constituent elements as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different constituent elements will be mainly described.
  • both end portions of the channel region 40a of the semiconductor layer 40 are removed by etching to form a notch 41.
  • the etching stopper layer 80 is formed on the channel region 40 a of the semiconductor layer 40. The etching stopper layer 80 protects the surface of the semiconductor layer 40 from being etched when the source metal film is etched to form the source electrode 60a and the drain electrode 60b.
  • the etching stopper layer 80 is made of silicon oxide. For this reason, as will be described later, the etching stopper layer 80 can supply oxygen to the channel region 40 a of the semiconductor layer 40 together with the passivation film 90. Note that a TFT in which an etching stopper layer is formed on the surface of a semiconductor layer like the TFT 500 may be referred to as an etch stop TFT.
  • FIGS. 14A to 14D and FIGS. 15A to 15C are process cross-sectional views illustrating each manufacturing process of the TFT 500.
  • the same steps as those shown in (C) will be briefly described, and different steps will be mainly described.
  • membrane formed in each process, process conditions, etc. are the same as the case of 1st Embodiment, those description is abbreviate
  • the gate electrode 20 is formed on the insulating substrate 15.
  • a gate insulating film 30 composed of a silicon nitride film 31 and a silicon oxide film 32 is formed so as to cover the entire insulating substrate 15 including the gate electrode 20.
  • An oxide semiconductor film (not shown) is formed on the gate insulating film 30 by a sputtering method. Since the oxide semiconductor film immediately after deposition contains a large amount of oxygen, the entire oxide semiconductor film is a high-resistance region. As shown in FIG. 14C, a resist pattern 48 is formed over the oxide semiconductor film above the gate electrode 20. The oxide semiconductor film is etched using the resist pattern 48 as a mask to form the semiconductor layer 40. Thereafter, the resist pattern 48 is peeled off.
  • a silicon oxide film 85 is formed by plasma CVD so as to cover the entire insulating substrate 15 including the semiconductor layer 40.
  • the thickness of the silicon oxide film 85 is 50 to 200 nm.
  • a resist pattern 88 is formed on the silicon oxide film 85.
  • the silicon oxide film 85 is etched using the resist pattern 88 as a mask to form an etching stopper layer 80.
  • the resist pattern 88 is peeled off, and a source metal film 65 is formed using a sputtering method so as to cover the entire insulating substrate 15 including the etching stopper layer 80.
  • a resist pattern 68 separated on the left and right on the etching stopper layer is formed on the source metal film 65.
  • the source metal film 65 is etched using the resist pattern 68 as a mask to form a source electrode 60a and a drain electrode 60b separated on the left and right on the etching stopper layer 80. Thereafter, the resist pattern 68 is peeled off.
  • the entire insulating substrate 15 including the etching stopper layer 80, the source electrode 60a, and the drain electrode 60b is covered with a passivation film 90.
  • the insulating substrate 15 is heated when the passivation film 90 is formed. Therefore, the source electrode 60 a and the drain electrode 60 b take oxygen from the semiconductor layer 40 and reduce the semiconductor layer 40 by supplying hydrogen to the semiconductor layer 40.
  • the low resistance region 40b is formed in the semiconductor layer 40 in the vicinity of the ends of the source electrode 60a and the drain electrode 60b. Since the etching stopper layer is formed on the high resistance region sandwiched between the two low resistance regions 40b, oxygen is not easily released from the high resistance region and remains as the high resistance region 40c.
  • oxygen is supplied from the silicon oxide constituting the etching stopper layer 80 to the IGZO constituting the channel region 40a.
  • the low resistance region 40b takes in oxygen and its area becomes narrow.
  • the area of the low-resistance region 40b of the channel region 40a is narrowed and the channel region sandwiched between the low-resistance regions 40b is the same as the effect exhibited by the TFT 100 according to the first embodiment.
  • a high resistance region 40c is formed in 40a.
  • the possibility that the source electrode 60a and the drain electrode 60b are short-circuited by the overlap of the low resistance region 40b on the source electrode 60a side and the low resistance region 40b on the drain electrode 60b side can be reduced.
  • TFT> typical TFTs 100 to 500 are described among TFTs to which the present invention can be applied. However, other TFTs obtained by appropriately combining these TFTs 100 to 500 have the same effect.
  • the notch 51 of the semiconductor layer 50 is provided not only at both ends in the width direction of the channel region 50a, but also by providing one or more between them. May be.
  • the TFT 500 with the TFT 500, in the channel stop structure TFT one or a plurality of notches 41 of the semiconductor layer 40 are provided not only at both ends in the width direction of the channel region 40a but also between them. May be.
  • the notch 51 of the semiconductor layer 50 is formed on one side in the width direction of the channel region 50a and on the inner side along the length direction of the channel region 50a. One or more may be provided at the position.
  • FIG. 16 is a block diagram showing a configuration of the liquid crystal display device 10 including the TFT 100 according to the first embodiment.
  • a liquid crystal display device 10 illustrated in FIG. 16 includes a liquid crystal panel 2 (also referred to as a “display unit”), a display control circuit 3, a gate driver 4, and a source driver 5.
  • the liquid crystal panel 2 includes n (n is an integer of 1 or more) gate wirings G1 to Gn extending in the horizontal direction and m (m is an integer of 1 or more) extending in a direction intersecting the gate wirings G1 to Gn.
  • Source wirings S1 to Sm are formed.
  • Pixel forming portions Pij are arranged near intersections of the i-th gate line Gi (i is an integer of 1 to n) and the j-th source line Sj (j is an integer of 1 to m). .
  • the display control circuit 3 is supplied with a control signal SC such as a horizontal synchronizing signal and a vertical synchronizing signal and an image signal DT from the outside of the liquid crystal display device 10. Based on these signals, the display control circuit 3 outputs a control signal SC1 to the gate driver 4, and outputs a control signal SC2 and an image signal DT to the source driver 5.
  • a control signal SC such as a horizontal synchronizing signal and a vertical synchronizing signal and an image signal DT
  • the gate driver 4 is connected to the gate lines G1 to Gn, and the source driver 5 is connected to the source lines S1 to Sm.
  • the gate driver 4 sequentially applies a high level signal indicating the selected state to the gate lines G1 to Gn.
  • the gate wirings G1 to Gn are sequentially selected one by one. For example, when the i-th gate line Gi is selected, the pixel formation portions Pi1 to Pim for one row are selected at once.
  • the source driver 5 applies a signal voltage corresponding to the image signal DT to each of the source lines S1 to Sm. As a result, the signal voltage corresponding to the image signal DT is written into the pixel formation portions Pi1 to Pim for one selected row. In this way, the liquid crystal display device 10 displays an image on the liquid crystal panel 2.
  • FIG. 17 is a plan view showing a pattern arrangement in the pixel formation portion Pij provided in the liquid crystal panel 2.
  • the liquid crystal panel 2 is surrounded by an i-th gate line Gi extending in the horizontal direction, a j-th source line Sj extending in a direction intersecting the gate line Gi, the gate line Gi, and the source line Sj.
  • a pixel forming portion Pij disposed in the region.
  • the pixel formation portion Pij includes a TFT 100 shown in FIGS. 1A to 1C as a TFT functioning as a switching element.
  • the gate electrode 20 of the TFT 100 is electrically connected to the gate wiring Gi.
  • An island-shaped semiconductor layer 40 is formed above the gate electrode 20.
  • One end of the semiconductor layer 40 is electrically connected to the source electrode 60a connected to the source wiring Sj, and the other end of the semiconductor layer 40 is electrically connected to the drain electrode 60b. Further, the drain electrode 60 b is electrically connected to the pixel electrode 7 through the contact hole 6.
  • the pixel electrode 7 and a counter electrode constitute a pixel capacitor that holds a signal voltage corresponding to the image signal DT for a predetermined time.
  • the display quality of the liquid crystal display device 10 can be improved by using the TFT 100 having a large on / off ratio as a switching element of each pixel formation portion Pij provided in the liquid crystal panel 2.
  • the reason why the display quality of the liquid crystal display device 10 is improved by increasing the on / off ratio will be described.
  • the on-current may be increased and the off-current may be decreased.
  • the signal voltage of the image signal DT supplied from the source wiring Sj can be charged to the pixel capacitor (the pixel capacitor and the auxiliary capacitor when the auxiliary capacitor is also formed) in a short time.
  • the number of formation parts Pij can be increased.
  • the signal voltage written in the pixel capacitor can be held for a long time by reducing the off-state current.
  • the present invention can also be applied to an organic EL (Electro Luminescence) display device.
  • the present invention is suitable for a thin film transistor used in a display device such as an active matrix liquid crystal display device, and is particularly suitable for a thin film transistor used as a switching element formed in the pixel formation portion.
  • SYMBOLS 10 Liquid crystal display device 15 ... Insulating substrate 20 ... Gate electrode 30 ... Gate insulating film 31 ... Silicon nitride film 32 ... Silicon oxide film 40, 50 ... Semiconductor layer 40a, 50a ... Channel region 40b, 50b ... Low resistance region 40c, 50c ... high resistance regions 41, 51 ... notches 42 ... notches 60a, 70a ... source electrodes 60b, 70b ... drain electrodes 80 ... etching stopper layer 90 ... passivation film 100-500 ... TFT (thin film transistor)

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Abstract

Une couche semi-conductrice (40) est formée à partir d'un semi-conducteur oxyde dans lequel la largeur d'une zone de canal (40a) est inférieure aux largeurs d'électrodes de source et de drain (60a, 60b) et l'aire de la surface latérale est élargie. La couche semi-conductrice (40) est intercalée entre une pellicule d'isolation de gâchette (30) et une pellicule de passivation (90) et est soumise à un recuit dans une atmosphère contenant de l'oxygène. En conséquence, l'oxygène externe et l'oxygène contenu dans la pellicule d'isolation de gâchette (30) et la pellicule de passivation (90) sont fournis à la zone de canal (40a), les aires de zones à faible résistance (40b) deviennent petites, et la zone intercalée entre les deux zones à faible résistance (40b) devient une zone à résistance élevée (40c). En même temps, la résistance de contact entre la couche semi-conductrice (40) et les électrodes de source et de drain (60a, 60b) est maintenue basse. Ainsi, le ratio d'activation et de désactivation devient large et des propriétés de transistor convenables sont obtenues.
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WO2017144994A1 (fr) * 2016-02-22 2017-08-31 株式会社半導体エネルギー研究所 Transistor et son procédé de fabrication, tranche à semi-conducteurs et dispositif électronique
KR20200123207A (ko) 2019-02-25 2020-10-28 가부시키가이샤 알박 플라즈마 cvd 장치 및 플라즈마 cvd 방법
CN112071915A (zh) * 2019-06-10 2020-12-11 堺显示器制品株式会社 薄膜晶体管及其制造方法以及显示装置
CN112349733A (zh) * 2020-09-09 2021-02-09 湖北长江新型显示产业创新中心有限公司 阵列基板、阵列基板的制造方法及显示装置
JP2021120974A (ja) * 2020-01-30 2021-08-19 株式会社Flosfia 半導体装置および半導体システム
JPWO2022043809A1 (fr) * 2020-08-27 2022-03-03
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JP2006261423A (ja) * 2005-03-17 2006-09-28 Ricoh Co Ltd 薄膜トランジスタ及びそれを用いた画像表示装置
WO2007086368A1 (fr) * 2006-01-30 2007-08-02 Sharp Kabushiki Kaisha Transistor à film mince, et substrat matriciel actif et dispositif d’affichage pourvus d’un tel transistor à film mince
JP2011109084A (ja) * 2009-10-21 2011-06-02 Semiconductor Energy Lab Co Ltd 半導体装置

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JP2017147378A (ja) * 2016-02-18 2017-08-24 株式会社神戸製鋼所 薄膜トランジスタ
WO2017144994A1 (fr) * 2016-02-22 2017-08-31 株式会社半導体エネルギー研究所 Transistor et son procédé de fabrication, tranche à semi-conducteurs et dispositif électronique
US11411120B2 (en) 2017-09-05 2022-08-09 Ulvac, Inc. Method for manufacturing semiconductor device using plasma CVD process
KR20200123207A (ko) 2019-02-25 2020-10-28 가부시키가이샤 알박 플라즈마 cvd 장치 및 플라즈마 cvd 방법
CN112071915A (zh) * 2019-06-10 2020-12-11 堺显示器制品株式会社 薄膜晶体管及其制造方法以及显示装置
JP2021120974A (ja) * 2020-01-30 2021-08-19 株式会社Flosfia 半導体装置および半導体システム
JP7539630B2 (ja) 2020-01-30 2024-08-26 株式会社Flosfia 半導体装置および半導体システム
JPWO2022043809A1 (fr) * 2020-08-27 2022-03-03
JP7796027B2 (ja) 2020-08-27 2026-01-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
CN112349733A (zh) * 2020-09-09 2021-02-09 湖北长江新型显示产业创新中心有限公司 阵列基板、阵列基板的制造方法及显示装置
CN112349733B (zh) * 2020-09-09 2022-09-06 湖北长江新型显示产业创新中心有限公司 阵列基板、阵列基板的制造方法及显示装置

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