WO2012034371A1

WO2012034371A1 - Mos transistor

Info

Publication number: WO2012034371A1
Application number: PCT/CN2011/070949
Authority: WO
Inventors: Genyi Wang; Tzong Shiann Wo
Original assignee: CSMC Technologies Fab1 Co Ltd; CSMC Technologies Fab2 Co Ltd
Current assignee: CSMC Technologies Fab1 Co Ltd; CSMC Technologies Fab2 Co Ltd
Priority date: 2010-09-14
Filing date: 2011-02-12
Publication date: 2012-03-22
Anticipated expiration: 2013-03-14
Also published as: CN102403352A

Abstract

A metal oxide semiconductor (MOS) transistor (200) includes, in part, a semiconductor substrate (201), an epitaxial layer (202) formed above the substrate (201), a well region (203) formed in the epitaxial layer (202), a multitude of trenches (210) formed in the well region (203) with each trench (210) having formed therein a gate oxide layer (212) and a polysilicon gate (211), a multitude of contact holes (220) formed in the well region (203) wherein each contact hole (220) is positioned between a pair of adjacent trenches (210) and has disposed therein an adhesion layer (232) and a first metal layer (233) forming a metal plug, a multitude of body contact regions (204) positioned below the contact holes (220), and a multitude of source regions (231) formed in the well region (203). Each source region (231) is positioned between a trench (210) and a contact hole (220). The substrate (201), the epitaxial layer (202), and the source regions (231) are of a first conductivity type. The well region (203) and the body contact regions (204) are of a second conductivity type opposite the first conductivity type. The MOS transistor can minimize various parasitic effects and improve performance thereof. A method is also provided.

Description

MOS TRANSISTOR

Background of the Disclosure

[0001] The present invention relates to a transistor structure, and in particular to a trench vertical double diffused metal oxide semiconductor transistor structure.

[0002] Double diffused metal oxide semiconductor (DMOS) transistors are known. A DMOS transistor has a trench and is formed using a self-aligned submicron process that benefits from the difference in lateral diffusion speeds of two kinds of impurity atoms. DMOS transistors can operate at relatively high frequencies and thus achieve high operating speeds.

[0003] A DMOS transistor differs from a conventional MOS transistors in two main respects. In a DMOS transistor P type and N type impurities are diffused sequentially through the same oxide layer window to form a short channel. Furthermore, a DMOS transistor includes a lightly doped N- drift region between its channel and drain regions. The doping concentration of the lightly doped N- drift region is substantially less than the doping concentration of the channel region. The lightly doped N- drift region sustains most of the applied drain voltage so as to minimize short channel effects and improve drain breakdown voltage characteristics.

[0004] A DMOS transistor may be a lateral DMOS (LDMOS) transistor or a vertical DMOS (VDMOS) transistor. The use of vertical DMOS transistors is on the rise due to their high performance and integration.

[0005] Figure 1 is a cross-sectional view of a conventional TDMOS transistor 100, as known in the prior art. As shown in Figure 1, TDMOS transistor 100 includes an N+ semiconductor substrate 101, an N- epitaxial layer 102, a P-type well region 103, polysilicon gate 130 formed in the trench extending to epitaxial layer 102, N+ doped source region 111, and gate oxide layer 131. The drain of TDMOS transistor 100 is coupled to metal layer 120 formed on the backside of substrate 101. The source of TDMOS transistor 100 is coupled to metal layer 110 formed on the surface of source region 111 and p-type well 103. Since P-well 103 is relatively lightly doped, its contact with metal layer 110 results in various parasitic effects that adversely affects transistor 100's performance.

Summary of the Disclosure

[0006] A MOS transistor, in accordance with one embodiment of the present invention, includes, in part, a semiconductor substrate, an epitaxial layer formed above the substrate, a well region formed in the epitaxial layer, a multitude of trenches formed in the well region with each trench having formed therein a gate oxide layer and a polysilicon gate, a multitude of contact holes formed in the well region wherein each contact hole is positioned between a pair of adjacent trenches and has disposed therein an adhesion layer and a first metal layer forming a metal plug, a multitude of body contact regions positioned below the contact holes, and a multitude of source regions formed in the well region. Each source region is positioned between a trench and a contact hole. The substrate, the epitaxial layer, and the source regions are of the first conductivity type. The well region and the body contact regions are of the second conductivity type opposite the first conductivity type.

[0007] In one embodiment, each contact hole has an opening between 0.2μιη and 0.5μιη and a depth greater than an ion injection depth of the source region but less than the depth of the trenches. In one embodiment, the doping concentration of the body contact regions is greater than the doping concentration of the well region. In one embodiment, the adhesion layer includes a Ti/TiN laminated layer. In one embodiment, the first metal layer is a tungsten layer. In one embodiment, the gate oxide layer formed in each trench extends outwardly so as to cover a surface of the source region adjacent that trench.

[0008] In one embodiment, the MOS transistor further includes an oxide layer formed above the polysilicon gates of the trenches. The MOS transistor further includes, in part, a dielectric layer formed over the oxide layer covering surfaces of the source regions. The dielectric layer is also formed over the oxide layer covering the surfaces of the polysilicon gates. The surfaces of the dielectric layer and the first metal layer are substantially coplanar. In one embodiment, the dielectric layer is a borophosphosilicate glass layer.

[0009] In one embodiment, the MOS transistor further includes, in part, a second metal layer formed above the dielectric layer and the first metal layer. In one embodiment, the second metal layer is a laminated layer that includes, in part, an adhesion layer and a third metal layer. In one embodiment, the third metal layer is an AlSiCu alloy. In one embodiment, the first conductivity type is N type and the second conductivity type is P type. In yet another embodiment, the first conductivity type is P type semiconductor and the second conductivity type is N type.

Brief Description of the Drawings

[0010] Figure 1 is a cross-sectional view of a trench vertical double diffused metal oxide semiconductor transistor, as known in the prior art.

[0011] Figure 2 is a cross-sectional view of a metal oxide semiconductor transistor, in accordance with one embodiment of the present invention.

Detailed Description of the Embodiments

[0012] Figure 2 is a cross-sectional view of an MOS transistor 200, in accordance with one embodiment of the present invention. MOS transistor 200, which is a trench vertical double diffused metal oxide semiconductor (alternatively referred to herein as TDMOS) transistor, is shown as including a semiconductor substrate 201 having a first conductivity type, an epitaxial layer 202 having the first conductivity type and formed above substrate 201, a well region 203 of a second conductivity type formed in epitaxial layer 202, and a multitude of trenches 210 formed in well region 203. As shown, trenches 210 extend into epitaxial layer 202. Each trench 210 includes a gate oxide layer 212 formed along the walls and bottom of that trench, and a polysilicon gate 211. MOS transistor 200 is also shown as including a multitude of contact holes 220 extending in well region 203. Each contact hole 220 is positioned between a pair of adjacent trenches 210 and includes an adhesion layer 232 and a metal layer 233 forming a metal plug. TDMOS transistor 200 is also shown as including a multitude of body contact regions 204 of the second conductivity type. Each body contact region 204 is positioned along the bottom as well along the sides near the bottom of an associated contact hole 220 in well region 203. TDMOS transistor 200 is also shown as including a multitude of source regions 231 of the first conductivity type formed in well region 203. Each source region 231 is positioned between a trench 210 and a contact hole 220.

[0013] In accordance with one exemplary embodiment of the present invention, substrate 201 and source regions 231 of the MOS transistor 200 are heavily doped. The doping concentration of source regions 231 is less than that of substrate 201. Epitaxial layer 202 is relatively lightly doped and has a doping concentration that is less than that of source regions 231. Body contact regions 204 are heavily doped. Well region 203 is lightly doped and has a doping concentration that is less than that of body contact regions 204.

[0014] In accordance with one exemplary embodiment of the present invention, contact holes 220 of the TDMOS transistor have an opening between 0.2μιη to 0.5μιη and a depth between 0.35μιη and Ιμιη. The depth of contact holes 220 is greater than the ion injection depth of source region 231 (i.e., the depth that the impurities reach after they are implanted in the source and then diffused) and less than the depth of trenches 210. In one embodiment, contact holes 220 have an opening of 0.75μιη and a depth of 0.7μηι. Contact holes 220 are formed in well region 203 and have a depth that is less than the depth of well region 203.

[0015] In one embodiment, contact holes 220 have an opening of 0.4μιη and a depth of Ο.όμηι. In one embodiment, adhesion layer 232 formed in contact holes 220 includes a Ti/TiN laminated layer forming contacts with source regions 231. Adhesion layer 232 prevents metal 233 from diffusing out of the contact holes. In one embodiment, metal layer 233 is a layer of tungsten. Therefore, the metal plug in each contact hole 220 is a tungsten plug.

[0016] In accordance with one exemplary embodiment of the present invention, gate oxide layer 212 of the MOS transistor extends outwardly to cover the surface of source regions 231, as shown in Figure 2. In such embodiments, the upper surface of polysilicon gate 211 is covered with an oxide layer 214. In accordance with yet another exemplary embodiment of the present invention, the oxide layer covering the surfaces of source regions 231, and polysilicon gates 211 of the TDMOS transistor are covered with a relatively thin layer of oxide 214. Accordingly, in such embodiments, oxide layer 214 overlays gate oxide layer 212 (covering the surface of source regions 231) as well as polysilicon gates 211. In such embodiments, an insulating dielectric layer 213 is formed over gate oxide layer 212 and oxide layer 214, as shown. The surfaces of the insulating dielectric layer 213 and metal layer 233 are substantially coplanar. In some embodiments, dielectric layer 213 is a borophosphosilicate glass (BPSG).

[0017] As shown in Figure 2, a metal layer 230 is formed over dielectric layer 213 and metal layer 233. In some embodiments, as shown in Figure 2, metal layer 230 is of a laminated layer structure and includes an adhesion layer 232 and a metal layer 234.

[0018] In one embodiment, adhesion layer 232 is a Ti/TiN laminated layer. Adhesion layer 232 provides a significantly improved bonding between metal layers 233 and 234. Ti/TiN has an excellent filling capability and forms a strong bond with silicon body. Ti/TiN bonds strongly with insulation dielectric layer 213 so as to significantly improve the stability of the metal structure. In some embodiments, metal layer 234 is an AlSiCu alloy used for connecting the source regions to an external source.

[0019] In accordance with one embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type. Accordingly, in such embodiments, substrate 201 which forms the drain region of TDMOS transistor 200 is of N type conductivity. Epitaxial layer 202 which has a lower doping concentration than substrate 201 is also of N type conductivity. Source region 231 is a heavily doped N type region. Accordingly, in such embodiments, TDMOS transistor 200 is a P-channel vertical trench MOS transistor. The channel of such a transistor is a lightly doped P-type region extending from N+ type source region 231 along the side walls of trenches 210 to N type epitaxial layer 202. To form a channel in such embodiments, a positive voltage VQ_S greater than threshold voltage Vt is applied between the gate region 211 and source region 231. The application of this voltage causes the P-type channel to be inverted to an N-type so as to form a conductive path between source region 231 and drain region 201. When the voltage of the drain is higher than the voltage of the source (i.e. V_DS>0 is applied between the source and drain regions) electrons in the N-type source region reach the drain region via the conductive channel region, thereby causing a drain-source current to flow from the drain to the source. The larger the value of VQ_S is, the smaller the corresponding channel resistance will be, and under the same V_DS bias, the larger the drain source current will be. After flowing through the channel, the current reaches semiconductor substrate 201 (the drain of TDMOS transistor 200) and received by drain metal layer 120.

[0020] In accordance with another embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type. Accordingly, in such embodiments, substrate 201 which forms the drain region of TDMOS transistor 200 is of P type conductivity. Epitaxial layer 202 which has a lower doping concentration than substrate 201 is also of P type conductivity. Source region 231 is a heavily doped P type region. Accordingly, in such embodiments, TDMOS transistor 200 is an N-channel vertical trench MOS transistor. The channel of such a transistor is a lightly doped N-type region extending from P+ doped source region 231 along the side walls of trenches 210 to P-type epitaxial layer 202. To form a channel in such embodiments, a negative voltage VQ_S whose absolute value is greater than the absolute value of the threshold voltage Vt is applied between the gate region 211 and source region 231. The application of this voltage causes the N-type channel to be inverted to a P-type so as to form a conductive path between source region 231 and drain region 201. When the voltage of the drain is lower than the voltage of the source (i.e. V_DS<0 is applied between the source and drain regions), holes in the P-type source region reach the drain region via the conductive channel region, thereby causing a source-drain current to flow from the source to the drain. The more negative is the value of VQ_S, the smaller the corresponding channel resistance will be, and under the same V_DS bias, the larger the drain source current will be. After flowing through the channel, the current reaches semiconductor substrate 201 (the drain of TDMOS transistor 200) and received by drain metal layer 120.

[0021] In accordance with one embodiment of the present invention, as described above, adhesion layer 232 and metal layer 233 fill contact holes 220. Each contact hole 220 is shown as being positioned between a pair of source regions 231. A heavily doped body contact region 204 is formed along the bottom as well along the sides of its associated contact hole 220. Accordingly, contacts between metal layer 233 and the silicon body as well as contacts between metal layer 233 and the source regions are made through contact holes 220. Source regions 231 make contacts with metal layer 233 via the side walls of contact holes 220. The silicon body forms contacts with metal layer 233 via the bottom as well as the sides of contact holes 220 and heavily doped regions 204. Consequently contacts between the source regions and the silicon body are made via metal layer 233. In other words, in various embodiments of a TDMOS transistor of the present invention, silicon body regions that contact metal layer 233 are all heavily doped, thereby effectively minimizing various parasitic effects and improving transistor's performance. Furthermore, because the metal plugs enable the contact holes 220 to have narrower openings, the size of transistor 200 is advantageously reduced enhancing its integration.

[0022] The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. Other additions, subtractions or modifications are obvious in view of the present invention and are intended to fall within the scope of the appended claim.

Claims

1. A MOS transistor, comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer formed above the substrate and having a first conductivity type;

a well region formed in the epitaxial layer and having a second conductivity type;

a plurality of trenches formed in the well region, each trench comprising a gate oxide layer and a polysilicon gate;

a plurality of contact holes formed in the well region, each contact hole positioned between a pair of adjacent trenches and having disposed therein an adhesion layer and a first metal layer forming a metal plug;

a plurality of body contact regions positioned below the plurality of contact holes and having a second conductivity type; and

a plurality of source regions formed in the well region and having the first conductivity type, each source region positioned between one of the plurality of trenches and one of the plurality of contact holes.

2. The MOS transistor of claim 1 wherein each contact hole has an opening between 0.2μιη and 0.5μιη and a depth greater than an ion injection depth of the source region and less than a depth of the trenches.

3. The MOS transistor of claim 1 wherein a doping concentration of the body contact regions is greater than a doping concentration of the well region.

4. The MOS transistor of claim 1 wherein the adhesion layer comprises a Ti/TiN laminated layer.

The MOS transistor of claim 1 wherein the first metal layer is a tungsten layer.

6. The MOS transistor of claim 1 wherein the gate oxide layer formed in each trench extends outwardly to cover a surface of a source region adjacent the trench.

7. The MOS transistor of claim 6 wherein the MOS transistor further comprises an oxide layer formed above the polysilicon gates of the plurality of trenches.

8. The MOS transistor of claim 7 wherein the MOS transistor further comprises a dielectric layer formed over the oxide layer covering surfaces of the source regions, said dielectric layer being also formed over the oxide layer covering surfaces of the polysilicon gates.

9. The MOS transistor of claim 8 wherein surfaces of the dielectric layer and the first metal layer are substantially coplanar.

10. The MOS transistor of claim 8 wherein said dielectric layer is a borophosphosilicate glass layer.

11. The MOS transistor of claim 9 wherein the MOS transistor further comprises a second metal layer formed above the dielectric layer and the first metal layer.

12. The MOS transistor of claim 11 wherein the second metal layer is a laminated layer comprising an adhesion layer and a third metal layer.

13. The MOS transistor of claim 12 wherein the third metal layer is an AlSiCu alloy.

14. The MOS transistor of claim 1 wherein the first conductivity type is N type and the second conductivity type is P type.

15. The MOS transistor of claim 1 wherein the first conductivity type is P type and the second conductivity type is N type.

16. A method of forming an MOS transistor, the method comprising: providing a semiconductor substrate of a first conductivity type;

forming an epitaxial layer of the first conductivity type above the substrate; forming a well region of a second conductivity type in the epitaxial layer;

forming a plurality of trenches in the well region, each trench comprising a gate oxide layer and a polysilicon gate;

forming a plurality of contact holes in the well region, each contact hole positioned between a pair of adjacent trenches and having disposed therein an adhesion layer and a first metal layer forming a metal plug;

forming a plurality of body contact regions of the second conductivity type below the plurality of contact holes; and

forming a plurality of source regions of the first conductivity type in the well region, each source region positioned between one of the plurality of trenches and one of the plurality of contact holes.

17. The method of claim 16 wherein a doping concentration of the body contact regions is greater than a doping concentration of the well region.

18. The method of claim 16 wherein the adhesion layer comprises a Ti/TiN laminated layer.

19. The method of claim 16 wherein the gate oxide layer formed in each trench extends outwardly to cover a surface of a source region adjacent the trench.

20. The method of claim 19 wherein the MOS transistor further comprises an oxide layer formed above the polysilicon gates of the plurality of trenches.