[go: up one dir, main page]

WO2012033664A3 - Methods and circuits for precise termination - Google Patents

Methods and circuits for precise termination Download PDF

Info

Publication number
WO2012033664A3
WO2012033664A3 PCT/US2011/049586 US2011049586W WO2012033664A3 WO 2012033664 A3 WO2012033664 A3 WO 2012033664A3 US 2011049586 W US2011049586 W US 2011049586W WO 2012033664 A3 WO2012033664 A3 WO 2012033664A3
Authority
WO
WIPO (PCT)
Prior art keywords
bias
termination
circuits
methods
receive amplifiers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2011/049586
Other languages
French (fr)
Other versions
WO2012033664A4 (en
WO2012033664A2 (en
Inventor
Kambiz Kaviani
Amir Amirkhany
Aliazam Abbasfar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Publication of WO2012033664A2 publication Critical patent/WO2012033664A2/en
Publication of WO2012033664A3 publication Critical patent/WO2012033664A3/en
Publication of WO2012033664A4 publication Critical patent/WO2012033664A4/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Networks Using Active Elements (AREA)

Abstract

Described are integrated signal interfaces that include receive amplifiers and termination elements. Termination control circuitry calibrates the impedances through the termination elements to take into account the transconductance of the receive amplifiers. Transconductance bias circuitry can be used to bias the receive amplifiers, and the bias can be derived from a reference voltage. The interfaces can derive the common-mode voltage from received signals as the reference voltage, rather than from a dedicated voltage reference.
PCT/US2011/049586 2010-09-10 2011-08-29 Methods and circuits for precise termination Ceased WO2012033664A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38158410P 2010-09-10 2010-09-10
US61/381,584 2010-09-10

Publications (3)

Publication Number Publication Date
WO2012033664A2 WO2012033664A2 (en) 2012-03-15
WO2012033664A3 true WO2012033664A3 (en) 2012-07-12
WO2012033664A4 WO2012033664A4 (en) 2012-08-23

Family

ID=45811123

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/049586 Ceased WO2012033664A2 (en) 2010-09-10 2011-08-29 Methods and circuits for precise termination

Country Status (1)

Country Link
WO (1) WO2012033664A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10255220B2 (en) 2015-03-30 2019-04-09 Rambus Inc. Dynamic termination scheme for memory communication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080136256A1 (en) * 2006-12-11 2008-06-12 Amit Gattani Network devices with solid state transformer and electronic load circuit to provide termination of open-drain transmit drivers of a physical layer module
US7620121B1 (en) * 2004-12-09 2009-11-17 Xilinx, Inc. DC balance compensation for AC-coupled circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7620121B1 (en) * 2004-12-09 2009-11-17 Xilinx, Inc. DC balance compensation for AC-coupled circuits
US20080136256A1 (en) * 2006-12-11 2008-06-12 Amit Gattani Network devices with solid state transformer and electronic load circuit to provide termination of open-drain transmit drivers of a physical layer module

Also Published As

Publication number Publication date
WO2012033664A4 (en) 2012-08-23
WO2012033664A2 (en) 2012-03-15

Similar Documents

Publication Publication Date Title
EP2532092A4 (en) Generation of differential signals
WO2012166425A3 (en) Methods of amplifying whole genome of a single cell
WO2014015256A3 (en) Enzymatic oxidation of 5-hydroxymethylfurfural and derivatives thereof
WO2011112579A3 (en) High-speed differential comparator circuitry with accurately adjustable threshold
WO2013061252A3 (en) Post-filter common-gain determination
WO2009146321A8 (en) Ligand functionalized substrates
WO2011133504A3 (en) Nanozymes, methods of making nanozymes, and methods of using nanozymes
EP2383885A4 (en) Transimpedance amplifier
EP2449689B8 (en) Method for connecting signal paths, and function group designed therefor
WO2010011264A3 (en) Impedance matching
TW201129809A (en) Differential sensing system and method for using the same
WO2011005289A3 (en) Methods and kits for measuring enzyme activity
EP2963813A4 (en) Digital amplifier, three-value signal output method, and speaker
WO2012075117A3 (en) Small molecule-polymer conjugates and methods of making same
WO2011019426A3 (en) Vicinity sensor systems and related methods
EP2676384A4 (en) Characterization of non-ase noise on optical signals
GB2475348B (en) Gain control for an audio signal
WO2013163297A8 (en) Modified glycoproteins
WO2013078196A8 (en) Compensation network using an orthogonal compensation network
IN2014CN02257A (en)
EP2434642A4 (en) Transimpedance amplifier, integrated circuit, and system
WO2013023653A3 (en) Circuit arrangement and method for transmitting signals
WO2011005345A3 (en) Apparatus and methods for implementing multi-channel tuners
WO2013023651A3 (en) Circuit arrangement and method for transmitting signals
WO2012151496A3 (en) Intra-pair skew cancellation for differential signaling

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11823966

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 27.06.2013)

122 Ep: pct application non-entry in european phase

Ref document number: 11823966

Country of ref document: EP

Kind code of ref document: A2