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WO2012033664A3 - Methods and circuits for precise termination - Google Patents

Methods and circuits for precise termination Download PDF

Info

Publication number
WO2012033664A3
WO2012033664A3 PCT/US2011/049586 US2011049586W WO2012033664A3 WO 2012033664 A3 WO2012033664 A3 WO 2012033664A3 US 2011049586 W US2011049586 W US 2011049586W WO 2012033664 A3 WO2012033664 A3 WO 2012033664A3
Authority
WO
WIPO (PCT)
Prior art keywords
bias
termination
circuits
methods
receive amplifiers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2011/049586
Other languages
French (fr)
Other versions
WO2012033664A4 (en
WO2012033664A2 (en
Inventor
Kambiz Kaviani
Amir Amirkhany
Aliazam Abbasfar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Publication of WO2012033664A2 publication Critical patent/WO2012033664A2/en
Publication of WO2012033664A3 publication Critical patent/WO2012033664A3/en
Publication of WO2012033664A4 publication Critical patent/WO2012033664A4/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)
  • Networks Using Active Elements (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Described are integrated signal interfaces that include receive amplifiers and termination elements. Termination control circuitry calibrates the impedances through the termination elements to take into account the transconductance of the receive amplifiers. Transconductance bias circuitry can be used to bias the receive amplifiers, and the bias can be derived from a reference voltage. The interfaces can derive the common-mode voltage from received signals as the reference voltage, rather than from a dedicated voltage reference.
PCT/US2011/049586 2010-09-10 2011-08-29 Methods and circuits for precise termination Ceased WO2012033664A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38158410P 2010-09-10 2010-09-10
US61/381,584 2010-09-10

Publications (3)

Publication Number Publication Date
WO2012033664A2 WO2012033664A2 (en) 2012-03-15
WO2012033664A3 true WO2012033664A3 (en) 2012-07-12
WO2012033664A4 WO2012033664A4 (en) 2012-08-23

Family

ID=45811123

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/049586 Ceased WO2012033664A2 (en) 2010-09-10 2011-08-29 Methods and circuits for precise termination

Country Status (1)

Country Link
WO (1) WO2012033664A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10255220B2 (en) 2015-03-30 2019-04-09 Rambus Inc. Dynamic termination scheme for memory communication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080136256A1 (en) * 2006-12-11 2008-06-12 Amit Gattani Network devices with solid state transformer and electronic load circuit to provide termination of open-drain transmit drivers of a physical layer module
US7620121B1 (en) * 2004-12-09 2009-11-17 Xilinx, Inc. DC balance compensation for AC-coupled circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7620121B1 (en) * 2004-12-09 2009-11-17 Xilinx, Inc. DC balance compensation for AC-coupled circuits
US20080136256A1 (en) * 2006-12-11 2008-06-12 Amit Gattani Network devices with solid state transformer and electronic load circuit to provide termination of open-drain transmit drivers of a physical layer module

Also Published As

Publication number Publication date
WO2012033664A4 (en) 2012-08-23
WO2012033664A2 (en) 2012-03-15

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