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WO2012081144A1 - Semiconductor device and production method for same - Google Patents

Semiconductor device and production method for same Download PDF

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Publication number
WO2012081144A1
WO2012081144A1 PCT/JP2011/004523 JP2011004523W WO2012081144A1 WO 2012081144 A1 WO2012081144 A1 WO 2012081144A1 JP 2011004523 W JP2011004523 W JP 2011004523W WO 2012081144 A1 WO2012081144 A1 WO 2012081144A1
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Prior art keywords
semiconductor device
manufacturing
electrode
metal fine
electrodes
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PCT/JP2011/004523
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French (fr)
Japanese (ja)
Inventor
信雄 青井
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Panasonic Corp
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Panasonic Corp
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    • H10W90/00
    • H10W72/01204
    • H10W72/01225
    • H10W72/01935
    • H10W72/0198
    • H10W72/072
    • H10W72/241
    • H10W72/251
    • H10W72/252
    • H10W72/29
    • H10W72/9415
    • H10W72/952
    • H10W90/722
    • H10W90/724

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a chip-chip stacking, a chip-wafer stacking or a wafer-wafer stacking semiconductor device and a manufacturing method thereof.
  • the semiconductor integrated circuit device is three-dimensionally stacked to expand the wiring area, thereby enabling the wiring cross-sectional area to be increased and the wiring length to be shortened. That is, it is possible to improve performance while increasing the degree of integration.
  • the electrodes are joined together by a method in which the electrodes are thermocompression-bonded in chip-chip lamination, chip-wafer lamination, or wafer-wafer lamination.
  • FIG. 5 shows a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique.
  • a through electrode 101 is formed in a first substrate 100 having an element formation surface (front surface) 100a and an opposite surface (back surface) 100b.
  • a transistor 102 is formed over the surface 100 a of the first substrate 100, and a wiring layer 103 having a multilayer wiring electrically connected to the transistor 102 and the through electrode 101 is formed.
  • the top portion of the through electrode 101 serving as the back surface side electrode is exposed.
  • the first substrate 100 includes a second substrate 200 having an element formation surface (front surface) 200a and an opposite surface (back surface) 200b, a back surface 100 of the first substrate 100, and a front surface 200a of the second substrate 200. They are stacked so as to face each other.
  • a transistor 201 is formed over the surface 200 a of the second substrate 200, and a wiring layer 202 having a multilayer wiring electrically connected to the transistor 201 is formed.
  • an electrode pad 203 connected to the top portion of the through electrode 101 serving as the back side electrode of the first substrate 100 is formed.
  • the back surface side electrode is formed by exposing the top of the through electrode 101 on the back surface 100b side of the first substrate 100 using grinding, CMP (chemical mechanical polishing), dry etching, or the like, as shown in FIG.
  • the position of the top portion (bottom surface of the exposed portion) of the through electrode 101 varies.
  • the diameter of the through electrode 101 is typically about 5 ⁇ m to about 100 ⁇ m
  • the height of the exposed portion (back surface side electrode) of the through electrode 101 is typically about 0.5 ⁇ m to about 10 ⁇ m.
  • the size of the position variation at the top of the through electrode 101 is typically about 0.1 ⁇ m to about 1 ⁇ m.
  • Such positional variations include the thickness variation of the first substrate 100 itself, the resist pattern dimensional variation in the lithography process when the through electrode 101 is formed, and the penetration due to the variation in the dry etching rate within the wafer surface. This occurs due to variations in the height of the exposed portion of the electrode 101 itself.
  • the bottom surface of the through electrode 101 of the first substrate 100 and the top surface of the electrode pad 203 of the second substrate 200 are parallel to each other due to substrate thickness variation or warpage within the wafer surface. Since it cannot be held, the distance between the top portion of the through electrode 101 (the bottom surface of the back-side electrode) and the upper surface of the electrode pad 203 also varies within the wafer surface.
  • Patent Literature In order to solve the problems of the conventional three-dimensional integration technique, a technique has been proposed in which an assembly of metal particles is interposed between the electrodes when the electrodes of each substrate are joined together (Patent Literature). 1).
  • Patent Document 1 it is necessary to dispose a liquid material containing metal particles on each electrode using an ink jet apparatus, which complicates the process and deteriorates the throughput. At the same time, an increase in cost is inevitable.
  • an object of the present invention is to provide a new three-dimensional integration technique that can easily prevent a bonding failure between electrodes of each substrate.
  • a method of manufacturing a semiconductor device includes a first substrate on which a plurality of first electrodes are formed, and each first electrode of the first substrate.
  • first adhesion layer made of metal fine particles constituting the first metal fine particle layer on the top of each first electrode by adhering a part of the first metal fine particle layer; (B) and, after the step (b), the first electrodes and the first electrodes corresponding to the first electrodes.
  • the second electrodes are opposed to each other, and the first electrodes and the second electrodes corresponding to the first electrodes are connected via the first adhesion layer,
  • a layer made of metal fine particles is interposed between the electrodes. For this reason, even if there is a variation in the distance between the electrodes of each substrate due to the variation in the height of the electrodes, the variation in the thickness of the substrate (wafer), etc., a layer made of metal fine particles is formed according to the distance between the electrodes. By deform
  • step (c) heat treatment is performed while the first electrodes and the second electrodes corresponding to the first electrodes are pressure-bonded to each other.
  • each of the metal fine particles constituting the first adhesion layer is melted and integrated, whereby each of the first electrodes and each of the second electrodes corresponding to the first electrodes. And may be joined. If it does in this way, the electrodes of each board
  • the temperature of the heat treatment in the step (c) may be 150 ° C. or higher.
  • the surface of the metal fine particles constituting the first metal fine particle layer may be coated with a first organic material film. If it does in this way, oxidation and aggregation of metal particulates can be prevented.
  • the first organic material film covering the surface of the metal fine particles constituting the first adhesion layer may be detached from the surface. If it does in this way, since each metal microparticle can be fuse
  • the first organic material film may be, for example, a SAM film, and the SAM film may contain, for example, alkanethiol.
  • heat treatment may be performed while the top of each first electrode is pressed against the first metal fine particle layer. If it does in this way, a part of metal fine particle layer can adhere reliably on the top part of each electrode on a board
  • the temperature of the heat treatment in the step (b) may be 50 ° C. or higher and 200 ° C. or lower. In this way, it is possible to prevent an increase in melting point due to aggregation due to melting of the metal fine particles while reliably attaching a part of the metal fine particle layer on the top of each electrode on the substrate.
  • the electrodes can be joined at a predetermined temperature.
  • the metal fine particles constituting the first metal fine particle layer may have a particle size of 1 mm (0.1 nm) or more and 1 ⁇ m (1000 nm) or less, More preferably, it may be several tens or more and several hundreds of nm or less.
  • the metal fine particles when the average particle size of the metal fine particles is 50 nm or less, the metal fine particles can be melted in a low-temperature process of, for example, about 350 ° C. or less, so that the bonding strength between the electrodes is reduced while reducing damage to the semiconductor device. Can be strong. Such an effect can be obtained if the majority of the metal fine particles have a particle size of about 50 nm or less.
  • metal fine particles having a particle diameter exceeding 50 nm may be present. More preferably, the average particle diameter of the metal fine particles may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less. Also in this case, the particle size of the majority of the metal fine particles may be about 40 nm or less, and metal fine particles having a particle size exceeding 40 nm may be present.
  • the above relationship between the particle size and the process temperature is for the case where the metal fine particles are copper fine particles, but the same tendency (particle size) may be obtained for other metal fine particles such as gold and silver. The melting point decreases as the size of the material decreases.
  • the first metal fine particle layer may include fine particles having hardness higher than that of each of the first electrodes and each of the second electrodes.
  • the first metal fine particle layer may be one or more metal fine particles selected from a metal group composed of copper, silver, and gold, or the metal It may contain fine particles of an alloy of two or more metals selected from the group.
  • the first metal fine particle layer has a higher hardness than any of copper, silver and gold (that is, a Mohs hardness of 4 or more) and a conductivity of 1 ⁇ 10 7 / m ⁇ or more.
  • the metal fine particles may further be included. In this way, when the electrodes of each substrate are joined together, the natural oxide film and the contaminated layer formed on the electrode surfaces can be removed by the polishing effect of fine particles of other metals to expose the electrode surfaces.
  • the other metal is a metal selected from one or more metals selected from the group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum, and osmium.
  • An alloy of two or more metals selected from may be used.
  • a step (d) of forming a second metal fine particle layer on the second support member, and the respective steps of the second substrate before the step (c), a step (d) of forming a second metal fine particle layer on the second support member, and the respective steps of the second substrate.
  • the top part of the second electrode is brought into contact with the second metal fine particle layer on the second support member, and a part of the second metal fine particle layer is adhered on the top part of each second electrode.
  • step (E) further comprising a step (e) of forming a second adhesion layer made of metal fine particles constituting the second metal fine particle layer on the top of each second electrode, and in the step (c) By connecting the first electrodes and the second electrodes corresponding to the first electrodes through the first adhesion layer and the second adhesion layer, the first electrodes
  • the substrate and the second substrate may be laminated.
  • the surface of the metal fine particles constituting the second metal fine particle layer may be coated with a second organic material film. If it does in this way, oxidation and aggregation of metal particulates can be prevented.
  • the second organic material film covering the surface of the metal fine particles constituting the second adhesion layer may be detached from the surface. If it does in this way, since each metal microparticle can be fuse
  • the second organic material film may be, for example, a SAM film, and the SAM film may contain, for example, alkanethiol.
  • heat treatment may be performed while the top of each second electrode is pressed against the second metal fine particle layer. If it does in this way, a part of metal fine particle layer can adhere reliably on the top part of each electrode on a board
  • the temperature of the heat treatment in the step (e) may be 50 ° C. or higher and 200 ° C. or lower. In this way, it is possible to prevent an increase in melting point due to aggregation due to melting of the metal fine particles while reliably attaching a part of the metal fine particle layer on the top of each electrode on the substrate.
  • the electrodes can be joined at a predetermined temperature.
  • the metal fine particles constituting the second metal fine particle layer may have a particle size of 1 mm (0.1 nm) or more and 1 ⁇ m (1000 nm) or less, More preferably, it may be several tens or more and several hundreds of nm or less.
  • the metal fine particles when the average particle size of the metal fine particles is 50 nm or less, the metal fine particles can be melted in a low-temperature process of, for example, about 350 ° C. or less, so that the bonding strength between the electrodes is reduced while reducing damage to the semiconductor device. Can be strong. Such an effect can be obtained if the majority of the metal fine particles have a particle size of about 50 nm or less.
  • metal fine particles having a particle diameter exceeding 50 nm may be present. More preferably, the average particle diameter of the metal fine particles may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less. Also in this case, the particle size of the majority of the metal fine particles may be about 40 nm or less, and metal fine particles having a particle size exceeding 40 nm may be present.
  • the above relationship between the particle size and the process temperature is for the case where the metal fine particles are copper fine particles, but the same tendency (particle size) may be obtained for other metal fine particles such as gold and silver. The melting point decreases as the size of the material decreases.
  • the second metal fine particle layer may include fine particles having hardness higher than that of each of the first electrodes and each of the second electrodes.
  • the second metal fine particle layer may be one or more metal fine particles selected from a metal group composed of copper, silver, and gold, or the metal It may contain fine particles of an alloy of two or more metals selected from the group.
  • the second metal fine particle layer has a hardness higher than any of copper, silver and gold (that is, a Mohs hardness of 4 or more) and a conductivity of 1 ⁇ 10 7 / m ⁇ or more.
  • the metal fine particles may further be included. In this way, when the electrodes of each substrate are joined together, the natural oxide film and the contaminated layer formed on the electrode surfaces can be removed by the polishing effect of fine particles of other metals to expose the electrode surfaces.
  • the other metal is a metal selected from one or more metals selected from the group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum, and osmium.
  • An alloy of two or more metals selected from may be used.
  • At least one of the first electrodes and the second electrodes may be a tip portion of a through electrode.
  • At least one of the first electrodes and the second electrodes may be made of metal.
  • the metal constituting at least one of the first electrodes and the second electrodes may be copper or a copper alloy.
  • a semiconductor device includes a first substrate, a plurality of first electrodes formed on the first substrate, a second substrate, and the first substrate on the second substrate.
  • a plurality of second electrodes formed at positions corresponding to the first electrodes, and the first electrodes and the second electrodes corresponding to the first electrodes,
  • a plurality of metal fine particles are connected via a layer formed by melting and integrating, whereby the first substrate and the second substrate are laminated.
  • the electrodes of each substrate are connected through a layer formed by melting and integrating a plurality of metal fine particles. For this reason, even if there is a variation in the distance between the electrodes of each substrate due to the variation in the height of the electrodes, the variation in the thickness of the substrate (wafer), etc., a layer made of metal fine particles is formed according to the distance between the electrodes. By deform
  • the particle diameter of the plurality of metal fine particles may be 1 mm (0.1 nm) or more and 1 ⁇ m (1000 nm) or less, more preferably several mm or more and several hundreds. It may be less than or equal to nm.
  • the metal fine particles when the average particle size of the metal fine particles is 50 nm or less, the metal fine particles can be melted in a low-temperature process of, for example, about 350 ° C. or less, so that the bonding strength between the electrodes is reduced while reducing damage to the semiconductor device. Can be strong. Such an effect can be obtained if the majority of the metal fine particles have a particle size of about 50 nm or less.
  • metal fine particles having a particle diameter exceeding 50 nm may be present. More preferably, the average particle diameter of the metal fine particles may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less. Also in this case, the particle size of the majority of the metal fine particles may be about 40 nm or less, and metal fine particles having a particle size exceeding 40 nm may be present.
  • the above relationship between the particle size and the process temperature is for the case where the metal fine particles are copper fine particles, but the same tendency (particle size) may be obtained for other metal fine particles such as gold and silver. The melting point decreases as the size of the material decreases.
  • the plurality of metal fine particles may include fine particles having hardness higher than that of each of the first electrodes and each of the second electrodes.
  • the plurality of metal fine particles are selected from one or two or more metal fine particles selected from a metal group composed of copper, silver, and gold, or the metal group.
  • Two or more metal alloy fine particles may be included.
  • the plurality of metal fine particles have higher hardness than any of copper, silver, and gold metals (that is, Mohs hardness is 4 or more) and other metals having conductivity of 1 ⁇ 10 7 / m ⁇ or more. Further fine particles may be included. In this way, when the electrodes of each substrate are joined together, the natural oxide film and the contaminated layer formed on the electrode surfaces can be removed by the polishing effect of fine particles of other metals to expose the electrode surfaces. Therefore, the junction yield between the electrodes can be further improved.
  • the other metal is one selected from the group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum and osmium, or a metal selected from the group of metals. It may be an alloy of two or more selected metals.
  • At least one of the first electrodes and the second electrodes may be a tip portion of a through electrode.
  • At least one of the first electrodes and the second electrodes may be made of metal.
  • the metal constituting at least one of the first electrodes and the second electrodes may be copper or a copper alloy.
  • each of the first electrodes is formed so as to protrude from the surface of the first substrate, and the upper surface of each of the second electrodes is the surface of the second electrode. It may be formed so as to be substantially flush with the surface of the second substrate.
  • FIGS. 1A to 1E are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment.
  • 4A to 4H are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment.
  • FIG. 5 is a cross-sectional view of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique.
  • FIGS. 1A to 1E are cross-sectional views showing respective steps of a semiconductor device manufacturing method according to the first embodiment.
  • a metal fine particle layer 51 is formed on a support member 50 made of, for example, a silicon substrate.
  • the metal fine particle layer 51 is formed by, for example, using a solution in which copper fine particles having a SAM film (self-assembled monomolecular film) formed on the surface and having a diameter of several tens to several hundreds of nanometers are dispersed. You may carry out by carrying out spin coating on 50.
  • the polymer constituting the SAM film for example, alkanethiol having 7 or more carbon atoms may be used. More specifically, 3- (6-mercaptohexyl) thiophene known as a polymer that can coordinate to the surface of copper fine particles and stabilize the fine particles can also be used.
  • the solvent in the solution in which the above-described copper fine particles are dispersed is performed, for example, at a temperature of about 60 ° C. to about 150 ° C. Volatilize.
  • a plurality of electrodes 11 made of, for example, copper are formed on a substrate 10 made of, for example, silicon.
  • the electrode 11 may be formed on the substrate 10 using, for example, an electroless plating method.
  • a through electrode is formed in advance in the substrate 10, and then the substrate 10 is ground from the back surface (opposite surface of the element forming surface) to expose the front end portion of the through electrode.
  • the part may be used as the electrode 11.
  • the height of the electrodes 11 is, for example, about 5 ⁇ m, and the distance between the electrodes 11 is, for example, about 5 ⁇ m.
  • the tops of the electrodes 11 of the substrate 10 are brought into pressure contact with the metal fine particle layer 51 on the support member 50 at a pressure of 2 MPa, for example, for about 2 minutes.
  • a pressure of 2 MPa for example, for about 2 minutes.
  • FIG. 1C when the top of each electrode 11 of the substrate 10 is separated from the metal fine particle layer 51 on the support member 50, a part of the metal fine particle layer 51 adheres on the top of each electrode 11.
  • the adhesion layer 12 made of metal fine particles constituting the metal fine particle layer 51 is formed on the top of each electrode 11.
  • the temperature of this heat treatment may be set, for example, in a range from about 50 ° C. to about 200 ° C., but is not limited to this temperature range. However, it is desirable to set the temperature of the heat treatment to about 200 ° C. or less.
  • the metal fine particles constituting a part of the attached metal fine particle layer 51 This is because some of them may melt and cause aggregation.
  • the melting point of the metal fine particles becomes higher depending on the particle size. In other words, the melting point of the metal fine particles whose particle diameter is expanded by aggregation is higher than the melting point of the original metal fine particles before aggregation. As a result, the temperature required for joining the electrodes in the next process rises, causing damage to the semiconductor device.
  • a plurality of electrodes 21 made of, for example, copper are formed on a substrate 20 made of, for example, silicon.
  • Each electrode 21 is provided at a position corresponding to each electrode 11 of the substrate 10.
  • the formation of the electrode 21 on the substrate 20 may be performed using, for example, an electroless plating method.
  • a through electrode is formed in the substrate 20 in advance, and then the substrate 20 is ground from the back surface (opposite surface of the element forming surface) to expose the front end portion of the through electrode.
  • the part may be used as the electrode 21.
  • the height of the electrodes 21 is, for example, about 5 ⁇ m, and the distance between the electrodes 21 is, for example, about 5 ⁇ m.
  • each electrode 11 and each electrode 21 on the substrate 20 face each other, FIG.
  • the electrodes 11 and the electrodes 22 are pressure-bonded to each other at a pressure of 5 MPa, for example, for about 5 minutes through the adhesion layer 12.
  • substrate 20 are laminated
  • an adhesive may be applied between the substrate 10 and the substrate 20 when the substrate 10 and the substrate 20 are laminated.
  • an adhesive called underfill may be filled between the substrate 10 and the substrate 20.
  • the underfill material is sucked into the gap between the substrate 10 and the substrate 20 using surface tension. Before forming the bonding between the electrodes by the adhesion layer 12 made of metal fine particles, or by applying an adhesive to at least one of the substrate 10 and the substrate 20 in advance. A method of curing the adhesive after bonding may be used.
  • the heat treatment may be performed at a temperature of about 150 ° C. or more, for example.
  • the SAM film covering the surface of each metal fine particle constituting the adhesion layer 12 is detached, and the metal surface of each metal fine particle is exposed.
  • melting of the metal fine particles occurs even at a relatively low temperature, and as a result, the metal fine particles are integrated, so that the electrode 11 and the electrode 21 can be reliably bonded via the adhesion layer 12.
  • the adhesion layer 12 made of metal fine particles undergoes plastic deformation, as shown in FIG.
  • the adhesion layer 12 made of metal fine particles when the distance between the electrode 11 and the electrode 21 is relatively narrow, the adhesion layer 12 made of metal fine particles is relatively When the distance between the electrode 11 and the electrode 12 is relatively wide, the adhesion layer 12 made of metal fine particles is deformed relatively small. That is, in the bonding between each electrode 11 and the electrode 21, the adhesion layer 12 made of metal fine particles acts as a buffer region. For this reason, even if the space
  • the semiconductor device of this embodiment manufactured by the method described above corresponds to the substrate 10, the plurality of electrodes 11 formed on the substrate 10, the substrate 20, and each electrode 11 of the substrate 10 on the substrate 20.
  • Each electrode 11 and each electrode 21 corresponding to each electrode 11 are connected via an adhesion layer 12 formed by melting and integrating a plurality of metal fine particles.
  • the substrate 10 and the substrate 20 are laminated.
  • the adhesion layer 12 made of metal fine particles is interposed between each electrode 11 and each electrode 21. ing. For this reason, the distance between each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 varies due to the height variation of the electrode 11 or the electrode 21 or the thickness variation of the substrate 10 or the substrate 20. Even if there is, the adhesion layer 12 made of metal fine particles is deformed according to the distance between the electrodes, so that each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 can be reliably bonded. .
  • each electrode 11 on the substrate 10 is brought into contact with the metal fine particle layer 51 previously formed on the support member 50, whereby the adhesion layer made of metal fine particles is respectively formed on the top of each electrode 11. Therefore, the throughput can be improved and the cost can be reduced as compared with the case where a liquid material containing metal particles is disposed on each electrode using an inkjet apparatus.
  • the particle size of the metal fine particles constituting the metal fine particle layer 51 may be 1 mm (0.1 nm) or more and 1 ⁇ m (1000 nm) or less, more preferably several mm or more. And it may be several hundred nm or less.
  • the metal fine particles when the average particle diameter of the metal fine particles constituting the metal fine particle layer 51 is 50 nm or less, the metal fine particles can be melted in a low temperature process of, for example, about 350 ° C. or less, thereby reducing damage to the semiconductor device. The bonding strength between the electrodes can be increased. Such an effect can be obtained when the particle size of the majority of the metal fine particles in the metal fine particle layer 51 is about 50 nm or less.
  • metal fine particles having a particle diameter exceeding 50 nm may exist in the metal fine particle layer 51.
  • the average particle diameter of the metal fine particles constituting the metal fine particle layer 51 may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less, for example.
  • the particle diameter of the majority of the metal fine particles in the metal fine particle layer 51 may be about 40 nm or less, and metal fine particles having a particle diameter exceeding 40 nm may exist in the metal fine particle layer 51.
  • the above relationship between the particle size and the process temperature is for the case where the metal fine particles constituting the metal fine particle layer 51 are copper fine particles, but even if the metal fine particles are other metal fine particles such as gold and silver. , The same tendency (decrease in melting point with the refinement of particle size) is observed.
  • the metal fine particle layer 51 may include fine particles having a hardness higher than that of each electrode 11 and each electrode 21.
  • the surface of each electrode 11 or the natural oxide film or the contamination layer formed on the surface of each electrode 21 is Since the surface of each electrode 11 and the surface of each electrode 21 can be exposed by removing by the polishing effect by the fine particles having higher hardness than the electrode 11 and each electrode 21, the bonding yield between each electrode 11 and each electrode 21 can be further increased. Can be improved.
  • the metal fine particle layer 51 is composed of one or more metal fine particles selected from a metal group composed of copper, silver, gold, platinum, nickel, or the like, or of the metal group. It may contain fine particles of an alloy of two or more metals selected from the inside. In this case, the metal fine particle layer 51 is made of other metals having higher hardness than any of copper, silver and gold (that is, Mohs hardness of 4 or more) and conductivity of 1 ⁇ 10 7 / m ⁇ or more. It may further contain fine particles. In this way, when each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 are joined, the surface of each electrode 11 and the natural oxide film, the contamination layer, etc.
  • the other metal having high hardness is one or more selected from the metal group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum and osmium, or the metal It may be an alloy of two or more metals selected from the metal group.
  • copper is used as the material of the electrode 11 and the electrode 21, but the material of the electrode 11 and the electrode 21 is not particularly limited as long as the material has conductivity.
  • a copper alloy or other metal may be used instead of copper.
  • the material of the electrode 11 and the material of the electrode 21 may be different.
  • each electrode 21 is formed on the surface of the substrate 20 (if an interlayer film including wiring or the like is formed on the substrate 20, the interlayer Each electrode 21 was formed so as to protrude from the outermost surface of the film: the same applies hereinafter.
  • each electrode 21 is formed so that the surface of the substrate 20 and the upper surface of each electrode 21 are substantially flush with each other, and each electrode 21 and the substrate 10 are formed. You may join each electrode 11 above.
  • silicon substrates are used as the substrate 10 and the substrate 20, but the substrate materials of the substrate 10 and the substrate 20 are not particularly limited, and the material of the substrate 10 and the material of the substrate 20 are not limited. And may be different.
  • a silicon substrate is used as the support member 50, but the support member 50 is not particularly limited to a substrate or the like as long as a metal fine particle layer can be formed.
  • the semiconductor device and the manufacturing method thereof include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device).
  • the semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is laminated) or the wafer-wafer lamination (lamination of the wafer state semiconductor devices) and the manufacturing method thereof.
  • FIGS. 4A to 4H are cross-sectional views showing respective steps of a semiconductor device manufacturing method according to a modification of the first embodiment. 4A to 4H, the same components as those of the first embodiment shown in FIGS. 1A to 1E are denoted by the same reference numerals.
  • a metal fine particle layer 51 is formed on a support member 50 made of, for example, a silicon substrate.
  • the metal fine particle layer 51 is formed in the same manner as in the first embodiment, for example, with a SAM film (self-assembled monomolecular film) formed on the surface and a diameter of about several to several hundred nm. You may carry out by spin-coating the solution which disperse
  • SAM film self-assembled monomolecular film
  • the rotational speed and processing time in the spin coating of the solution in which the copper fine particles are dispersed are, for example, in the range from about 1000 rpm to about 5000 rpm, and from about 50 seconds to about 300 seconds, respectively, as in the first embodiment. You may set to the range.
  • the heat treatment is performed at a temperature from about 60 ° C. to about 150 ° C., for example, as in the first embodiment.
  • the solvent in the solution in which the copper fine particles are dispersed is volatilized.
  • a plurality of electrodes 11 made of, for example, copper are formed on a substrate 10 made of, for example, silicon.
  • the electrode 11 on the substrate 10 may be formed using, for example, an electroless plating method, as in the first embodiment.
  • a through electrode is formed in advance in the substrate 10, and then the substrate 10 is ground from the back surface (opposite surface of the element forming surface) to expose the front end portion of the through electrode.
  • the part may be used as the electrode 11.
  • the height of the electrodes 11 is, for example, about 5 ⁇ m, and the distance between the electrodes 11 is, for example, about 5 ⁇ m.
  • the top of each electrode 11 of the substrate 10 is placed on the metal fine particle layer 51 on the support member 50.
  • the pressure contact is performed at a pressure of 2 MPa for about 2 minutes.
  • the top of each electrode 11 of the substrate 10 is separated from the metal fine particle layer 51 on the support member 50 as shown in FIG. Then, a part of the metal fine particle layer 51 adheres to the top of each electrode 11, and the adhesion layer 12 made of the metal fine particles constituting the metal fine particle layer 51 is formed on the top of each electrode 11.
  • the metal fine particle layer is formed on the top of each electrode 11 by performing heat treatment. It becomes possible to adhere a part of 51 reliably.
  • the temperature of this heat treatment may be set, for example, in a range from about 50 ° C. to about 200 ° C., but is not limited to this temperature range. However, it is desirable to set the temperature of the heat treatment to about 200 ° C. or less.
  • the metal fine particles constituting a part of the attached metal fine particle layer 51 This is because some of them may melt and cause aggregation.
  • the melting point of the metal fine particles becomes higher depending on the particle size. In other words, the melting point of the metal fine particles whose particle diameter is expanded by aggregation is higher than the melting point of the original metal fine particles before aggregation. As a result, the temperature required for joining the electrodes in the next process rises, causing damage to the semiconductor device.
  • a metal fine particle layer 61 is formed on a support member 60 made of, for example, a silicon substrate.
  • the formation of the metal fine particle layer 61 is similar to the formation of the metal fine particle layer 51 described above.
  • a SAM film self-assembled monomolecular film
  • the thickness is about several to several hundred nm. You may carry out by spin-coating the solution which disperse
  • alkanethiol having 7 or more carbon atoms may be used as in the formation of the metal fine particle layer 51 described above, and more specifically, coordination is performed on the surface of the copper fine particles. Then, 3- (6-mercaptohexyl) thiophene, which is known as a polymer capable of stabilizing the fine particles, may be used.
  • 3- (6-mercaptohexyl) thiophene which is known as a polymer capable of stabilizing the fine particles, may be used.
  • the number of rotations and the processing time in the spin coating of the solution in which copper fine particles are dispersed are, for example, in the range from about 1000 rpm to about 5000 rpm, and from about 50 seconds to 300 seconds, as in the formation of the metal fine particle layer 51. You may set to the range to about second.
  • a heat treatment is performed at a temperature from about 60 ° C. to about 150 ° C., for example. Volatilize.
  • a plurality of electrodes 21 made of, for example, copper are formed on a substrate 20 made of, for example, silicon.
  • Each electrode 21 is provided at a position corresponding to each electrode 11 of the substrate 10.
  • the formation of the electrode 21 on the substrate 20 may be performed using, for example, an electroless plating method.
  • a through electrode is formed in the substrate 20 in advance, and then the substrate 20 is ground from the back surface (opposite surface of the element forming surface) to expose the front end portion of the through electrode.
  • the part may be used as the electrode 21.
  • the height of the electrodes 21 is, for example, about 5 ⁇ m, and the distance between the electrodes 21 is, for example, about 5 ⁇ m.
  • the tops of the electrodes 21 of the substrate 20 are brought into pressure contact with the metal fine particle layer 61 on the support member 60 at a pressure of 2 MPa, for example, for about 2 minutes.
  • a part of the metal fine particle layer 61 adheres on the top of each electrode 21.
  • the adhesion layer 22 made of metal fine particles constituting the metal fine particle layer 61 is formed on the top of each electrode 21.
  • the temperature of this heat treatment may be set, for example, in a range from about 50 ° C. to about 200 ° C., but is not limited to this temperature range. However, it is desirable to set the temperature of the heat treatment to about 200 ° C. or less.
  • the metal fine particles constituting a part of the attached metal fine particle layer 61 This is because some of them may melt and cause aggregation.
  • the melting point of the metal fine particles becomes higher depending on the particle size. In other words, the melting point of the metal fine particles whose particle diameter is expanded by aggregation is higher than the melting point of the original metal fine particles before aggregation. As a result, the temperature required for joining the electrodes in the next process rises, causing damage to the semiconductor device.
  • each electrode 11 and the electrodes 22 are bonded to each other at a pressure of 5 MPa, for example, for about 5 minutes.
  • substrate 20 are laminated
  • an adhesive may be applied between the substrate 10 and the substrate 20 when the substrate 10 and the substrate 20 are laminated.
  • an adhesive called underfill may be filled between the substrate 10 and the substrate 20.
  • the underfill material is sucked into the gap between the substrate 10 and the substrate 20 using surface tension. Before forming the bonding between the electrodes by the adhesion layer 12 made of metal fine particles, or by applying an adhesive to at least one of the substrate 10 and the substrate 20 in advance. A method of curing the adhesive after bonding may be used.
  • each electrode 11 and each electrode 22 are pressure-bonded to each other, for example, heat treatment may be performed at a temperature of about 150 ° C. or higher.
  • heat treatment may be performed at a temperature of about 150 ° C. or higher.
  • the SAM film covering the surface of each metal fine particle constituting the adhesion layer 12 and the adhesion layer 22 is detached, and the metal surface of each metal fine particle is exposed.
  • melting of each metal fine particle occurs even at a relatively low temperature, and as a result, each metal fine particle is integrated, so that the electrode 11 and the electrode 21 can be reliably bonded via the adhesion layer 12 and the adhesion layer 22. Can do.
  • the adhesion layer 12 and the adhesion layer 22 each made of metal fine particles cause plastic deformation, when the distance between the electrode 11 and the electrode 21 is relatively narrow, the adhesion layer 12 and the adhesion layer each made of metal fine particles, respectively.
  • the adhesion layer 12 and the adhesion layer 22 made of metal fine particles are respectively relatively deformed. That is, in the bonding between each electrode 11 and the electrode 21, the adhesion layer 12 and the adhesion layer 22 each made of metal fine particles act as a buffer region. For this reason, even if the space
  • the semiconductor device of this modification manufactured by the method described above corresponds to the substrate 10, the plurality of electrodes 11 formed on the substrate 10, the substrate 20, and each electrode 11 of the substrate 10 on the substrate 20.
  • the adhesion layer 12 and the adhesion layer 22 are formed by integrating each electrode 11 and each electrode 21 corresponding to each electrode 11 by melting a plurality of metal fine particles.
  • the substrate 10 and the substrate 20 are laminated.
  • the throughput is improved as compared with the case where a liquid material containing metal particles is arranged on each electrode using an ink jet device. And cost can be reduced.
  • the particle size of the metal fine particles constituting the metal fine particle layers 51 and 61 may be 1 mm (0.1 nm) or more and 1 ⁇ m (1000 nm) or less, more preferably several mm. Above and several hundred nm or less may be sufficient.
  • the metal fine particles can be melted in a low temperature process of, for example, about 350 ° C. or less, thereby reducing damage to the semiconductor device.
  • the bonding strength between the electrodes can be increased.
  • the particle diameters of the majority of the metal fine particles in the metal fine particle layers 51 and 61 are about 50 nm or less.
  • metal fine particles having a particle diameter exceeding 50 nm may be present in the metal fine particle layers 51 and 61.
  • the average particle diameter of the metal fine particles constituting the metal fine particle layers 51 and 61 may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less, for example.
  • the particle diameters of the majority of the metal fine particles in the metal fine particle layers 51 and 61 may be about 40 nm or less, and even if metal fine particles having a particle diameter exceeding 40 nm exist in the metal fine particle layers 51 and 61. Good.
  • the above relationship between the particle size and the process temperature is for the case where the metal fine particles constituting the metal fine particle layers 51 and 61 are copper fine particles. However, the same tendency (decrease in melting point accompanying the refinement of particle size) is observed.
  • At least one of the metal fine particle layers 51 and 61 may contain fine particles having a hardness higher than that of each electrode 11 and each electrode 21.
  • the surface of each electrode 11 or the natural oxide film or the contamination layer formed on the surface of each electrode 21 is Since the surface of each electrode 11 and the surface of each electrode 21 can be exposed by removing by the polishing effect by the fine particles having higher hardness than the electrode 11 and each electrode 21, the bonding yield between each electrode 11 and each electrode 21 can be further increased. Can be improved.
  • At least one of the metal fine particle layers 51 and 61 is a metal fine particle selected from one or two or more of a metal group composed of copper, silver, gold, platinum, nickel, and the like, Alternatively, it may contain fine particles of an alloy of two or more metals selected from the metal group.
  • at least one of the metal fine particle layers 51 and 61 is higher in hardness than any metal of copper, silver, and gold (that is, the Mohs hardness is 4 or more) and has a conductivity of 1 ⁇ 10 7 / m ⁇ or more. It may further contain other metal fine particles.
  • the other metal having high hardness is one or more selected from the metal group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum and osmium, or the metal It may be an alloy of two or more metals selected from the metal group.
  • the material of the electrode 11 and the electrode 21 is not particularly limited as long as the material has conductivity.
  • a copper alloy or other metal may be used instead of copper.
  • the material of the electrode 11 and the material of the electrode 21 may be different.
  • silicon substrates are used as the substrate 10 and the substrate 20, but the substrate materials of the substrate 10 and the substrate 20 are not particularly limited, and the material of the substrate 10 and the material of the substrate 20 are not limited. And may be different.
  • silicon substrates are used as the support member 50 and the support member 60.
  • the support member 50 and the support member 60 are particularly limited to a substrate or the like as long as a metal fine particle layer can be formed.
  • the support member 50 and the support member 60 may be different types of members.
  • the semiconductor device and the manufacturing method thereof according to this modification include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and before dicing)
  • the semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is laminated) or the wafer-wafer lamination (lamination of the wafer state semiconductor devices) and the manufacturing method thereof.
  • the bonding failure between the electrodes of each substrate due to the variation in the height of the electrodes, the variation in the thickness of the substrates, and the like is useful as a method for bonding electrodes using metal fine particles in a chip-chip stacked, chip-wafer stacked or wafer-wafer stacked semiconductor device.

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  • Electrodes Of Semiconductors (AREA)

Abstract

Provided is a semiconductor device with a metal microparticle layer (51) formed on top of a supporting member (50). An adhesion layer (12) comprising metal microparticles constituting the metal microparticle layer (51) is formed on top of the top part of an electrode (11) formed on top of a substrate (10), by bringing the top part of the electrode (11) into contact with the metal microparticle layer (51) on top of the supporting member (50) and adhering part of the metal microparticle layer (51) to the top of the top part of the electrode (11). The substrate (10) and a substrate (20) are laminated by making the electrode (11) formed on top of the substrate (10) face an electrode (21) formed on top of the substrate (20), and by connecting the electrode (11) and the electrode (21) via the adhesion layer (12).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof

 本発明は、半導体装置及びその製造方法に関し、特に、チップ-チップ積層、チップ-ウェハ積層又はウェハ-ウェハ積層された半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a chip-chip stacking, a chip-wafer stacking or a wafer-wafer stacking semiconductor device and a manufacturing method thereof.

 近年、半導体集積回路装置の高集積化、高機能化及び高速化に伴って、例えば貫通電極などを用いた基板のチップ-チップ積層、チップ-ウェハ積層又はウェハ-ウェハ積層による3次元集積化技術が提案されている(例えば非特許文献1参照)。 In recent years, as semiconductor integrated circuit devices have become highly integrated, highly functional, and high-speed, for example, three-dimensional integration technology by chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking of substrates using through electrodes, etc. Has been proposed (see Non-Patent Document 1, for example).

 これは、従来のSoC(System on Chip)のような2次元的な微細化においては、配線の断面積の縮小に伴う電子の粒界散乱や界面散乱によって引き起こされる配線抵抗の上昇と、配線長の増大によって引き起こされる配線遅延の増加とに起因して、性能が劣化してしまうことが懸念されているためである。 In two-dimensional miniaturization like the conventional SoC (System on (Chip), an increase in wiring resistance caused by grain boundary scattering or interface scattering of electrons accompanying reduction in the cross-sectional area of wiring, and wiring length This is because there is a concern that the performance deteriorates due to an increase in wiring delay caused by an increase in the number of lines.

 そこで、3次元集積化技術においては、半導体集積回路装置を3次元的に積層することによって、配線可能エリアを拡大し、それにより、配線断面積の増大と配線長の短縮とを可能とする。すなわち、集積度を高めつつ、性能向上を実現することができる。 Therefore, in the three-dimensional integration technology, the semiconductor integrated circuit device is three-dimensionally stacked to expand the wiring area, thereby enabling the wiring cross-sectional area to be increased and the wiring length to be shortened. That is, it is possible to improve performance while increasing the degree of integration.

 また、3次元集積化技術においてシリコン基板等の基板を積層する場合、基板間の電気的な接続のために、各基板の電極同士の間での接合が必須となる。通常、各電極同士の接合には、チップ-チップ積層、チップ-ウェハ積層又はウェハ-ウェハ積層において電極同士を加熱圧着する方法が用いられる。 In addition, when a substrate such as a silicon substrate is stacked in the three-dimensional integration technology, bonding between electrodes of each substrate is essential for electrical connection between the substrates. Usually, the electrodes are joined together by a method in which the electrodes are thermocompression-bonded in chip-chip lamination, chip-wafer lamination, or wafer-wafer lamination.

特開2006-128272号公報JP 2006-128272 A

ITRS(The International Technology Roadmap for Semiconductors) 2007 Assembly and Packaging Chapter(和訳版)、P.41-42ITRS (The International Technology Roadmap for Semiconductors) 2007 Assembly and Packaging Chapter (Japanese translation), P.41-42

 しかしながら、前述の従来の3次元集積化技術においては、各基板の電極同士の間で接合不良が生じるという問題がある。以下、図面を参照しながら、具体的に説明する。 However, the above-described conventional three-dimensional integration technique has a problem that bonding failure occurs between the electrodes of each substrate. Hereinafter, it demonstrates concretely, referring drawings.

 図5は、従来の3次元集積化技術を用いて基板が積層されてなる半導体装置の断面構成を示している。図5に示すように、素子形成面(表面)100a及びその反対面(裏面)100bを有する第1の基板100中に貫通電極101が形成されている。第1の基板100の表面100a上には、トランジスタ102が形成されていると共に、トランジスタ102及び貫通電極101と電気的に接続する多層配線を有する配線層103が形成されている。第1の基板100の裏面100bには、裏面側電極となる貫通電極101の頂部が露出している。第1の基板100は、素子形成面(表面)200a及びその反対面(裏面)200bを有する第2の基板200と、第1の基板100の裏面100と第2の基板200の表面200aとが対向するように積層されている。第2の基板200の表面200a上には、トランジスタ201が形成されていると共に、トランジスタ201と電気的に接続する多層配線を有する配線層202が形成されている。配線層202の最表面部には、第1の基板100の裏面側電極となる貫通電極101の頂部と接続する電極パッド203が形成されている。 FIG. 5 shows a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique. As shown in FIG. 5, a through electrode 101 is formed in a first substrate 100 having an element formation surface (front surface) 100a and an opposite surface (back surface) 100b. A transistor 102 is formed over the surface 100 a of the first substrate 100, and a wiring layer 103 having a multilayer wiring electrically connected to the transistor 102 and the through electrode 101 is formed. On the back surface 100b of the first substrate 100, the top portion of the through electrode 101 serving as the back surface side electrode is exposed. The first substrate 100 includes a second substrate 200 having an element formation surface (front surface) 200a and an opposite surface (back surface) 200b, a back surface 100 of the first substrate 100, and a front surface 200a of the second substrate 200. They are stacked so as to face each other. A transistor 201 is formed over the surface 200 a of the second substrate 200, and a wiring layer 202 having a multilayer wiring electrically connected to the transistor 201 is formed. On the outermost surface portion of the wiring layer 202, an electrode pad 203 connected to the top portion of the through electrode 101 serving as the back side electrode of the first substrate 100 is formed.

 ところが、第1の基板100の裏面100b側においてグラインド、CMP(chemical mechanical polishing )又はドライエッチング等を用いて貫通電極101の頂部を露出させて裏面側電極を形成する際に、図5に示すように、貫通電極101の頂部(露出部分の底面)の位置にバラツキが生じてしまう。ここで、貫通電極101の径は、典型的には5μm程度~100μm程度であり、貫通電極101の露出部分(裏面側電極)の高さは、典型的には0.5μm程度~10μm程度であり、貫通電極101の頂部の位置バラツキの大きさは、典型的には0.1μm程度~1μm程度である。 However, when the back surface side electrode is formed by exposing the top of the through electrode 101 on the back surface 100b side of the first substrate 100 using grinding, CMP (chemical mechanical polishing), dry etching, or the like, as shown in FIG. In addition, the position of the top portion (bottom surface of the exposed portion) of the through electrode 101 varies. Here, the diameter of the through electrode 101 is typically about 5 μm to about 100 μm, and the height of the exposed portion (back surface side electrode) of the through electrode 101 is typically about 0.5 μm to about 10 μm. The size of the position variation at the top of the through electrode 101 is typically about 0.1 μm to about 1 μm.

 このような位置バラツキは、第1の基板100自体の厚さバラツキ、貫通電極101を形成する際のリソグラフィ工程におけるレジストパターンの寸法バラツキ、及び、ドライエッチング速度のウェハ面内でのバラツキに伴う貫通電極101の露出部分自体の高さバラツキ等に起因して発生する。 Such positional variations include the thickness variation of the first substrate 100 itself, the resist pattern dimensional variation in the lithography process when the through electrode 101 is formed, and the penetration due to the variation in the dry etching rate within the wafer surface. This occurs due to variations in the height of the exposed portion of the electrode 101 itself.

 また、図5に示すように、ウェハ面内での基板厚さバラツキや反りにより、第1の基板100の貫通電極101の底面と、第2の基板200の電極パッド203の上面とを平行に保持することができないため、ウェハ面内において、貫通電極101の頂部(裏面側電極の底面)と電極パッド203の上面との間の距離にもバラツキが生じる。 Further, as shown in FIG. 5, the bottom surface of the through electrode 101 of the first substrate 100 and the top surface of the electrode pad 203 of the second substrate 200 are parallel to each other due to substrate thickness variation or warpage within the wafer surface. Since it cannot be held, the distance between the top portion of the through electrode 101 (the bottom surface of the back-side electrode) and the upper surface of the electrode pad 203 also varies within the wafer surface.

 以上に述べたような、電極の高さバラツキや、各基板の電極間の距離バラツキに起因して、各基板の電極同士を加熱圧着させた場合に、ウェハ面内で印加される圧力にバラツキが生じる。その結果、最悪、ウェハ内の一部分において対向する両電極間に空隙が生じて接合が形成されないという不良が発生する。 Due to variations in electrode height and distance between electrodes on each substrate as described above, the pressure applied within the wafer surface varies when electrodes on each substrate are thermocompression bonded. Occurs. As a result, in the worst case, there occurs a defect that a gap is generated between the opposing electrodes in a part of the wafer and a bond is not formed.

 このような従来の3次元集積化技術の問題点に対して、各基板の電極同士を接合する際に当該電極同士の間に金属粒子の集合体を介在させる技術が提案されている(特許文献1参照)。しかしながら、特許文献1に開示されている方法においては、インクジェット装置を用いて、金属粒子を含む液状物を各電極上に配置していく必要があるため、工程が複雑になってスループットが悪化すると共に、コストの増大も避けられない。 In order to solve the problems of the conventional three-dimensional integration technique, a technique has been proposed in which an assembly of metal particles is interposed between the electrodes when the electrodes of each substrate are joined together (Patent Literature). 1). However, in the method disclosed in Patent Document 1, it is necessary to dispose a liquid material containing metal particles on each electrode using an ink jet apparatus, which complicates the process and deteriorates the throughput. At the same time, an increase in cost is inevitable.

 前記に鑑み、本発明は、各基板の電極同士の間での接合不良を簡単に防止できる新たな3次元集積化技術を提供することを目的とする。 In view of the above, an object of the present invention is to provide a new three-dimensional integration technique that can easily prevent a bonding failure between electrodes of each substrate.

 前記の目的を達成するために、本発明に係る半導体装置の製造方法は、複数の第1の電極が形成されている第1の基板と、前記第1の基板の前記各第1の電極と対応する位置に複数の第2の電極が形成されている第2の基板とが積層されてなる半導体装置の製造方法であって、第1の支持部材上に第1の金属微粒子層を形成する工程(a)と、前記第1の基板の前記各第1の電極の頂部を前記第1の支持部材上の前記第1の金属微粒子層に接触させて前記各第1の電極の頂部上に前記第1の金属微粒子層の一部を付着させることにより、前記各第1の電極の頂部上に、前記第1の金属微粒子層を構成する金属微粒子からなる第1の付着層を形成する工程(b)と、前記工程(b)の後、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを互いに対向させ、前記第1の付着層を介して、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを接続することにより、前記第1の基板と前記第2の基板とを積層する工程(c)とを備えている。 In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a first substrate on which a plurality of first electrodes are formed, and each first electrode of the first substrate. A method of manufacturing a semiconductor device in which a second substrate on which a plurality of second electrodes are formed at corresponding positions is laminated, wherein a first metal fine particle layer is formed on a first support member Step (a), and the top of each first electrode of the first substrate is brought into contact with the first metal fine particle layer on the first support member so as to be on the top of each first electrode. Forming a first adhesion layer made of metal fine particles constituting the first metal fine particle layer on the top of each first electrode by adhering a part of the first metal fine particle layer; (B) and, after the step (b), the first electrodes and the first electrodes corresponding to the first electrodes. The second electrodes are opposed to each other, and the first electrodes and the second electrodes corresponding to the first electrodes are connected via the first adhesion layer, A step (c) of laminating a first substrate and the second substrate.

 本発明に係る半導体装置の製造方法によると、各基板の電極同士を接続する際に当該電極同士の間に金属微粒子からなる層を介在させている。このため、電極の高さバラツキや基板(ウェハ)の厚さバラツキ等に起因して各基板の電極間の距離にバラツキがあったとしても、当該電極間距離に応じて金属微粒子からなる層が変形することによって、各基板の電極同士を確実に接合することができる。また、予め支持部材上に形成されている金属微粒子層に、基板上の複数の電極の頂部を一括して接触させることにより、各電極の頂部上にそれぞれ金属微粒子からなる層を形成するため、インクジェット装置を用いて金属粒子を含む液状物を各電極上に配置していく場合と比較して、スループットを向上させることができると共にコストを低減させることができる。 According to the method of manufacturing a semiconductor device according to the present invention, when the electrodes of each substrate are connected to each other, a layer made of metal fine particles is interposed between the electrodes. For this reason, even if there is a variation in the distance between the electrodes of each substrate due to the variation in the height of the electrodes, the variation in the thickness of the substrate (wafer), etc., a layer made of metal fine particles is formed according to the distance between the electrodes. By deform | transforming, the electrodes of each substrate can be reliably joined. In addition, in order to form a layer made of metal fine particles on the top of each electrode by bringing the tops of the plurality of electrodes on the substrate into contact with the metal fine particle layer formed on the support member in advance, Throughput can be improved and costs can be reduced as compared with the case where a liquid material containing metal particles is arranged on each electrode using an ink jet device.

 従って、本発明に係る半導体装置の製造方法によると、各基板の電極同士の間での接合不良を簡単に防止することができる。 Therefore, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to easily prevent poor bonding between the electrodes of each substrate.

 本発明に係る半導体装置の製造方法において、前記工程(c)において、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを互いに圧着させながら加熱処理を行うことにより、前記第1の付着層を構成する前記金属微粒子のそれぞれを融解させて一体化させ、それによって、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを接合してもよい。このようにすると、各基板の電極同士を確実に接合することができる。この場合、前記工程(c)の前記加熱処理の温度は150℃以上であってもよい。 In the method for manufacturing a semiconductor device according to the present invention, in the step (c), heat treatment is performed while the first electrodes and the second electrodes corresponding to the first electrodes are pressure-bonded to each other. Thus, each of the metal fine particles constituting the first adhesion layer is melted and integrated, whereby each of the first electrodes and each of the second electrodes corresponding to the first electrodes. And may be joined. If it does in this way, the electrodes of each board | substrate can be joined reliably. In this case, the temperature of the heat treatment in the step (c) may be 150 ° C. or higher.

 本発明に係る半導体装置の製造方法において、前記工程(a)において、前記第1の金属微粒子層を構成する前記金属微粒子の表面を第1の有機材料膜によってコーティングしてもよい。このようにすると、金属微粒子の酸化や凝集を防止することができる。この場合、前記工程(c)において、前記第1の付着層を構成する前記金属微粒子の表面を覆う前記第1の有機材料膜を当該表面から脱離させてもよい。このようにすると、各金属微粒子を融解させて一体化させることができるため、各基板の電極同士を確実に接合することができる。ここで、前記第1の有機材料膜は、例えばSAM膜であってもよいし、前記SAM膜は、例えばアルカンチオールを含んでいてもよい。 In the method for manufacturing a semiconductor device according to the present invention, in the step (a), the surface of the metal fine particles constituting the first metal fine particle layer may be coated with a first organic material film. If it does in this way, oxidation and aggregation of metal particulates can be prevented. In this case, in the step (c), the first organic material film covering the surface of the metal fine particles constituting the first adhesion layer may be detached from the surface. If it does in this way, since each metal microparticle can be fuse | melted and integrated, the electrodes of each board | substrate can be joined reliably. Here, the first organic material film may be, for example, a SAM film, and the SAM film may contain, for example, alkanethiol.

 本発明に係る半導体装置の製造方法において、前記工程(b)において、前記各第1の電極の頂部を前記第1の金属微粒子層に圧接させながら加熱処理を行ってもよい。このようにすると、基板上の各電極の頂部上に金属微粒子層の一部を確実に付着させることができる。この場合、前記工程(b)の前記加熱処理の温度は50℃以上で且つ200℃以下であってもよい。このようにすると、基板上の各電極の頂部上に金属微粒子層の一部を確実に付着させながら、金属微粒子の溶融に伴う凝集に起因する融点の上昇を防止できるので、後工程における各基板の電極同士の接合を所定の温度で行うことができる。 In the method of manufacturing a semiconductor device according to the present invention, in the step (b), heat treatment may be performed while the top of each first electrode is pressed against the first metal fine particle layer. If it does in this way, a part of metal fine particle layer can adhere reliably on the top part of each electrode on a board | substrate. In this case, the temperature of the heat treatment in the step (b) may be 50 ° C. or higher and 200 ° C. or lower. In this way, it is possible to prevent an increase in melting point due to aggregation due to melting of the metal fine particles while reliably attaching a part of the metal fine particle layer on the top of each electrode on the substrate. The electrodes can be joined at a predetermined temperature.

 本発明に係る半導体装置の製造方法において、前記第1の金属微粒子層を構成する前記金属微粒子の粒径は、1Å(0.1nm)以上で且つ1μm(1000nm)以下であってもよいし、より好ましくは、数Å以上で且つ数百nm以下であってもよい。特に、金属微粒子の平均粒径が50nm以下であると、例えば350℃程度以下の低温プロセスにおいて金属微粒子を溶融させることができるので、半導体装置へのダメージを低減しつつ、電極同士の接合強度を強くすることができる。このような効果は、過半数の金属微粒子の粒径が50nm程度以下であれば得ることができる。言い換えると、50nmを超える粒径の金属微粒子が存在していてもよい。また、より好ましくは、例えば250℃程度以下の低温プロセスにおいて金属微粒子を溶融させるために、金属微粒子の平均粒径が40nm程度以下であってもよい。この場合も、過半数の金属微粒子の粒径が40nm程度以下であればよく、40nmを超える粒径の金属微粒子が存在していてもよい。尚、以上の粒径とプロセス温度との関係は、金属微粒子が銅の微粒子の場合についてのものであるが、金や銀等の他の金属の微粒子であっても、同様の傾向(粒径の微細化に伴う融点の低下)が見られる。 In the method of manufacturing a semiconductor device according to the present invention, the metal fine particles constituting the first metal fine particle layer may have a particle size of 1 mm (0.1 nm) or more and 1 μm (1000 nm) or less, More preferably, it may be several tens or more and several hundreds of nm or less. In particular, when the average particle size of the metal fine particles is 50 nm or less, the metal fine particles can be melted in a low-temperature process of, for example, about 350 ° C. or less, so that the bonding strength between the electrodes is reduced while reducing damage to the semiconductor device. Can be strong. Such an effect can be obtained if the majority of the metal fine particles have a particle size of about 50 nm or less. In other words, metal fine particles having a particle diameter exceeding 50 nm may be present. More preferably, the average particle diameter of the metal fine particles may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less. Also in this case, the particle size of the majority of the metal fine particles may be about 40 nm or less, and metal fine particles having a particle size exceeding 40 nm may be present. The above relationship between the particle size and the process temperature is for the case where the metal fine particles are copper fine particles, but the same tendency (particle size) may be obtained for other metal fine particles such as gold and silver. The melting point decreases as the size of the material decreases.

 本発明に係る半導体装置の製造方法において、前記第1の金属微粒子層は、前記各第1の電極及び前記各第2の電極よりも高い硬度を持つ微粒子を含んでいてもよい。このようにすると、各基板の電極同士を接合する際に、電極表面に形成された自然酸化膜や汚染層等を、電極よりも高い硬度を持つ微粒子による研磨効果によって除去して電極表面を露出させることができるので、電極同士の接合歩留りをさらに向上させることができる。 In the method for manufacturing a semiconductor device according to the present invention, the first metal fine particle layer may include fine particles having hardness higher than that of each of the first electrodes and each of the second electrodes. In this way, when the electrodes of each substrate are joined together, the natural oxide film and the contamination layer formed on the electrode surfaces are removed by the polishing effect by the fine particles having hardness higher than that of the electrodes to expose the electrode surfaces. Therefore, the junction yield between the electrodes can be further improved.

 本発明に係る半導体装置の製造方法において、前記第1の金属微粒子層は、銅、銀及び金から構成される金属群の中から1つ若しくは2つ以上選ばれた金属の微粒子、又は当該金属群の中から選ばれた2つ以上の金属の合金の微粒子を含んでいてもよい。この場合、前記第1の金属微粒子層は、銅、銀及び金のいずれの金属よりも硬度が高く(つまりモース硬度が4以上であり)且つ導電率が1×10/mΩ以上である他の金属の微粒子をさらに含んでいてもよい。このようにすると、各基板の電極同士を接合する際に、電極表面に形成された自然酸化膜や汚染層等を、他の金属の微粒子による研磨効果によって除去して電極表面を露出させることができるので、電極同士の接合歩留りをさらに向上させることができる。ここで、前記他の金属は、タングステン、コバルト、ニッケル、ルテニウム、ロジウム、イリジウム、モリブデン及びオスミウムから構成される金属群の中から1つ若しくは2つ以上選ばれた金属、又は当該金属群の中から選ばれた2つ以上の金属の合金であってもよい。 In the method of manufacturing a semiconductor device according to the present invention, the first metal fine particle layer may be one or more metal fine particles selected from a metal group composed of copper, silver, and gold, or the metal It may contain fine particles of an alloy of two or more metals selected from the group. In this case, the first metal fine particle layer has a higher hardness than any of copper, silver and gold (that is, a Mohs hardness of 4 or more) and a conductivity of 1 × 10 7 / mΩ or more. The metal fine particles may further be included. In this way, when the electrodes of each substrate are joined together, the natural oxide film and the contaminated layer formed on the electrode surfaces can be removed by the polishing effect of fine particles of other metals to expose the electrode surfaces. Therefore, the junction yield between the electrodes can be further improved. Here, the other metal is a metal selected from one or more metals selected from the group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum, and osmium. An alloy of two or more metals selected from may be used.

 本発明に係る半導体装置の製造方法において、前記工程(c)の前に、第2の支持部材上に第2の金属微粒子層を形成する工程(d)と、前記第2の基板の前記各第2の電極の頂部を前記第2の支持部材上の前記第2の金属微粒子層に接触させて前記各第2の電極の頂部上に前記第2の金属微粒子層の一部を付着させることにより、前記各第2の電極の頂部上に、前記第2の金属微粒子層を構成する金属微粒子からなる第2の付着層を形成する工程(e)とをさらに備え、前記工程(c)において、前記第1の付着層及び前記第2の付着層を介して、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを接続することにより、前記第1の基板と前記第2の基板とを積層してもよい。この場合、前記工程(d)において、前記第2の金属微粒子層を構成する前記金属微粒子の表面を第2の有機材料膜によってコーティングしてもよい。このようにすると、金属微粒子の酸化や凝集を防止することができる。この場合、前記工程(c)において、前記第2の付着層を構成する前記金属微粒子の表面を覆う前記第2の有機材料膜を当該表面から脱離させてもよい。このようにすると、各金属微粒子を融解させて一体化させることができるため、各基板の電極同士を確実に接合することができる。ここで、前記第2の有機材料膜は、例えばSAM膜であってもよいし、前記SAM膜は、例えばアルカンチオールを含んでいてもよい。 In the method for manufacturing a semiconductor device according to the present invention, before the step (c), a step (d) of forming a second metal fine particle layer on the second support member, and the respective steps of the second substrate. The top part of the second electrode is brought into contact with the second metal fine particle layer on the second support member, and a part of the second metal fine particle layer is adhered on the top part of each second electrode. (E) further comprising a step (e) of forming a second adhesion layer made of metal fine particles constituting the second metal fine particle layer on the top of each second electrode, and in the step (c) By connecting the first electrodes and the second electrodes corresponding to the first electrodes through the first adhesion layer and the second adhesion layer, the first electrodes The substrate and the second substrate may be laminated. In this case, in the step (d), the surface of the metal fine particles constituting the second metal fine particle layer may be coated with a second organic material film. If it does in this way, oxidation and aggregation of metal particulates can be prevented. In this case, in the step (c), the second organic material film covering the surface of the metal fine particles constituting the second adhesion layer may be detached from the surface. If it does in this way, since each metal microparticle can be fuse | melted and integrated, the electrodes of each board | substrate can be joined reliably. Here, the second organic material film may be, for example, a SAM film, and the SAM film may contain, for example, alkanethiol.

 本発明に係る半導体装置の製造方法において、前記工程(e)において、前記各第2の電極の頂部を前記第2の金属微粒子層に圧接させながら加熱処理を行ってもよい。このようにすると、基板上の各電極の頂部上に金属微粒子層の一部を確実に付着させることができる。この場合、前記工程(e)の前記加熱処理の温度は50℃以上で且つ200℃以下であってもよい。このようにすると、基板上の各電極の頂部上に金属微粒子層の一部を確実に付着させながら、金属微粒子の溶融に伴う凝集に起因する融点の上昇を防止できるので、後工程における各基板の電極同士の接合を所定の温度で行うことができる。 In the method for manufacturing a semiconductor device according to the present invention, in the step (e), heat treatment may be performed while the top of each second electrode is pressed against the second metal fine particle layer. If it does in this way, a part of metal fine particle layer can adhere reliably on the top part of each electrode on a board | substrate. In this case, the temperature of the heat treatment in the step (e) may be 50 ° C. or higher and 200 ° C. or lower. In this way, it is possible to prevent an increase in melting point due to aggregation due to melting of the metal fine particles while reliably attaching a part of the metal fine particle layer on the top of each electrode on the substrate. The electrodes can be joined at a predetermined temperature.

 本発明に係る半導体装置の製造方法において、前記第2の金属微粒子層を構成する前記金属微粒子の粒径は、1Å(0.1nm)以上で且つ1μm(1000nm)以下であってもよいし、より好ましくは、数Å以上で且つ数百nm以下であってもよい。特に、金属微粒子の平均粒径が50nm以下であると、例えば350℃程度以下の低温プロセスにおいて金属微粒子を溶融させることができるので、半導体装置へのダメージを低減しつつ、電極同士の接合強度を強くすることができる。このような効果は、過半数の金属微粒子の粒径が50nm程度以下であれば得ることができる。言い換えると、50nmを超える粒径の金属微粒子が存在していてもよい。また、より好ましくは、例えば250℃程度以下の低温プロセスにおいて金属微粒子を溶融させるために、金属微粒子の平均粒径が40nm程度以下であってもよい。この場合も、過半数の金属微粒子の粒径が40nm程度以下であればよく、40nmを超える粒径の金属微粒子が存在していてもよい。尚、以上の粒径とプロセス温度との関係は、金属微粒子が銅の微粒子の場合についてのものであるが、金や銀等の他の金属の微粒子であっても、同様の傾向(粒径の微細化に伴う融点の低下)が見られる。 In the method of manufacturing a semiconductor device according to the present invention, the metal fine particles constituting the second metal fine particle layer may have a particle size of 1 mm (0.1 nm) or more and 1 μm (1000 nm) or less, More preferably, it may be several tens or more and several hundreds of nm or less. In particular, when the average particle size of the metal fine particles is 50 nm or less, the metal fine particles can be melted in a low-temperature process of, for example, about 350 ° C. or less, so that the bonding strength between the electrodes is reduced while reducing damage to the semiconductor device. Can be strong. Such an effect can be obtained if the majority of the metal fine particles have a particle size of about 50 nm or less. In other words, metal fine particles having a particle diameter exceeding 50 nm may be present. More preferably, the average particle diameter of the metal fine particles may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less. Also in this case, the particle size of the majority of the metal fine particles may be about 40 nm or less, and metal fine particles having a particle size exceeding 40 nm may be present. The above relationship between the particle size and the process temperature is for the case where the metal fine particles are copper fine particles, but the same tendency (particle size) may be obtained for other metal fine particles such as gold and silver. The melting point decreases as the size of the material decreases.

 本発明に係る半導体装置の製造方法において、前記第2の金属微粒子層は、前記各第1の電極及び前記各第2の電極よりも高い硬度を持つ微粒子を含んでいてもよい。このようにすると、各基板の電極同士を接合する際に、電極表面に形成された自然酸化膜や汚染層等を、電極よりも高い硬度を持つ微粒子による研磨効果によって除去して電極表面を露出させることができるので、電極同士の接合歩留りをさらに向上させることができる。 In the method for manufacturing a semiconductor device according to the present invention, the second metal fine particle layer may include fine particles having hardness higher than that of each of the first electrodes and each of the second electrodes. In this way, when the electrodes of each substrate are joined together, the natural oxide film and the contamination layer formed on the electrode surfaces are removed by the polishing effect by the fine particles having hardness higher than that of the electrodes to expose the electrode surfaces. Therefore, the junction yield between the electrodes can be further improved.

 本発明に係る半導体装置の製造方法において、前記第2の金属微粒子層は、銅、銀及び金から構成される金属群の中から1つ若しくは2つ以上選ばれた金属の微粒子、又は当該金属群の中から選ばれた2つ以上の金属の合金の微粒子を含んでいてもよい。この場合、前記第2の金属微粒子層は、銅、銀及び金のいずれの金属よりも硬度が高く(つまりモース硬度が4以上であり)且つ導電率が1×10/mΩ以上である他の金属の微粒子をさらに含んでいてもよい。このようにすると、各基板の電極同士を接合する際に、電極表面に形成された自然酸化膜や汚染層等を、他の金属の微粒子による研磨効果によって除去して電極表面を露出させることができるので、電極同士の接合歩留りをさらに向上させることができる。ここで、前記他の金属は、タングステン、コバルト、ニッケル、ルテニウム、ロジウム、イリジウム、モリブデン及びオスミウムから構成される金属群の中から1つ若しくは2つ以上選ばれた金属、又は当該金属群の中から選ばれた2つ以上の金属の合金であってもよい。 In the method of manufacturing a semiconductor device according to the present invention, the second metal fine particle layer may be one or more metal fine particles selected from a metal group composed of copper, silver, and gold, or the metal It may contain fine particles of an alloy of two or more metals selected from the group. In this case, the second metal fine particle layer has a hardness higher than any of copper, silver and gold (that is, a Mohs hardness of 4 or more) and a conductivity of 1 × 10 7 / mΩ or more. The metal fine particles may further be included. In this way, when the electrodes of each substrate are joined together, the natural oxide film and the contaminated layer formed on the electrode surfaces can be removed by the polishing effect of fine particles of other metals to expose the electrode surfaces. Therefore, the junction yield between the electrodes can be further improved. Here, the other metal is a metal selected from one or more metals selected from the group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum, and osmium. An alloy of two or more metals selected from may be used.

 本発明に係る半導体装置の製造方法において、前記各第1の電極及び前記各第2の電極の少なくとも一方は、貫通電極の先端部であってもよい。 In the method for manufacturing a semiconductor device according to the present invention, at least one of the first electrodes and the second electrodes may be a tip portion of a through electrode.

 本発明に係る半導体装置の製造方法において、前記各第1の電極及び前記各第2の電極の少なくとも一方は、金属から構成されていてもよい。この場合、前記各第1の電極及び前記各第2の電極の少なくとも一方を構成する前記金属は銅又は銅合金であってもよい。 In the method for manufacturing a semiconductor device according to the present invention, at least one of the first electrodes and the second electrodes may be made of metal. In this case, the metal constituting at least one of the first electrodes and the second electrodes may be copper or a copper alloy.

 本発明に係る半導体装置は、第1の基板と、前記第1の基板上に形成された複数の第1の電極と、第2の基板と、前記第2の基板上における前記第1の基板の前記各第1の電極と対応する位置に形成された複数の第2の電極とを備え、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とが、複数の金属微粒子が融解して一体化してなる層を介して接続されており、それによって、前記第1の基板と前記第2の基板とが積層されている。 A semiconductor device according to the present invention includes a first substrate, a plurality of first electrodes formed on the first substrate, a second substrate, and the first substrate on the second substrate. A plurality of second electrodes formed at positions corresponding to the first electrodes, and the first electrodes and the second electrodes corresponding to the first electrodes, A plurality of metal fine particles are connected via a layer formed by melting and integrating, whereby the first substrate and the second substrate are laminated.

 本発明に係る半導体装置によると、各基板の電極同士を、複数の金属微粒子が融解して一体化してなる層を介して接続している。このため、電極の高さバラツキや基板(ウェハ)の厚さバラツキ等に起因して各基板の電極間の距離にバラツキがあったとしても、当該電極間距離に応じて金属微粒子からなる層が変形することによって、各基板の電極同士を確実に接合することができる。 According to the semiconductor device of the present invention, the electrodes of each substrate are connected through a layer formed by melting and integrating a plurality of metal fine particles. For this reason, even if there is a variation in the distance between the electrodes of each substrate due to the variation in the height of the electrodes, the variation in the thickness of the substrate (wafer), etc., a layer made of metal fine particles is formed according to the distance between the electrodes. By deform | transforming, the electrodes of each substrate can be reliably joined.

 本発明に係る半導体装置において、前記複数の金属微粒子の粒径は、1Å(0.1nm)以上で且つ1μm(1000nm)以下であってもよいし、より好ましくは、数Å以上で且つ数百nm以下であってもよい。特に、金属微粒子の平均粒径が50nm以下であると、例えば350℃程度以下の低温プロセスにおいて金属微粒子を溶融させることができるので、半導体装置へのダメージを低減しつつ、電極同士の接合強度を強くすることができる。このような効果は、過半数の金属微粒子の粒径が50nm程度以下であれば得ることができる。言い換えると、50nmを超える粒径の金属微粒子が存在していてもよい。また、より好ましくは、例えば250℃程度以下の低温プロセスにおいて金属微粒子を溶融させるために、金属微粒子の平均粒径が40nm程度以下であってもよい。この場合も、過半数の金属微粒子の粒径が40nm程度以下であればよく、40nmを超える粒径の金属微粒子が存在していてもよい。尚、以上の粒径とプロセス温度との関係は、金属微粒子が銅の微粒子の場合についてのものであるが、金や銀等の他の金属の微粒子であっても、同様の傾向(粒径の微細化に伴う融点の低下)が見られる。 In the semiconductor device according to the present invention, the particle diameter of the plurality of metal fine particles may be 1 mm (0.1 nm) or more and 1 μm (1000 nm) or less, more preferably several mm or more and several hundreds. It may be less than or equal to nm. In particular, when the average particle size of the metal fine particles is 50 nm or less, the metal fine particles can be melted in a low-temperature process of, for example, about 350 ° C. or less, so that the bonding strength between the electrodes is reduced while reducing damage to the semiconductor device. Can be strong. Such an effect can be obtained if the majority of the metal fine particles have a particle size of about 50 nm or less. In other words, metal fine particles having a particle diameter exceeding 50 nm may be present. More preferably, the average particle diameter of the metal fine particles may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less. Also in this case, the particle size of the majority of the metal fine particles may be about 40 nm or less, and metal fine particles having a particle size exceeding 40 nm may be present. The above relationship between the particle size and the process temperature is for the case where the metal fine particles are copper fine particles, but the same tendency (particle size) may be obtained for other metal fine particles such as gold and silver. The melting point decreases as the size of the material decreases.

 本発明に係る半導体装置において、前記複数の金属微粒子は、前記各第1の電極及び前記各第2の電極よりも高い硬度を持つ微粒子を含んでいてもよい。このようにすると、各基板の電極同士を接合する際に、電極表面に形成された自然酸化膜や汚染層等を、電極よりも高い硬度を持つ微粒子による研磨効果によって除去して電極表面を露出させることができるので、電極同士の接合歩留りをさらに向上させることができる。 In the semiconductor device according to the present invention, the plurality of metal fine particles may include fine particles having hardness higher than that of each of the first electrodes and each of the second electrodes. In this way, when the electrodes of each substrate are joined together, the natural oxide film and the contamination layer formed on the electrode surfaces are removed by the polishing effect by the fine particles having hardness higher than that of the electrodes to expose the electrode surfaces. Therefore, the junction yield between the electrodes can be further improved.

 本発明に係る半導体装置において、前記複数の金属微粒子は、銅、銀及び金から構成される金属群の中から1つ若しくは2つ以上選ばれた金属の微粒子、又は当該金属群の中から選ばれた2つ以上の金属の合金の微粒子を含んでいてもよい。この場合、前記複数の金属微粒子は、銅、銀及び金のいずれの金属よりも硬度が高く(つまりモース硬度が4以上であり)且つ導電率が1×10/mΩ以上である他の金属の微粒子をさらに含んでいてもよい。このようにすると、各基板の電極同士を接合する際に、電極表面に形成された自然酸化膜や汚染層等を、他の金属の微粒子による研磨効果によって除去して電極表面を露出させることができるので、電極同士の接合歩留りをさらに向上させることができる。尚、前記他の金属は、タングステン、コバルト、ニッケル、ルテニウム、ロジウム、イリジウム、モリブデン及びオスミウムから構成される金属群の中から1つ若しくは2つ以上選ばれた金属、又は当該金属群の中から選ばれた2つ以上の金属の合金であってもよい。 In the semiconductor device according to the present invention, the plurality of metal fine particles are selected from one or two or more metal fine particles selected from a metal group composed of copper, silver, and gold, or the metal group. Two or more metal alloy fine particles may be included. In this case, the plurality of metal fine particles have higher hardness than any of copper, silver, and gold metals (that is, Mohs hardness is 4 or more) and other metals having conductivity of 1 × 10 7 / mΩ or more. Further fine particles may be included. In this way, when the electrodes of each substrate are joined together, the natural oxide film and the contaminated layer formed on the electrode surfaces can be removed by the polishing effect of fine particles of other metals to expose the electrode surfaces. Therefore, the junction yield between the electrodes can be further improved. The other metal is one selected from the group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum and osmium, or a metal selected from the group of metals. It may be an alloy of two or more selected metals.

 本発明に係る半導体装置において、前記各第1の電極及び前記各第2の電極の少なくとも一方は、貫通電極の先端部であってもよい。 In the semiconductor device according to the present invention, at least one of the first electrodes and the second electrodes may be a tip portion of a through electrode.

 本発明に係る半導体装置において、前記各第1の電極及び前記各第2の電極の少なくとも一方は、金属から構成されていてもよい。この場合、前記各第1の電極及び前記各第2の電極の少なくとも一方を構成する前記金属は銅又は銅合金であってもよい。 In the semiconductor device according to the present invention, at least one of the first electrodes and the second electrodes may be made of metal. In this case, the metal constituting at least one of the first electrodes and the second electrodes may be copper or a copper alloy.

 本発明に係る半導体装置において、前記各第1の電極は、前記第1の基板の表面から突き出るように形成されており、前記各第2の電極は、前記各第2の電極の上面が前記第2の基板の表面と実質的に面一になるように形成されていてもよい。 In the semiconductor device according to the present invention, each of the first electrodes is formed so as to protrude from the surface of the first substrate, and the upper surface of each of the second electrodes is the surface of the second electrode. It may be formed so as to be substantially flush with the surface of the second substrate.

 本発明によると、各基板の電極同士の間での接合不良を簡単に防止できる新たな3次元集積化技術を提供することができる。 According to the present invention, it is possible to provide a new three-dimensional integration technique that can easily prevent a bonding failure between electrodes of each substrate.

図1(a)~(e)は、第1の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。FIGS. 1A to 1E are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the first embodiment. 図2は、第1の実施形態に係る半導体装置を示す断面図である。FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. 図3は、第1の実施形態の変形例に係る半導体装置を示す断面図である。FIG. 3 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment. 図4(a)~(h)は、第1の実施形態の変形例に係る半導体装置の製造方法の各工程を示す断面図である。4A to 4H are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment. 図5は、従来の3次元集積化技術を用いて基板が積層されてなる半導体装置の断面図である。FIG. 5 is a cross-sectional view of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique.

 (第1の実施形態)
 以下、第1の実施形態に係る半導体装置及びその製造方法について、図面を参照しながら説明する。
(First embodiment)
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described below with reference to the drawings.

 図1(a)~(e)は、第1の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。 FIGS. 1A to 1E are cross-sectional views showing respective steps of a semiconductor device manufacturing method according to the first embodiment.

 まず、図1(a)に示すように、例えばシリコン基板等からなる支持部材50上に金属微粒子層51を形成する。金属微粒子層51の形成は、例えば、SAM膜(自己組織化単分子膜)が表面に形成されており且つ数Å程度から数百nm程度までの直径を持つ銅微粒子を分散した溶液を支持部材50上に回転塗布することによって行ってもよい。SAM膜を構成する高分子としては、例えば、炭素数7以上のアルカンチオールを用いてもよい。より具体的には、銅微粒子の表面に配位して当該微粒子を安定させることができる高分子として知られている、3-(6-メルカプトヘキシル(mercaptohexyl ))チオフェン(thiophene )を用いてもよい(Journal of Nanomaterials Volume 2008, Article ID649130参照)。このようなSAM膜のチオール基が金属微粒子表面に配位することによって、金属微粒子の酸化及び凝集を防ぐことができる。また、銅微粒子を分散した溶液の回転塗布における回転数及び処理時間はそれぞれ、例えば、1000rpm程度から5000rpm程度までの範囲、及び、50秒程度から300秒程度までの範囲に設定してもよい。 First, as shown in FIG. 1A, a metal fine particle layer 51 is formed on a support member 50 made of, for example, a silicon substrate. The metal fine particle layer 51 is formed by, for example, using a solution in which copper fine particles having a SAM film (self-assembled monomolecular film) formed on the surface and having a diameter of several tens to several hundreds of nanometers are dispersed. You may carry out by carrying out spin coating on 50. As the polymer constituting the SAM film, for example, alkanethiol having 7 or more carbon atoms may be used. More specifically, 3- (6-mercaptohexyl) thiophene known as a polymer that can coordinate to the surface of copper fine particles and stabilize the fine particles can also be used. Good (see Journal of Nanomaterials Volume 2008, Article ID649130). By such a thiol group of the SAM film being coordinated to the surface of the metal fine particles, oxidation and aggregation of the metal fine particles can be prevented. Moreover, you may set the rotation speed and processing time in the spin coating of the solution which disperse | distributed copper microparticles | fine-particles, for example in the range from about 1000 rpm to about 5000 rpm, and the range from about 50 second to about 300 second, respectively.

 次に、支持部材50上に回転塗布により金属微粒子層51を形成した後、例えば60℃程度から150℃程度までの温度で加熱処理を行うことにより、前述の銅微粒子を分散した溶液中の溶媒を揮発させる。 Next, after the metal fine particle layer 51 is formed on the support member 50 by spin coating, the solvent in the solution in which the above-described copper fine particles are dispersed is performed, for example, at a temperature of about 60 ° C. to about 150 ° C. Volatilize.

 次に、例えばシリコンからなる基板10上に、例えば銅からなる複数の電極11を形成する。ここで、基板10上における電極11の形成を、例えば無電解めっき法を用いて行ってもよい。或いは、例えば、基板10中に予め貫通電極を形成しておき、その後、基板10を裏面(素子形成面の反対面)側から研削することにより、当該貫通電極の先端部を露出させ、当該先端部を電極11として用いてもよい。また、本実施形態において、電極11の高さは例えば5μm程度であり、電極11同士の間隔は例えば5μm程度である。 Next, a plurality of electrodes 11 made of, for example, copper are formed on a substrate 10 made of, for example, silicon. Here, the electrode 11 may be formed on the substrate 10 using, for example, an electroless plating method. Alternatively, for example, a through electrode is formed in advance in the substrate 10, and then the substrate 10 is ground from the back surface (opposite surface of the element forming surface) to expose the front end portion of the through electrode. The part may be used as the electrode 11. In the present embodiment, the height of the electrodes 11 is, for example, about 5 μm, and the distance between the electrodes 11 is, for example, about 5 μm.

 次に、図1(b)に示すように、基板10の各電極11の頂部を、支持部材50上の金属微粒子層51に、例えば2MPaの圧力で2分間程度圧接する。その後、図1(c)に示すように、基板10の各電極11の頂部を支持部材50上の金属微粒子層51から離すと、各電極11の頂部上に金属微粒子層51の一部が付着して、各電極11の頂部上に、金属微粒子層51を構成する金属微粒子からなる付着層12が形成される。 Next, as shown in FIG. 1B, the tops of the electrodes 11 of the substrate 10 are brought into pressure contact with the metal fine particle layer 51 on the support member 50 at a pressure of 2 MPa, for example, for about 2 minutes. Thereafter, as shown in FIG. 1C, when the top of each electrode 11 of the substrate 10 is separated from the metal fine particle layer 51 on the support member 50, a part of the metal fine particle layer 51 adheres on the top of each electrode 11. Thus, the adhesion layer 12 made of metal fine particles constituting the metal fine particle layer 51 is formed on the top of each electrode 11.

 尚、基板10の各電極11の頂部を、支持部材50上の金属微粒子層51に圧着する際に、加熱処理を行うことにより、各電極11の頂部上に金属微粒子層51の一部を確実に付着させることが可能となる。この加熱処理の温度を、例えば50℃程度から200℃程度までの範囲に設定してもよいが、この温度範囲に限定されるものではない。しかしながら、前記加熱処理の温度を200℃程度以下に設定することが望ましい。その理由は、200℃程度を超える温度で、各電極11の頂部上に金属微粒子層51の一部を付着させた場合には、当該付着した金属微粒子層51の一部を構成する金属微粒子の一部が溶融して凝集を生じるおそれがあるからである。このような凝集により、粒子径が拡大した金属微粒子が生じると、当該金属微粒子の融点は粒度に依存して高くなる。言い換えると、凝集により粒子径が拡大した金属微粒子の融点は、凝集前の元の金属微粒子の融点よりも高くなる。その結果、次工程における電極同士の接合に必要な温度が上昇してしまい、半導体装置に対するダメージを招くことになってしまう。 In addition, when the top part of each electrode 11 of the board | substrate 10 is crimped | bonded to the metal fine particle layer 51 on the support member 50, a part of metal fine particle layer 51 is reliably ensured on the top part of each electrode 11 by heat-processing. It becomes possible to adhere to. The temperature of this heat treatment may be set, for example, in a range from about 50 ° C. to about 200 ° C., but is not limited to this temperature range. However, it is desirable to set the temperature of the heat treatment to about 200 ° C. or less. The reason is that when a part of the metal fine particle layer 51 is attached on the top of each electrode 11 at a temperature exceeding about 200 ° C., the metal fine particles constituting a part of the attached metal fine particle layer 51 This is because some of them may melt and cause aggregation. When metal fine particles having an enlarged particle diameter are generated by such aggregation, the melting point of the metal fine particles becomes higher depending on the particle size. In other words, the melting point of the metal fine particles whose particle diameter is expanded by aggregation is higher than the melting point of the original metal fine particles before aggregation. As a result, the temperature required for joining the electrodes in the next process rises, causing damage to the semiconductor device.

 次に、図1(d)に示すように、例えばシリコンからなる基板20上に、例えば銅からなる複数の電極21を形成する。各電極21は、基板10の各電極11と対応する位置に設けられている。ここで、基板20上における電極21の形成を、例えば無電解めっき法を用いて行ってもよい。或いは、例えば、基板20中に予め貫通電極を形成しておき、その後、基板20を裏面(素子形成面の反対面)側から研削することにより、当該貫通電極の先端部を露出させ、当該先端部を電極21として用いてもよい。また、本実施形態において、電極21の高さは例えば5μm程度であり、電極21同士の間隔は例えば5μm程度である。 Next, as shown in FIG. 1D, a plurality of electrodes 21 made of, for example, copper are formed on a substrate 20 made of, for example, silicon. Each electrode 21 is provided at a position corresponding to each electrode 11 of the substrate 10. Here, the formation of the electrode 21 on the substrate 20 may be performed using, for example, an electroless plating method. Alternatively, for example, a through electrode is formed in the substrate 20 in advance, and then the substrate 20 is ground from the back surface (opposite surface of the element forming surface) to expose the front end portion of the through electrode. The part may be used as the electrode 21. In the present embodiment, the height of the electrodes 21 is, for example, about 5 μm, and the distance between the electrodes 21 is, for example, about 5 μm.

 次に、各電極11の頂部上に金属微粒子からなる付着層12が形成された基板10を、各電極11と基板20上の各電極21とが対向するように配置した後、図1(e)に示すように、付着層12を介して、各電極11と各電極22とを、例えば5MPaの圧力で5分間程度互いに圧着する。これにより、基板10と基板20とが積層される。 Next, after the substrate 10 on which the adhesion layer 12 made of metal fine particles is formed on the top of each electrode 11 is arranged so that each electrode 11 and each electrode 21 on the substrate 20 face each other, FIG. ), The electrodes 11 and the electrodes 22 are pressure-bonded to each other at a pressure of 5 MPa, for example, for about 5 minutes through the adhesion layer 12. Thereby, the board | substrate 10 and the board | substrate 20 are laminated | stacked.

 尚、基板10と基板20とを積層させる際に、基板10と基板20との間に接着剤を塗布してもよい。具体的には、基板10と基板20との間に、アンダーフィルと呼ばれる接着剤を充填してもよい。また、接着剤の充填方法としては、金属微粒子からなる付着層12による電極同士の接合を形成した後に、基板10と基板20との間の隙間に表面張力を利用してアンダーフィル材料を吸い込ませて熱処理により当該材料を硬化させる方法、又は、金属微粒子からなる付着層12による電極同士の接合を形成する前に、予め基板10及び基板20の少なくとも一方に接着剤を塗布しておき、電極同士の接合後に当該接着剤を硬化させる方法等を用いてもよい。 Note that an adhesive may be applied between the substrate 10 and the substrate 20 when the substrate 10 and the substrate 20 are laminated. Specifically, an adhesive called underfill may be filled between the substrate 10 and the substrate 20. In addition, as a method for filling the adhesive, after the electrodes are bonded by the adhesion layer 12 made of metal fine particles, the underfill material is sucked into the gap between the substrate 10 and the substrate 20 using surface tension. Before forming the bonding between the electrodes by the adhesion layer 12 made of metal fine particles, or by applying an adhesive to at least one of the substrate 10 and the substrate 20 in advance. A method of curing the adhesive after bonding may be used.

 また、本実施形態においては、各電極11と各電極22とを互いに圧着する際に、例えば150℃程度以上の温度で加熱処理を行ってもよい。これにより、付着層12を構成している各金属微粒子の表面を覆っているSAM膜が脱離して各金属微粒子の金属表面が露出する。このため、比較的低温においても各金属微粒子の融解が起こり、その結果、各金属微粒子が一体化するので、付着層12を介して電極11と電極21とを確実に接合することができる。このとき、金属微粒子からなる付着層12は塑性変形を起こすため、図2に示すように、電極11と電極21との間隔が相対的に狭い場合には、金属微粒子からなる付着層12が相対的に大きく変形し、電極11と電極12との間隔が相対的に広い場合には、金属微粒子からなる付着層12が相対的に小さく変形する。すなわち、各電極11と電極21との接合において、金属微粒子からなる付着層12は緩衝領域として作用する。このため、各電極11と各電極21との間隔がばらついていても、各電極11と各電極21とを圧着により確実に接合することができるので、信頼性の高い電極接合の形成が高歩留りで可能となる。 In the present embodiment, when the electrodes 11 and the electrodes 22 are pressure-bonded to each other, the heat treatment may be performed at a temperature of about 150 ° C. or more, for example. As a result, the SAM film covering the surface of each metal fine particle constituting the adhesion layer 12 is detached, and the metal surface of each metal fine particle is exposed. For this reason, melting of the metal fine particles occurs even at a relatively low temperature, and as a result, the metal fine particles are integrated, so that the electrode 11 and the electrode 21 can be reliably bonded via the adhesion layer 12. At this time, since the adhesion layer 12 made of metal fine particles undergoes plastic deformation, as shown in FIG. 2, when the distance between the electrode 11 and the electrode 21 is relatively narrow, the adhesion layer 12 made of metal fine particles is relatively When the distance between the electrode 11 and the electrode 12 is relatively wide, the adhesion layer 12 made of metal fine particles is deformed relatively small. That is, in the bonding between each electrode 11 and the electrode 21, the adhesion layer 12 made of metal fine particles acts as a buffer region. For this reason, even if the space | interval of each electrode 11 and each electrode 21 varies, each electrode 11 and each electrode 21 can be reliably joined by crimping | compression-bonding, Therefore Formation of highly reliable electrode joining is high yield. Is possible.

 以上に説明した方法により製造された本実施形態の半導体装置は、基板10と、基板10上に形成された複数の電極11と、基板20と、基板20上における基板10の各電極11と対応する位置に形成された複数の電極21とを備え、各電極11と当該各電極11に対応する各電極21とが、複数の金属微粒子が融解して一体化してなる付着層12を介して接続されており、それによって、基板10と基板20とが積層されている。 The semiconductor device of this embodiment manufactured by the method described above corresponds to the substrate 10, the plurality of electrodes 11 formed on the substrate 10, the substrate 20, and each electrode 11 of the substrate 10 on the substrate 20. Each electrode 11 and each electrode 21 corresponding to each electrode 11 are connected via an adhesion layer 12 formed by melting and integrating a plurality of metal fine particles. Thus, the substrate 10 and the substrate 20 are laminated.

 本実施形態によると、基板10上の各電極11と基板20上の各電極21とを接続する際に、各電極11と各電極21との間に、金属微粒子からなる付着層12を介在させている。このため、電極11若しくは電極21の高さバラツキ又は基板10若しくは基板20の厚さバラツキ等に起因して、基板10上の各電極11と基板20上の各電極21との間の距離にバラツキがあったとしても、当該電極間距離に応じて金属微粒子からなる付着層12が変形することによって、基板10上の各電極11と基板20上の各電極21とを確実に接合することができる。また、予め支持部材50上に形成されている金属微粒子層51に、基板10上の各電極11の頂部を一括して接触させることにより、各電極11の頂部上にそれぞれ金属微粒子からなる付着層12を形成するため、インクジェット装置を用いて金属粒子を含む液状物を各電極上に配置していく場合と比較して、スループットを向上させることができると共にコストを低減させることができる。 According to this embodiment, when each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 are connected, the adhesion layer 12 made of metal fine particles is interposed between each electrode 11 and each electrode 21. ing. For this reason, the distance between each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 varies due to the height variation of the electrode 11 or the electrode 21 or the thickness variation of the substrate 10 or the substrate 20. Even if there is, the adhesion layer 12 made of metal fine particles is deformed according to the distance between the electrodes, so that each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 can be reliably bonded. . In addition, the top of each electrode 11 on the substrate 10 is brought into contact with the metal fine particle layer 51 previously formed on the support member 50, whereby the adhesion layer made of metal fine particles is respectively formed on the top of each electrode 11. Therefore, the throughput can be improved and the cost can be reduced as compared with the case where a liquid material containing metal particles is disposed on each electrode using an inkjet apparatus.

 従って、本実施形態によると、基板10上の各電極11と基板20上の各電極21との間での接合不良を簡単に防止することができる。 Therefore, according to this embodiment, it is possible to easily prevent a bonding failure between each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20.

 尚、本実施形態において、金属微粒子層51を構成する金属微粒子の粒径は、1Å(0.1nm)以上で且つ1μm(1000nm)以下であってもよいし、より好ましくは、数Å以上で且つ数百nm以下であってもよい。特に、金属微粒子層51を構成する金属微粒子の平均粒径が50nm以下であると、例えば350℃程度以下の低温プロセスにおいて金属微粒子を溶融させることができるので、半導体装置へのダメージを低減しつつ、電極同士の接合強度を強くすることができる。このような効果は、金属微粒子層51中の過半数の金属微粒子の粒径が50nm程度以下であれば得ることができる。言い換えると、金属微粒子層51中に50nmを超える粒径の金属微粒子が存在していてもよい。また、より好ましくは、例えば250℃程度以下の低温プロセスにおいて金属微粒子を溶融させるために、金属微粒子層51を構成する金属微粒子の平均粒径が40nm程度以下であってもよい。この場合も、金属微粒子層51中の過半数の金属微粒子の粒径が40nm程度以下であればよく、金属微粒子層51中に40nmを超える粒径の金属微粒子が存在していてもよい。尚、以上の粒径とプロセス温度との関係は、金属微粒子層51を構成する金属微粒子が銅の微粒子の場合についてのものであるが、金や銀等の他の金属の微粒子であっても、同様の傾向(粒径の微細化に伴う融点の低下)が見られる。 In the present embodiment, the particle size of the metal fine particles constituting the metal fine particle layer 51 may be 1 mm (0.1 nm) or more and 1 μm (1000 nm) or less, more preferably several mm or more. And it may be several hundred nm or less. In particular, when the average particle diameter of the metal fine particles constituting the metal fine particle layer 51 is 50 nm or less, the metal fine particles can be melted in a low temperature process of, for example, about 350 ° C. or less, thereby reducing damage to the semiconductor device. The bonding strength between the electrodes can be increased. Such an effect can be obtained when the particle size of the majority of the metal fine particles in the metal fine particle layer 51 is about 50 nm or less. In other words, metal fine particles having a particle diameter exceeding 50 nm may exist in the metal fine particle layer 51. More preferably, the average particle diameter of the metal fine particles constituting the metal fine particle layer 51 may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less, for example. Also in this case, the particle diameter of the majority of the metal fine particles in the metal fine particle layer 51 may be about 40 nm or less, and metal fine particles having a particle diameter exceeding 40 nm may exist in the metal fine particle layer 51. The above relationship between the particle size and the process temperature is for the case where the metal fine particles constituting the metal fine particle layer 51 are copper fine particles, but even if the metal fine particles are other metal fine particles such as gold and silver. , The same tendency (decrease in melting point with the refinement of particle size) is observed.

 また、本実施形態において、金属微粒子層51は、各電極11及び各電極21よりも高い硬度を持つ微粒子を含んでいてもよい。このようにすると、基板10上の各電極11と基板20上の各電極21とを接合する際に、各電極11表面や各電極21表面に形成された自然酸化膜や汚染層等を、各電極11及び各電極21よりも高い硬度を持つ微粒子による研磨効果によって除去して各電極11表面や各電極21表面を露出させることができるので、各電極11と各電極21との接合歩留りをさらに向上させることができる。 In the present embodiment, the metal fine particle layer 51 may include fine particles having a hardness higher than that of each electrode 11 and each electrode 21. In this way, when each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 are joined, the surface of each electrode 11 or the natural oxide film or the contamination layer formed on the surface of each electrode 21 is Since the surface of each electrode 11 and the surface of each electrode 21 can be exposed by removing by the polishing effect by the fine particles having higher hardness than the electrode 11 and each electrode 21, the bonding yield between each electrode 11 and each electrode 21 can be further increased. Can be improved.

 また、本実施形態において、金属微粒子層51は、銅、銀、金、白金及びニッケル等から構成される金属群の中から1つ若しくは2つ以上選ばれた金属の微粒子、又は当該金属群の中から選ばれた2つ以上の金属の合金の微粒子を含んでいてもよい。この場合、金属微粒子層51は、銅、銀及び金のいずれの金属よりも硬度が高く(つまりモース硬度が4以上であり)且つ導電率が1×10/mΩ以上である他の金属の微粒子をさらに含んでいてもよい。このようにすると、基板10上の各電極11と基板20上の各電極21とを接合する際に、各電極11表面や各電極21表面に形成された自然酸化膜や汚染層等を、前述の硬度が高い他の金属の微粒子による研磨効果によって除去して各電極11表面や各電極21表面を露出させることができるので、各電極11と各電極21との接合歩留りをさらに向上させることができる。ここで、前述の硬度が高い他の金属は、タングステン、コバルト、ニッケル、ルテニウム、ロジウム、イリジウム、モリブデン及びオスミウムから構成される金属群の中から1つ若しくは2つ以上選ばれた金属、又は当該金属群の中から選ばれた2つ以上の金属の合金であってもよい。 In the present embodiment, the metal fine particle layer 51 is composed of one or more metal fine particles selected from a metal group composed of copper, silver, gold, platinum, nickel, or the like, or of the metal group. It may contain fine particles of an alloy of two or more metals selected from the inside. In this case, the metal fine particle layer 51 is made of other metals having higher hardness than any of copper, silver and gold (that is, Mohs hardness of 4 or more) and conductivity of 1 × 10 7 / mΩ or more. It may further contain fine particles. In this way, when each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 are joined, the surface of each electrode 11 and the natural oxide film, the contamination layer, etc. formed on the surface of each electrode 21 are Since the surface of each electrode 11 and the surface of each electrode 21 can be exposed by the polishing effect of other metal fine particles having a high hardness, the bonding yield between each electrode 11 and each electrode 21 can be further improved. it can. Here, the other metal having high hardness is one or more selected from the metal group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum and osmium, or the metal It may be an alloy of two or more metals selected from the metal group.

 また、本実施形態において、電極11及び電極21の材料として、銅を用いたが、電極11及び電極21の材料は導電性を有していれば、特に限定されるものではない。例えば、電極11及び電極21の材料として、銅に代えて、銅合金又は他の金属等を用いてもよい。また、電極11の材料と電極21の材料とが異なっていてもよい。 In the present embodiment, copper is used as the material of the electrode 11 and the electrode 21, but the material of the electrode 11 and the electrode 21 is not particularly limited as long as the material has conductivity. For example, as a material of the electrode 11 and the electrode 21, a copper alloy or other metal may be used instead of copper. Further, the material of the electrode 11 and the material of the electrode 21 may be different.

 また、本実施形態において、基板20上に複数の電極21を形成する際に、各電極21が基板20の表面(基板20上に配線等を含む層間膜が形成されている場合には当該層間膜の最表面:以下同じ)から突き出るように各電極21を形成した。しかし、これに代えて、例えば図3に示すように、基板20の表面と各電極21の上面とが実質的に面一になるように各電極21を形成し、当該各電極21と基板10上の各電極11とを接合してもよい。 In the present embodiment, when the plurality of electrodes 21 are formed on the substrate 20, each electrode 21 is formed on the surface of the substrate 20 (if an interlayer film including wiring or the like is formed on the substrate 20, the interlayer Each electrode 21 was formed so as to protrude from the outermost surface of the film: the same applies hereinafter. However, instead of this, for example, as shown in FIG. 3, each electrode 21 is formed so that the surface of the substrate 20 and the upper surface of each electrode 21 are substantially flush with each other, and each electrode 21 and the substrate 10 are formed. You may join each electrode 11 above.

 また、本実施形態において、基板10及び基板20として、シリコン基板を用いたが、基板10及び基板20のそれぞれの基板材料は、特に限定されるものではないし、基板10の材料と基板20の材料とが異なっていてもよい。 In this embodiment, silicon substrates are used as the substrate 10 and the substrate 20, but the substrate materials of the substrate 10 and the substrate 20 are not particularly limited, and the material of the substrate 10 and the material of the substrate 20 are not limited. And may be different.

 また、本実施形態において、支持部材50として、シリコン基板を用いたが、支持部材50は、金属微粒子層の形成が可能であれば、基板等に特に限定されるものではない。 In this embodiment, a silicon substrate is used as the support member 50, but the support member 50 is not particularly limited to a substrate or the like as long as a metal fine particle layer can be formed.

 また、本実施形態に係る半導体装置及びその製造方法は、チップ-チップ積層(ウェハダイシングにより得られたチップ状態の半導体装置同士の積層)、チップ-ウェハ積層(チップ状態の半導体装置と、ダイシング前のウェハ状態の半導体装置との積層)、又はウェハ-ウェハ積層(ウェハ状態の半導体装置同士の積層)された半導体装置及びその製造方法のいずれにも適用可能である。 In addition, the semiconductor device and the manufacturing method thereof according to the present embodiment include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device). The semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is laminated) or the wafer-wafer lamination (lamination of the wafer state semiconductor devices) and the manufacturing method thereof.

 (第1の実施形態の変形例)
 以下、第1の実施形態の変形例に係る半導体装置及びその製造方法について、図面を参照しながら説明する。
(Modification of the first embodiment)
Hereinafter, a semiconductor device and a method for manufacturing the same according to a modification of the first embodiment will be described with reference to the drawings.

 図4(a)~(h)は、第1の実施形態の変形例に係る半導体装置の製造方法の各工程を示す断面図である。尚、図4(a)~(h)において、図1(a)~(e)に示す第1の実施形態と同じ構成要素には同じ符号を付している。 FIGS. 4A to 4H are cross-sectional views showing respective steps of a semiconductor device manufacturing method according to a modification of the first embodiment. 4A to 4H, the same components as those of the first embodiment shown in FIGS. 1A to 1E are denoted by the same reference numerals.

 まず、第1の実施形態の図1(a)に示す工程と同様に、図4(a)に示すように、例えばシリコン基板等からなる支持部材50上に金属微粒子層51を形成する。金属微粒子層51の形成は、第1の実施形態と同様に、例えば、SAM膜(自己組織化単分子膜)が表面に形成されており且つ数Å程度から数百nm程度までの直径を持つ銅微粒子を分散した溶液を支持部材50上に回転塗布することによって行ってもよい。また、銅微粒子を分散した溶液の回転塗布における回転数及び処理時間はそれぞれ、第1の実施形態と同様に、例えば、1000rpm程度から5000rpm程度までの範囲、及び、50秒程度から300秒程度までの範囲に設定してもよい。 First, similarly to the process shown in FIG. 1A of the first embodiment, as shown in FIG. 4A, a metal fine particle layer 51 is formed on a support member 50 made of, for example, a silicon substrate. The metal fine particle layer 51 is formed in the same manner as in the first embodiment, for example, with a SAM film (self-assembled monomolecular film) formed on the surface and a diameter of about several to several hundred nm. You may carry out by spin-coating the solution which disperse | distributed copper fine particles on the support member 50. FIG. Further, the rotational speed and processing time in the spin coating of the solution in which the copper fine particles are dispersed are, for example, in the range from about 1000 rpm to about 5000 rpm, and from about 50 seconds to about 300 seconds, respectively, as in the first embodiment. You may set to the range.

 次に、支持部材50上に回転塗布により金属微粒子層51を形成した後、第1の実施形態と同様に、例えば60℃程度から150℃程度までの温度で加熱処理を行うことにより、前述の銅微粒子を分散した溶液中の溶媒を揮発させる。 Next, after the metal fine particle layer 51 is formed on the support member 50 by spin coating, the heat treatment is performed at a temperature from about 60 ° C. to about 150 ° C., for example, as in the first embodiment. The solvent in the solution in which the copper fine particles are dispersed is volatilized.

 次に、例えばシリコンからなる基板10上に、例えば銅からなる複数の電極11を形成する。ここで、基板10上における電極11の形成を、第1の実施形態と同様に、例えば無電解めっき法を用いて行ってもよい。或いは、例えば、基板10中に予め貫通電極を形成しておき、その後、基板10を裏面(素子形成面の反対面)側から研削することにより、当該貫通電極の先端部を露出させ、当該先端部を電極11として用いてもよい。また、本変形例においても、電極11の高さは例えば5μm程度であり、電極11同士の間隔は例えば5μm程度である。 Next, a plurality of electrodes 11 made of, for example, copper are formed on a substrate 10 made of, for example, silicon. Here, the electrode 11 on the substrate 10 may be formed using, for example, an electroless plating method, as in the first embodiment. Alternatively, for example, a through electrode is formed in advance in the substrate 10, and then the substrate 10 is ground from the back surface (opposite surface of the element forming surface) to expose the front end portion of the through electrode. The part may be used as the electrode 11. Also in this modification, the height of the electrodes 11 is, for example, about 5 μm, and the distance between the electrodes 11 is, for example, about 5 μm.

 次に、第1の実施形態の図1(b)に示す工程と同様に、図4(b)に示すように、基板10の各電極11の頂部を、支持部材50上の金属微粒子層51に、例えば2MPaの圧力で2分間程度圧接する。その後、第1の実施形態の図1(c)に示す工程と同様に、図4(c)に示すように、基板10の各電極11の頂部を支持部材50上の金属微粒子層51から離すと、各電極11の頂部上に金属微粒子層51の一部が付着して、各電極11の頂部上に、金属微粒子層51を構成する金属微粒子からなる付着層12が形成される。 Next, similarly to the step shown in FIG. 1B of the first embodiment, as shown in FIG. 4B, the top of each electrode 11 of the substrate 10 is placed on the metal fine particle layer 51 on the support member 50. For example, the pressure contact is performed at a pressure of 2 MPa for about 2 minutes. Thereafter, similarly to the step shown in FIG. 1C of the first embodiment, the top of each electrode 11 of the substrate 10 is separated from the metal fine particle layer 51 on the support member 50 as shown in FIG. Then, a part of the metal fine particle layer 51 adheres to the top of each electrode 11, and the adhesion layer 12 made of the metal fine particles constituting the metal fine particle layer 51 is formed on the top of each electrode 11.

 尚、本変形例においても、基板10の各電極11の頂部を、支持部材50上の金属微粒子層51に圧着する際に、加熱処理を行うことにより、各電極11の頂部上に金属微粒子層51の一部を確実に付着させることが可能となる。この加熱処理の温度を、例えば50℃程度から200℃程度までの範囲に設定してもよいが、この温度範囲に限定されるものではない。しかしながら、前記加熱処理の温度を200℃程度以下に設定することが望ましい。その理由は、200℃程度を超える温度で、各電極11の頂部上に金属微粒子層51の一部を付着させた場合には、当該付着した金属微粒子層51の一部を構成する金属微粒子の一部が溶融して凝集を生じるおそれがあるからである。このような凝集により、粒子径が拡大した金属微粒子が生じると、当該金属微粒子の融点は粒度に依存して高くなる。言い換えると、凝集により粒子径が拡大した金属微粒子の融点は、凝集前の元の金属微粒子の融点よりも高くなる。その結果、次工程における電極同士の接合に必要な温度が上昇してしまい、半導体装置に対するダメージを招くことになってしまう。 In this modified example, when the top of each electrode 11 of the substrate 10 is pressure-bonded to the metal fine particle layer 51 on the support member 50, the metal fine particle layer is formed on the top of each electrode 11 by performing heat treatment. It becomes possible to adhere a part of 51 reliably. The temperature of this heat treatment may be set, for example, in a range from about 50 ° C. to about 200 ° C., but is not limited to this temperature range. However, it is desirable to set the temperature of the heat treatment to about 200 ° C. or less. The reason is that when a part of the metal fine particle layer 51 is attached on the top of each electrode 11 at a temperature exceeding about 200 ° C., the metal fine particles constituting a part of the attached metal fine particle layer 51 This is because some of them may melt and cause aggregation. When metal fine particles having an enlarged particle diameter are generated by such aggregation, the melting point of the metal fine particles becomes higher depending on the particle size. In other words, the melting point of the metal fine particles whose particle diameter is expanded by aggregation is higher than the melting point of the original metal fine particles before aggregation. As a result, the temperature required for joining the electrodes in the next process rises, causing damage to the semiconductor device.

 次に、図4(d)に示すように、例えばシリコン基板等からなる支持部材60上に金属微粒子層61を形成する。金属微粒子層61の形成は、前述の金属微粒子層51の形成と同様に、例えば、SAM膜(自己組織化単分子膜)が表面に形成されており且つ数Å程度から数百nm程度までの直径を持つ銅微粒子を分散した溶液を支持部材50上に回転塗布することによって行ってもよい。SAM膜を構成する高分子としては、前述の金属微粒子層51の形成と同様に、例えば、炭素数7以上のアルカンチオールを用いてもよく、より具体的には、銅微粒子の表面に配位して当該微粒子を安定させることができる高分子として知られている、3-(6-メルカプトヘキシル)チオフェン)を用いてもよい。このようなSAM膜のチオール基が金属微粒子表面に配位することによって、金属微粒子の酸化及び凝集を防ぐことができる。また、銅微粒子を分散した溶液の回転塗布における回転数及び処理時間はそれぞれ、前述の金属微粒子層51の形成と同様に、例えば、1000rpm程度から5000rpm程度までの範囲、及び、50秒程度から300秒程度までの範囲に設定してもよい。 Next, as shown in FIG. 4D, a metal fine particle layer 61 is formed on a support member 60 made of, for example, a silicon substrate. The formation of the metal fine particle layer 61 is similar to the formation of the metal fine particle layer 51 described above. For example, a SAM film (self-assembled monomolecular film) is formed on the surface, and the thickness is about several to several hundred nm. You may carry out by spin-coating the solution which disperse | distributed the copper fine particle with a diameter on the supporting member 50. FIG. As the polymer constituting the SAM film, for example, alkanethiol having 7 or more carbon atoms may be used as in the formation of the metal fine particle layer 51 described above, and more specifically, coordination is performed on the surface of the copper fine particles. Then, 3- (6-mercaptohexyl) thiophene, which is known as a polymer capable of stabilizing the fine particles, may be used. By such a thiol group of the SAM film being coordinated to the surface of the metal fine particles, oxidation and aggregation of the metal fine particles can be prevented. In addition, the number of rotations and the processing time in the spin coating of the solution in which copper fine particles are dispersed are, for example, in the range from about 1000 rpm to about 5000 rpm, and from about 50 seconds to 300 seconds, as in the formation of the metal fine particle layer 51. You may set to the range to about second.

 次に、支持部材60上に回転塗布により金属微粒子層61を形成した後、例えば60℃程度から150℃程度までの温度で加熱処理を行うことにより、前述の銅微粒子を分散した溶液中の溶媒を揮発させる。 Next, after the metal fine particle layer 61 is formed on the support member 60 by spin coating, a heat treatment is performed at a temperature from about 60 ° C. to about 150 ° C., for example. Volatilize.

 次に、例えばシリコンからなる基板20上に、例えば銅からなる複数の電極21を形成する。各電極21は、基板10の各電極11と対応する位置に設けられている。ここで、基板20上における電極21の形成を、例えば無電解めっき法を用いて行ってもよい。或いは、例えば、基板20中に予め貫通電極を形成しておき、その後、基板20を裏面(素子形成面の反対面)側から研削することにより、当該貫通電極の先端部を露出させ、当該先端部を電極21として用いてもよい。また、本変形例において、電極21の高さは例えば5μm程度であり、電極21同士の間隔は例えば5μm程度である。 Next, a plurality of electrodes 21 made of, for example, copper are formed on a substrate 20 made of, for example, silicon. Each electrode 21 is provided at a position corresponding to each electrode 11 of the substrate 10. Here, the formation of the electrode 21 on the substrate 20 may be performed using, for example, an electroless plating method. Alternatively, for example, a through electrode is formed in the substrate 20 in advance, and then the substrate 20 is ground from the back surface (opposite surface of the element forming surface) to expose the front end portion of the through electrode. The part may be used as the electrode 21. In the present modification, the height of the electrodes 21 is, for example, about 5 μm, and the distance between the electrodes 21 is, for example, about 5 μm.

 次に、図4(e)に示すように、基板20の各電極21の頂部を、支持部材60上の金属微粒子層61に、例えば2MPaの圧力で2分間程度圧接する。その後、図4(f)に示すように、基板20の各電極21の頂部を支持部材60上の金属微粒子層61から離すと、各電極21の頂部上に金属微粒子層61の一部が付着して、各電極21の頂部上に、金属微粒子層61を構成する金属微粒子からなる付着層22が形成される。 Next, as shown in FIG. 4E, the tops of the electrodes 21 of the substrate 20 are brought into pressure contact with the metal fine particle layer 61 on the support member 60 at a pressure of 2 MPa, for example, for about 2 minutes. Thereafter, as shown in FIG. 4 (f), when the top of each electrode 21 of the substrate 20 is separated from the metal fine particle layer 61 on the support member 60, a part of the metal fine particle layer 61 adheres on the top of each electrode 21. Thus, the adhesion layer 22 made of metal fine particles constituting the metal fine particle layer 61 is formed on the top of each electrode 21.

 尚、基板20の各電極21の頂部を、支持部材60上の金属微粒子層61に圧着する際に、加熱処理を行うことにより、各電極21の頂部上に金属微粒子層61の一部を確実に付着させることが可能となる。この加熱処理の温度を、例えば50℃程度から200℃程度までの範囲に設定してもよいが、この温度範囲に限定されるものではない。しかしながら、前記加熱処理の温度を200℃程度以下に設定することが望ましい。その理由は、200℃程度を超える温度で、各電極21の頂部上に金属微粒子層61の一部を付着させた場合には、当該付着した金属微粒子層61の一部を構成する金属微粒子の一部が溶融して凝集を生じるおそれがあるからである。このような凝集により、粒子径が拡大した金属微粒子が生じると、当該金属微粒子の融点は粒度に依存して高くなる。言い換えると、凝集により粒子径が拡大した金属微粒子の融点は、凝集前の元の金属微粒子の融点よりも高くなる。その結果、次工程における電極同士の接合に必要な温度が上昇してしまい、半導体装置に対するダメージを招くことになってしまう。 In addition, when the top part of each electrode 21 of the board | substrate 20 is crimped | bonded to the metal fine particle layer 61 on the supporting member 60, a part of metal fine particle layer 61 is ensured on the top part of each electrode 21 by performing heat processing. It becomes possible to adhere to. The temperature of this heat treatment may be set, for example, in a range from about 50 ° C. to about 200 ° C., but is not limited to this temperature range. However, it is desirable to set the temperature of the heat treatment to about 200 ° C. or less. The reason is that when a part of the metal fine particle layer 61 is attached on the top of each electrode 21 at a temperature exceeding about 200 ° C., the metal fine particles constituting a part of the attached metal fine particle layer 61 This is because some of them may melt and cause aggregation. When metal fine particles having an enlarged particle diameter are generated by such aggregation, the melting point of the metal fine particles becomes higher depending on the particle size. In other words, the melting point of the metal fine particles whose particle diameter is expanded by aggregation is higher than the melting point of the original metal fine particles before aggregation. As a result, the temperature required for joining the electrodes in the next process rises, causing damage to the semiconductor device.

 次に、図4(g)に示すように、各電極11の頂部上に金属微粒子からなる付着層12が形成された基板10と、各電極21の頂部上に金属微粒子からなる付着層22が形成された基板20とを、各電極11と各電極21とが対向するように配置した後、図4(h)に示すように、付着層12及び付着層22を介して、各電極11と各電極22とを、例えば5MPaの圧力で5分間程度互いに圧着する。これにより、基板10と基板20とが積層される。 Next, as shown in FIG. 4G, the substrate 10 on which the adhesion layer 12 made of metal fine particles is formed on the top of each electrode 11, and the adhesion layer 22 made of metal fine particles on the top of each electrode 21. After the formed substrate 20 is arranged so that each electrode 11 and each electrode 21 face each other, as shown in FIG. 4 (h), each electrode 11 and The electrodes 22 are bonded to each other at a pressure of 5 MPa, for example, for about 5 minutes. Thereby, the board | substrate 10 and the board | substrate 20 are laminated | stacked.

 尚、基板10と基板20とを積層させる際に、基板10と基板20との間に接着剤を塗布してもよい。具体的には、基板10と基板20との間に、アンダーフィルと呼ばれる接着剤を充填してもよい。また、接着剤の充填方法としては、金属微粒子からなる付着層12による電極同士の接合を形成した後に、基板10と基板20との間の隙間に表面張力を利用してアンダーフィル材料を吸い込ませて熱処理により当該材料を硬化させる方法、又は、金属微粒子からなる付着層12による電極同士の接合を形成する前に、予め基板10及び基板20の少なくとも一方に接着剤を塗布しておき、電極同士の接合後に当該接着剤を硬化させる方法等を用いてもよい。 Note that an adhesive may be applied between the substrate 10 and the substrate 20 when the substrate 10 and the substrate 20 are laminated. Specifically, an adhesive called underfill may be filled between the substrate 10 and the substrate 20. In addition, as a method for filling the adhesive, after the electrodes are bonded by the adhesion layer 12 made of metal fine particles, the underfill material is sucked into the gap between the substrate 10 and the substrate 20 using surface tension. Before forming the bonding between the electrodes by the adhesion layer 12 made of metal fine particles, or by applying an adhesive to at least one of the substrate 10 and the substrate 20 in advance. A method of curing the adhesive after bonding may be used.

 また、本変形例においては、各電極11と各電極22とを互いに圧着する際に、例えば150℃程度以上の温度で加熱処理を行ってもよい。これにより、付着層12及び付着層22をそれぞれ構成している各金属微粒子の表面を覆っているSAM膜が脱離して各金属微粒子の金属表面が露出する。このため、比較的低温においても各金属微粒子の融解が起こり、その結果、各金属微粒子が一体化するので、付着層12及び付着層22を介して電極11と電極21とを確実に接合することができる。このとき、それぞれ金属微粒子からなる付着層12及び付着層22は塑性変形を起こすため、電極11と電極21との間隔が相対的に狭い場合には、それぞれ金属微粒子からなる付着層12及び付着層22が相対的に大きく変形し、電極11と電極12との間隔が相対的に広い場合には、それぞれ金属微粒子からなる付着層12及び付着層22が相対的に小さく変形する。すなわち、各電極11と電極21との接合において、それぞれ金属微粒子からなる付着層12及び付着層22は緩衝領域として作用する。このため、各電極11と各電極21との間隔がばらついていても、各電極11と各電極21とを圧着により確実に接合することができるので、信頼性の高い電極接合の形成が高歩留りで可能となる。 Moreover, in this modification, when each electrode 11 and each electrode 22 are pressure-bonded to each other, for example, heat treatment may be performed at a temperature of about 150 ° C. or higher. As a result, the SAM film covering the surface of each metal fine particle constituting the adhesion layer 12 and the adhesion layer 22 is detached, and the metal surface of each metal fine particle is exposed. For this reason, melting of each metal fine particle occurs even at a relatively low temperature, and as a result, each metal fine particle is integrated, so that the electrode 11 and the electrode 21 can be reliably bonded via the adhesion layer 12 and the adhesion layer 22. Can do. At this time, since the adhesion layer 12 and the adhesion layer 22 each made of metal fine particles cause plastic deformation, when the distance between the electrode 11 and the electrode 21 is relatively narrow, the adhesion layer 12 and the adhesion layer each made of metal fine particles, respectively. When 22 is relatively greatly deformed and the distance between the electrode 11 and the electrode 12 is relatively wide, the adhesion layer 12 and the adhesion layer 22 made of metal fine particles are respectively relatively deformed. That is, in the bonding between each electrode 11 and the electrode 21, the adhesion layer 12 and the adhesion layer 22 each made of metal fine particles act as a buffer region. For this reason, even if the space | interval of each electrode 11 and each electrode 21 varies, each electrode 11 and each electrode 21 can be reliably joined by crimping | compression-bonding, Therefore Formation of highly reliable electrode joining is high yield. Is possible.

 以上に説明した方法により製造された本変形例の半導体装置は、基板10と、基板10上に形成された複数の電極11と、基板20と、基板20上における基板10の各電極11と対応する位置に形成された複数の電極21とを備え、各電極11と当該各電極11に対応する各電極21とが、複数の金属微粒子が融解して一体化してなる付着層12及び付着層22を介して接続されており、それによって、基板10と基板20とが積層されている。 The semiconductor device of this modification manufactured by the method described above corresponds to the substrate 10, the plurality of electrodes 11 formed on the substrate 10, the substrate 20, and each electrode 11 of the substrate 10 on the substrate 20. The adhesion layer 12 and the adhesion layer 22 are formed by integrating each electrode 11 and each electrode 21 corresponding to each electrode 11 by melting a plurality of metal fine particles. Thus, the substrate 10 and the substrate 20 are laminated.

 本変形例によると、基板10上の各電極11と基板20上の各電極21とを接続する際に、各電極11と各電極21との間に、それぞれ金属微粒子からなる付着層12及び付着層22を介在させている。このため、電極11若しくは電極21の高さバラツキ又は基板10若しくは基板20の厚さバラツキ等に起因して、基板10上の各電極11と基板20上の各電極21との間の距離にバラツキがあったとしても、当該電極間距離に応じて、それぞれ金属微粒子からなる付着層12及び付着層22が変形することによって、基板10上の各電極11と基板20上の各電極21とを確実に接合することができる。また、予め支持部材50及び60上に形成されている金属微粒子層51及び61に、基板10及び20上の各電極11及び21の頂部を一括して接触させることにより、各電極11及び21の頂部上に、それぞれ金属微粒子からなる付着層12及び付着層22を形成するため、インクジェット装置を用いて金属粒子を含む液状物を各電極上に配置していく場合と比較して、スループットを向上させることができると共にコストを低減させることができる。 According to this modification, when each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 are connected, the adhesion layer 12 made of metal fine particles and the adhesion between each electrode 11 and each electrode 21. Layer 22 is interposed. For this reason, the distance between each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 varies due to the height variation of the electrode 11 or the electrode 21 or the thickness variation of the substrate 10 or the substrate 20. Even if there is, the adhesion layer 12 and the adhesion layer 22 made of metal fine particles are deformed according to the distance between the electrodes, so that each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 are securely connected. Can be joined. Further, by bringing the tops of the electrodes 11 and 21 on the substrates 10 and 20 into contact with the metal fine particle layers 51 and 61 formed on the support members 50 and 60 in advance, In order to form the adhesion layer 12 and the adhesion layer 22 each made of metal fine particles on the top, the throughput is improved as compared with the case where a liquid material containing metal particles is arranged on each electrode using an ink jet device. And cost can be reduced.

 従って、本変形例によると、基板10上の各電極11と基板20上の各電極21との間での接合不良を簡単に防止することができる。 Therefore, according to this modification, it is possible to easily prevent a bonding failure between each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20.

 尚、本変形例において、金属微粒子層51及び61を構成する金属微粒子の粒径は、1Å(0.1nm)以上で且つ1μm(1000nm)以下であってもよいし、より好ましくは、数Å以上で且つ数百nm以下であってもよい。特に、金属微粒子層51及び61を構成する金属微粒子の平均粒径が50nm以下であると、例えば350℃程度以下の低温プロセスにおいて金属微粒子を溶融させることができるので、半導体装置へのダメージを低減しつつ、電極同士の接合強度を強くすることができる。このような効果は、金属微粒子層51及び61中の過半数の金属微粒子の粒径が50nm程度以下であれば得ることができる。言い換えると、金属微粒子層51及び61中に50nmを超える粒径の金属微粒子が存在していてもよい。また、より好ましくは、例えば250℃程度以下の低温プロセスにおいて金属微粒子を溶融させるために、金属微粒子層51及び61を構成する金属微粒子の平均粒径が40nm程度以下であってもよい。この場合も、金属微粒子層51及び61中の過半数の金属微粒子の粒径が40nm程度以下であればよく、金属微粒子層51及び61中に40nmを超える粒径の金属微粒子が存在していてもよい。尚、以上の粒径とプロセス温度との関係は、金属微粒子層51及び61を構成する金属微粒子が銅の微粒子の場合についてのものであるが、金や銀等の他の金属の微粒子であっても、同様の傾向(粒径の微細化に伴う融点の低下)が見られる。 In this modification, the particle size of the metal fine particles constituting the metal fine particle layers 51 and 61 may be 1 mm (0.1 nm) or more and 1 μm (1000 nm) or less, more preferably several mm. Above and several hundred nm or less may be sufficient. In particular, when the average particle diameter of the metal fine particles constituting the metal fine particle layers 51 and 61 is 50 nm or less, the metal fine particles can be melted in a low temperature process of, for example, about 350 ° C. or less, thereby reducing damage to the semiconductor device. However, the bonding strength between the electrodes can be increased. Such an effect can be obtained if the particle diameters of the majority of the metal fine particles in the metal fine particle layers 51 and 61 are about 50 nm or less. In other words, metal fine particles having a particle diameter exceeding 50 nm may be present in the metal fine particle layers 51 and 61. More preferably, the average particle diameter of the metal fine particles constituting the metal fine particle layers 51 and 61 may be about 40 nm or less in order to melt the metal fine particles in a low temperature process of about 250 ° C. or less, for example. Also in this case, the particle diameters of the majority of the metal fine particles in the metal fine particle layers 51 and 61 may be about 40 nm or less, and even if metal fine particles having a particle diameter exceeding 40 nm exist in the metal fine particle layers 51 and 61. Good. The above relationship between the particle size and the process temperature is for the case where the metal fine particles constituting the metal fine particle layers 51 and 61 are copper fine particles. However, the same tendency (decrease in melting point accompanying the refinement of particle size) is observed.

 また、本変形例において、金属微粒子層51及び61の少なくとも一方は、各電極11及び各電極21よりも高い硬度を持つ微粒子を含んでいてもよい。このようにすると、基板10上の各電極11と基板20上の各電極21とを接合する際に、各電極11表面や各電極21表面に形成された自然酸化膜や汚染層等を、各電極11及び各電極21よりも高い硬度を持つ微粒子による研磨効果によって除去して各電極11表面や各電極21表面を露出させることができるので、各電極11と各電極21との接合歩留りをさらに向上させることができる。 Further, in the present modification, at least one of the metal fine particle layers 51 and 61 may contain fine particles having a hardness higher than that of each electrode 11 and each electrode 21. In this way, when each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 are joined, the surface of each electrode 11 or the natural oxide film or the contamination layer formed on the surface of each electrode 21 is Since the surface of each electrode 11 and the surface of each electrode 21 can be exposed by removing by the polishing effect by the fine particles having higher hardness than the electrode 11 and each electrode 21, the bonding yield between each electrode 11 and each electrode 21 can be further increased. Can be improved.

 また、本変形例において、金属微粒子層51及び61の少なくとも一方は、銅、銀、金、白金及びニッケル等から構成される金属群の中から1つ若しくは2つ以上選ばれた金属の微粒子、又は当該金属群の中から選ばれた2つ以上の金属の合金の微粒子を含んでいてもよい。この場合、金属微粒子層51及び61の当該少なくとも一方は、銅、銀及び金のいずれの金属よりも硬度が高く(つまりモース硬度が4以上であり)且つ導電率が1×10/mΩ以上である他の金属の微粒子をさらに含んでいてもよい。このようにすると、基板10上の各電極11と基板20上の各電極21とを接合する際に、各電極11表面や各電極21表面に形成された自然酸化膜や汚染層等を、前述の硬度が高い他の金属の微粒子による研磨効果によって除去して各電極11表面や各電極21表面を露出させることができるので、各電極11と各電極21との接合歩留りをさらに向上させることができる。ここで、前述の硬度が高い他の金属は、タングステン、コバルト、ニッケル、ルテニウム、ロジウム、イリジウム、モリブデン及びオスミウムから構成される金属群の中から1つ若しくは2つ以上選ばれた金属、又は当該金属群の中から選ばれた2つ以上の金属の合金であってもよい。 Further, in the present modification, at least one of the metal fine particle layers 51 and 61 is a metal fine particle selected from one or two or more of a metal group composed of copper, silver, gold, platinum, nickel, and the like, Alternatively, it may contain fine particles of an alloy of two or more metals selected from the metal group. In this case, at least one of the metal fine particle layers 51 and 61 is higher in hardness than any metal of copper, silver, and gold (that is, the Mohs hardness is 4 or more) and has a conductivity of 1 × 10 7 / mΩ or more. It may further contain other metal fine particles. In this way, when each electrode 11 on the substrate 10 and each electrode 21 on the substrate 20 are joined, the surface of each electrode 11 and the natural oxide film, the contamination layer, etc. formed on the surface of each electrode 21 are Since the surface of each electrode 11 and the surface of each electrode 21 can be exposed by the polishing effect of other metal fine particles having a high hardness, the bonding yield between each electrode 11 and each electrode 21 can be further improved. it can. Here, the other metal having high hardness is one or more selected from the metal group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum and osmium, or the metal It may be an alloy of two or more metals selected from the metal group.

 また、本変形例において、電極11及び電極21の材料として、銅を用いたが、電極11及び電極21の材料は導電性を有していれば、特に限定されるものではない。例えば、電極11及び電極21の材料として、銅に代えて、銅合金又は他の金属等を用いてもよい。また、電極11の材料と電極21の材料とが異なっていてもよい。 In this modification, copper is used as the material of the electrode 11 and the electrode 21, but the material of the electrode 11 and the electrode 21 is not particularly limited as long as the material has conductivity. For example, as a material of the electrode 11 and the electrode 21, a copper alloy or other metal may be used instead of copper. Further, the material of the electrode 11 and the material of the electrode 21 may be different.

 また、本変形例において、基板10及び基板20として、シリコン基板を用いたが、基板10及び基板20のそれぞれの基板材料は、特に限定されるものではないし、基板10の材料と基板20の材料とが異なっていてもよい。 In this modification, silicon substrates are used as the substrate 10 and the substrate 20, but the substrate materials of the substrate 10 and the substrate 20 are not particularly limited, and the material of the substrate 10 and the material of the substrate 20 are not limited. And may be different.

 また、本変形例において、支持部材50及び支持部材60として、シリコン基板を用いたが、支持部材50及び支持部材60は、金属微粒子層の形成が可能であれば、基板等に特に限定されるものではないし、支持部材50と支持部材60とが異なる種類の部材であってもよい。 In this modification, silicon substrates are used as the support member 50 and the support member 60. However, the support member 50 and the support member 60 are particularly limited to a substrate or the like as long as a metal fine particle layer can be formed. However, the support member 50 and the support member 60 may be different types of members.

 また、本変形例に係る半導体装置及びその製造方法は、チップ-チップ積層(ウェハダイシングにより得られたチップ状態の半導体装置同士の積層)、チップ-ウェハ積層(チップ状態の半導体装置と、ダイシング前のウェハ状態の半導体装置との積層)、又はウェハ-ウェハ積層(ウェハ状態の半導体装置同士の積層)された半導体装置及びその製造方法のいずれにも適用可能である。 In addition, the semiconductor device and the manufacturing method thereof according to this modification include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and before dicing) The semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is laminated) or the wafer-wafer lamination (lamination of the wafer state semiconductor devices) and the manufacturing method thereof.

 以上に説明したように、本発明に係る半導体装置及びその製造方法は、積層基板間の接続において、電極の高さバラツキや基板の厚さバラツキ等に起因する各基板の電極同士の接合不良の発生を防止できるものであり、特に、チップ-チップ積層、チップ-ウェハ積層又はウェハ-ウェハ積層された半導体装置における金属微粒子を用いた電極同士の接合方法として有用である。 As described above, in the semiconductor device and the manufacturing method thereof according to the present invention, in the connection between the stacked substrates, the bonding failure between the electrodes of each substrate due to the variation in the height of the electrodes, the variation in the thickness of the substrates, and the like. In particular, it is useful as a method for bonding electrodes using metal fine particles in a chip-chip stacked, chip-wafer stacked or wafer-wafer stacked semiconductor device.

 10、20  基板
 11、21  電極
 12、22  付着層
 50、60  支持部材
 51、61  金属微粒子層
10, 20 Substrate 11, 21 Electrode 12, 22 Adhesive layer 50, 60 Support member 51, 61 Metal fine particle layer

Claims (39)

 複数の第1の電極が形成されている第1の基板と、前記第1の基板の前記各第1の電極と対応する位置に複数の第2の電極が形成されている第2の基板とが積層されてなる半導体装置の製造方法であって、
 第1の支持部材上に第1の金属微粒子層を形成する工程(a)と、
 前記第1の基板の前記各第1の電極の頂部を前記第1の支持部材上の前記第1の金属微粒子層に接触させて前記各第1の電極の頂部上に前記第1の金属微粒子層の一部を付着させることにより、前記各第1の電極の頂部上に、前記第1の金属微粒子層を構成する金属微粒子からなる第1の付着層を形成する工程(b)と、
 前記工程(b)の後、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを互いに対向させ、前記第1の付着層を介して、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを接続することにより、前記第1の基板と前記第2の基板とを積層する工程(c)とを備えていることを特徴とする半導体装置の製造方法。
A first substrate on which a plurality of first electrodes are formed; a second substrate on which a plurality of second electrodes are formed at positions corresponding to the first electrodes of the first substrate; Is a method of manufacturing a semiconductor device in which
Forming a first metal fine particle layer on the first support member (a);
The top of each first electrode of the first substrate is brought into contact with the first metal fine particle layer on the first support member so that the first metal fine particles are formed on the top of each first electrode. Forming a first adhesion layer made of metal fine particles constituting the first metal fine particle layer on the top of each first electrode by adhering a part of the layer (b);
After the step (b), the first electrodes and the second electrodes corresponding to the first electrodes are opposed to each other, and the first electrodes are interposed through the first adhesion layer. A step (c) of laminating the first substrate and the second substrate by connecting the second electrode corresponding to the first electrode and the second electrode corresponding to the first electrode. A method of manufacturing a semiconductor device.
 請求項1に記載の半導体装置の製造方法において、
 前記工程(c)において、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを互いに圧着させながら加熱処理を行うことにより、前記第1の付着層を構成する前記金属微粒子のそれぞれを融解させて一体化させ、それによって、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを接合することを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 1,
In the step (c), the first adhesion layer is formed by performing heat treatment while pressing the first electrodes and the second electrodes corresponding to the first electrodes. Each of the metal fine particles to be melted and integrated, thereby joining each first electrode and each second electrode corresponding to each first electrode Manufacturing method.
 請求項2に記載の半導体装置の製造方法において、
 前記工程(c)の前記加熱処理の温度は150℃以上であることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 2,
The method of manufacturing a semiconductor device, wherein the temperature of the heat treatment in the step (c) is 150 ° C. or higher.
 請求項1~3のいずれか1項に記載の半導体装置の製造方法において、
 前記工程(a)において、前記第1の金属微粒子層を構成する前記金属微粒子の表面を第1の有機材料膜によってコーティングすることを特徴とする半導体装置の製造方法。
The method for manufacturing a semiconductor device according to any one of claims 1 to 3,
In the step (a), the surface of the metal fine particles constituting the first metal fine particle layer is coated with a first organic material film.
 請求項4に記載の半導体装置の製造方法において、
 前記工程(c)において、前記第1の付着層を構成する前記金属微粒子の表面を覆う前記第1の有機材料膜を当該表面から脱離させることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 4,
In the step (c), the method of manufacturing a semiconductor device, wherein the first organic material film covering the surface of the metal fine particles constituting the first adhesion layer is detached from the surface.
 請求項4又は5に記載の半導体装置の製造方法において、
 前記第1の有機材料膜はSAM膜であることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 4 or 5,
The method of manufacturing a semiconductor device, wherein the first organic material film is a SAM film.
 請求項6に記載の半導体装置の製造方法において、
 前記SAM膜はアルカンチオールを含むことを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 6,
The method of manufacturing a semiconductor device, wherein the SAM film contains alkanethiol.
 請求項1~7のいずれか1項に記載の半導体装置の製造方法において、
 前記工程(b)において、前記各第1の電極の頂部を前記第1の金属微粒子層に圧接させながら加熱処理を行うことを特徴とする半導体装置の製造方法。
The method of manufacturing a semiconductor device according to any one of claims 1 to 7,
In the step (b), the semiconductor device manufacturing method is characterized in that heat treatment is performed while the top of each first electrode is pressed against the first metal fine particle layer.
 請求項8に記載の半導体装置の製造方法において、
 前記工程(b)の前記加熱処理の温度は50℃以上で且つ200℃以下であることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 8,
The method for manufacturing a semiconductor device, wherein the temperature of the heat treatment in the step (b) is 50 ° C. or higher and 200 ° C. or lower.
 請求項1~9のいずれか1項に記載の半導体装置の製造方法において、
 前記第1の金属微粒子層を構成する前記金属微粒子の粒径は、1Å以上で且つ1μm以下であることを特徴とする半導体装置の製造方法。
The method of manufacturing a semiconductor device according to any one of claims 1 to 9,
The method of manufacturing a semiconductor device, wherein the metal fine particles constituting the first metal fine particle layer have a particle diameter of 1 to 1 μm.
 請求項1~10のいずれか1項に記載の半導体装置の製造方法において、
 前記第1の金属微粒子層は、前記各第1の電極及び前記各第2の電極よりも高い硬度を持つ微粒子を含むことを特徴とする半導体装置の製造方法。
The method of manufacturing a semiconductor device according to any one of claims 1 to 10,
The method of manufacturing a semiconductor device, wherein the first metal fine particle layer includes fine particles having hardness higher than that of each of the first electrodes and each of the second electrodes.
 請求項1~11のいずれか1項に記載の半導体装置の製造方法において、
 前記第1の金属微粒子層は、銅、銀及び金から構成される金属群の中から1つ若しくは2つ以上選ばれた金属の微粒子、又は当該金属群の中から選ばれた2つ以上の金属の合金の微粒子を含むことを特徴とする半導体装置の製造方法。
The method of manufacturing a semiconductor device according to any one of claims 1 to 11,
The first metal fine particle layer may be one or more metal fine particles selected from a metal group composed of copper, silver and gold, or two or more metal fine particles selected from the metal group. A method for manufacturing a semiconductor device, comprising fine particles of a metal alloy.
 請求項12に記載の半導体装置の製造方法において、
 前記第1の金属微粒子層は、銅、銀及び金のいずれの金属よりも硬度が高く且つ導電率が1×10/mΩ以上である他の金属の微粒子をさらに含むことを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 12,
The first metal fine particle layer further includes fine particles of another metal having a higher hardness than any one of copper, silver and gold and having an electric conductivity of 1 × 10 7 / mΩ or more. Device manufacturing method.
 請求項13に記載の半導体装置の製造方法において、
 前記他の金属は、タングステン、コバルト、ニッケル、ルテニウム、ロジウム、イリジウム、モリブデン及びオスミウムから構成される金属群の中から1つ若しくは2つ以上選ばれた金属、又は当該金属群の中から選ばれた2つ以上の金属の合金であることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 13,
The other metal is selected from one or more metals selected from the group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum and osmium, or selected from the group of metals. A method of manufacturing a semiconductor device, which is an alloy of two or more metals.
 請求項1~14のいずれか1項に記載の半導体装置の製造方法において、
 前記工程(c)の前に、
 第2の支持部材上に第2の金属微粒子層を形成する工程(d)と、
 前記第2の基板の前記各第2の電極の頂部を前記第2の支持部材上の前記第2の金属微粒子層に接触させて前記各第2の電極の頂部上に前記第2の金属微粒子層の一部を付着させることにより、前記各第2の電極の頂部上に、前記第2の金属微粒子層を構成する金属微粒子からなる第2の付着層を形成する工程(e)とをさらに備え、
 前記工程(c)において、前記第1の付着層及び前記第2の付着層を介して、前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とを接続することにより、前記第1の基板と前記第2の基板とを積層することを特徴とする半導体装置の製造方法。
The method of manufacturing a semiconductor device according to any one of claims 1 to 14,
Before the step (c),
A step (d) of forming a second metal fine particle layer on the second support member;
The top of each second electrode of the second substrate is brought into contact with the second metal fine particle layer on the second support member so that the second metal fine particles are formed on the top of each second electrode. A step (e) of forming a second adhesion layer made of metal fine particles constituting the second metal fine particle layer on the top of each second electrode by adhering a part of the layer; Prepared,
In the step (c), the first electrodes and the second electrodes corresponding to the first electrodes are connected via the first adhesive layer and the second adhesive layer. Thus, the method of manufacturing a semiconductor device, wherein the first substrate and the second substrate are stacked.
 請求項15に記載の半導体装置の製造方法において、
 前記工程(d)において、前記第2の金属微粒子層を構成する前記金属微粒子の表面を第2の有機材料膜によってコーティングすることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 15,
In the step (d), the surface of the metal fine particles constituting the second metal fine particle layer is coated with a second organic material film.
 請求項16に記載の半導体装置の製造方法において、
 前記工程(c)において、前記第2の付着層を構成する前記金属微粒子の表面を覆う前記第2の有機材料膜を当該表面から脱離させることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 16,
In the step (c), the method of manufacturing a semiconductor device, wherein the second organic material film covering the surface of the metal fine particles constituting the second adhesion layer is detached from the surface.
 請求項16又は17に記載の半導体装置の製造方法において、
 前記第2の有機材料膜はSAM膜であることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 16 or 17,
The method of manufacturing a semiconductor device, wherein the second organic material film is a SAM film.
 請求項18に記載の半導体装置の製造方法において、
 前記SAM膜はアルカンチオールを含むことを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 18,
The method of manufacturing a semiconductor device, wherein the SAM film contains alkanethiol.
 請求項15~19のいずれか1項に記載の半導体装置の製造方法において、
 前記工程(e)において、前記各第2の電極の頂部を前記第2の金属微粒子層に圧接させながら加熱処理を行うことを特徴とする半導体装置の製造方法。
The method of manufacturing a semiconductor device according to any one of claims 15 to 19,
In the step (e), a semiconductor device manufacturing method is characterized in that heat treatment is performed while the top of each second electrode is pressed against the second metal fine particle layer.
 請求項20に記載の半導体装置の製造方法において、
 前記工程(e)の前記加熱処理の温度は50℃以上で且つ200℃以下であることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 20,
The method for manufacturing a semiconductor device, wherein the temperature of the heat treatment in the step (e) is 50 ° C. or higher and 200 ° C. or lower.
 請求項15~21のいずれか1項に記載の半導体装置の製造方法において、
 前記第2の金属微粒子層を構成する前記金属微粒子の粒径は、1Å以上で且つ1μm以下であることを特徴とする半導体装置の製造方法。
The method for manufacturing a semiconductor device according to any one of claims 15 to 21,
The method of manufacturing a semiconductor device, wherein the metal fine particles constituting the second metal fine particle layer have a particle size of 1 to 1 μm.
 請求項15~22のいずれか1項に記載の半導体装置の製造方法において、
 前記第2の金属微粒子層は、前記各第1の電極及び前記各第2の電極よりも高い硬度を持つ微粒子を含むことを特徴とする半導体装置の製造方法。
The method for manufacturing a semiconductor device according to any one of claims 15 to 22,
The method for manufacturing a semiconductor device, wherein the second metal fine particle layer includes fine particles having hardness higher than that of the first electrodes and the second electrodes.
 請求項15~23のいずれか1項に記載の半導体装置の製造方法において、
 前記第2の金属微粒子層は、銅、銀及び金から構成される金属群の中から1つ若しくは2つ以上選ばれた金属の微粒子、又は当該金属群の中から選ばれた2つ以上の金属の合金の微粒子を含むことを特徴とする半導体装置の製造方法。
The method of manufacturing a semiconductor device according to any one of claims 15 to 23,
The second metal fine particle layer may be one or more metal fine particles selected from a metal group composed of copper, silver and gold, or two or more metal fine particles selected from the metal group. A method for manufacturing a semiconductor device, comprising fine particles of a metal alloy.
 請求項24に記載の半導体装置の製造方法において、
 前記第2の金属微粒子層は、銅、銀及び金のいずれの金属よりも硬度が高く且つ導電率が1×10/mΩ以上である他の金属の微粒子をさらに含むことを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 24,
The second metal fine particle layer further includes fine particles of another metal having higher hardness than any one of copper, silver, and gold and having an electric conductivity of 1 × 10 7 / mΩ or more. Device manufacturing method.
 請求項25に記載の半導体装置の製造方法において、
 前記他の金属は、タングステン、コバルト、ニッケル、ルテニウム、ロジウム、イリジウム、モリブデン及びオスミウムから構成される金属群の中から1つ若しくは2つ以上選ばれた金属、又は当該金属群の中から選ばれた2つ以上の金属の合金であることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 25,
The other metal is selected from one or more metals selected from the group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum and osmium, or selected from the group of metals. A method of manufacturing a semiconductor device, which is an alloy of two or more metals.
 請求項1~26のいずれか1項に記載の半導体装置の製造方法において、
 前記各第1の電極及び前記各第2の電極の少なくとも一方は、貫通電極の先端部であることを特徴とする半導体装置の製造方法。
In the method of manufacturing a semiconductor device according to any one of claims 1 to 26,
At least one of each said 1st electrode and each said 2nd electrode is a front-end | tip part of a penetration electrode, The manufacturing method of the semiconductor device characterized by the above-mentioned.
 請求項1~27のいずれか1項に記載の半導体装置の製造方法において、
 前記各第1の電極及び前記各第2の電極の少なくとも一方は、金属から構成されていることを特徴とする半導体装置の製造方法。
The method for manufacturing a semiconductor device according to any one of claims 1 to 27,
At least one of each said 1st electrode and each said 2nd electrode is comprised from the metal, The manufacturing method of the semiconductor device characterized by the above-mentioned.
 請求項28に記載の半導体装置の製造方法において、
 前記各第1の電極及び前記各第2の電極の少なくとも一方を構成する前記金属は、銅又は銅合金であることを特徴とする半導体装置の製造方法。
The method of manufacturing a semiconductor device according to claim 28.
The method of manufacturing a semiconductor device, wherein the metal constituting at least one of the first electrodes and the second electrodes is copper or a copper alloy.
 第1の基板と、
 前記第1の基板上に形成された複数の第1の電極と、
 第2の基板と、
 前記第2の基板上における前記第1の基板の前記各第1の電極と対応する位置に形成された複数の第2の電極とを備え、
 前記各第1の電極と当該各第1の電極に対応する前記各第2の電極とが、複数の金属微粒子が融解して一体化してなる層を介して接続されており、それによって、前記第1の基板と前記第2の基板とが積層されていることを特徴とする半導体装置。
A first substrate;
A plurality of first electrodes formed on the first substrate;
A second substrate;
A plurality of second electrodes formed on the second substrate at positions corresponding to the first electrodes of the first substrate;
The first electrodes and the second electrodes corresponding to the first electrodes are connected via a layer formed by melting and integrating a plurality of metal fine particles, whereby the A semiconductor device, wherein a first substrate and the second substrate are stacked.
 請求項30に記載の半導体装置において、
 前記複数の金属微粒子の粒径は、1Å以上で且つ1μm以下であることを特徴とする半導体装置。
The semiconductor device according to claim 30, wherein
The semiconductor device according to claim 1, wherein a particle diameter of the plurality of metal fine particles is 1 μm or more and 1 μm or less.
 請求項30又は31に記載の半導体装置において、
 前記複数の金属微粒子は、前記各第1の電極及び前記各第2の電極よりも高い硬度を持つ微粒子を含むことを特徴とする半導体装置。
The semiconductor device according to claim 30 or 31,
The semiconductor device, wherein the plurality of metal fine particles include fine particles having hardness higher than that of each of the first electrodes and each of the second electrodes.
 請求項30~32のいずれか1項に記載の半導体装置において、
 前記複数の金属微粒子は、銅、銀及び金から構成される金属群の中から1つ若しくは2つ以上選ばれた金属の微粒子、又は当該金属群の中から選ばれた2つ以上の金属の合金の微粒子を含むことを特徴とする半導体装置。
The semiconductor device according to any one of claims 30 to 32,
The plurality of metal fine particles may be one or more metal fine particles selected from a metal group composed of copper, silver, and gold, or two or more metal particles selected from the metal group. A semiconductor device comprising fine particles of an alloy.
 請求項33に記載の半導体装置において、
 前記複数の金属微粒子は、銅、銀及び金のいずれの金属よりも硬度が高く且つ導電率が1×10/mΩ以上である他の金属の微粒子をさらに含むことを特徴とする半導体装置。
The semiconductor device according to claim 33.
The plurality of metal fine particles further includes fine particles of another metal having a higher hardness than any one of copper, silver, and gold and having an electric conductivity of 1 × 10 7 / mΩ or more.
 請求項34に記載の半導体装置において、
 前記他の金属は、タングステン、コバルト、ニッケル、ルテニウム、ロジウム、イリジウム、モリブデン及びオスミウムから構成される金属群の中から1つ若しくは2つ以上選ばれた金属、又は当該金属群の中から選ばれた2つ以上の金属の合金であることを特徴とする半導体装置。
The semiconductor device according to claim 34, wherein
The other metal is selected from one or more metals selected from the group consisting of tungsten, cobalt, nickel, ruthenium, rhodium, iridium, molybdenum and osmium, or selected from the group of metals. A semiconductor device comprising an alloy of two or more metals.
 請求項30~35のいずれか1項に記載の半導体装置において、
 前記各第1の電極及び前記各第2の電極の少なくとも一方は、貫通電極の先端部であることを特徴とする半導体装置。
The semiconductor device according to any one of claims 30 to 35,
At least one of each said 1st electrode and each said 2nd electrode is a front-end | tip part of a penetration electrode, The semiconductor device characterized by the above-mentioned.
 請求項30~36のいずれか1項に記載の半導体装置において、
 前記各第1の電極及び前記各第2の電極の少なくとも一方は、金属から構成されていることを特徴とする半導体装置。
The semiconductor device according to any one of claims 30 to 36,
At least one of each said 1st electrode and each said 2nd electrode is comprised from the metal, The semiconductor device characterized by the above-mentioned.
 請求項37に記載の半導体装置において、
 前記各第1の電極及び前記各第2の電極の少なくとも一方を構成する前記金属は、銅又は銅合金であることを特徴とする半導体装置。
38. The semiconductor device according to claim 37, wherein
The semiconductor device, wherein the metal constituting at least one of the first electrodes and the second electrodes is copper or a copper alloy.
 請求項30~38のいずれか1項に記載の半導体装置において、
 前記各第1の電極は、前記第1の基板の表面から突き出るように形成されており、
 前記各第2の電極は、前記各第2の電極の上面が前記第2の基板の表面と実質的に面一になるように形成されていることを特徴とする半導体装置。
The semiconductor device according to any one of claims 30 to 38,
Each of the first electrodes is formed so as to protrude from the surface of the first substrate,
Each of the second electrodes is formed so that the upper surface of each of the second electrodes is substantially flush with the surface of the second substrate.
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