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WO2012054368A2 - Cellule solaire hybride de type multijonction comportant des nanofils en silicium alignés verticalement pourvus de films minces - Google Patents

Cellule solaire hybride de type multijonction comportant des nanofils en silicium alignés verticalement pourvus de films minces Download PDF

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Publication number
WO2012054368A2
WO2012054368A2 PCT/US2011/056508 US2011056508W WO2012054368A2 WO 2012054368 A2 WO2012054368 A2 WO 2012054368A2 US 2011056508 W US2011056508 W US 2011056508W WO 2012054368 A2 WO2012054368 A2 WO 2012054368A2
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Prior art keywords
array
nanowires
nanowire
silicon layer
layer
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WO2012054368A3 (fr
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Jun Qu
Theodore M. Besmann
Sheng Dai
Xiaoguang Zhang
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UT Battelle LLC
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UT Battelle LLC
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/17—Photovoltaic cells having only PIN junction potential barriers
    • H10F10/174—Photovoltaic cells having only PIN junction potential barriers comprising monocrystalline or polycrystalline materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/10—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material
    • H10F71/103—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/122—Active materials comprising only Group IV materials
    • H10F77/1228—Active materials comprising only Group IV materials porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/143—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies comprising quantum structures
    • H10F77/1437—Quantum wires or nanorods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/148—Shapes of potential barriers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a photovoltaic device, and particularly to a photovoltaic device including semiconductor nanowires, and methods of manufacturing the same.
  • the majority of solar photovoltaic modules are silicon-based.
  • Conventional solar cells are single junction devices in which the junction extends over a large planar region and formed in a high qualify single crystalline silicon substrate. Fabrication of such solar cells requires high production costs and energy inputs.
  • photovoltaic devices can be formed at a substantially reduced production cost by employing a thin amorphous silicon film deposited over a large area at a low temperature or even room temperature via plasma enhanced physical vapor deposition (PECVD).
  • PECVD plasma enhanced physical vapor deposition
  • enhancements in photovoltaic properties include high carrier-collection efficiency due to short transport distances, high optical absorptance for medium- to high- frequency photon energy, and very low reflectance.
  • the optical absorptance for coaxial silicon nanowires can be greater than 0.95, which is significantly higher than optical absorptance about 0.4 - 0.6 for conventional thin films, and the reflectance for the coaxial silicon nanowires can be less than 0.1, which is significantly less than the reflectance about 0.4 - 0.6 for the conventional thin films.
  • High- aspect-ratio nanowires allow the use of a sufficient thickness of material to obtain good optical absorption while simultaneously providing short collection lengths for excited carriers in a direction normal to the light absorption.
  • the short collection lengths facilitate the efficient collection of photogenerated carriers in materials with low minority-carrier diffusion lengths.
  • the contact resistance can be particularly high for the coaxial silicon nanowire configuration because both the core and shell are connected with the current collectors on their "tiny" ends yielding a very small contact area.
  • VLS vapor-liquid-solid
  • PLD pulsed laser deposition
  • CVD chemical vapor deposition
  • Metallic nanoparticles such as gold nanoparticles are usually used as catalysts.
  • the metallic nanoparticles are potential contaminants resulting in increased carrier recombination within the wires impairing cell performance.
  • the nanowires produced are usually not aligned well.
  • the minimal contact area with the substrate makes the conventional nanowires vulnerable to pull-off by mechanical stress, e.g., wind and vibration, and/or thermomechanical stress, e.g., mismatch of thermal expansion coefficients between silicon nanowires and substrate, experienced in actual operation environments.
  • a low-cost method for forming a photovoltaic device, which is a high- performance nanostructured multijunction cell.
  • the multiple P-N junctions or P-I-N junctions are contiguously joined to form a single contiguous P-N junction or a single contiguous P-I-N junction.
  • the photovoltaic device integrates vertically-aligned semiconductor nanowires including a doped semiconductor material with a thin silicon layer having an opposite type of doping. This novel hybrid cell can provide a higher efficiency than conventional photovoltaic devices through the combination of the enhanced photon absorptance, reduced contact resistance, and short carrier transport paths in the nanowires.
  • Room temperature processes or low temperature processes such as plasma-enhanced chemical vapor deposition (PECVD) and electrochemical processes can be employed for fabrication of this photovoltaic device in a low- cost, scalable, and energy-efficient manner.
  • PECVD plasma-enhanced chemical vapor deposition
  • electrochemical processes can be employed for fabrication of this photovoltaic device in a low- cost, scalable, and energy-efficient manner.
  • the method includes: providing a substrate including a silicon layer having a first conductivity type doping; forming an array of nanopores in the silicon layer by anodization; and forming a nanowire-including structure by depositing at least a doped semiconductor material having a second conductivity type in the array of nanopores, wherein the nanowire-including structure includes an array of nanowires filling the array of nanopores and a doped semiconductor layer, the doped semiconductor layer is attached to the array of nanowires and includes at least a portion of the doped semiconductor material, and the second conductivity type is the opposite of the first conductivity type.
  • a photovoltaic structure which includes: a silicon layer having a first conductivity type doping; and a nanowire-including structure including at least a doped semiconductor material having a second conductivity type, wherein the nanowire-including structure includes an array of nanowires and a doped
  • the array of nanowires is embedded in the silicon layer
  • the doped semiconductor layer is attached to the array of nanowires and includes at least a portion of the doped semiconductor material
  • the second conductivity type is the opposite of the first conductivity type
  • FIG. 1 is a schematic view of a first exemplary structure including a silicon layer having a doping of a first conductivity type according to a first embodiment of the present disclosure.
  • FIG. 2 is a schematic view of the first exemplary structure after formation of nanopores in the silicon layer according to the first embodiment of the present disclosure.
  • FIG. 3 is a magnified view of a nanopore in FIG. 2.
  • FIG. 4 is a scanning electron micrograph (SEM) of a cleaved porous single-crystalline silicon material as known in prior art.
  • FIG. 5 is a schematic view of the first exemplary structure after formation of a nanowire- including structure containing a doped semiconductor material having a doping of a second conductivity type according to the first embodiment of the present disclosure.
  • FIG. 6 is a magnified view of a nanowire in FIG. 5.
  • FIG. 7 is a schematic view of the first exemplary structure after formation of a second conductive material layer according to the first embodiment of the present disclosure.
  • FIG. 8 is a schematic view of a second exemplary structure after formation of an intrinsic semiconductor material layer according to a second embodiment of the present disclosure.
  • FIG. 9 is a schematic view of the second exemplary structure after formation of a nanowire-including structure containing a doped semiconductor material having a doping of the second conductivity type and the intrinsic semiconductor material according to the second embodiment of the present disclosure.
  • FIG. 10 is a magnified view of a nanowire in FIG. 9.
  • FIG. 11 is a schematic view of the second exemplary structure after formation of a second conductive plate according to the second embodiment of the present disclosure.
  • FIG. 12 is a graph illustrating voltage profiles along a nanowire axis for cylindrical and conical nanowires.
  • FIG. 13 is a graph showing the results of a simulation for the electrostatic potential of a nanowire as a function of wire geometry Detailed Description of the Invention
  • the present invention relates to a photovoltaic device including semiconductor nanowires, and methods of manufacturing the same, which are now described in detail with accompanying figures. It is noted that like and corresponding elements mentioned herein and illustrated in the drawings are referred to by like reference numerals. It is also noted that proportions of various elements in the accompanying figures are not drawn to scale to enable clear illustration of elements having smaller dimensions relative to other elements having larger dimensions.
  • room temperature refers to a temperature in a range from 15 °C to 40 °C.
  • a "nanopore” is a pore that has a lateral dimension that does not exceed 1,000 nm.
  • a “nanowire” is a structure that has a lengthwise dimension along a lengthwise direction, wherein the lengthwise dimension is at least an order of magnitude greater than a maximum lateral dimension in directions perpendicular to the lengthwise direction, and the maximum lateral dimension does not exceed 1,000 nm.
  • a “nanothread” is a nanowire that does not include any laterally protruding structures in any direction that is different from a lengthwise direction.
  • a direction is “substantially vertical” if the direction deviates from a vertical direction by no more than 2 degrees.
  • a unique photovoltaic structure includes a hybrid nanostructured multijunction photovoltaic device, which combines a thin planar semiconductor film structure with vertically- aligned semiconductor nanowires.
  • the hybrid nanostructured multijunction photovoltaic device includes a P-N junction or a P-I-N junction on a surface of the thin planar semiconductor film and a plurality of P-N junctions or a plurality of P-I-N junctions on surfaces of the vertically- aligned semiconductor nanowires.
  • All P-N junctions in the hybrid nanostructured multijunction photovoltaic device are contiguously connected to one another to constitute a single contiguous P-N junction or a single contiguous P-I-N junction.
  • This photovoltaic structure substantially enhances energy conversion efficiency above the energy conversion efficiency of either a thin film solar cell or a nanowires cell.
  • This photovoltaic structure can be fabricated at relatively low cost. A non-limiting exemplary method of forming this photovoltaic structure is illustrated by the schematic views illustrated in FIGS. 1, 2, 3, 5, 6, 7, 8, 9, 10, and 11.
  • a first exemplary structure includes a substrate, which includes a silicon layer 20 having a first conductivity type and a first conductive material layer 10.
  • the substrate can consist of a stack of the first conductive material layer 10 and the silicon layer 20, or can further include at least another layer located at the bottom of the first conductive material layer 10 such as a dielectric substrate (such as a glass substrate or any other dielectric substrate) or another conductive material layer.
  • the first conductive material layer 10 can be a metallic layer including a metallic material.
  • the metallic material can be aluminum, copper, or any other elemental metal or a conductive metallic alloy.
  • the first conductive material layer 10 is a first conductive plate that functions as a first electrode of a photovoltaic device to be formed.
  • the silicon layer 20 includes silicon and at least one dopant having the first conductivity type.
  • the first conductivity type can be p-type or n-type.
  • P-doped silicon material can be formed by doping silicon with a p-type dopant such as B, Al, Ga, and/or In.
  • N-doped silicon material can be formed by doping silicon with an n-type dopant such as P, As, and/or Sb.
  • the silicon layer 20 can have the same constant thickness throughout.
  • the silicon layer 20 can include amorphous or polycrystalline hydrogenated silicon having a doping of the first conductivity type, which can be deposited, for example, by plasma enhanced chemical vapor deposition (PECVD), low temperature chemical vapor deposition (LPCVD), physical vapor deposition (PVD, i.e., sputtering), or by any other suitable deposition methods known in the art.
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low temperature chemical vapor deposition
  • PVD physical vapor deposition
  • sputtering physical vapor deposition
  • Hydrogen present in an amorphous or polycrystalline hydrogenated silicon film has the effect of passivating dangling bonds of silicon atoms, and de-localizing the electronic states caused by the dangling bonds of the silicon atoms, thereby enhancing the conductivity of the amorphous or polycrystalline hydrogenated silicon film over an amorphous or polycrystalline silicon film without hydrogen.
  • the silicon layer 20 can be deposited directly on the conductive metal layer 10 so that the conductive metal layer 10 contacts the silicon layer 20.
  • the thickness of the silicon layer 20 can be from 1 micron to 1,000 microns, although lesser and greater thicknesses can also be employed.
  • the silicon layer 20 can include an n-type amorphous silicon thin film including phosphorus as n-type dopants and be deposited on a metal plate including aluminum or stainless steel by PECVD.
  • a silicon- containing reactant gas such as SitU and an n-type dopant gas such as PH 3 can be employed for the PECVD process. Because plasma provides energy to the reactant gas and the dopant gas, it is generally unnecessary to elevate the temperature of the metal plate to deposit the silicon layer 20.
  • the process parameters for the PECVD process can be tailored to achieve the desired film thickness and dopant concentration for the silicon layer 20.
  • the silicon layer 20 can include single crystalline silicon.
  • the silicon layer 20 can have any crystallographic orientation.
  • the silicon layer 20 can have one of the major crystallographic orientations along which formation of nanapores is accelerated during anodization.
  • the stack of the first conductive material layer 10 and the silicon layer 20 can be formed by depositing the first conductive material layer 10 on a substrate including the silicon layer 20 that includes single crystalline silicon having a doping of the first conductivity type, or can be formed by transferring the silicon layer 20 that includes single crystalline silicon having a doping of the first conductivity type, for example, by wafer bonding.
  • the thickness of the silicon layer 20 can be from 1 micron to 1,000 microns, although lesser and greater thicknesses can also be employed.
  • an array of nanopores 22 is formed in the silicon layer 20 by anodization. It is known that an array of nanopores 22 can be formed in a silicon layer by anodization. Specifically, the nanopores 22 can be formed with vertical alignment in the silicon layer 20 by an electrochemical anodization process in a HF-containing solution under suitable conditions. The anodization process for producing vertically aligned nanopores in the silicon layer 20 is an etch process.
  • the anodization process requires a specific match among processing parameters, i.e., among the HF-concentration in an aqueous etchant, the dopant concentration in the silicon layer 20, and the current density during the anodization process, in order to form the vertically aligned nanopores successfully.
  • FIG. 4 a scanning electron micrograph (SEM) of a cleaved porous n-doped single crystalline silicon sample is shown as reported in P. Granitzer, K. Rump, and H. Krenn, "Nanomagnetic Ni- Array in Porous Silicon as a Possible Magnetic Field Sensor in the High Field Range up to 7 T," Mater. Res. Soc. Symp. Proc, 876E (2005) R8.9.1-5.
  • the array of nanopores can have a "fir tree" configuration, which includes a primary trench and a plurality of ancillary trenches extruding from the primary trench.
  • the primary trench extends from the top to the bottom of each nanopore, and each of the ancillary trenches extends a short distance and typically has a smaller lateral dimension than the primary trench.
  • the ancillary trenches extend a distance that is less than 1/10, and typically less than 1/100, of the length of the primary trench.
  • the silicon layer 20 as anodized can include nanopores 22 with porosity ranging from about 30 % to about 80 %, i.e., the volume of the nanopores can be from about 30 % to 80 % of the original volume of silicon before anodization.
  • the nanopores can be branched and exhibit a very characteristic "fir tree" configuration known in the art.
  • structures having high porosity can be formed employing a single crystalline silicon layer.
  • the silicon layer 20 can be heat-treated after formation of the nanopores 22 to induce significant migration of silicon atoms and to substantially increase feature sizes as needed.
  • the lateral dimensions of the nanopores 22 can be increased up to 1,000 nm if desired.
  • the nanopores 22 can have a fir tree configuration, in which each nanopore 22 includes a primary trench 22P and a plurality of ancillary trenches 22A extruding from the primary trench 22P.
  • the ancillary trenches 22 are also referred to as "side pockets,” and have a length that is at least one order of magnitude less than the depth of a nanopore 22, i.e., the length of the primary trench 22P in the nanopore 22.
  • ancillary trenches 22 have a length that is at least two orders of magnitude less than the depth of the nanopore 22.
  • the silicon layer 20 has a planar top surface 20T from which the array of nanopores 22 extends into the silicon layer 20.
  • the distal ends, i.e., the pointy ends that do not adjoin a primary trench 22P, of the plurality of ancillary trenches 22A generally point away from the opening 220 of the primary trench 22P.
  • first elements generally points away from a second element if more than 90 % of the first elements point away from the second element.
  • the lengthwise direction of each nanopore 22 can be substantially vertical.
  • the lengthwise direction of a primary trench 22P therein can be substantially perpendicular to the planar top surface 20T of the silicon layer 20.
  • the anodization process can be performed in an aqueous hydrofluoric acid, and nanopores 22 in the array of nanopores are laterally spaced from one another.
  • the nanopores 22 in the array of nanopores can have a vertical dimension from 1 micron to 100 micron, although lesser and greater vertical dimensions can also be employed.
  • the nanopores 22 in the array of nanopores can have a maximum lateral dimension from 5 nm to 1,000 nm, although lesser and greater maximum lateral dimensions can also be employed.
  • the depth of the nanopores 22 depends on the etching time, i.e., the duration of the anodization process, and can be from 1 micron to 1,000 microns.
  • an n-type hydrogen-containing amorphous silicon film can be employed for the silicon layer 20, which is anodized in an aqueous HF acid solution to generate a high-density array of vertically- aligned nanopores.
  • the nanopores 22 extend vertically into the silicon layer 20, but does not reach the first conductive material layer 10 so that a P-N junction or a P-I-N junction to be subsequently formed is not electrically shorted to the first conductive material layer 10.
  • porous silicon can be formed by electrolytic anodization in a solution containing HF.
  • An HF-resistant electrode such as one made of platinum, is biased negatively, and a substrate including amorphous, microcrystalline, or single-crystalline silicon is biased positively.
  • the porosity, measured in terms of the mass loss, of the resulting porous silicon layer is typically proportional to the electrical current density and inversely proportional to the HF concentration.
  • the depth of the resulting porous silicon layer formed within a region of silicon can be proportional to the anodization time for a given dopant concentration and current density.
  • the actual structure of the porous silicon material depends on the type and
  • porous silicon materials A common characteristic of porous silicon materials is the enormous surface area associated with high-density pores.
  • the total surface area per unit volume in a porous silicon material is estimated to be 100 - 200 m 2 /cm 3 , i.e., 100-200 square meters of surface area per each cubic centimeter in volume.
  • the concentration of the hydrofluoric acid solution can be about 10 % in weight percentage
  • the current density can be about 100 mA/cm 2
  • the dopant concentration in the silicon layer 20 can be from about 10 /cm to about 10 /cm .
  • the porous silicon structure in the silicon layer 20 can be tailored with different morphologies. For dopant concentrations greater than 10 17 /cm 3 , the growth mechanism of the nanopores is controlled by a charge transfer through band-to-band tunneling of charge carriers across the space charge region.
  • the porous silicon structure can include highly oriented nanopores in a rectangular array, which is a different arrangement from honeycomb structures of pores formed in anodic alumina.
  • a nanowire-including structure is formed by depositing a doped semiconductor material in the array of nanopores 22 and on the planar top surface 20T of the silicon layer 20.
  • the nanowire-including structure is an integral assembly, i.e., an assembly of a single contiguous construction, of a doped semiconductor layer 40L and an array of nanowires 40N.
  • the doped semiconductor material layer 40L is planar and has the same thickness throughout. As such, the doped semiconductor material layer 40L is a planar doped semiconductor portion having a constant thickness.
  • the integral assembly of the doped semiconductor layer 40L and the array of nanowires 40N is herein referred to as a doped nanowire-including structure 40, which constitutes the entirety of the nanowire-including structure.
  • the doped semiconductor material has a doping of a second conductivity type, which is the opposite of the first conductivity type.
  • the first conductivity type is p-type
  • the second conductivity type is n-type, and vice versa.
  • the silicon layer 20 is a p-doped silicon layer
  • the doped nanowire-including structure 40 is n-doped, and vice versa.
  • the dopant concentration of the doped nanowire-including structure 40 can be from 1.0 x 10 16 /cm 3 to 1.0 x
  • the array of nanowires 40N fills the array of nanopores 22 (See FIGS. 2 and 3) and includes portions of the deposited doped semiconductor material.
  • the doped semiconductor layer 40L is attached to the array of nanowires and includes another portion of the doped semiconductor material. Because the array of nanowires 40N and the doped semiconductor layer 40L are formed simultaneously in a same deposition process, the array of nanowires 40N and the doped semiconductor layer 40L have the same composition.
  • the doped semiconductor material can be amorphous or polycrystalline, and has a doping of the second conductivity type, i.e., includes dopant atoms having the second conductivity type.
  • the doped semiconductor material of the doped nanowire-including structure 40 can include silicon, germanium, a silicon- containing alloy that may contain carbon or germanium, a germanium-containing alloy that may contain carbon or silicon, and/or a compound semiconductor material.
  • the doped semiconductor material can be a hydrogenated semiconductor material in which the hydrogen atoms reduce the dangling bonds of semiconductor atoms therein.
  • the array of nanowires 40N filling the array of nanopores 22 also has a fir tree configuration.
  • the array of nanowires 40N includes a primary nanothread 40P and a plurality of ancillary nanothreads 40A extruding from the primary nanothread 40P.
  • the array of nanowires 40N extends from interface between the silicon layer 20 and the doped semiconductor layer 40L the into the silicon layer 20.
  • the interface between the silicon layer 20 and the doped semiconductor layer 40L is the same as the planar top surface 20T of the silicon layer 20.
  • Distal ends of the plurality of ancillary nanothreads 40A generally point away from the interface between the silicon layer 20 and the doped semiconductor layer 40L.
  • the doped semiconductor layer 40L and the array of nanowires 40N can be deposited by an electrodeposition process employing a non-aqueous solvent, a
  • the non-aqueous solvent can be an ionic liquid.
  • Chemistry for the electrodeposition can be selected to deposit the doped semiconductor layer 40L and the array of nanowires 40N at room temperature, although electrodeposition processes at temperatures higher or lower than the room temperature can also be employed.
  • the doped semiconductor material is deposited directly on surfaces of the array of nanopores 22 in the silicon layer 20 and directly on the planar top surface 20T of the silicon layer 20.
  • a doped semiconductor material can be any suitable semiconductor material.
  • a doped semiconductor material can be any suitable semiconductor material.
  • the doped semiconductor material is p-doped if the silicon layer is n-doped, and vice versa. Electrodeposition of the doped silicon material can be effected at room temperature employing ionic liquid electrolytes. Ionic liquids are composed solely of cations and anions, and yet are liquids at room temperature. Ionic liquids can offer a large
  • germanium or silicon nanowires were demonstrated employing an ionic liquid, which was 1 -butyl- 1 -methylpyrrolidinium bis(trifluoromethylsulfonyl)imide ([Pyl,4]Tf2N).
  • the ionic liquid contained GeCl 4 or SiCl 4 as solutes, and commercially available track-etched polycarbonate membranes (a non-semiconductor material) having a nominal pore diameter from 90 nm to 400 nm were used as templates.
  • a deposition rate for amorphous silicon was estimated to be about 2 - 3 microns per hour in R. Al-Salman et al.
  • the doped semiconductor material can be p-doped silicon, p-doped germanium, or a p-doped silicon-germanium alloy, and the silicon layer 20 can have an n-type doping.
  • the array of nanowires 40N includes p-type silicon nanowires, which grow inside the array of nanopores 22 located in the silicon layer 20, which is an n-type film.
  • the growth of the array of nanowires 40N can be effected by electrodeposition in an ionic liquid electrolyte dissolving a silicon salt such as SiCl 4 and a dopant source such as AICI3.
  • the ionic liquid employed for the non-aqueous solvent can be 1 -butyl- 1- methylpyrrolidinium bis(trifluoromethylsulfonyl)imide.
  • the semiconductor-element-containing ionic liquid electrolyte can include at least one of SiCl 4 and GeCl 4 .
  • the dopant-containing electrolyte can be A1C1 3 .
  • the species for the semiconductor-element-containing ionic liquid electrolyte and the dopant-containing electrolyte may be replaced with appropriate substitute electrolytes to provide a doped semiconductor material including a different semiconductor material and/or a different p-type or n-type dopant.
  • the electrodeposition method of the present disclosure provides an enhanced deposition rate compared with the method of R. Al-Salman et al. Since the p-type silicon material is deposited simultaneously on the bottom surfaces and sidewalls of the nanopores 22 in the silicon layer 20, the growth rate of the nanowires 40N according to the present disclosure is much greater than the growth rate of silicon or germanium in PC membranes as reported in R. Al- Salman et al, in which the growth proceeds only from the bottom surfaces of the PC membranes that act as a template.
  • each nanowire 40N may include a seam 40S along the lengthwise direction of the nanowire 40N.
  • the length of the seam 40S in each nanowire 40N is less than the entire length of the nanowire 40N, but differ from the entire length of the nanowire 40N only by a dimension on the order of the maximum lateral dimension of the nanowire 40N.
  • the electrodeposition method of the present disclosure provides deposition of the doped semiconductor material directly on a semiconductor material, i.e., the semiconductor material on the surfaces of the nanopores 22 in the silicon layer 20 and the planar top surface 20T of the silicon layer 20.
  • the method of R. Al-Salman et al. deposits a silicon material on a dielectric surface, i.e., the surface of a polycarbonate matrix comprising a dielectric polymer.
  • each nanopore 22 in the silicon layer 20 is filled with a semiconductor nanowire having a doping of the opposite type of doping as the silicon layer 20.
  • Each region around an interface between a nanowire 40N and the silicon layer 20 forms a P-N junction.
  • the nanowires 40N form a vertically aligned array in which the lengthwise direction of each nanowire 40N is substantially parallel to one another, an array of substantially vertical P-N junctions is formed across the silicon layer 20 and the array of nanowires 40N.
  • a planar P-N junction is formed at the planar interface between the planar top surface 20T of the silicon layer 20 and a planar bottom surface of the doped semiconductor layer 40L.
  • the planar P-N junction and the array of substantially vertical P-N junctions around the array of nanowires 40N collectively constitute a single contiguous P-N junction.
  • the contiguous P-N junction is formed between the silicon layer 20 and an assembly of the array of nanowires 40N and the doped semiconductor layer 40L.
  • the array of nanowires 40N consists of portions of the doped semiconductor material having a doping of the second conductivity type.
  • a nanowire 40N has a maximum lateral dimension of about 50 nm and an adjacent pair of nanowires 40N is laterally spaced by a distance of about 100 nm, about 100 million substantially vertical P-N junctions are formed on a 1 mm 2 planar surface area.
  • a high-density substantially vertical nanowire P-N junction array is embedded in the silicon layer 20.
  • the substantially vertical nanowire P-N junction array has the benefit of decoupling the absorption of light from charge transport by allowing lateral diffusion of minority carriers to the substantially vertical P-N junctions, which are nanometers away rather than many microns away as in conventional silicon cells.
  • This hybrid multijunction cell is also expected to combine the photon absorptance of the thin film (in the form of the doped semiconductor layer 40L and an upper portion of the silicon layer 20) and the photon
  • the absorptance of the photovoltaic device employing the silicon layer 20 and the doped nanowire-including structure 40 is greater than the absorptance of a thin film solar cell or the absorptance of a solar cell employing only an array of nanowires.
  • the electrodeposition process of the present disclosure for depositing semiconductor nanowires inside an array of nanopores is a new process, and as such, requires a systematic designing and fine tuning of the process parameters to achieve fast uniform growth and avoid porosity in the semiconductor nanowire.
  • a semiconductor material is deposited on all exposed semiconductor surfaces including the bottom surfaces and the sidewalls of the nanopores 22 as well as on the top planar surface of the silicon layer 20. Since the deposition rate is greater at a location with less potential drop (lower resistance), the growth of the semiconductor nanowires can be a bottom-up fill process that follows the electrical resistance profile. However, an imperfect geometry of nanopores may cause interrupts in the fill process, resulting in at least one seam 40S.
  • a narrower section in the middle of a nanopore 22 may produce an early seal that traps unwanted electrolytes therein. Reducing the aspect ratio and/or creating conic shape nanopores (lesser lateral dimensions at the bottom of the nanopores) can alleviate this issue.
  • a second conductive material layer 50 is formed on a planar top surface of the doped semiconductor layer 40L.
  • the second conductive material layer 50 can include a transparent conductive oxide material.
  • Exemplary transparent conductive oxide materials include, but are not limited to, indium tin oxide ( ⁇ ) and zinc oxide.
  • the second conductive material layer 50 is a second conductive plate that functions as a second electrode of the photovoltaic device of the present disclosure.
  • a second exemplary structure according to a second embodiment of the present disclosure is derived from the first exemplary structure of FIGS. 2 and 2 A by depositing an intrinsic semiconductor material layer 30 directly on surfaces of the array of nanopores 22 and the planar top surface 20T of the silicon layer 20.
  • the intrinsic semiconductor material layer 30 includes an intrinsic semiconductor material.
  • the intrinsic semiconductor material in the intrinsic semiconductor material layer can include silicon, germanium, a silicon-containing alloy that may contain carbon or germanium, a germanium-containing alloy that may contain carbon or silicon, and/or a compound
  • the intrinsic semiconductor material can be a hydrogenated semiconductor material in which the hydrogen atoms reduce the dangling bonds of
  • the intrinsic semiconductor material layer 30 can be deposited by an electrodeposition process employing a non-aqueous solvent and the semiconductor-element-containing electrolyte without employing any dopant-containing electrolyte.
  • the non-aqueous solvent employed for electrodeposition of the intrinsic semiconductor material layer 30 can be the same as the non-aqueous solvent employed for electrodeposition of the doped nanowire-including structure 40 illustrated in FIGS. 5 and 6.
  • the intrinsic semiconductor material layer 30 is deposited as a single contiguous layer without any hole therein.
  • the intrinsic semiconductor material layer 30 includes an array of intrinsic nanowire shells 30N and a planar intrinsic semiconductor portion 30L.
  • the array of intrinsic nanowire shells 30N include portions of the intrinsic semiconductor material layer 30 located within, and partially filling, the array of nanopores 22.
  • the array of intrinsic nanowire shells 30N is located below a top planar surface 20T (See FIG. 3) of the silicon layer 20.
  • the planar intrinsic semiconductor portion 30L is a planar portion of the intrinsic semiconductor material layer 30 and contacts the planar top surface 20T (See FIG. 3) of the silicon layer 20.
  • the planar intrinsic semiconductor portion 30L has a constant thickness throughout. The thickness of the intrinsic semiconductor material layer 30 is less than half the nominal lateral dimension of each nanopore 22, so that the nanopores 22 are not filled by the intrinsic semiconductor material layer 30.
  • the electrodeposition process to form the doped nanowire-including structure 40 at a processing step corresponding to FIGS. 5 and 6 in the first embodiment can be employed to form the intrinsic semiconductor material layer 30 provided that any dopant-containing electrolyte is removed from the electrodeposition chemistry and the processing time is shortened appropriately.
  • the intrinsic semiconductor material layer 30 is deposited simultaneously on the bottom surfaces and sidewalls of the nanopores 22 and directly on the doped silicon material on all surfaces of the nanopores 22 in the silicon layer 20.
  • the thickness of the intrinsic semiconductor material layer 30 can be from 5 nm to 100 nm, although lesser and greater thicknesses can also be employed.
  • a doped semiconductor material is deposited employing the same processing step as the processing step of FIGS. 5 and 6 according to the first embodiment.
  • the doped semiconductor material is deposited directly on exposed surfaces of the intrinsic semiconductor material layer 30. Further, the doped semiconductor material is deposited simultaneously on all exposed bottom surfaces and sidewalls of the intrinsic semiconductor material layer 30 in the nanopores 22.
  • the portions of the doped semiconductor material filling the array of nanopores 22 form an array of doped nanowire cores 40C.
  • the planar portion of the doped semiconductor material located above the top surface of the planar intrinsic semiconductor portion 30L form a doped semiconductor layer 40L.
  • a pair of a doped nanowire core 40C and an intrinsic nanowire shell 30N filling the same nanopore 22 collectively form a nanowire (40C, 30N).
  • the stack of the planar intrinsic semiconductor portion 30L and the doped semiconductor layer 40L collectively form a planar semiconductor material stack having a constant total thickness.
  • a nanowire-including structure of the second embodiment includes an array of nanowires (40C, 30N), the planar intrinsic semiconductor portion 30L, and the doped semiconductor layer 40L.
  • An array of doped nanowire cores 40C and the doped semiconductor layer 40L is of integral construction without any interface therein.
  • An array of intrinsic nanowire shells and the planar intrinsic semiconductor portion 30L is of integral construction without any interface therein.
  • the array of nanowires (40C, 30N) fills the array of nanopores 22 (See FIGS. 2 and 3).
  • Each nanowire (40C, 30N) includes a doped nanowire core 40C and an intrinsic nanowire shell 30N embedding and spacing the doped nanowire core 40C from the silicon layer 20. Because the array of doped nanowire cores 40C and the doped semiconductor layer 40L are formed simultaneously in a same deposition process, the array of doped nanowire cores 40C and the doped semiconductor layer 40L have the same composition.
  • the doped semiconductor material can be amorphous or polycrystalline, and has a doping of the second conductivity type, i.e., includes dopant atoms having the second conductivity type.
  • the doped semiconductor material of the array of doped nanowire cores 40C and the doped semiconductor layer 40L can include silicon, germanium, a silicon-containing alloy that may contain carbon or germanium, a germanium-containing alloy that may contain carbon or silicon, and/or a compound
  • the doped semiconductor material can be a hydrogenated
  • the array of doped nanowire cores 40C and the doped semiconductor layer 40L of the second embodiment can have the same composition as the array of nanowires 40N and the doped semiconductor layer 40L of the first embodiment, and can be formed by employing the same processing step employed to form the array of nanowires 40N and the doped semiconductor layer 40L in the first embodiment.
  • the array of nanowires (40C, 30N) filling the array of nanopores 22 also has a fir tree configuration.
  • the array of nanowires (40C, 30N) includes a primary nanothread 40P and a plurality of ancillary nanothreads 40A extruding from the primary nanothread 40P.
  • a primary nanothread 40P includes most of a doped nanowire core 40C and a significant portion of an intrinsic nanowire shell 30N filling a same nanopore 22.
  • An ancillary nanothread 40A typically includes only a portion of the intrinsic nanowire shell 30N, although the ancillary nanothread 40A may include a portion of the doped nanowire core 40C in some cases (if the size of an ancillary trench 22A is significant; See FIG. 3).
  • the array of nanowires (40C, 30N) extends from interface between the silicon layer 20 and the planar intrinsic semiconductor portion 30L the into the silicon layer 20.
  • the interface between the silicon layer 20 and the planar intrinsic semiconductor portion 30L is the same as the planar top surface 20T of the silicon layer 20.
  • Distal ends of the plurality of ancillary nanothreads 40A generally point away from the interface between the silicon layer 20 and the planar intrinsic semiconductor portion 30L.
  • the growth rate of the doped nanowire cores 40C according to the present disclosure is much greater than the growth rate of silicon or germanium in PC membranes as reported in R. Al-Salman et ai, in which the growth proceeds only from the bottom surfaces of the PC membranes that act as a template. Further, because the bottom surfaces of the intrinsic nanowire shell 30N have a shorter distance to the first conductive material layer 10 that functions as an electrode than sidewalls of the intrinsic nanowire shell 30N, the bottom surfaces of the intrinsic nanowire shell 30N are in the paths of the least electrical resistance during the electrodeposition process.
  • each doped nanowire cores 40C may include a seam 40S along the lengthwise direction of the doped nanowire cores 40C.
  • the length of the seam 40S in each doped nanowire cores 40C is less than the entire length of the doped nanowire cores 40C, but differ from the entire length of the doped nanowire cores 40C only by a dimension on the order of the maximum lateral dimension of the doped nanowire cores 40C.
  • the electrodeposition method employed to form the array of doped nanowire cores 40C and the doped semiconductor layer 40L provides deposition of the doped semiconductor material directly on a semiconductor material, i.e., the semiconductor material on the surfaces of the intrinsic semiconductor material layer 30.
  • Ionic liquid-based electrolytes with unique large electrochemical windows may offer more flexibility in terms of selecting the size, the spacing, and the depth of the nanopores 22 during the anodization process illustrated in FIGS. 2 and 3.
  • each nanopore 22 in the silicon layer 20 is filled with a semiconductor nanowire having a doping of the opposite type of doping as the silicon layer 20.
  • Each nanowire (40C, 30N) in the array of nanowires includes a doped nanowire core 40C embedded in an intrinsic nanowire shell 30N.
  • the doped nanowire core 40C includes the doped semiconductor material
  • the intrinsic nanowire shell 30N includes the intrinsic semiconductor material.
  • Each region around an interface between a nanowire (40C, 30N) and the silicon layer 20 forms a P-I-N junction.
  • the nanowires (40C, 30N) form a vertically aligned array in which the lengthwise direction of each nanowire (40C, 30N) is substantially parallel to one another, an array of substantially vertical P-I-N junctions is formed across the silicon layer 20 and the array of nanowires (40C, 30N). Further, a planar P-I-N junction is formed across all portions of the planar intrinsic semiconductor portion 30L. The planar P-I-N junction and the array of substantially vertical P-I-N junctions around the array of nanowires (40C, 30N) collectively constitute a single contiguous P-I-N junction.
  • the contiguous P-I- N junction is formed between the silicon layer 20 and an assembly of the array of nanowires (40C, 30N) and the doped semiconductor layer 40L.
  • the array of nanowires (40C, 30N) includes portions of the doped semiconductor material having a doping of the second conductivity type, i.e., the array of the doped nanowire cores 40C, and portions of the intrinsic semiconductor material, i.e., the array of the intrinsic nanowire shells 30N.
  • the intrinsic semiconductor layer 30 forms the intrinsic portion of the contiguous P-I-N junction.
  • a nanowire (40C, 30N) has a maximum lateral dimension of about 50 nm and an adjacent pair of nanowires (40C, 30N) is laterally spaced by a distance of about 100 nm, about 100 million substantially vertical P-I-N junctions are formed on a 1 mm 2 planar surface area.
  • a high-density substantially vertical nanowire P-I-N junction array is embedded in the silicon layer 20.
  • the substantially vertical nanowire P-I-N junction array has the benefit of decoupling the absorption of light from charge transport by allowing lateral diffusion of minority carriers to the substantially vertical P-I-N junctions, which are nanometers away rather than many microns away as in conventional silicon cells.
  • the hybrid multij unction cell of the second embodiment is also expected to combine the photon absorptance of the thin film (in the form of the doped semiconductor layer 40L, the planar intrinsic semiconductor portion 30L, and an upper portion of the silicon layer 20) and the photon absorptance of the array of nanowires (40C, 30N) and the portions of the silicon layer 20 that laterally surround the array of nanowires (40C, 3 ON).
  • FIG. 8 and FIGS. 9 and 10 can be integrated into a single electrodeposition step, in which a dopant electrolyte is added to the non-aqueous solution at the beginning of the electrodepositon of the doped semiconductor material, i.e., at the beginning of the processing step corresponding to FIGS. 9 and 10.
  • a semiconductor material can be electrodeposited without a dopant for a first period of time to form the intrinsic semiconductor layer 30 in the outer portion of the nanopores 22, followed by filling of the nanopores 22 with the doped semiconductor material.
  • the thickness of the intrinsic semiconductor layer 30 in the outer portion of the nanopores 22
  • semiconductor layer 30 can be adjusted by controlling the timing of the addition of a dopant- containing electrolyte.
  • the addition of the intrinsic semiconductor layer 30 between the silicon layer 20 having a doping of the first conductivity type and the doped semiconductor material having a doping of the second conductivity type can enhance the performance of the photovoltaic device.
  • a second conductive material layer 50 can be formed employing the same processing step as in FIG. 7 of the first embodiment.
  • the hybrid photovoltaic device of the present disclosure can eliminate or reduce the high contact resistance problem for prior art photovoltaic devices that employ nanowires directly grown on an electrode.
  • semiconductor nanowires i.e., nanowires 40N in the first embodiment or nanowires (40C, 3 ON) in the second embodiment
  • the large contact area between the silicon layer 20 and the first electrode, i.e., the first conductive material layer 10 provide low contact resistance on one side.
  • the large contact area between the doped semiconductor layer 40L and the second electrode, i.e., the second conductive material layer 50 provide low contact resistance on the other side.
  • Performance of the hybrid photovoltaic device of the present disclosure can be enhanced by optimizing the dimensional parameters of semiconductor nano wires (i.e., nanowires 40N in the first embodiment or nanowires (40C, 30N) in the second embodiment).
  • Such dimensional parameters include the maximum lateral dimension (e.g., diameter), the length, and the spacing of the semiconductor nanowires, the dopant concentrations in the silicon layer 10 and the doped semiconductor material of the doped semiconductor layer 40L, and the thickness of the intrinsic semiconductor layer 30 in the second embodiment.
  • longer nanowires and thicker semiconductor layers tend to absorb more photon energy, but also increase manufacturing cost because of increased usage of semiconductor material(s) and longer processing time.
  • Dopant concentrations in semiconductor nanowires must be sufficiently high so that the semiconductor nanowires are not fully depleted.
  • doped silicon having a dopant concentration of about 1.0 x 10 18 /cm 3 yield a depletion width of about 50 nm, which corresponds to a maximum lateral dimension of about 100 nm.
  • a semiconductor nanowire having a slightly greater maximum lateral dimension may be used. Use of a higher dopant concentration for the doped portion of the semiconductor nanowires can enable a lesser maximum lateral dimension for the semiconductor nanowire.
  • One factor that can help improve carrier transport characteristics is the electric field strength along the length of the wire.
  • the field strength depends sensitively on the dimension and the geometric shape of the semiconductor nanowire.
  • a long, straight semiconductor nanowire does not have homogeneous electric field along the length of the wire.
  • the voltage drop occurs mostly at the two ends of the semiconductor nanowire.
  • This is a disadvantage for carrier collection.
  • a cone-shaped nanostructure produces a more uniform electric field along its axis, leading to better carrier collection efficiency.
  • the geometric parameters of the semiconductor nanowire can be optimized to enhance carrier transport and to improve the energy conversion efficiency.
  • the electronic structure of the semiconductor material, the dopant concentration level, the operating temperature, and applied electrical bias affect the carrier density in the photovoltaic device of the present disclosure.
  • FIG. 13 a preliminary work on this subject demonstrates that when the diameter of the semiconductor nanowire is comparable to the Debye length, the electric field along the length of the semiconductor nanowire cannot be completely screened even if the length of the semiconductor nanowire is much longer than the Debye length.
  • the photovoltaic device of the present disclosure provides high energy conversion efficiency by combining the photon absorptance of thin film and nanowires and by taking advantage of very short carrier transport paths and a self-aligned one-dimensional structure of a high-density P-N junction or P-I-N junction array.
  • the density of substantially vertical junctions can be from 1.0 x 10 7 /mm 2 to 1.0 x 10 9 /mm 2 .
  • the high contact resistance issue in prior art semiconductor nanowires is eliminated or significantly alleviated by avoiding direct contacts between the semiconductor nanowires and the electrode.
  • the photovoltaic device of the present disclosure provides a robust and reliable nanostructure, in which semiconductor nanowires are embedded in a mechanically supportive thin film matrix, i.e., the silicon layer 20.
  • the photovoltaic device of the present disclosure can be manufactured employing inexpensive and scalable processes. Specifically, the processes employed to manufacture the photovoltaic device of the present disclosure can employ a low-temperature PECVD process for deposition of the silicon layer 20 and electrochemical processes without involving high temperatures or metal catalysts (potential contaminants) as required in prior art methods for forming semiconductor nanowires.
  • the high carrier-collection efficiency of nanowire P-N or P- I-N junctions allows the use of lower-quality semiconductor material for the semiconductor nanowires of the present disclosure.
  • the disclosed method for manufacturing the photovoltaic device is versatile and flexible, and is applicable to large surface areas.
  • deposition can be made on foils or non-planar surfaces, i.e., curved surfaces having a finite radius of curvature.
  • the method of the present disclosure can be employed to roll-to-roll processing techniques, and is suitable for complex geometries.
  • the hybrid nanostructure of the present disclosure can also be employed for other types of energy harvesting, conversion, and storage applications, such as batteries and thermoelectric devices.

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Abstract

Cette invention concerne un procédé à bas coût de formation d'un dispositif photovoltaïque qui est une cellule multijonction nanostructurée haute performance. Les multiples jonctions P-N ou jonctions P-I-N sont jointes de manière contiguë pour former une seule jonction P-N contiguë ou une seule jonction P-I-N contiguë. Le dispositif photovoltaïque comporte des nanofils semi-conducteurs alignés verticalement comprenant un matériau semi-conducteur dopé pourvus d'une couche mince de silicium ayant un type de dopage opposé. Cette nouvelle cellule hybride peut fournir un rendement supérieur à des dispositifs photovoltaïques classiques grâce à une combinaison d'une absorbance améliorée des photons, d'une résistance réduite au contact, et des courts trajets de transport dans les nanofils. Des procédés à température ambiante ou des procédés à basses températures tels que des procédés de dépôt chimique en phase vapeur assistés par plasma (PECVD) et électrochimiques peuvent être utilisés pour fabriquer ce dispositif photovoltaïque de manière économique, évolutive et économe en énergie.
PCT/US2011/056508 2010-10-19 2011-10-17 Cellule solaire hybride de type multijonction comportant des nanofils en silicium alignés verticalement pourvus de films minces Ceased WO2012054368A2 (fr)

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