WO2011132302A1 - Charging control method and discharging control method for electricity storage device - Google Patents

Abstract

Disclosed are a charging control method and a discharging control method for an electricity storage device, by which variations in the interterminal voltage of an electric double-layer capacitor can be suppressed without using a parallel monitor by switching series-parallel connections exclusively. In the charging control method, the block voltage (Vb), which is the sum of the interterminal voltage (Vc) of two electric double layer capacitors that form a block, is compared for each block during the elapse of a prescribed interval of time (Ti). In addition, k blocks are connected in parallel in order from the block with the highest block voltage (Vb), and the connection modes of the electric double-layer capacitors of the other (n-k) blocks are switched in a manner such that the blocks are connected in series. Furthermore, the comparison of the block voltages (Vb) and switching of the block connection modes are repeated for each interval of time (Ti) until the output voltage (Vt) of an electricity storage unit (21) reaches the upper limit (VU) of the acceptable input voltage range of a power converter (22).

Description

Charge control method and discharge control method for power storage device

The present invention relates to a charge control method and a discharge control method for a power storage device using an electric double layer capacitor as a power storage device.

Electric double layer capacitors (Electric Double Layer Capacitors) are attracting attention as new storage devices that replace secondary batteries due to their long cycle life and wide operating temperature range.

Referring to FIG. 16, a power supply system using an electric double layer capacitor (hereinafter simply referred to as “capacitor”) as an electricity storage device will be described. The DC power supplied from the DC power source 1 such as a solar battery is temporarily stored in the power storage unit 21 of the power storage device 2.

Unlike the secondary battery, the capacitor has a voltage between terminals that varies greatly in proportion to the amount of stored charge, and therefore cannot store the power stored in the power storage unit 21 directly to the load 3. For this reason, the power stored in the power storage unit 21 is supplied to the load 3 after the voltage is stabilized in the power converter 22 such as a DC-DC converter or a DC-AC inverter. The control unit 23 controls charging / discharging in the power storage unit 21.

In the power supply system of FIG. 16, the power converter 22 has an allowable input voltage range. Therefore, in order to continuously supply stable power to the load 3, the output voltage (hereinafter referred to as “power storage unit voltage”) Vt of the power storage unit 21 must be maintained within the allowable input voltage range of the power converter 22. I must.

In addition, since the output voltage of a capacitor alone is low, the power storage unit 21 is often used by connecting a plurality of capacitors in series. Further, in order to secure the necessary accumulated charge amount, a plurality of capacitors are often connected in parallel. Therefore, power storage unit 21 of a power storage device using a capacitor is generally configured by connecting a plurality of capacitors in series and in parallel.

Conventionally, in the power storage device 2 in which the power storage unit 21 is configured by a plurality of capacitors, in order to improve the charge / discharge characteristics and the depth of discharge, a charge control method using two methods of “serial switching” and “parallel monitor” A discharge control method is employed (see, for example, Patent Document 1). Hereinafter, the power storage device described in Patent Document 1 adopting these two methods will be described with reference to the drawings.

First, “series-parallel switching” will be explained. “Series-parallel switching” is one of the methods used for improving the charge / discharge characteristics and the discharge depth in the power storage device 2 in which the power storage unit 21 is configured by connecting a plurality of capacitors in series or in parallel. It is.

The power storage unit 21 of the power storage device 2 using “series-parallel switching” described in Patent Document 1 is configured as shown in FIG. That is, one circuit block (hereinafter simply abbreviated as “block”) is constituted by a pair of capacitors C, C having the same capacitance and a plurality of switches S for switching the series connection and the parallel connection of the pair of capacitors C, C. The blocks are connected in n stages (B1 to Bn) in series.

The serial-parallel switching method described in Patent Document 1 will be described by taking as an example a case where the power storage unit 21 is configured by three-stage blocks (B1 to B3) as shown in FIG. FIG. 19 is a simplified diagram showing the connection pattern of capacitor C of power storage unit 21 in FIG.

When all the capacitors C constituting the power storage unit 21 start charging from a completely discharged state, first, the switches S12, S22, and S32 are turned on (that is, closed), and the switches S11, S13, S21, S23, S31, and S33 are turned off. By setting (that is, opening), as shown in FIG. 19A, the capacitors C of all the blocks are connected in series, and charging is started.

Charge is accumulated in each capacitor C as charging progresses, and the storage unit voltage Vt increases. Each time the power storage unit voltage Vt reaches the upper limit of the allowable input voltage range of the power converter 22, the switches (S11 to S33) in FIG. 18 are appropriately turned on or off. Then, the capacitors C of each block are arranged in a predetermined order such that the power storage unit voltage Vt falls within the allowable input voltage range of the power converter 22, for example, FIG. 19B → FIG. 19C → FIG. In order of (d), switching from the serial connection to the parallel connection is performed in stages, and charging is performed so that the capacitors C of each block are finally connected in parallel.

Further, at the time of discharging, whenever the storage unit voltage Vt reaches the lower limit value of the allowable input voltage range of the power converter 22 as the storage unit voltage Vt drops, the switches (S11 to S33) in FIG. By turning off, the capacitor of each block in a predetermined order opposite to that during charging, for example, in the order of FIG. 19 (d) → FIG. 19 (c) → FIG. 19 (b) → FIG. C is gradually switched from parallel connection to series connection, and discharging is performed. As described above, the series-parallel switching is performed in order to improve the charge / discharge characteristics and the depth of discharge by maintaining the power storage unit voltage Vt within the allowable input voltage range of the power converter 22.

Next, “Parallel monitor” will be described. Generally, the capacitance of a capacitor varies greatly. Therefore, when a plurality of capacitors are connected in series and charged, a capacitor having a small capacitance is fully charged. If the charging is further continued, the capacitor having a small electrostatic capacity becomes overcharged, which causes deterioration, and in the worst case, it is destroyed.

Therefore, in a power storage device using a capacitor as a power storage device, a circuit called “parallel monitor” configured by a resistor R and a switch S as shown in FIG. There are many. When the terminal voltage of each capacitor C exceeds the rated voltage (the upper limit of the terminal voltage at which the capacitor can be used safely), this parallel monitor turns on the switch S as shown in FIG. The capacitor C is prevented from being overcharged by forcibly bypassing Ic.

Next, problems of the power storage device charging control method described in Patent Document 1 will be described. Even if the power storage unit 21 is composed of a plurality of capacitors having the same nominal capacitance, the amount of charge flowing into each capacitor C of the blocks connected in parallel by series-parallel switching is transferred to each capacitor C of the blocks connected in series. Approximately half of the amount of charge flowing in. Furthermore, since actual capacitors also have capacitance errors and self-discharge characteristics, variations occur in the voltage between terminals of each capacitor.

Due to this variation, when any capacitor C in a block connected in series is fully charged, the capacitor C is in a period until the capacitors C in other blocks connected in parallel reach full charge. In order to avoid falling into overcharge, the terminal voltage must be kept at the rated voltage by the parallel monitor. As a result, heat loss due to the resistance of the parallel monitor occurs, and the charging efficiency decreases.

That is, in the conventional charge control method described in Patent Document 1, the variation in the voltage between the terminals of the capacitor between the blocks becomes very large, and the operation time of the parallel monitor becomes long to prevent overcharge. Loss increases and as a result, charging efficiency decreases.

In order to solve the above-described problems, the inventors have developed a control method for serial-parallel switching that suppresses variations in voltage between terminals of all capacitors constituting the power storage unit (see Patent Document 2).

The charging control method of the power storage device developed by the inventors is not only for preventing overcharging of the parallel monitor, but also by controlling the parallel monitor at regular intervals so that the voltage between terminals of each capacitor is within a certain range. It is also used as a countermeasure for so-called “cross current” that occurs when the capacitors of each block are switched from serial connection to parallel connection, for correction so as to be within the range (called constant correction). With this and the serial / parallel switching control method described later, the operation time of the parallel monitor and the heat generated by the operation can be significantly reduced as compared with the method described in Patent Document 1, and the charging efficiency can be increased.

The control method of serial / parallel switching of each block described in Patent Document 2 will be described by taking as an example a case where it is applied to the power storage unit 21 configured by three blocks (B1, B2, B3) shown in FIG. 22 is a diagram showing a simplified connection pattern of capacitor C of power storage unit 21 in FIG.

In the charging process, when all the capacitors C are completely discharged, the switches S13, S01, S23, S02 and S33 are turned on, and the switches S11, S12, S21, S22, S31 and S32 are turned off. Charging is started from a state in which all capacitors C are connected in series as shown in 22 (a).

Of the three blocks (B1 to B3) of the power storage unit 21, the power storage unit voltage Vt reaches the upper limit of the allowable input voltage range of the power converter 22 to appropriately control the switches (S01 to S33). Then, the capacitor C of any one block is switched to the parallel connection, and the power storage unit voltage Vt is lowered within the allowable input voltage range of the power converter 22.

At this time, blocks having the highest sum of voltages between terminals of the two capacitors C in the block (hereinafter referred to as “block voltage”) are preferentially connected in parallel. That is, the state shown in FIG. 22 (a) is switched to the state shown in FIG. 22 (b), FIG. 22 (c), or FIG. 22 (d).

Thereafter, charging is continued and the block is set so that the storage unit voltage Vt falls within the allowable input voltage range of the power converter 22 every time the storage unit voltage Vt reaches the upper limit value of the allowable input voltage range of the power converter 22. The block with the highest voltage is selected, the capacitor C of that block is switched to parallel connection, and the power storage unit voltage Vt is lowered. At this time, for example, the block connected in parallel is switched to the serial connection, such as switching from the state of FIG. 22B to the state of FIG. 22D, and the other one block is switched from the serial connection to the parallel connection.

However, while one block to be connected in parallel is changed several times, the charging proceeds further, the voltage between terminals of each capacitor C increases, and the voltage of the power storage unit voltage no matter which one block is connected in parallel Vt does not fall within the allowable input voltage range of the power converter 22.

In such a state, each capacitor C is charged while maintaining the power storage unit voltage Vt within the allowable input voltage range of the power converter 22 by increasing the number of blocks to be connected in parallel. That is, the state is switched from any of the states of FIG. 22 (b), FIG. 22 (c), or FIG. 22 (d) to any of the states of FIG. 22 (e), FIG. 22 (f), or FIG. It is done. Also in this case, two blocks are selected in descending order of the block voltage, and the capacitors C of these blocks are connected in parallel.

Charging further proceeds, and the power storage unit voltage Vt exceeds the allowable input voltage range of the power converter 22 regardless of the state shown in FIGS. 22 (e), 22 (f), and 22 (g). In this state, the state is finally switched to the state of FIG. 22 (h), and charging is continued until all capacitors C are almost fully charged.

As shown in FIG. 22 (h), the capacitors C of all the blocks (B1 to B3) are connected in parallel, and the power storage unit voltage Vt when all the capacitors C are fully charged is It is set to be within the allowable input voltage range.

Further, in the discharging process, when all the capacitors C are fully charged, discharging starts from the state of FIG. 22 (h) (all blocks are in parallel), and the power storage unit voltage Vt becomes the power converter 22. When the voltage falls to the lower limit value of the allowable input voltage range, the capacitor C of any one block is switched to the serial connection. Thereby, power storage unit voltage Vt is boosted, and discharge is maintained such that power storage unit voltage Vt falls within the allowable input voltage range of power converter 22. At this time, the blocks are connected in series preferentially from the block having the higher block voltage. That is, the state shown in FIG. 22 (h) is switched to the state shown in FIG. 22 (e), FIG. 22 (f), or FIG. 22 (g).

Similarly, the block voltage is set so that the power storage unit voltage Vt falls within the allowable input voltage range of the power converter 22 every time the power storage unit voltage Vt decreases to the lower limit value of the allowable input voltage range of the power converter 22. The highest block is preferentially connected in series to increase the power storage unit voltage Vt. At this time, for example, the block connected in series is returned to the parallel connection, such as switching from the state of FIG. 22E to the state of FIG. 22F, and the other one block is connected in series.

When the discharge further proceeds and the capacitor C in any one block is connected in series, if the storage unit voltage Vt decreases to the lower limit value of the allowable input voltage range of the power converter 22, the number of blocks to be connected in series is reduced. increase. Also in this case, two blocks are preferentially selected in descending order of block voltage and connected in series. That is, the state is switched from the state of FIG. 22 (e), FIG. 22 (f) or FIG. 22 (g) to the state of FIG. 22 (b), FIG. 22 (c) or FIG. It is done.

Then, the discharge further proceeds, and the power storage unit voltage Vt drops to the lower limit value of the allowable input voltage range of the power converter 22 regardless of the state shown in FIGS. 22 (b), 22 (c) and 22 (d). Then, finally, the state is switched to the state of FIG. 22A in which all the capacitors C constituting the block are connected in series, and the discharge is continued.

As described above, discharging is performed so that the storage unit voltage Vt maintains the allowable input voltage range of the power converter 22 by switching the series-parallel connection state of each block.

As described above, the feature of the serial-parallel switching method described in Patent Document 2 is that the order of blocks to be serial-parallel switched and the pattern of serial-parallel switching are not fixed as in the method described in Patent Document 1. It is in. By doing so, it is possible to finely control the voltage across the terminals of the capacitors C in each block, and furthermore, it is possible to suppress variations in the voltages across the terminals of all the capacitors C constituting the power storage unit 21.

Japanese Patent Laid-Open No. 11-215695 International Publication WO2007 / 046138

As described above, the conventional charge control method and discharge control method for a power storage device achieve efficient charge and discharge by using series-parallel switching control and a parallel monitor together. However, in the control method described in Patent Document 2 as well as the control method described in Patent Document 1, series-parallel switching is performed because the storage unit voltage Vt is the upper limit of the allowable input voltage range of the power converter 22. In Japanese Patent Application Laid-Open No. 2004-260628, the correction is always performed by parallel monitoring. However, the number of series-parallel switching is small, and the terminal voltage of each capacitor still varies. It was.

Therefore, it is difficult to completely eliminate the parallel monitor in the conventional power storage device control method, and power loss due to the parallel monitor cannot be avoided.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional problems, and a power storage device charge control method capable of suppressing variations in voltage between terminals of a capacitor only by switching a series-parallel connection without using a parallel monitor. It is another object of the present invention to provide a discharge control method.

In order to achieve the above object, a method for controlling the charge of a power storage device according to the present invention includes, as power storage means, a block composed of two capacitors having the same capacitance and a plurality of switches in series (n Is a natural number of 2 or more), and each block is a power storage device capable of switching the connection of the two capacitors in series or in parallel by turning on / off the plurality of switches. A charge control method comprising:
When a predetermined interval time elapses, a block voltage that is a sum of voltages between terminals of two capacitors constituting the block is compared for each block,
Connection of capacitors of each block so that k blocks (k is a natural number equal to or less than n) are connected in parallel and other (nk) blocks are connected in series in order from the block with the highest block voltage. Switch state,
In addition, the comparison of the block voltages and the switching of the connection state of each block are repeated at each interval time until the output voltage of the power storage unit reaches a preset first voltage value.

Here, when the output voltage of the power storage unit reaches the first voltage value, the number of blocks connected in parallel among the n blocks is changed from k to (k + 1). Moreover, it is preferable to use the upper limit value of the allowable input voltage range of the power converter connected to the output side of the power storage means as the first voltage value.

Note that the two capacitors constituting the block may be formed by connecting a plurality of capacitors having the same capacitance in parallel.

In the discharge control method for a power storage device according to the present invention, as a power storage means, n blocks (n is a natural number of 2 or more) connected in series with two capacitors having the same capacitance and a plurality of switches are connected. The capacitor group is used, and each block is a discharge control method of a power storage device that can switch the connection of the two capacitors in series or in parallel by turning on / off the plurality of switches,
When a predetermined interval time elapses, the block voltage that is the sum of the voltages across the terminals of each capacitor constituting the block is compared for each block,
In order from the block with the highest block voltage, (nk) (k is a natural number less than n) blocks are connected in series, and the other k capacitors are connected in parallel so that the other blocks are connected in parallel. Switch state,
In addition, the comparison of the block voltages and the switching of the connection state of each block are repeated at each interval time until the output voltage of the power storage means reaches a preset second voltage value.

Here, when the output voltage of the power storage means reaches the second voltage value, the number of blocks connected in series among the n blocks is changed from (nk) to (nk + 1). Change to Moreover, it is preferable to use the lower limit value of the allowable input voltage range of the power converter connected to the output side of the power storage means as the second voltage value.

Note that the two capacitors constituting the block may be formed by connecting a plurality of capacitors having the same capacitance in parallel.

Further, when a capacitor having a lower limit voltage is used as the capacitor, it is preferable that the discharge is stopped when the voltage between terminals of any one of the capacitors constituting the power storage unit falls below the lower limit voltage. .

According to the charge control method for a power storage device according to the present invention, since the series-parallel connection of each block is switched so that the block voltage does not vary every short interval time, the variation in the voltage between the terminals of the capacitor can be suppressed.

That is, due to the series-parallel switching, the electric charge flowing into each capacitor of the block connected in series becomes about twice the electric charge flowing into each capacitor of the block connected in parallel. By actively utilizing the equalization of the voltage between the terminals of the capacitor, it is possible to suppress variations in the block voltage and the voltages between the terminals of each capacitor.

As a result, there is no need for a parallel monitor to prevent overcharging, and heat loss is eliminated, improving charging efficiency.

Further, according to the discharge control method for a power storage device according to the present invention, the series-parallel connection of each block is switched so as to eliminate the variation in the block voltage every short interval time, so that the variation in the voltage between the terminals of the capacitor can be suppressed. In addition, since the time until the power storage unit voltage reaches the second voltage value (for example, the lower limit value of the allowable input voltage range of the power converter) is delayed, the discharging time of the power storage means, that is, the operation of the power converter The time can be lengthened.

FIG. 1 is a block diagram illustrating a configuration of a power supply system including a power storage device. FIG. 2 is a circuit diagram showing a specific example of the configuration of the power storage unit of FIG. FIG. 3 is an explanatory diagram of “block voltage”. FIG. 4 is a graph showing a temporal change in the power storage unit voltage Vt. FIG. 5 is a graph showing temporal changes in the block voltage in the present invention and the conventional charge control method. FIG. 6 is a diagram illustrating capacitor switching control in the charge control method of the present invention. FIG. 7 shows a block configuration of the power storage unit. FIG. 8 is a circuit diagram illustrating a configuration example of a block. FIG. 9 is a flowchart for carrying out the charge control method of the present invention. FIG. 10 is a diagram illustrating capacitor switching control in the discharge control method of the present invention. FIG. 11 is a flowchart for carrying out the discharge control method of the present invention. FIG. 12 is a flowchart in a case where the discharge control method of the present invention is performed on a power storage device using a capacitor in which upper limit voltage and lower limit voltage are limited. FIG. 13 is a flowchart when the charge control method and the discharge control method of the present invention are combined. FIG. 14 is a flowchart in the case where the charge control method and the discharge control method of the present invention are performed on a power storage device using a capacitor in which the upper limit voltage and the lower limit voltage are limited. FIG. 15 is a graph showing temporal changes in the power storage unit voltage Vt and the capacitor terminal voltage Vc when charge control and discharge control are performed according to the flow of FIG. FIG. 16 is a block diagram illustrating a configuration of a power supply system using a plurality of capacitors as an electricity storage device. FIG. 17 is a circuit diagram illustrating a configuration of the power storage unit. FIG. 18 is a circuit diagram of a power storage unit configured by three blocks. FIG. 19 is a diagram showing a simplified connection pattern of capacitor C in the power storage unit shown in FIG. FIG. 20 is a circuit diagram illustrating the “parallel monitor”. FIG. 21 is a circuit diagram illustrating a configuration of the power storage unit described in Patent Document 2. FIG. 22 is a simplified view of the connection pattern of capacitor C in the power storage unit shown in FIG.

Hereinafter, a charge control method and a discharge control method (hereinafter simply referred to as “charge control method” and “discharge control method”) for a power storage device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 illustrates a configuration of a power supply system including a power storage device. In the present embodiment, a charge control method performed by power storage device 2 in FIG. 1 will be described.

The power storage device 2 stores the DC power supplied from the DC power source 1 and supplies the DC power to the load 3 as it is or converted into AC power. The DC power supply 1 is preferably a current source, but may be a voltage source. As the DC power source 1, for example, a solar cell, a wind power generator, an engine generator, or the like is used. However, other power supply sources can be used. To use.

<Configuration of power storage device>
The power storage device 2 includes a power storage unit 21, a power converter 22, and a control unit 23. The power storage unit 21 stores DC power supplied from the DC power supply 1. The power converter 22 is composed of a DC-AC inverter or the like, converts the DC power stored in the power storage unit 21 into AC power, and stabilizes the output voltage. When the load 3 is driven by direct current power, a DC-DC converter or the like is used as the power converter 22.

The power storage unit 21 that is a power storage unit of the power storage device 2 is a block in which n blocks (n is a natural number of 2 or more) connected in series are two blocks each having two capacitors (that is, electric double layer capacitors). A specific example of the configuration of the power storage unit 21 is shown in FIG.

In the power storage unit 21 of FIG. 2, five blocks (B1 to B5) are connected in series. Each block (B1 to B5) is composed of two capacitors C and three switches S having the same capacitance. By switching each switch S on and off, the two capacitors C are connected in series or Connected in parallel. The reason for configuring each block with two capacitors will be described in detail later.

The electric double layer capacitor in the narrow sense means a symmetric electric double layer capacitor using electric double layer capacitance for both the positive electrode and the negative electrode of the electrode, but the electric double layer capacitor in the broad sense includes a symmetric capacitor. In addition, an asymmetric type electric double layer capacitor in which one pole is a redox pseudocapacitance (redox pseudocapacitance) generated with a redox reaction and the other pole is an electric double layer capacitance is also included. . The present invention can be applied to an electric double layer capacitor in a broad sense.

As the switch S, a semiconductor switch composed of an FET or the like is usually used. However, when the amount of current flowing through the switch S is large, a thyristor or IGBT may be used.

1, the control unit 23 controls charging / discharging in the power storage unit 21. The control unit 23 includes a series / parallel switching circuit 24, an inter-terminal voltage detection circuit 25, a power storage unit voltage detection circuit 26, and a control circuit 27.

The series-parallel switching circuit 24 switches between the state in which the two capacitors C are connected in series and the state in which the capacitors are connected in parallel by switching each of the three switches S in each block.

The inter-terminal voltage detection circuit 25 detects the inter-terminal voltage Vc of the capacitor C in each block. The power storage unit voltage detection circuit 26 detects the output voltage of the power storage unit 21, that is, the power storage unit voltage Vt. The inter-terminal voltage Vc detected by the inter-terminal voltage detection circuit 25 and the power storage unit voltage Vt detected by the power storage unit voltage detection circuit 26 are input to the control circuit 27.

The control circuit 27 includes a block voltage calculation circuit 28 and an oscillation circuit 29. The block voltage calculation circuit 28 calculates the block voltage Vb of each block based on the terminal voltage Vc of each capacitor C detected by the terminal voltage detection circuit 25. The oscillation circuit 29 generates a pulse for each interval period from the clock signal and outputs it as a timing signal for the series-parallel switching circuit 24 and the inter-terminal voltage detection circuit 25.

The control circuit 27 controls the series / parallel switching circuit 24 based on the block voltage Vb calculated by the block voltage calculation circuit 28 and the storage unit voltage Vt output from the storage unit voltage detection circuit 26.

When the control circuit 27 is configured by a CPU (Central Processing Unit), the functions of the control circuit 27, the block voltage calculation circuit 28, and the oscillation circuit 29 are software (programs) stored in a ROM (Read Only Memory). This is realized by reading out to the CPU and executing it.

Here, with reference to FIG. 3, the aforementioned “block voltage” Vb will be described in detail. The “block voltage” Vb defined in this specification is not a voltage across the block but a value obtained by adding a voltage between terminals of two capacitors constituting the block.

Specifically, when the capacitors C1 and C2 constituting the block are connected in series as shown in FIG. 3A, the block voltage Vb is the voltage Vc1 between the terminals of the capacitor C1 and the voltage between the terminals of the capacitor C2. A value obtained by adding Vc2. Similarly, when the capacitors C1 and C2 are connected in parallel as shown in FIG. 3B, the block voltage Vb is a value obtained by adding the inter-terminal voltage Vc3 of the capacitor C1 and the inter-terminal voltage Vc4 of the capacitor C2. Become.

Note that power for operation is supplied to each circuit in the control unit 23 and the power converter 22 from a power source such as a storage battery (not shown). However, a part of the DC power stored in the power storage unit 21 may be used as operating power without providing a power source. In this case, the control circuit 27 needs to control the discharge so that the amount of power stored in the power storage unit 21 does not fall below the amount of power required by the control circuit 27.

<Capacitor connection state switching control>
Next, switching control of the connection state of the capacitor in the present invention will be described. The charge control method according to the present invention is the same as the control method described in Patent Document 2 described above, in which the block is switched in series and parallel when the storage unit voltage Vt reaches a preset first voltage value. . In the present invention, the block voltage Vb is always detected at every predetermined interval time except when the capacitors of all the blocks are connected in series and when the capacitors of all the blocks are connected in parallel. The series-parallel connection is switched so that the variation in the voltage Vb is reduced.

Specifically, in the charge control method according to the present invention, when a predetermined interval time Ti elapses, the block voltage Vb of each capacitor constituting the block is compared for each block, and k blocks (in order from the block having the highest block voltage Vb) k is a natural number equal to or less than n), and the connection state of the capacitors in each block is switched so that the other (n−k) blocks are connected in series. The comparison of the block voltage Vb and the switching of the connection state of each block are repeated for each interval time Ti until the power storage unit voltage Vt reaches a preset first voltage value.

The first voltage value is normally set to a value that provides the best efficiency, that is, the upper limit value of the allowable input voltage range of the power converter 22, but the efficiency is not limited even if it is set to a lower value. Although slightly reduced, the effect of the charge control method of the present invention is exhibited.

Hereinafter, suppression of variation in block voltage in the charge control method of the present invention will be described in comparison with the charge control method described in Patent Document 2. In addition, in order to make the explanation easy to understand, here, a case where the power storage unit 21 is configured by three blocks will be described as an example. The first voltage value is set to the upper limit value of the allowable input voltage range of the power converter 22.

FIG. 4 is a graph showing temporal changes in the power storage unit voltage Vt, FIG. 5A is a graph showing temporal changes in the block voltage in the charge control method of the present invention, and FIG. It is a graph which shows the time change of the block voltage in a charge control method.

In both the charge control method described in Patent Document 2 and the charge control method according to the present invention, electric charge is accumulated in each capacitor of the power storage unit, and eventually, as shown in FIG. 4, the power storage unit voltage at point a (time Ta). When Vt reaches the upper limit value of the allowable input voltage range of power converter 22, the number of blocks connected in parallel increases by one, and power storage unit voltage Vt decreases. When charging further proceeds, power storage unit voltage Vt again reaches the upper limit value of the allowable input voltage range of power converter 22 at point b (time Tb).

In this process, in the charge control method described in Patent Document 2, the transition of the block voltage of each block is as shown in FIG. That is, the series-parallel connection is switched at point a (time Ta) when the storage unit voltage Vt reaches the upper limit of the allowable input voltage range of the power converter 22, and at this time, the block B1 having the highest block voltage Vb is switched. Two capacitors are connected in parallel. As a result, the charging speed of the two capacitors in the block B1 becomes slow, and the difference in the block voltage Vb from the other blocks (blocks B2 and B3) decreases.

However, even when the block voltage Vb of the block B1 falls below the block voltage Vb of the block B2 at the point c (time Tc), the storage unit voltage Vt reaches the upper limit value of the allowable input voltage range of the power converter 22 again. The switching of the series-parallel connection is not performed until (time Tb), and the two capacitors of the block B1 are continuously charged while being connected in parallel. As a result, when the point b (time Tb) is reached, the block voltage Vb of the block B1 is much lower than the block voltages Vb of the other blocks (B2, B3), which causes the block voltage Vb to vary.

On the other hand, in the charge control method of the present invention, as in the method described in Patent Document 2, series-parallel connection is performed at point a (time Ta) when the storage unit voltage Vt reaches the upper limit of the allowable input voltage range of the power converter 22. However, even at points other than point a (time Ta), the block voltage Vb of each block is always detected at every predetermined interval time Ti, and the connection state is switched so that variations in the block voltage Vb are reduced. Done.

That is, as shown in FIG. 5A, after the connection state of the two capacitors of the block B1 having the highest block voltage Vb at the point a (time Ta) is changed from series to parallel, the block voltage Vb of the block B2 is When it becomes the highest at the point c (time Tc), the connection state of the two capacitors in the block B1 is returned in series at this point, and the connection state of the two capacitors in the block B2 is switched in parallel. Similarly, after the time Tc, the block voltage Vb of each block is always detected at every predetermined interval time Ti, and the two capacitors of the block having the highest block voltage Vb are switched to the parallel connection. The two capacitors in the block that were were returned to the serial connection. As shown in FIG. 5A, the switching of the block connection state is repeated every interval time Ti, thereby suppressing the variation in the block voltage Vb.

Referring to FIG. 6, the switching control of the capacitor connection state will be described more specifically. 6, the case where the power storage unit 21 shown in FIG. 2, that is, the power storage unit 21 in which five blocks (B1 to B5) are connected in series, will be described.

As shown in the upper part of FIG. 6, at time T1, among the five blocks (B1 to B5) constituting the storage unit 21, two blocks B1 and B2 are connected in parallel, and the other three blocks are They are connected in series (ie k = 2).

When the interval time Ti elapses in this state, the block voltage Vb of each block calculated by the block voltage calculation circuit 28 is B3, B5, B4, B1, Suppose B2. At time T2 (= T1 + Ti), the control circuit 27 switches the connection between the blocks B3 and B5 having a high voltage level in parallel, and instead switches the blocks B1 and B2 connected in parallel to series connection. The connection state of each block when the time T2 has elapsed is shown in the upper part of FIG.

Similarly, when the interval time Ti elapses from time T2, the block voltage Vb of each block calculated by the block voltage calculation circuit 28 is B4, B1, Assume that B2, B3, and B5 are obtained. At time T3 (= T2 + Ti), the control circuit 27 switches the blocks B4 and B1 having a high voltage level from series connection to parallel connection, and instead switches the blocks B3 and B5 having low voltage level connected in parallel to series connection. . The connection state of each block when the time T3 has elapsed is shown in the upper part of FIG.

By setting the interval time Ti to a short time (for example, within 10 seconds) and repeating the switching operation described above, the variation in the block voltage Vb of each block is suppressed as shown in the graph of FIG. Furthermore, variations in the terminal voltage Vc of the capacitors constituting the block are also suppressed. As a result, since the inter-terminal voltage Vc of each capacitor does not exceed the rated voltage until almost all capacitors are fully charged, it is not necessary to provide a parallel monitor.

When charging is started from a completely discharged state, the capacitors C of all the blocks are connected in series, so that the block voltage of each block and the voltage between terminals of each capacitor are not changed until the series-parallel switching is started. It varies. However, each capacitor does not reach the rated voltage during this period, and the block voltage of each block and the voltage between terminals of each capacitor are equalized by subsequent series-parallel switching.

Furthermore, in the final stage of charging, the capacitors C of all the blocks are connected in parallel, and when the power storage unit as shown in FIG. 2 is used, the block voltage of each block varies. However, until the capacitors C of all the blocks are connected in parallel, the block voltage of the block and the voltage between terminals of each capacitor are equalized by serial / parallel switching. Are very few.

<Reason for configuring a block with two capacitors>
Next, the reason why each block of the power storage unit 21 is composed of two capacitors in the present invention will be described. Both the power storage unit 21A shown in FIG. 7A and the power storage unit 21B shown in FIG. 7B are each composed of a total of 12 capacitors C having the same nominal capacitance. In the power storage unit 21A of FIG. 7A, one block includes four capacitors C, and the two capacitors C are connected in series. On the other hand, in the power storage unit 21B of FIG. 7B, one block is composed of two capacitors C, and each capacitor C is a single capacitor.

The number of switching patterns for series-parallel connection of power storage unit 21A shown in FIG. 7A is 8 (= 2 ³ ), but the number of switching patterns for series-parallel connection of power storage unit 21B shown in FIG. 64 (= 2 ⁶ ). Therefore, regarding the control of the block voltage of each block and the inter-terminal voltage Vb of each capacitor, the configuration of power storage unit 21B can be controlled more finely than the configuration of power storage unit 21A.

That is, the configuration of the power storage unit 21B can reduce variations in the block voltage Vb of each block and the inter-terminal voltage Vc of each capacitor compared to the configuration of the power storage unit 21A. Furthermore, the fluctuation | variation of the electrical storage part voltage Vt by serial / parallel switching can be suppressed.

In addition, when each of the capacitors C in each block in FIG. 7B is configured by a plurality of capacitors (two in the figure) having the same capacitance connected in parallel as shown in FIG. These can be regarded as one capacitor in terms of characteristics. Therefore, a block having the configuration shown in FIG.

<Flow of charge control>
FIG. 9 shows a flow for carrying out the charge control method according to the present invention. Hereinafter, the flow of charge control will be described with reference to the block diagram of FIG. 1 and the flowchart of FIG. 9.

It is assumed that at the time when charging control is started, each capacitor C of the power storage unit 21 is in a completely discharged state, that is, all the capacitors C are in a state where no charge is accumulated.

In step S11, the control circuit 27 instructs the series-parallel switching circuit 24 to serially connect the capacitors C of all blocks (B1 to B5 in the case of the power storage unit as shown in FIG. 2). That is, out of the total number of blocks n (n = 5 in FIG. 2), the number k of blocks in which the capacitor C is connected in parallel is “0”. Charging is started in this state (step S12).

In step S13, the control circuit 27 waits for the interval time Ti to elapse, and after the interval time Ti elapses, proceeds to the processing in step S14.

In step S14, the inter-terminal voltage detection circuit 25 measures the inter-terminal voltage Vc of each capacitor C of the power storage unit 21. The power storage unit voltage detection circuit 26 measures a power storage unit voltage Vt that is an output voltage of the power storage unit 21.

In step S15, the block voltage calculation circuit 28 of the control circuit 27 calculates the block voltage Vb of each block based on the terminal voltage Vc of each capacitor C detected by the terminal voltage detection circuit 25.

In step S16, the control circuit 27 determines whether or not the terminal voltage Vc of each capacitor C is equal to or lower than the rated voltage VCU. When the inter-terminal voltage Vc of any capacitor C exceeds the rated voltage VCU (NO), the process proceeds to step S21, and when the inter-terminal voltage Vc of any capacitor C does not exceed the rated voltage VCU (YES). Advances to step S17.

In step S21, the control circuit 27 stops charging and ends the charging control. As described above, in the charge control method of the present invention, as a result of suppressing variation in the capacitor terminal voltage Vc, the terminal voltage Vc of the capacitor C is rated as long as all the capacitors C are not fully charged. Never exceed the voltage. Therefore, when the inter-terminal voltage Vc of any capacitor C exceeds the rated voltage, it is determined that all the capacitors C are almost fully charged, or the capacitance of any capacitor C is abnormal. To stop charging.

In step S <b> 17, control circuit 27 determines whether or not power storage unit voltage Vt exceeds upper limit value VU of the allowable input voltage range of power converter 22 based on power storage unit voltage Vt detected by power storage unit voltage detection circuit 26. To do. When power storage unit voltage Vt exceeds upper limit value VU (NO), the process proceeds to step 18, and when power storage unit voltage Vt does not exceed upper limit value VU (YES), the process proceeds to step S20.

In step S18, if the number k of parallel-connected blocks is n (YES), the process proceeds to step S21, and it is determined that all capacitors C are fully charged, and charging is stopped.

On the other hand, if the number k of parallel-connected blocks is not “n” in step 18 (NO), the process proceeds to step S19, the block number k is set to “k + 1”, and then the process proceeds to step S20.

In step S20, the control circuit 27 controls the series / parallel switching shown in FIG. That is, k blocks of capacitors C are connected in parallel from the block with the highest block voltage Vb, and the other (nk) blocks of capacitors C are connected in series.

After the process of step S20 is completed, the process returns to the process of step S13, and the processes of steps S14 to S20 are repeated every interval time Ti until the power storage unit voltage Vt exceeds the upper limit value VU of the allowable input voltage range.

As described above, according to the charge control method of the present invention, the variation in the block voltage Vb is not limited to when the power storage unit voltage Vt reaches the upper limit value of the allowable input voltage range of the power converter 22 but also at every predetermined interval time. The series-parallel switching control is performed so that the number is reduced. As a result, not only variations in the block voltage Vb but also variations in the voltage Vc between the terminals of each capacitor C can be suppressed.

This eliminates the need for a parallel monitor to prevent overcharging, which is required in conventional charge control methods, and to take measures against the "cross current" that occurs when a capacitor is switched from series connection to parallel connection. Also disappear. As a result, heat loss due to the resistors constituting the parallel monitor is eliminated, and charging efficiency is improved.

(Embodiment 2)
In the present embodiment, a discharge control method according to the present invention will be described. The configurations of power storage device 2 and power storage unit 21 used for the discharge control are the same as those described in the first embodiment.

The discharge control method according to the present invention is always the same as the charge control method described in the first embodiment, except when the capacitors of all the blocks are connected in series and when the capacitors of all the blocks are connected in parallel. The block voltage Vb is detected at every predetermined interval time, and the series-parallel connection is switched so that the variation of the block voltage Vb between the blocks is reduced.

Specifically, in the discharge control method according to the present invention, when a predetermined interval time Ti elapses, the block voltage Vb of each capacitor constituting the block is compared for each block, and (n− k) The connection state of the capacitors of each block is switched so that the blocks (k is a natural number equal to or less than n) are connected in series and the other k blocks are connected in parallel. The comparison of the block voltage Vb and the switching of the connection state of each block are repeated every interval time Ti until the output voltage Vt of the power storage unit 21 reaches a preset second voltage value.

The second voltage value is usually set to a value that provides the best efficiency, that is, the lower limit value of the allowable input voltage range of the power converter 22, but the efficiency slightly decreases even if it is set to a higher value. However, the effect of the discharge control method of the present invention is exhibited.

<Capacitor connection state switching control>
Next, the switching control of the connection state of the capacitor in the discharge control method of the present invention will be specifically described with reference to FIG. Here, the temporal change in the storage unit voltage Vt and the block voltage Vb is not shown in a graph, but the storage unit voltage Vt and the block voltage Vb are shown in the graphs of FIGS. 4 and 5A. The shape is almost inverted up and down.

As shown in the upper part of FIG. 10, at time T5, two blocks B1 and B2 are connected in series among the five blocks (B1 to B5, that is, n = 5) constituting the storage unit 21, and the other blocks The three blocks are connected in parallel (ie k = 3).

When the interval time Ti elapses in this state, the block voltage Vb of each block calculated by the block voltage calculation circuit 28 is B4, B5, B3, B2, Suppose B1. At time T6 (= T5 + Ti), the control circuit 27 switches the connection between the blocks B4 and B5 having a high voltage level from parallel to series, and switches the blocks B1 and B2 connected in series to parallel connection instead. The upper part of FIG. 10 shows the connection state of each block when time T6 has elapsed.

Similarly, when the interval time Ti elapses from time T6, the block voltage Vb of each block calculated by the block voltage calculation circuit 28 is B3, B2, B1, Suppose B5 and B4. At time T7 (= T6 + Ti), the control circuit 27 switches the blocks B3 and B2 having a higher block voltage level among the blocks connected in parallel to serial connection, and instead connects the blocks B4 and B5 connected in series in parallel. Switch to connection. The upper part of FIG. 10 shows the connection state of each block when time T6 has elapsed.

When the two capacitors constituting the block are connected in series, if the capacitance of the two capacitors C varies, if the discharge is continued, the voltage across the terminals of the capacitor having a smaller capacitance is: The voltage drops faster than the terminal voltage Vc of the capacitor having a large capacitance. Therefore, the time until the power storage unit voltage Vt reaches the lower limit value of the allowable input voltage range of the power converter 22 is increased, and as a result, the discharge time of the power storage unit 21, that is, the operation time of the power converter 22 is shortened.

On the other hand, by setting the interval time Ti to a short time (for example, within 10 seconds) and repeating the switching operation described above, the variation in the block voltage Vb of each block is suppressed, and furthermore, the capacitors constituting the block Variations in the inter-terminal voltage Vc are also suppressed, and as a result, the discharge time of the power storage unit 21 (operation time of the power converter 22) can be lengthened.

<Discharge control flow>
FIG. 11 shows a flow for carrying out the discharge control method of the present invention. Hereinafter, the flow of discharge control will be described with reference to the block diagram of FIG. 1 and the flowchart of FIG. 11 when discharging from a fully charged state.

At the time of starting the discharge control, each capacitor C of the power storage unit 21 is almost fully charged. In step S31, the capacitors C of all the blocks (B1 to B5 in the case of the power storage unit shown in FIG. 2) are connected in parallel. That is, out of the total number of blocks n (n = 5 in the case of FIG. 2), the number k of blocks in which the capacitor C is connected in parallel is “n”. In this state, discharge is started (step S32).

In step S33, the control circuit 27 waits for the interval time Ti to elapse, and after the interval time Ti elapses, proceeds to the process of step S34.

In step 34, the inter-terminal voltage detection circuit 25 measures the inter-terminal voltage Vc of each capacitor C of the power storage unit 21. The storage unit voltage detection circuit 26 measures the storage unit voltage Vt.

In step S35, the block voltage calculation circuit 28 of the control circuit 27 calculates the block voltage Vb of each block based on the terminal voltage Vc of the capacitor C detected by the terminal voltage detection circuit 25.

In step S36, the control circuit 27 determines whether or not the power storage unit voltage Vt is equal to or higher than the lower limit value VL of the allowable input voltage range of the power converter 22. When the power storage unit voltage Vt falls below the lower limit value VL (NO), the process proceeds to step 37. On the other hand, when power storage unit voltage Vt is equal to or higher than lower limit value VL (YES), the process proceeds to step S39.

In step S37, when the number of blocks k connected in parallel is “0” (YES), the process proceeds to step S40, and the power storage unit 21 cannot supply a voltage equal to or higher than the lower limit value VL of the allowable input voltage range of the power converter 22. Judgment is made and discharge is stopped. On the other hand, if the number k of parallel-connected blocks is not “0” (NO), the process proceeds to step S38, the number k of parallel blocks is set to (k−1), and then the process proceeds to step S39.

In step S39, the control circuit 27 controls the series / parallel switching shown in FIG. That is, (k) blocks of capacitors C are connected in series from the block with the highest block voltage Vb, and the other k blocks of capacitors C are connected in parallel.

After the process of step S39 is completed, the process returns to the process of step S33, and the processes of steps S34 to S39 are repeated every time the interval time Ti elapses until the power storage unit voltage Vt becomes less than the lower limit value VL of the allowable input voltage range.

There are capacitors that are limited only in the upper limit voltage (rated voltage) depending on the type, and those that are limited in both the upper limit voltage and the lower limit voltage. When a capacitor with restrictions on the upper limit voltage and the lower limit voltage such as a lithium ion capacitor is used as the electricity storage device, it is necessary to slightly change the flow of discharge control. FIG. 12 shows a flow in the case of using a capacitor in which the upper limit voltage and the lower limit voltage are limited.

In the flow of FIG. 12, step S41 is added between steps S35 and S36 of the flow of FIG. That is, in step S41, the control circuit 27 determines whether or not the terminal voltage Vc of each capacitor C is higher than the lower limit voltage VCL. When the inter-terminal voltage Vc of any one of the capacitors C becomes equal to or lower than the lower limit voltage VCL (NO), the process proceeds to step S40 and the discharge is stopped. On the other hand, if the inter-terminal voltage Vc of any capacitor C is higher than the rated lower limit voltage VCL (YES), the process proceeds to step S36.

As described above, in the discharge control method of the present invention, the variation in the voltage Vc between the terminals of the capacitor is suppressed. Therefore, when the voltage Vc between the terminals of any one of the capacitors C becomes the lower limit voltage VCL, It is determined that the discharge of the capacitor C has been completed, or it is determined that there is an abnormality in the capacitance of any one of the capacitors C, and charging is stopped.

As described above, in the discharge control method according to the present invention, not only when the storage unit voltage Vt reaches the lower limit value of the allowable input voltage range of the power converter 22 but also at each predetermined interval time, Series / parallel switching control is performed so that the variation is reduced. As a result, not only the variation in the block voltage Vb but also the variation in the voltage Vc between the terminals of each capacitor C can be suppressed, so the time until the voltage Vt between the terminals reaches the lower limit value of the allowable input voltage range of the power converter 22 is reduced. The discharge time, that is, the operating time of the power converter 22 can be extended by increasing the discharge time.

(Embodiment 3)
In the present embodiment, a case where the charge control method and the discharge control method according to the present invention are combined, that is, a case where discharge is performed while charging will be described. FIG. 13 shows a flow when the charge control method and the discharge control method of the present invention are implemented in combination. In the figure, the same steps as those in FIGS. 9 and 11 are denoted by the same reference numerals, and description thereof is omitted.

Hereinafter, the flow of FIG. 13 will be described with a focus on steps different from those of FIGS. 9 and 11. In the flow of FIG. 13, the allowable input voltage range of the power converter 22 is larger than the rated voltage (upper limit voltage) of each capacitor, that is, (VU−VL)> the rated voltage (upper limit voltage) of each capacitor. It is assumed that.

The control starts from a state in which all the capacitors C are completely discharged, that is, a state in which the capacitors C of all the blocks are connected in series (the number of blocks connected in parallel k = 0) (step S11), and subsequently The charge control described in FIG. 9 (steps S12 to S17) is performed. Until the power storage unit voltage Vt reaches the upper limit value VU of the allowable input voltage range of the power converter 22, charging is performed with all the capacitors C connected in series, and the process of switching the connection state of each block (step) S20) is not performed.

In step S17, the power storage unit voltage Vt is compared with the upper limit value VU of the allowable input voltage range of the power converter, and when the power storage unit voltage Vt exceeds the upper limit value VU (NO), a discharge is possible. Discharging is started (step S32), and then the control circuit 27 instructs the series-parallel switching circuit 24 to set the number k of parallel connection blocks to “1” (step S51).

The control circuit 27 subsequently performs the process of step S20, that is, performs serial / parallel switching of the blocks, and subsequently executes the steps (steps S13 to S21) of the charging control described in FIG.

In step S17 in the lower part of the flow of FIG. 13, when the power storage unit voltage Vt does not exceed the upper limit value VU of the allowable input voltage range of the power converter (YES), the process proceeds to step S36. In step S36, the control circuit 27 determines whether or not the power storage unit voltage Vt is lower than the lower limit value VL of the allowable input voltage range of the power converter 22 due to discharging, and if it is lower than the lower limit value VL (NO). The process proceeds to step S37, and if not lower (YES), the process proceeds to step S52.

In step S52, the control circuit 27 determines whether or not the charging of the power storage unit 21 is stopped. When the charging is stopped (YES), the control circuit 27 proceeds to the process of step S53 and restarts the charging, and then returns to the process of step S20. On the other hand, when the charging is not stopped (NO), the process directly returns to step S20.

In step S37, when the number of blocks k connected in parallel is “0” (YES), the process proceeds to step S40, and the power storage unit 21 cannot supply a voltage equal to or higher than the lower limit value VL of the allowable input voltage range of the power converter 22. Judgment is made and discharge is stopped. On the other hand, if the number k of parallel-connected blocks is not “0” (NO), the process proceeds to step S38, the number k of parallel blocks is set to (k−1), and then the process proceeds to step S39. The process returns to step S13 in the lower part of the flow.

Further, in FIG. 14, similarly to FIG. 12 described above, a capacitor having a limitation on the upper limit voltage (rated voltage) and the lower limit voltage is used as an electricity storage device, and the charge control method and the discharge control method of the present invention are combined. The flow in the case of implementation is shown.

In the flow of FIG. 14, step S41 is added between step S17 and step S36 shown in the lower part of the flow of FIG. That is, in step S41, the control circuit 27 determines whether or not the terminal voltage Vc of the capacitor C exceeds the lower limit voltage VCL. When the inter-terminal voltage Vc of any one of the capacitors C becomes equal to or lower than the lower limit voltage VCL (NO), the process proceeds to step S40 to stop discharging, and the inter-terminal voltage Vc of any capacitor C is higher than the lower limit voltage VCL. If yes (YES), the process proceeds to step S36.

15 (a) and 15 (b) show the storage unit voltage when charge control and discharge control are performed according to the flow of FIG. 13 for the storage unit 21 in which the five blocks shown in FIG. 2 are connected in series. 5 is a graph showing temporal changes in Vt and a voltage Vc between terminals of a capacitor C. The graph of FIG. 15 shows a case where the discharge to the load is performed after all the capacitors C are fully charged.

In the present embodiment, an electric double layer capacitor having a rated voltage of 2.7 [V] and a nominal capacitance of 5000 [F] is used as the capacitor C. Moreover, the allowable input voltage range of the power converter 22 was set to 10.5 to 15 [V], and the interval time Ti was set to 5 seconds to perform charge control and discharge control.

From the state in which all the capacitors C whose terminal voltage is 0 [V] are connected in series, charging is started with a constant current of 2 [A], and switching of the series-parallel connection is repeated, and all the blocks are in the parallel connection state. After charging was completed, charging was stopped. Thereafter, the load 3 of 30 [W] is connected to start discharging, the switching of the series-parallel connection is repeated, all the blocks return to the serial connection state, and the storage unit voltage Vt falls below 10.5 [V]. At that time, the discharge to the load 3 was stopped.

In the graph shown in FIG. 15B, it seems that one curve is drawn, but in FIG. 15B, the graph of the voltage Vc between the terminals of the ten capacitors constituting the power storage unit 21 is overlaid. It is drawn. As shown in FIG. 15B, it can be seen that by adopting the charge control method and the discharge control method according to the present invention, the variation in the terminal voltage Vc of the capacitor C is eliminated. In addition, the variation in the voltage between the terminals of the ten capacitors constituting the power storage unit 21, that is, the difference between the maximum value and the minimum value when fully charged (when charging was stopped) was 0.04 [V].

In each of the above-described embodiments, the circuit having the configuration shown in FIG. 2 is used as the power storage unit 21 that implements the charge control method and the discharge control method of the present invention. However, it goes without saying that the present invention is not limited to this. . For example, the same effect can be obtained by using the circuit having the configuration shown in FIG.

The charge control method and the discharge control method according to the present invention can be applied to various power supply systems without being limited by the amount of power to be handled because the charge / discharge efficiency is high and the configuration of the power storage device can be simplified. Is.

DESCRIPTION OF SYMBOLS 1 DC power supply 2 Power storage device 3 Load 21 Power storage part 22 Power converter 23 Control part 24 Series / parallel switching circuit 25 Voltage detection circuit between terminals 26 Power storage part voltage detection circuit 27 Control circuit 28 Block voltage calculation circuit 29 Oscillation circuit C Capacitor B block S switch

Claims (9)

As a power storage means, a capacitor group in which n blocks (n is a natural number of 2 or more) connected in series with two electric double layer capacitors and a plurality of switches having the same capacitance are used, The block is a charge control method for a power storage device that can switch the connection of the two electric double layer capacitors in series or in parallel by turning on / off the plurality of switches,
When a predetermined interval time elapses, a block voltage that is a sum of voltages between terminals of two electric double layer capacitors constituting the block is compared for each block,
The electric double layer of each block so that k blocks (k is a natural number equal to or less than n) are connected in parallel and the other (nk) blocks are connected in series from the block with the highest block voltage. Switch the connection state of the capacitor,
And the comparison of the block voltage and the switching of the connection state of each block are repeated at each interval time until the voltage of the power storage means reaches a preset first voltage value. Charge control method. When the voltage of the power storage means reaches the first voltage value, the number of blocks connected in parallel among the n blocks is changed from k to (k + 1). Item 2. A charge control method for a power storage device according to Item 1. 3. The method for controlling charging of a power storage device according to claim 2, wherein an upper limit value of an allowable input voltage range of a power converter connected to an output side of the power storage means is used as the first voltage value. 2. The electric storage according to claim 1, wherein each of the two electric double layer capacitors constituting the block is formed by connecting a plurality of electric double layer capacitors having the same capacitance in parallel. Device charging control method. As a power storage means, a capacitor group in which n blocks (n is a natural number of 2 or more) connected in series with two electric double layer capacitors having the same capacitance and a plurality of switches is used, and each of the blocks Is a discharge control method of a power storage device that can switch the connection of the two electric double layer capacitors in series or in parallel by turning on / off the plurality of switches,
When a predetermined interval time elapses, the block voltage that is the sum of the voltages across the terminals of each electric double layer capacitor constituting the block is compared for each block,
In order from the block having the highest block voltage, (n−k) blocks (k is a natural number equal to or less than n) are connected in series, and the other k blocks are connected in parallel. Switch the connection state of the capacitor,
The comparison of the block voltages and the switching of the connection state of each block are repeated at each interval time until the voltage of the power storage means reaches a preset second voltage value. Discharge control method. When the voltage of the power storage means reaches the second voltage value, the number of blocks connected in series among the n blocks is changed from (nk) to (nk + 1). The discharge control method for a power storage device according to claim 5, wherein: The method for controlling discharge of a power storage device according to claim 6, wherein a lower limit value of an allowable input voltage range of a power converter connected to the output side of the power storage means is used as the second voltage value. 6. The electric storage according to claim 5, wherein each of the two electric double layer capacitors constituting the block is formed by connecting a plurality of electric double layer capacitors having the same capacitance in parallel. Device discharge control method. When a capacitor having a lower limit voltage is used as the electric double layer capacitor, discharging is performed when the voltage between terminals of any of the electric double layer capacitors constituting the power storage means falls below the lower limit voltage. The method for controlling discharge of a power storage device according to claim 5, wherein the control is stopped.

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