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WO2011150732A1 - Modulator and design method thereof - Google Patents

Modulator and design method thereof Download PDF

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Publication number
WO2011150732A1
WO2011150732A1 PCT/CN2011/073749 CN2011073749W WO2011150732A1 WO 2011150732 A1 WO2011150732 A1 WO 2011150732A1 CN 2011073749 W CN2011073749 W CN 2011073749W WO 2011150732 A1 WO2011150732 A1 WO 2011150732A1
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WIPO (PCT)
Prior art keywords
analog
bit
digital
signal
modulator
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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PCT/CN2011/073749
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French (fr)
Chinese (zh)
Inventor
汪清勤
王新安
张兴
葛彬杰
冯晓星
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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Publication of WO2011150732A1 publication Critical patent/WO2011150732A1/en
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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/30Delta-sigma modulation
    • H03M3/322Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/344Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/30Delta-sigma modulation
    • H03M3/322Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/368Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/30Delta-sigma modulation
    • H03M3/39Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/30Delta-sigma modulation
    • H03M3/39Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type

Definitions

  • This invention relates to analog to digital conversion, and more particularly to a modulator and method of designing same. Background technique
  • the Delta-Sigma modulator-based ADC (modular-to-digital converter) is mainly used in low-speed, high-precision fields such as audio systems and instruments. Equipment, etc.
  • the Delt book a-Sigma modulator must reduce the oversampling rate. At the same time, it is necessary to increase the order of the loop filter or increase the number of bits of the quantizer to compensate for the loss of signal-to-noise ratio.
  • Multi-bit Delta-Sigma modulators have a very demanding requirement: The accuracy of a multi-bit feedback DAC (digital-to-analog converter) needs to meet or exceed the accuracy of the entire modulator, but existing process manufacturing techniques are difficult to make multi-bit feedback DACs Achieve high-precision indicators (such as 16-bit or higher). This is due to the fact that the matching error (or mismatch) between the basic unit components causes the nonlinearity of the multi-bit feedback DAC, which causes the modulator to produce harmonic distortion, which appears as a sharp harmonic in the spectrum of the modulator output signal. Glitch, in-band harmonic glitch can cause the modulator signal-to-noise ratio to be greatly reduced, so the main problem with multi-bit Delta-Sigma modulators is the nonlinearity of the feedback DAC.
  • the existing solutions include: laser correction or analog correction, digital correction, dual quantizer structure, DEM (Dynamic Element Matching) technology, PWM (Pulse WidthModulation, pulse width) Modulation) technology and so on.
  • DEM Dynamic Element Matching
  • PWM Pulse WidthModulation, pulse width Modulation
  • Background digital correction can eliminate the nonlinear effects of DAC, but the circuit structure is very complicated.
  • the cascaded dual quantizer structure (ie, the dual quantizer MASH structure).
  • Cascaded dual quantizer The structure generally uses a 1-bit feedback DAC for the first few stages and a multi-bit feedback DAC for the final stage.
  • This structure can shape the mismatch noise of the multi-bit feedback DAC, but the shaping order of the mismatch noise is at least lower than the shaping order of the quantization noise.
  • the first order, and the interstage coupling coefficient amplifies the quantization noise and mismatch noise, which all lead to a decrease in modulator performance.
  • this structure places high demands on analog circuits in order to avoid excessive noise leakage.
  • DEM technology According to the different order of the feedback DAC mismatch noise shaping, DEM technology can be divided into two categories, first, low-order mismatch noise shaping DEM technology (including 0th order and 1st order); second, high-order mismatch noise shaping DEM technology (including 2nd order and higher order).
  • Low-order mismatched noise shaping DEM technology can weaken the nonlinear effects of multi-bit feedback DACs to varying degrees, but they have high noise floor, large in-band harmonic spurs, and DAC noise and harmonic distortion with input signal amplitude fluctuations.
  • High-order mismatched noise shaping DEM technology can better attenuate the nonlinear effects of multi-bit feedback DACs, but they are not only complicated in circuit structure, but also unstable.
  • the technical problem to be solved by the present invention is to provide a modulator and a design method thereof, which can better solve the nonlinear problem of the multi-bit feedback DAC.
  • the present invention adopts the following technical solutions:
  • a modulator for analog to digital conversion comprising an analog filter, an analog adder, a multi-bit quantizer, a digital loop filter, a multi-bit feedback digital-to-analog converter
  • the analog filter is used to input an analog signal Premodulating and outputting to an input of the analog adder
  • the analog adder is used for summing analog signals and outputting to the multi-bit quantizer
  • the multi-bit quantizer is used to convert the analog signal into a multi-bit digital signal output
  • the digital loop filter is configured to filter a multi-bit digital signal output by the multi-bit quantizer and output to the multi-bit feedback digital-to-analog converter, wherein the multi-bit feedback digital-to-analog converter is used
  • the filtered multi-bit digital signal is converted to a feedback analog signal and output to the other input of the analog adder.
  • the modulator further includes at least one shunt feedback branch, and each of the shunt feedback branch inputs is connected to one of the digital loop filters, and outputs
  • the terminal is connected to a corresponding shunt signal feeding node of the analog filter, and each of the shunt feedback branches is provided with a signal shunt, a shunt feedback digital-to-analog converter and an adder from the input end to the output end.
  • the modulator is a Delta-Sigma modulator.
  • the present invention also provides an analog to digital converter comprising the modulator described above.
  • the present invention also provides a method of constructing a modulator for constructing a second modulator from a first modulator, the first modulator comprising an analog loop filter, a multi-bit quantizer, and a multi-bit feedback digital-to-analog conversion
  • An input end of the analog loop filter receives an analog signal input, and an output end is connected to an input end of the multi-bit quantizer, and an output end of the multi-bit quantizer outputs a multi-bit digital signal, and is connected to the An input end of the multi-bit feedback digital-to-analog converter, the output end of the multi-bit feedback digital-to-analog converter is connected to another input end of the analog loop filter
  • the constructing method comprises the following steps:
  • the path filter is decomposed into a first analog filter and a second analog filter, and an analog adder is added, and the device connection is adjusted as follows: two input ends of the analog adder are respectively connected to the first analog filter and the first An output end of the second analog filter, the output end is connected
  • Adjusting the second analog filter to a digital loop filter adjusting the device connection as follows to construct a second modulator: the input of the digital loop filter is connected to the output of the multi-bit quantizer, and the output The terminal is connected to an input end of the multi-bit feedback digital-to-analog converter, and an output end of the multi-bit feedback digital-to-analog converter is connected to an input end of the adder.
  • the invention also provides a signal splitting method for a modulator, the modulator being used for analog-to-digital conversion, including an analog filter, an analog adder, a multi-bit quantizer, a digital loop filter, a multi-bit feedback digital-to-analog converter,
  • the analog filter is configured to pre-modulate an input analog signal and output to an input of the analog adder, the analog adder is used for summing analog signals, and outputting to the multi-bit quantizer, a multi-bit quantizer for converting an analog signal to a multi-bit digital signal output; the digital loop filter for filtering a multi-bit digital signal output by the multi-bit quantizer and outputting to the multi-bit feedback digital-to-analog converter
  • the multi-bit feedback digital-to-analog converter is configured to convert the filtered multi-bit digital signal into a feedback analog signal and output to another input end of the analog adder; the signal shunting method includes the following steps:
  • each of the shunt feedback branches is connected to one of the signal shunt nodes, and a signal shunt, a shunt feedback digital-to-analog converter, and an adder are sequentially disposed from the input end;
  • FIG. 1 is a diagram showing the original structure of a digital noise shaping multi-bit Delta-Sigma modulator according to an embodiment of the present invention
  • Figure 2 is a block diagram showing the structure of a general-purpose conventional Delta-Sigma modulator
  • FIG. 3 is a block diagram showing the structure of a conventional conventional Delta-Sigma modulator equivalent to FIG. 2;
  • FIG. 4 is a digital noise shaping multi-bit including an accumulation unit according to an embodiment of the present invention;
  • 5 to 7 are digital noise shaping multi-bits including accumulation units according to an embodiment of the present invention
  • FIG. 8 is a structural diagram of a digital noise shaping multi-bit De 11 a-S i gma modulator with accumulation unit optimized by signal shunting according to an embodiment of the present invention
  • Figure 9 is a block diagram of a conventional fourth-order multi-bit Delta-Sigma modulator
  • Figure 10 is a structural diagram of a conventional fourth-order low-pass multi-bit Delta-Sigma modulator equivalent to Figure 9;
  • FIG. 11 is a diagram showing an original structure of a fourth-order low-pass digital noise shaping multi-bit De 11 a-S i gma modulator according to an embodiment of the present invention
  • 12 to 14 are schematic diagrams showing the internal signal shunting process of a fourth-order low-pass digital noise shaping multi-bit De lta-Si gma modulator according to an embodiment of the present invention
  • 15 is a structural diagram of a fourth-order low-pass digital noise shaping multi-bit De 1 ta-Sigma modulator optimized by signal shunting according to an embodiment of the present invention
  • Figure 16 is the spectrum when the three modulator output signals SNDR reach the maximum
  • Figure 17 is a plot of the three modulator output signals, SNDR, versus the input signal amplitude. detailed description
  • the present invention relates generally to analog-to-digital conversion, and more particularly to a Delta-Sigma analog-to-digital converter, and in particular to a core component thereof, a multi-bit Delta-Sigma modulator, for the purpose of solving multiple bits.
  • Delta-Sigma analog-to-digital converters are used in a wide range of applications, such as: security, audio, Such as audio systems, equipment and so on.
  • the Delta-Sigma modulator is a core component of the Delta-Sigma analog-to-digital converter.
  • the De 1 ta-S i gma analog-to-digital converter based on the multi-bit De 11 a- S i gma modulator of the present invention can be applied to high speed. , high precision analog to digital conversion.
  • the modulator is called digital noise shaping.
  • Bit Delta-Sigma modulator and will introduce the modulator mainly from three aspects, including: digital noise shaping multi-bit Delta-Sigma modulator, constructing digital noise shaping multi-bit Del from traditional Delta-Si gma modulator The ta-S i gma modulator method and the digital noise shaping method of the multi-bit Delta-Sigma modulator internal signal shunt.
  • the present invention provides a digital noise shaping multi-bit Delta-Sigma modulator, which is a universally-used serialized multi-bit De 11 aS i gma modulator, which can be implemented by a user by designing a filter as needed.
  • STF specific performance signal transfer functions
  • NTF noise transfer functions
  • FIG. 1 It mainly includes an analog filter 11, a digital loop filter 12, a multi-bit quantizer 13, a multi-bit feedback DAC 14, and an analog adder 15.
  • U(z) represents the input analog signal of the modulator
  • V(z) represents the output digital signal of the modulator
  • Y(z) represents the input analog signal of the multi-bit quantizer 13
  • E Q (z) represents multi-bit quantization
  • the quantization noise of the device 13, E D (z) represents the mismatch noise of the multi-bit feedback DAC 14.
  • the analog filter 11 is used to pre-modulate the input analog signal U(z) to L.
  • U(z) signal digital loop filter 12 is used to shape quantization noise E Q (z), mismatch noise E D (z), and pre-modulation signal L.
  • the multi-bit quantizer 13 is used to convert the analog signal Y (z) into a corresponding multi-bit digital signal
  • the multi-bit feedback DAC 14 is used to convert the multi-bit digital signal output from the digital loop filter 12 A corresponding analog signal (to distinguish the aforementioned input analog signal, referred to as a feedback analog signal)
  • the analog adder 15 is used for summing the analog filter 11 and the multi-bit feedback DAC 14 output signal (feedback analog signal) (analog signal sum That is, the input analog signal Y(z) of the multi-bit quantizer 13.
  • V(z) - ⁇ -U(z) + - ⁇ —E Q (z)-- ⁇ —E D (z) ( 1 )
  • the quantization noise transfer function is: NTF 0
  • V(z) U(z) + (lZ- 1 ) "E e (z)-(lZ- 1 )"E D (z) ( 2 )
  • Equation (2) shows that the quantization noise E Q (z) of the multi-bit quantizer 13 and the mismatch noise E D (z) of the multi-bit feedback DAC 14 are simultaneously subjected to n-order noise shaping, and therefore, digital noise shaping multi-bit Delta-Sigma
  • the modulator can effectively solve the nonlinear problem of multi-bit Delta-Sigma modulator feedback DAC.
  • the modulator structure and signal flow direction of the present invention are:
  • the analog filter 11 pre-modulates the input analog signal U(z) and outputs it to an input terminal of the analog adder 15, and the analog adder 15 performs an analog signal request.
  • the analog signal and Y (z) are obtained and output to the multi-bit quantizer 13, and the multi-bit quantizer 13 converts the analog signal and Y (z) into a multi-bit digital signal V (z) output;
  • the digital loop filter 12 The multi-bit digital signal V(z) outputted by the multi-bit quantizer 13 is filtered and output to the multi-bit feedback DAC 14, and the multi-bit feedback DAC 14 converts the filtered multi-bit digital signal into a feedback analog signal and outputs it to the analog adder.
  • the present invention proposes a digital noise shaping multi-bit Delta-Sigma modulator constructed from a conventional Delta-Sigma modulator. method.
  • the basic idea of the method is: From the traditional Delta-Sigma modulator, the transfer function of the feedback loop is separated from the analog loop filter, and the separated transfer function is transferred to the digital circuit side, and This transfer function is implemented using digital circuitry.
  • the basic principle of the method is: In the feedback loop of the modulator, the injection node of the multi-bit feedback DAC mismatch noise is transferred to the equivalent injection node of the quantization noise.
  • the specific implementation steps of the construction method are:
  • the general structure of the conventional multi-bit Delta-Sigma modulator is shown in Figure 2. It consists of an analog loop filter 21, a multi-bit quantizer 22, and a multi-bit feedback DAC23, where U(z) represents the input analog of the modulator. Signal, W(z) represents the output analog signal of the multi-bit feedback DAC23, V(z) table The output digital signal of the modulator is shown, Y(z) represents the input analog signal of the multi-bit quantizer 22, E Q (z) represents the quantization noise of the multi-bit quantizer 22, and E D (z) represents the loss of the multi-bit feedback DAC 23 With noise, and Y (z) and U (z), W (z) have the following relationship:
  • V(z) ⁇ U(z) + - ⁇ —E Q (z)-- ⁇ -E D (z) (4)
  • the filter 32 shown in FIG. 3 is transferred to the side of the digital circuit, and a digital noise shaping multi-bit Delta-Sigma modulator as shown in FIG. 1 is obtained (Note: in the process of implementing the modulator design, in order to save power Consumption and area, some types of digital loop filter 12 may require equivalent conversion).
  • the method can quickly construct a digital noise shaping multi-bit Delta-Sigma modulator. It can be observed from observation that the only change in this construction process is that the position of the filter 32 and the multi-bit feedback DAC 34 are mutually adjusted, which inevitably causes the mismatch noise transfer function NTF D to change. According to the above, the digital noise shaping multi-bit Delta-Sigma modulator input and output relationship is:
  • V(z) - ⁇ U(z)+- ⁇ —E Q (z)-- ⁇ —E D (z) ( 5 )
  • the noise is random, the sign can be ignored, and is equal to the quantization noise transfer function. It can be seen that the digital noise shaping multi-bit Delta-Sigma modulator not only inherits the shaping function of the quantization noise of the traditional modulator, but also increases the shaping function of the mismatch noise of the multi-bit feedback DAC. Therefore, the construction method can be traditionally The modulator effectively constructs a digital noise shaping multi-bit De 11 aS i gma modulator.
  • the above construction method is to construct the modulator (second modulator) of the present invention from a conventional modulator (first modulator), the first modulator including the analog loop filter 21, multi-bit quantization
  • the multi-bit feedback DAC 23 an input end of the analog loop filter 21 receives an analog signal input, the output end is connected to the input end of the multi-bit quantizer 22, and the output end of the multi-bit quantizer 22 outputs a multi-bit digital signal, and An input end of the multi-bit feedback DAC 23 is connected, and an output end of the multi-bit feedback DAC 23 is connected to the other input end of the analog loop filter 21, and the construction method comprises the following steps:
  • the analog loop filter 21 is decomposed into a first analog filter 31 and a second analog filter 32, and an analog adder 35 is added to adjust the device connection as follows:
  • the two inputs of the analog adder 35 are respectively connected to the first analog
  • the output ends of the filter 31 and the second analog filter 32 are connected to the input end of the multi-bit quantizer 33, the first analog filter 31 receives the analog signal input, and the input of the second analog filter 32 is connected to the multi-bit feedback.
  • the second analog filter 32 is adjusted to a digital loop filter, and the device connection is adjusted as follows to construct a second modulator: the input of the digital loop filter is connected to the output of the multi-bit quantizer 33, and the output is connected.
  • An input of the multi-bit feedback digital-to-analog converter 34 is coupled to an input of the adder. That is, the second analog filter 32 and the multi-bit feedback digital-to-analog converter 34 are mutually aligned, and then the second analog filter is transferred from the analog domain to the digital domain, thereby being converted into a digital loop filter.
  • the filters 11, 12 in the modulator shown in Figure 1 may contain units with cumulative effects, such as: integrators, resonators, accumulators, etc., when the modulator is operating, the output of these units It will increase greatly.
  • the modulator has limited operating voltage and limited register storage value when the circuit is implemented. If no measures are taken, this contradiction will inevitably lead to unstable operation of the modulator and collapse.
  • the present invention proposes a digital noise shaping multi-bit De ta-S i gma modulator internal signal shunting method.
  • the basic idea of the method is: From the digital filter, the shunt digital signal is derived from the input of the unit whose output is greatly increased, and then converted into a corresponding analog signal by the DAC, and finally the analog signal is fed back to the analog filter. Equivalent node of the device.
  • the basic principle of the method is to: Make the transfer function of the shunt signal consistent before and after being shunted.
  • the specific implementation steps of this method are:
  • the modulator shown in FIG. 4 is taken as an example (note that the signal shunting method is not limited to this example, and the internal signal shunting method of other modulators can be analogized according to this example) f ⁇ - ⁇ ' ⁇ -7T ⁇ . ii ⁇ i *il 3 ⁇ 4 ⁇ iil v/ . 3 ⁇ 4 41 ⁇ if ⁇ ⁇ S ⁇ 4 ?
  • the bit quantizer 44, the multi-bit feedback DAC 45 and the analog adder 46 are constructed, wherein inside the digital loop filter 42, a certain unit 43 having an accumulation function is located between the node 47 and the node 48, U(z), V( z), E Q (z), E D (z) represent the input analog signal of the modulator, the output digital signal of the modulator, the quantization noise of the multi-bit quantizer 44, and the mismatch noise of the multi-bit feedback DAC 45, respectively. It can be observed by observation that when the modulator operates, the output of the unit 43 having the cumulative action will greatly increase, so the node 47 at the input of the determining unit 43 is the signal shunting node.
  • a signal shunt is required to be inserted at node 47 of Fig. 4 to obtain a modulator structure as shown in Fig. 5.
  • the signal shunt 54 decomposes ⁇ ( into V nl (z) and V n2 (z), which There are the following relationships:
  • V n (Z) V z) + V n2 (z) (6)
  • V nl (z) is the derived shunt signal that is fed back to the signal feed node of the analog filter 51.
  • the shunt signal V nl (z) can be divided into two categories.
  • V nl (z) is a 1-bit digital signal, and the modulator containing only such shunt signal is classified as Class A digital noise.
  • Plastic multi-bit Delta-Sigma modulator this type of modulator does not need to introduce additional DEM technology
  • V nl (z) is a multi-bit digital signal, and the modulator containing this shunt signal is classified as Class B digital noise.
  • Shaped multi-bit Delta-Sigma modulators such modulators may require the introduction of additional DEM technology.
  • the shunt signal V nl (z) shown in FIG. 5 belongs to the digital signal, and before the signal fed back to the analog filter 51 is fed to the node, it needs to be converted into a corresponding analog signal, and the feedback is inserted after V nl (z).
  • the DAC gets the modulator structure shown in Figure 6.
  • the node 610 can be found in the analog filter 601, which is the feed node of the shunt signal, and the adder is inserted at the node 610 of FIG. A modulator structure as shown in Fig. 7 is obtained.
  • Step 5 closing the shunt signal feedback loop
  • the output of the feedback DAC 709 is connected to the negative input of the adder 703 to obtain a modulator structure as shown in FIG. 8, which is a digital noise shaping multi-bit Delta-Sigma modulator optimized by signal shunting.
  • the interior contains a shunt feedback branch. There are multiple units with greatly increased output, which requires multiple shunt feedback branches. The operation of the modulator is made more stable by the setting of the shunt feedback branch.
  • the Class A digital noise shaping multi-bit Delta-Sigma modulator of the present invention does not need to introduce DEM technology, and it is cascaded with Compared with the modulator of the quantizer structure, the quantization noise and the mismatch noise of the multi-bit feedback DAC can be shaped in the same order, and there is no problem that the quantization noise and the mismatch noise are amplified by the interstage coupling coefficient.
  • the Class B digital noise shaping multi-bit De 11 aS i gma modulator of the present invention may need to introduce DEM technology, but it can reduce the number of DACs fed back to the input of the modulator compared with the existing DEM technology.
  • the circuit structure of the feedback DAC is improved; on the other hand, the matching precision between the unit components of the feedback DAC is improved, and conditions are created for DEM technology (such as DWA technology, etc.) using 1st order mismatch noise shaping, which can Further reducing circuit complexity, both reducing the noise generated by digital circuits, but also saving power and area.
  • DEM technology such as DWA technology, etc.
  • the main features of the modulator of the present invention are:
  • a digital loop filter is inserted between the multi-bit quantizer and the multi-bit feedback DAC in the modulator.
  • the feedback node of the multi-bit feedback DAC output signal is transferred from the input of the modulator to
  • the input of the multi-bit quantizer forms a feedback loop composed of a multi-bit quantizer, a digital loop filter and a multi-bit feedback DAC, so that the injection nodes of the quantization noise EQ (z) and the mismatch noise ED (z) are at Equivalent position, under the action of the digital loop filter, these noises are simultaneously shaped (according to this modulation as "digital noise shaping multi-bit Delta-Sigma modulator"), solving multi-bit Delta
  • the nonlinear problem of the multi-bit feedback DAC in the -Sigma modulator as a core component of the Delta-Sigma analog-to-digital converter, can be applied to high-speed, high-precision analog-to-digital conversion.
  • the present invention also proposes a design method thereof, that is, constructing digital noise shaping multi-bit De l ta-S from a conventional Delta-Sigma modulator.
  • the construction of the igma modulator and the signal shunting method taken to make the modulator work more stable.
  • this embodiment first constructs a fourth-order low-pass digital noise shaping multi-bit De 11 aS i gma modulator from a conventional modulator; secondly, internal signal shunting is performed on the modulator; finally, the modulator is illustrated The working principle, and the performance simulation results of the modulator are given.
  • the conventional fourth-order pass-through multi-bit Delta-Sigma modulator is shown in FIG. 9, and the method for constructing a digital noise shaping multi-bit De 11 aS i gma modulator described above can be implemented by structural transformation.
  • the path filter 912 contains two transfer functions L. Separating, the modulator structure shown in FIG. 10 is obtained; in the second step, the filter 1018 shown in FIG. 10 is transferred to the side of the digital circuit to obtain a modulator structure as shown in FIG. 11, which is the implementation.
  • both the analog filter 1109 and the digital loop filter 1118 are composed of integrators, and the integrators are also connected in series, since the integrator has a cumulative effect, when modulation When the device starts to work, the amplitude of the output voltage of these analog integrators will increase greatly, and the absolute value of the output value of the digital integrator will also expand greatly, especially the output of the post-integrator will explode, according to The modulator internal signal shunting method described above can avoid this by signal shunting.
  • the nodes 1122, 1124, 1126, and 1128 before the digital integrators 1110, 1111, 1112, and 1113 are signal shunt nodes; and in the second step, the signal shunts are inserted at the nodes 1122, 1124, 1126, and 1128, respectively.
  • the modulator structure shown in Fig. 12 is obtained, in which the signal splitters 1218, 1219, 1220 and 1221 decompose the respective input signals V ( , v ⁇ z) ⁇ V "( and V to obtain the derived shunt signal They are 1 ⁇ 4( , 1 ⁇ 4'( , , and ( , these signals satisfy the following relationship:
  • V(z) V 1 (z) + V 2 (z)
  • V z) V; (z) + V 2 (z) ( ? )
  • V z) V;(z) + V;(z)
  • V" z) V; (z) + V; ⁇ z)
  • the derived signals ( , v; (z) , and ( are all digital signals, fed back to the analog filter Before the signals of 1209 are fed into the node, they need to be converted into corresponding analog signals, which are shown in Figure 1 ⁇ 4 ⁇ , ⁇ ;( ⁇ ), ⁇ and (after inserting the feedback DAC)
  • the modulator structure shown in Fig. 13; the fourth step, in Fig. 13, shows that the shunt signals 1 ⁇ 4 ⁇ , ( , ( and V' (the transfer functions before the paths 1334, 1335, 1336, and 1337 flow to the adder 1329) are observed.
  • nodes 1330, 1331, 1332, and 1333 as shown in Figure 13 are the corresponding shunt signal feed nodes, and the adders are inserted at these nodes to obtain Figure 14
  • the illustrated modulator structure which is a fourth-order low-pass digital noise shaping multi-bit Delta-Sigma modulator optimized by signal shunting, ends the internal signal shunting process of the entire modulator.
  • the fourth-order low-pass digital noise shaping multi-bit Delta-Sigma modulator consists of an analog filter 1509, a digital loop filter 1522, a multi-bit quantizer 1523, a multi-bit feedback DAC 1524, and a shunt signal feedback DAC ( 1525, 1526, 1527, 1528), and analog adder 1533.
  • the analog filter 1509 adopts a distributed feedforward structure, consisting of four cascaded analog integrators (1501, 1502, 1503, 1504) and four with certain gain coefficients ("1", 1505, 1506, 1507).
  • the feedforward branch, feedforward analog adder 1508 and four shunt signals are fed into the adders (1529, 1530, 1531, 1532); the digital loop filter 1522 also uses a distributed feedforward structure, consisting of four cascades Digital integrator (1510, 1511, 1512, 1513), three feedforward branches with a certain gain factor (1514, 1515, 1516), feedforward digital adder 1517 and four signal splitters (1518, 1519, 1520, 1521), U (z) represents the input analog signal of the modulator, V (z) represents the output digital signal of the modulator, and E Q (z) represents the quantization noise of the multi-bit quantizer 1523, E D (z) Indicates the mismatch noise of the multi-bit feedback DAC1524.
  • a distributed feedforward structure consisting of four cascades Digital integrator (1510, 1511, 1512, 1513), three feedforward branches with a certain gain factor (1514, 1515, 1516), feedforward digital adder 1517 and four signal splitters (1518, 1519
  • the analog filter 1509 is used to pre-modulate the input analog signal U(z) into a ( ⁇ )4[/( z ) signal
  • the digital loop filter 1522 is used to shape the quantization noise E Q (z), mismatch noise E D (z) and pre-modulation signal ( ⁇ ) 4 [/(, multi-bit quantizer 1523 is used to convert the analog signal output from the analog adder 1533 into a corresponding multi-bit digital signal
  • the multi-bit feedback DAC 1524 is used to digitally loop
  • the multi-bit digital signal outputted by the filter 1522 is converted into a corresponding analog signal
  • the analog adder 1533 is used to sum the output signals of the analog filter 1509 and the multi-bit feedback DAC 1524, the signal splitter 1518, 1519, 1520, 1521, the shunt signal Feedback DACs 1525, 1526, 1527, 1528 and shunt signals are fed to adders 1529, 1530, 1531, 1532 for signal shunting and feedback.
  • the input analog signal u(z) is analog filter 1509.
  • V(z) U(z) + (lZ- 1 ) 4 E Q (z)-(lZ- 1 ) 4 E D (z) ( 8 )
  • the modulator has a fourth-order noise shaping low-pass performance, and the input signal U(z) can pass directly through the modulator, while the quantization noise E Q (z) and the mismatch noise E D (z) At the same time, it is subject to 4th order shaping.
  • the SNDR Siena 1 o noisy s + Di st.ort. i on Ra io
  • the corresponding modulator model is established by using Ma tLab S imuL ink.
  • the key parameters of the model are as follows:
  • Multi-bit quantizer 1523 uses a 5-bit ideal model
  • the DAC1524 uses a 5-bit non-ideal model with a 1% mismatch between the DAC unit components;
  • shunt signal feedback DAC1525, 1526, 1527, 1528 use a one-bit model; d) the input signal frequency is 129394. 53125HZ;
  • a spectrum diagram of the modulator output signal SNDR as shown in FIG. 16 and a relationship between the modulator output signal SNDR and the input signal amplitude as shown in FIG. 17 can be obtained.
  • the ideal modulator cylinder with an ideal multi-bit feedback DAC is called an "ideal modulator”; the conventional modulator cylinder with a non-ideal multi-bit feedback DAC is called “non-ideal”.
  • a digital noise shaping multi-bit De ta-S i gma modulator cylinder with a non-ideal multi-bit feedback DAC is referred to as a "non-ideal digital noise shaping modulator.”
  • the dashed line, the solid thin line, and the solid thick line represent the output signal spectrum of the "ideal modulator”, “non-ideal modulator”, and “non-ideal digital noise shaping modulator”, respectively.
  • the noise floor is raised, and there are significant 3rd and 5th harmonics in the band, causing the maximum SNDR to drop sharply to 72.8dB, and the low-frequency part of the noise exhibits a horizontal shape, which indicates the traditional modulation.
  • the mismatch noise E D (z) of the multi-bit feedback DAC has no shaping function.
  • the noise floor is almost overlapped with the "ideal modulator”, and the maximum SNDR is maintained at 117. 8dB (the maximum SNDR of the "ideal modulator” is 116. 3dB).
  • the noise rises at a slope of 80dB/decade, which indicates that the digital noise shaping multi-bit De ta-S i gma modulator of the present invention can perform quantization noise E Q (z) and multi-bit feedback DAC mismatch noise E D (z) performs good shaping at the same time (this example is fourth-order noise shaping).
  • this example is fourth-order noise shaping
  • the dotted line, the solid thin line, and the solid thick line respectively represent the relationship between the output signal SNDR of the "ideal modulator", “non-ideal modulator”, and “non-ideal digital noise shaping modulator” and the input signal amplitude, Comparing the three, the SNDR of the "non-ideal digital noise shaping modulator” output signal is about 40 dB higher than the SNDR of the "non-ideal modulator” output signal, and the "non-ideal digital noise” is almost the entire range of the input signal amplitude.
  • the shaped modulator's SNDR of the output signal is almost equal to the SNDR of the "ideal modulator" output signal, which indicates that the digital noise shaping multi-bit De ta-S i gma modulator of the present invention has robust stability.
  • this modulator can effectively solve multiple bits

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Abstract

A modulator and a design method thereof are provided. The modulator includes an analog filter (11) for pre-modulating input analog signals; an analog adder (15) for summing the analog signals; a multi-bit quantizer (13) for converting the sum of the analog signals into multi-bit digital signals output; a digital loop filter (12) for filtering the multi-bit digital signals output from the multi-bit quantizer (13); and a multi-bit feedback digital-to-analog converter (14) for converting the filtered multi-bit digital signals to feedback analog signals. Steady modulators may be constructed rapidly according to this solution. The problem of non-linearity of the multi-bit feedback digital-to-analog converter can be solved by adopting the digital loop filter to shape the quantization noise and the mismatch noise simultaneously. The modulator has the stability and the ability of noise shaping, and can be used in high speed and high precision digital-to-analog conversion.

Description

一种调制器及其设计方法  Modulator and design method thereof

技术领域 Technical field

本发明涉及模数转换, 具体地说涉及一种调制器及其设计方法。 背景技术  This invention relates to analog to digital conversion, and more particularly to a modulator and method of designing same. Background technique

由于 Delta-Sigma (△_∑ )调制器工作时需要过采样, 传统上基于 Delta-Sigma 调制器的 ADC (模说数转换器)主要应用于低速、 高精度的领 域, 比如: 音频系统、 仪器设备等等, 随着通信系统向宽带方向发展, 高 速、 高精度 ADC 的需求与日倶增。 Delt书a-Sigma调制器要实现高速、 高精 度的性能必然要降低过采样率, 同时需要增加环路滤波器的阶数或者增加 量化器的位数来弥补信噪比的损失。  Since the Delta-Sigma (Δ_∑) modulator requires oversampling during operation, the Delta-Sigma modulator-based ADC (modular-to-digital converter) is mainly used in low-speed, high-precision fields such as audio systems and instruments. Equipment, etc. As communication systems move toward broadband, the demand for high-speed, high-precision ADCs is increasing. To achieve high-speed, high-precision performance, the Delt book a-Sigma modulator must reduce the oversampling rate. At the same time, it is necessary to increase the order of the loop filter or increase the number of bits of the quantizer to compensate for the loss of signal-to-noise ratio.

尽管增加环路滤波器的阶数或者增加量化器的位数这两种方案均有 利于提高调制器的性能,然而在量化器位数为 1的条件下,超过 2 阶的环 路滤波器很难保证系统的稳定;而增加量化器位数不仅可以减小量化噪声, 且可以增强系统的稳定。所以多位量化是高性能 Delta-Sigma 调制器的发 展趋势。  Although increasing the order of the loop filter or increasing the number of bits of the quantizer is beneficial to improve the performance of the modulator, under the condition that the quantizer has a bit number of 1, the loop filter of more than 2 orders is very It is difficult to ensure the stability of the system; increasing the number of quantizers not only reduces the quantization noise, but also enhances the stability of the system. So multi-bit quantization is the development trend of high performance Delta-Sigma modulators.

多位 Delta-Sigma 调制器有个很苛刻的要求: 多位反馈 DAC (数模转 换器) 的精度需要达到或超过整个调制器的精度, 但现有的工艺制造技术 很难使多位反馈 DAC达到高精度指标(比如 16位或更高精度)。 这是由于 基本单位元件间的匹配误差(或称为失配)造成了多位反馈 DAC的非线性, 它使调制器产生谐波失真, 在调制器输出信号的频谱中表现为尖锐的谐波 毛刺, 带内的谐波毛刺可导致调制器信噪比极大降低, 所以, 多位 Delta-Sigma调制器的主要问题是反馈 DAC的非线性。  Multi-bit Delta-Sigma modulators have a very demanding requirement: The accuracy of a multi-bit feedback DAC (digital-to-analog converter) needs to meet or exceed the accuracy of the entire modulator, but existing process manufacturing techniques are difficult to make multi-bit feedback DACs Achieve high-precision indicators (such as 16-bit or higher). This is due to the fact that the matching error (or mismatch) between the basic unit components causes the nonlinearity of the multi-bit feedback DAC, which causes the modulator to produce harmonic distortion, which appears as a sharp harmonic in the spectrum of the modulator output signal. Glitch, in-band harmonic glitch can cause the modulator signal-to-noise ratio to be greatly reduced, so the main problem with multi-bit Delta-Sigma modulators is the nonlinearity of the feedback DAC.

针对多位反馈 DAC的非线性问题, 已有的解决方法包括: 激光修正或 模拟校正、 数字校正、 双量化器结构、 DEM ( Dynamic Element Matching, 动态元件匹配)技术、 PWM (Pulse WidthModulation, 脉沖宽度调制) 技 术等等。 迄今最主流的解决方法有三:  For the nonlinear problem of multi-bit feedback DAC, the existing solutions include: laser correction or analog correction, digital correction, dual quantizer structure, DEM (Dynamic Element Matching) technology, PWM (Pulse WidthModulation, pulse width) Modulation) technology and so on. The most mainstream solutions to date have three:

其一,背景数字校正。背景数字校正可以艮好地消除 DAC非线性影响, 但电路结构非常复杂。  First, the background number is corrected. Background digital correction can eliminate the nonlinear effects of DAC, but the circuit structure is very complicated.

其二, 级联双量化器结构 (即双量化器 MASH 结构)。 级联双量化器 结构一般是前若干级使用 1位反馈 DAC ,末级使用多位反馈 DAC ,该结构可 以整形多位反馈 DAC的失配噪声, 但失配噪声的整形阶数比量化噪声的整 形阶数至少低一阶, 并且级间耦合系数会放大量化噪声和失配噪声, 这些 都会导致调制器性能下降。 另外, 为了避免过大的噪声泄漏, 该结构对模 拟电路提出了很高要求。 Second, the cascaded dual quantizer structure (ie, the dual quantizer MASH structure). Cascaded dual quantizer The structure generally uses a 1-bit feedback DAC for the first few stages and a multi-bit feedback DAC for the final stage. This structure can shape the mismatch noise of the multi-bit feedback DAC, but the shaping order of the mismatch noise is at least lower than the shaping order of the quantization noise. The first order, and the interstage coupling coefficient amplifies the quantization noise and mismatch noise, which all lead to a decrease in modulator performance. In addition, this structure places high demands on analog circuits in order to avoid excessive noise leakage.

其三, DEM技术。根据反馈 DAC 失配噪声被整形的阶数不同, DEM技 术可以分成两大类, 其一, 低阶失配噪声整形 DEM技术(包括 0 阶和 1 阶); 其二, 高阶失配噪声整形 DEM技术 (包括 2阶和更高阶)。 低阶失 配噪声整形 DEM技术在不同程度上可以削弱多位反馈 DAC 非线性的影 响,但它们存在噪声本底高、带内谐波毛刺大以及 DAC 噪声和谐波失真随 输入信号幅 度波动的问题; 高阶失配噪声整形 DEM技术可以更好地削弱 多位反馈 DAC 非线性的影响,但是, 它们不仅电路结构复杂, 而且存在不 稳定问题。  Third, DEM technology. According to the different order of the feedback DAC mismatch noise shaping, DEM technology can be divided into two categories, first, low-order mismatch noise shaping DEM technology (including 0th order and 1st order); second, high-order mismatch noise shaping DEM technology (including 2nd order and higher order). Low-order mismatched noise shaping DEM technology can weaken the nonlinear effects of multi-bit feedback DACs to varying degrees, but they have high noise floor, large in-band harmonic spurs, and DAC noise and harmonic distortion with input signal amplitude fluctuations. Problem; High-order mismatched noise shaping DEM technology can better attenuate the nonlinear effects of multi-bit feedback DACs, but they are not only complicated in circuit structure, but also unstable.

总之,如何更好地解决多位反馈 DAC的非线性问题,仍有改进的空间。 发明内容  In short, there is still room for improvement in how to better solve the nonlinear problem of multi-bit feedback DACs. Summary of the invention

本发明所要解决的技术问题是, 提供一种调制器及其设计方法, 能够 较好地解决多位反馈 DAC的非线性问题。  The technical problem to be solved by the present invention is to provide a modulator and a design method thereof, which can better solve the nonlinear problem of the multi-bit feedback DAC.

为解决上述技术问题, 本发明采用了以下技术方案:  In order to solve the above technical problems, the present invention adopts the following technical solutions:

一种调制器, 用于模数转换, 包括模拟滤波器、 模拟加法器、 多位量 化器、 数字环路滤波器、 多位反馈数模转换器, 所述模拟滤波器用于对输 入模拟信号进行预调制, 并输出到所述模拟加法器的一个输入端, 所述模 拟加法器用于模拟信号求和, 并输出到所述多位量化器, 所述多位量化器 用于将模拟信号和转换为多位数字信号输出; 所述数字环路滤波器用于对 多位量化器输出的多位数字信号滤波,并输出到所述多位反馈数模转换器, 所述多位反馈数模转换器用于将滤波后的多位数字信号转换为反馈模拟信 号, 并输出到所述模拟加法器的另一输入端。  A modulator for analog to digital conversion, comprising an analog filter, an analog adder, a multi-bit quantizer, a digital loop filter, a multi-bit feedback digital-to-analog converter, the analog filter is used to input an analog signal Premodulating and outputting to an input of the analog adder, the analog adder is used for summing analog signals and outputting to the multi-bit quantizer, the multi-bit quantizer is used to convert the analog signal into a multi-bit digital signal output; the digital loop filter is configured to filter a multi-bit digital signal output by the multi-bit quantizer and output to the multi-bit feedback digital-to-analog converter, wherein the multi-bit feedback digital-to-analog converter is used The filtered multi-bit digital signal is converted to a feedback analog signal and output to the other input of the analog adder.

在本发明的一种实施例中, 所述调制器还包括至少一条分流反馈支 路, 每一所述分流反馈支路输入端连接于所述数字环路滤波器中的一个信 号分流节点, 输出端连接于所述模拟滤波器中的一个对应的分流信号馈入 节点, 每一所述分流反馈支路从输入端到输出端依次设置有信号分流器、 分流反馈数模转换器、 加法器。 In an embodiment of the present invention, the modulator further includes at least one shunt feedback branch, and each of the shunt feedback branch inputs is connected to one of the digital loop filters, and outputs The terminal is connected to a corresponding shunt signal feeding node of the analog filter, and each of the shunt feedback branches is provided with a signal shunt, a shunt feedback digital-to-analog converter and an adder from the input end to the output end.

f 太 *昍 —^? s: ^Αΐ, . ¾ W 々軎古 S夂 frfr 入 右 县 1位数字信号或多位数字信号。 f too *昍—^? s: ^Αΐ, . 3⁄4 W 々軎古 S夂frfr into the right county 1-bit digital signal or multi-bit digital signal.

在本发明的一种实施例中, 所述调制器为 Del ta-S igma调制器。  In one embodiment of the invention, the modulator is a Delta-Sigma modulator.

本发明还提供了一种模数转换器, 包含上述的调制器。  The present invention also provides an analog to digital converter comprising the modulator described above.

本发明也提供了一种调制器的构造方法, 用于从第一调制器构造第二 调制器, 所述第一调制器包含模拟环路滤波器、 多位量化器、 多位反馈数 模转换器, 所述模拟环路滤波器的一输入端接受模拟信号输入, 输出端连 接所述多位量化器的输入端,所述多位量化器的输出端输出多位数字信号, 并连接所述多位反馈数模转换器的输入端, 所述多位反馈数模转换器的输 出端连接所述模拟环路滤波器的另一输入端,所述构造方法包含如下步骤: 将所述模拟环路滤波器分解为第一模拟滤波器和第二模拟滤波器, 增 设模拟加法器, 按如下方式调整器件连接: 所述模拟加法器的两个输入端 分别连接所述第一模拟滤波器和第二模拟滤波器的输出端, 输出端连接所 述多位量化器的输入端, 所述第一模拟滤波器接受模拟信号输入, 所述第 二模拟滤波器的输入端连接所述多位反馈数模转换器的输出端;  The present invention also provides a method of constructing a modulator for constructing a second modulator from a first modulator, the first modulator comprising an analog loop filter, a multi-bit quantizer, and a multi-bit feedback digital-to-analog conversion An input end of the analog loop filter receives an analog signal input, and an output end is connected to an input end of the multi-bit quantizer, and an output end of the multi-bit quantizer outputs a multi-bit digital signal, and is connected to the An input end of the multi-bit feedback digital-to-analog converter, the output end of the multi-bit feedback digital-to-analog converter is connected to another input end of the analog loop filter, and the constructing method comprises the following steps: The path filter is decomposed into a first analog filter and a second analog filter, and an analog adder is added, and the device connection is adjusted as follows: two input ends of the analog adder are respectively connected to the first analog filter and the first An output end of the second analog filter, the output end is connected to the input end of the multi-bit quantizer, the first analog filter accepts an analog signal input, and the second analog filter Into multi-bit output terminal connected to the terminal of the feedback DAC;

将第二模拟滤波器调整为数字环路滤波器, 按如下方式调整器件连接 从而构造出第二调制器: 所述数字环路滤波器的输入端连接所述多位量化 器的输出端, 输出端连接所述多位反馈数模转换器的输入端, 所述多位反 馈数模转换器的输出端连接所述加法器的一输入端。  Adjusting the second analog filter to a digital loop filter, adjusting the device connection as follows to construct a second modulator: the input of the digital loop filter is connected to the output of the multi-bit quantizer, and the output The terminal is connected to an input end of the multi-bit feedback digital-to-analog converter, and an output end of the multi-bit feedback digital-to-analog converter is connected to an input end of the adder.

本发明也提供一种调制器的信号分流方法, 所述调制器用于模数转 换, 包括模拟滤波器、 模拟加法器、 多位量化器、 数字环路滤波器、 多位 反馈数模转换器, 所述模拟滤波器用于对输入模拟信号进行预调制, 并输 出到所述模拟加法器的一个输入端, 所述模拟加法器用于模拟信号求和, 并输出到所述多位量化器, 所述多位量化器用于将模拟信号和转换为多位 数字信号输出; 所述数字环路滤波器用于对多位量化器输出的多位数字信 号滤波, 并输出到所述多位反馈数模转换器, 所述多位反馈数模转换器用 于将滤波后的多位数字信号转换为反馈模拟信号, 并输出到所述模拟加法 器的另一输入端; 所述信号分流方法包括如下步骤:  The invention also provides a signal splitting method for a modulator, the modulator being used for analog-to-digital conversion, including an analog filter, an analog adder, a multi-bit quantizer, a digital loop filter, a multi-bit feedback digital-to-analog converter, The analog filter is configured to pre-modulate an input analog signal and output to an input of the analog adder, the analog adder is used for summing analog signals, and outputting to the multi-bit quantizer, a multi-bit quantizer for converting an analog signal to a multi-bit digital signal output; the digital loop filter for filtering a multi-bit digital signal output by the multi-bit quantizer and outputting to the multi-bit feedback digital-to-analog converter The multi-bit feedback digital-to-analog converter is configured to convert the filtered multi-bit digital signal into a feedback analog signal and output to another input end of the analog adder; the signal shunting method includes the following steps:

确定所述数字环路滤波器中的至少一个信号分流节点;  Determining at least one signal shunt node of the digital loop filter;

设置至少一条分流反馈支路, 每一所述分流反馈支路的输入端连接于 一个所述信号分流节点, 并从输入端依次设置信号分流器、 分流反馈数模 转换器、 加法器;  And providing at least one shunt feedback branch, wherein the input end of each of the shunt feedback branches is connected to one of the signal shunt nodes, and a signal shunt, a shunt feedback digital-to-analog converter, and an adder are sequentially disposed from the input end;

将每一所述分流反馈支路的加法器插入到所述模拟滤波器的一个对 通过本发明提供的调制器结构, 可以实现量化噪声和失配噪声的同时 整形, 有效解决调制器中的多位反馈 DAC的非线性问题。 附图说明 Inserting an adder of each of the shunt feedback branches into a pair of the analog filters Through the modulator structure provided by the invention, simultaneous shaping of quantization noise and mismatch noise can be realized, and the nonlinear problem of the multi-bit feedback DAC in the modulator can be effectively solved. DRAWINGS

图 1是本发明一种实施例的数字噪声整形多位 Delta-Sigma调制器原 始结构图;  1 is a diagram showing the original structure of a digital noise shaping multi-bit Delta-Sigma modulator according to an embodiment of the present invention;

图 2是通用的传统 Delta-Sigma 调制器结构框图;  Figure 2 is a block diagram showing the structure of a general-purpose conventional Delta-Sigma modulator;

图 3是与图 2等价的通用的传统 Delta-Sigma 调制器结构框图; 图 4 是本发明一种实施例的含有累积单元的数字噪声整形多位 3 is a block diagram showing the structure of a conventional conventional Delta-Sigma modulator equivalent to FIG. 2; FIG. 4 is a digital noise shaping multi-bit including an accumulation unit according to an embodiment of the present invention;

Delta-Si gma调制器原始结构图; Original structure diagram of Delta-Si gma modulator;

图 5 ~7 是本发明一种实施例的含有累积单元的数字噪声整形多位 5 to 7 are digital noise shaping multi-bits including accumulation units according to an embodiment of the present invention

De lta-Si gma调制器内部信号分流过程的示意图; Schematic diagram of the internal signal shunting process of the De lta-Si gma modulator;

图 8是本发明一种实施例的经过信号分流优化的含有累积单元的数字 噪声整形多位 De 11 a- S i gma调制器结构图;  8 is a structural diagram of a digital noise shaping multi-bit De 11 a-S i gma modulator with accumulation unit optimized by signal shunting according to an embodiment of the present invention;

图 9是传统的四阶 通多位 Delta- Sigma调制器结构图;  Figure 9 is a block diagram of a conventional fourth-order multi-bit Delta-Sigma modulator;

图 10是与图 9等价的传统的四阶低通多位 Delta-Sigma调制器结构 图;  Figure 10 is a structural diagram of a conventional fourth-order low-pass multi-bit Delta-Sigma modulator equivalent to Figure 9;

图 11是本发明一种实施例的四阶低通数字噪声整形多位 De 11 a-S i gma 调制器原始结构图;  11 is a diagram showing an original structure of a fourth-order low-pass digital noise shaping multi-bit De 11 a-S i gma modulator according to an embodiment of the present invention;

图 12 ~ 14 是本发明一种实施例的四阶低通数字噪声整形多位 De lta-Si gma调制器内部信号分流过程的示意图;  12 to 14 are schematic diagrams showing the internal signal shunting process of a fourth-order low-pass digital noise shaping multi-bit De lta-Si gma modulator according to an embodiment of the present invention;

图 15 是本发明一种实施例的经过信号分流优化的四阶低通数字噪声 整形多位 De 1 ta-Sigma调制器结构图;  15 is a structural diagram of a fourth-order low-pass digital noise shaping multi-bit De 1 ta-Sigma modulator optimized by signal shunting according to an embodiment of the present invention;

图 16是三种调制器输出信号 SNDR达到最大时的频谱;  Figure 16 is the spectrum when the three modulator output signals SNDR reach the maximum;

图 17是三种调制器输出信号 SNDR与输入信号幅度的关系曲线。 具体实施方式  Figure 17 is a plot of the three modulator output signals, SNDR, versus the input signal amplitude. detailed description

下面通过具体实施方式结合附图对本发明作进一步详细说明。  The present invention will be further described in detail below with reference to the accompanying drawings.

本发明主要涉及模数转换, 具体地说涉及一种 Delta-Sigma模数转换 器, 尤其是其中的核心部件 -多位 Delta-Sigma 调制器, 目的是解决多位 The present invention relates generally to analog-to-digital conversion, and more particularly to a Delta-Sigma analog-to-digital converter, and in particular to a core component thereof, a multi-bit Delta-Sigma modulator, for the purpose of solving multiple bits.

De lta-Si gma调制器中的多位反馈 DAC的非线性问题。 Nonlinear problems with multi-bit feedback DACs in De lta-Si gma modulators.

Delta-Sigma模数转换器, 其应用领域非常广泛, 比如: 安防、 音频、 如音频系统、 仪器设备等。 Delta- Sigma调制器是 Delta- Sigma模数转换 器的一个核心部件,基于本发明的多位 De 11 a- S i gma调制器的 De 1 ta-S i gma 模数转换器, 可应用于高速、 高精度的模数转换。 Delta-Sigma analog-to-digital converters are used in a wide range of applications, such as: security, audio, Such as audio systems, equipment and so on. The Delta-Sigma modulator is a core component of the Delta-Sigma analog-to-digital converter. The De 1 ta-S i gma analog-to-digital converter based on the multi-bit De 11 a- S i gma modulator of the present invention can be applied to high speed. , high precision analog to digital conversion.

以下对本发明的具体实施方式进行阐述, 由于本发明的基本发明构思 是采用数字环路滤波器实现噪声 (包括量化噪声、 反馈 DAC失配噪声 )整 形, 因此, 称该调制器为数字噪声整形多位 Delta-Sigma调制器, 并将主 要从三个方面对该调制器进行介绍,包括:数字噪声整形多位 Delta-Sigma 调制器、 从传统 De lta-Si gma调制器构造数字噪声整形多位 Del ta-S i gma 调制器的方法及数字噪声整形多位 Delta-Sigma 调制器内部信号分流的 方法。  The specific embodiments of the present invention are described below. Since the basic inventive concept of the present invention is to implement noise shaping (including quantization noise, feedback DAC mismatch noise) by using a digital loop filter, the modulator is called digital noise shaping. Bit Delta-Sigma modulator, and will introduce the modulator mainly from three aspects, including: digital noise shaping multi-bit Delta-Sigma modulator, constructing digital noise shaping multi-bit Del from traditional Delta-Si gma modulator The ta-S i gma modulator method and the digital noise shaping method of the multi-bit Delta-Sigma modulator internal signal shunt.

第一方面, 本发明提出一种数字噪声整形多位 Delta-Sigma调制器, 它是一种普遍通用的系列化的多位 De 11 a-S i gma调制器, 用户可以根据需 要, 通过设计滤波器实现一系列特定性能的信号传递函数( STF )和噪声传 递函数(NTF)。 数字噪声整形多位 Delta-Sigma调制器原始结构如图 1所 示, 它主要包括模拟滤波器 11、 数字环路滤波器 12、 多位量化器 13、 多 位反馈 DAC 14、 模拟加法器 15。 其中, U(z)表示调制器的输入模拟信号, V(z)表示调制器的输出数字信号, Y(z)表示多位量化器 13 的输入模拟信 号, EQ(z)表示多位量化器 13的量化噪声, ED(z)表示多位反馈 DAC14的失 配噪声。 模拟滤波器 11用于把输入模拟信号 U(z)预调制成 L。*U(z)信号, 数字环路滤波器 12用于整形量化噪声 EQ(z)、失配噪声 ED (z)和预调制信号 L。* U (z) ,多位量化器 13用于把模拟信号 Y (z)转换成相应的多位数字信号, 多位反馈 DAC 14用于把数字环路滤波器 12输出的多位数字信号转换成相应 的模拟信号(为区分前述输入模拟信号, 称之为反馈模拟信号),模拟加法 器 15用于模拟滤波器 11与多位反馈 DAC14输出信号 (反馈模拟信号) 的 求和(模拟信号和, 即多位量化器 13的输入模拟信号 Y(z) )。 In a first aspect, the present invention provides a digital noise shaping multi-bit Delta-Sigma modulator, which is a universally-used serialized multi-bit De 11 aS i gma modulator, which can be implemented by a user by designing a filter as needed. A series of specific performance signal transfer functions (STF) and noise transfer functions (NTF). The original structure of the digital noise shaping multi-bit Delta-Sigma modulator is shown in FIG. 1. It mainly includes an analog filter 11, a digital loop filter 12, a multi-bit quantizer 13, a multi-bit feedback DAC 14, and an analog adder 15. Where U(z) represents the input analog signal of the modulator, V(z) represents the output digital signal of the modulator, Y(z) represents the input analog signal of the multi-bit quantizer 13, and E Q (z) represents multi-bit quantization The quantization noise of the device 13, E D (z), represents the mismatch noise of the multi-bit feedback DAC 14. The analog filter 11 is used to pre-modulate the input analog signal U(z) to L. *U(z) signal, digital loop filter 12 is used to shape quantization noise E Q (z), mismatch noise E D (z), and pre-modulation signal L. * U (z), the multi-bit quantizer 13 is used to convert the analog signal Y (z) into a corresponding multi-bit digital signal, and the multi-bit feedback DAC 14 is used to convert the multi-bit digital signal output from the digital loop filter 12 A corresponding analog signal (to distinguish the aforementioned input analog signal, referred to as a feedback analog signal), the analog adder 15 is used for summing the analog filter 11 and the multi-bit feedback DAC 14 output signal (feedback analog signal) (analog signal sum That is, the input analog signal Y(z) of the multi-bit quantizer 13.

该调制器正常工作时, 首先, 输入模拟信号 U(z)被模拟滤波器 11预 调制成 L。*U(z)信号,接着, L。*U(z)信号、量化噪声 EQ(z)和失配噪声 ED(z) 一起注入包含有数字环路滤波器 12的反馈环路,最后,这些信号都被数字 环路滤波器 12整形后从调制器输出。 根据图 1, 经过推导可得: When the modulator is operating normally, first, the input analog signal U(z) is pre-modulated to L by the analog filter 11. *U(z) signal, then, L. The *U(z) signal, the quantization noise E Q (z), and the mismatch noise E D (z) are injected together into a feedback loop including the digital loop filter 12, and finally, these signals are all subjected to the digital loop filter 12 After shaping, it is output from the modulator. According to Figure 1, after derivation:

V(z)=-^-U(z) + -^—EQ(z)--^—ED(z) ( 1 ) V(z)=-^-U(z) + -^—E Q (z)--^—E D (z) ( 1 )

l + ^ l + Z^ l + ^  l + ^ l + Z^ l + ^

(其中, 信号传递函数为: STF i (where the signal transfer function is: STF i

1 + L, 量化噪声传递函数为: NTF0 1 + L, The quantization noise transfer function is: NTF 0

l + Z^ 失配噪声传递函数为: NTFD = -一―) l + Z^ The mismatch noise transfer function is: NTF D = - one -)

1 +  1 +

由(1)式可知, 通过设计适当的滤波器 11和 12可以实现一系列特定 性能的 STF和 NTF (比如 LP (低通)、 BP (带通)、 HP (高通)等等 ), 并且 (1)式也表明量化噪声 EQ(z)和失配噪声 ED (z)可以同时被整形, 例如: 取 = ( -)^ = (T.i , 把它们代入 (1 ) 式可得: As can be seen from equation (1), a series of specific performances of STF and NTF (such as LP (low pass), BP (band pass), HP (high pass), etc.) can be realized by designing appropriate filters 11 and 12, and Equation 1) also shows that the quantization noise E Q (z) and the mismatch noise E D (z) can be shaped at the same time, for example: Take = ( -)^ = ( - T .i , substituting them into (1) :

ΰ Z-1 Z-l  ΰ Z-1 Z-l

V(z) = U(z) + (l-Z-1)"Ee(z)-(l-Z-1)"ED(z) ( 2 ) V(z) = U(z) + (lZ- 1 ) "E e (z)-(lZ- 1 )"E D (z) ( 2 )

(2)式表明多位量化器 13的量化噪声 EQ(z)和多位反馈 DAC14的失配 噪声 ED(z)同时受到了 n阶噪声整形,因此,数字噪声整形多位 Delta-Sigma 调制器可以有效解决多位 Delta-Sigma调制器反馈 DAC的非线性问题。 Equation (2) shows that the quantization noise E Q (z) of the multi-bit quantizer 13 and the mismatch noise E D (z) of the multi-bit feedback DAC 14 are simultaneously subjected to n-order noise shaping, and therefore, digital noise shaping multi-bit Delta-Sigma The modulator can effectively solve the nonlinear problem of multi-bit Delta-Sigma modulator feedback DAC.

综上, 本发明的调制器结构及信号流向是: 模拟滤波器 11 对输入模 拟信号 U(z)进行预调制, 并输出到模拟加法器 15的一个输入端, 模拟加 法器 15进行模拟信号求和,得到模拟信号和 Y (z)并输出到多位量化器 13, 多位量化器 13将模拟信号和 Y (z)转换为多位数字信号 V (z)输出; 数字环 路滤波器 12对多位量化器 13输出的多位数字信号 V(z)滤波,并输出到多 位反馈 DAC14, 多位反馈 DAC14将滤波后的多位数字信号转换为反馈模拟 信号, 并输出到模拟加法器 15的另一输入端。  In summary, the modulator structure and signal flow direction of the present invention are: The analog filter 11 pre-modulates the input analog signal U(z) and outputs it to an input terminal of the analog adder 15, and the analog adder 15 performs an analog signal request. And, the analog signal and Y (z) are obtained and output to the multi-bit quantizer 13, and the multi-bit quantizer 13 converts the analog signal and Y (z) into a multi-bit digital signal V (z) output; the digital loop filter 12 The multi-bit digital signal V(z) outputted by the multi-bit quantizer 13 is filtered and output to the multi-bit feedback DAC 14, and the multi-bit feedback DAC 14 converts the filtered multi-bit digital signal into a feedback analog signal and outputs it to the analog adder. The other input of 15.

第二方面, 为了更快捷地构造如图 1 所示的数字噪声整形多位 Delta-Sigma调制器, 本发明提出一种从传统 Delta-Sigma调制器构造数 字噪声整形多位 Delta-Sigma调制器的方法。 该方法的基本思想是: 从传 统的 Delta-Sigma调制器出发, 把反馈环路的传递函数从模拟环路滤波器 中分离出来, 再把这个分离出来的传递函数转移到数字电路一侧, 并采用 数字电路来实现此传递函数。 该方法的基本原则是: 在调制器的反馈环路 中,把多位反馈 DAC失配噪声的注入节点转移到量化噪声的等价注入节点。 该构造方法的具体实施步骤是:  In a second aspect, in order to construct a digital noise shaping multi-bit Delta-Sigma modulator as shown in FIG. 1 more quickly, the present invention proposes a digital noise shaping multi-bit Delta-Sigma modulator constructed from a conventional Delta-Sigma modulator. method. The basic idea of the method is: From the traditional Delta-Sigma modulator, the transfer function of the feedback loop is separated from the analog loop filter, and the separated transfer function is transferred to the digital circuit side, and This transfer function is implemented using digital circuitry. The basic principle of the method is: In the feedback loop of the modulator, the injection node of the multi-bit feedback DAC mismatch noise is transferred to the equivalent injection node of the quantization noise. The specific implementation steps of the construction method are:

i)第一步, 分离传递函数  i) the first step, separate transfer function

通用的传统多位 Delta-Sigma调制器结构框图如图 2所示, 它由模拟 环路滤波器 21、 多位量化器 22和多位反馈 DAC23构成, 其中 U(z)表示调 制器的输入模拟信号, W(z)表示多位反馈 DAC23的输出模拟信号, V(z)表 示调制器的输出数字信号,Y(z)表示多位量化器 22 的输入模拟信号, EQ(z) 表示多位量化器 22的量化噪声, ED(z)表示多位反馈 DAC23的失配噪声, 并且 Y(z)与 U(z)、 W(z)存在如下关系: The general structure of the conventional multi-bit Delta-Sigma modulator is shown in Figure 2. It consists of an analog loop filter 21, a multi-bit quantizer 22, and a multi-bit feedback DAC23, where U(z) represents the input analog of the modulator. Signal, W(z) represents the output analog signal of the multi-bit feedback DAC23, V(z) table The output digital signal of the modulator is shown, Y(z) represents the input analog signal of the multi-bit quantizer 22, E Q (z) represents the quantization noise of the multi-bit quantizer 22, and E D (z) represents the loss of the multi-bit feedback DAC 23 With noise, and Y (z) and U (z), W (z) have the following relationship:

F(z) = L0[/(z)-Z1W(z) ( 3) F(z) = L 0 [/(z)-Z 1 W(z) ( 3)

根据图 2, 经过推导可得:  According to Figure 2, after derivation:

V(z)=^U(z) + -^—EQ(z)--^-ED(z) (4) V(z)=^U(z) + -^—E Q (z)--^-E D (z) (4)

l + ^ l + Z^ l + ^ 由(4)式可知, 通常情况下这种调制器无法整形多位反馈 DAC23 的失 配噪声 ED(z)。根据(3)式,把如图 2所示的模拟环路滤波器 21中的两个传 递函数 L。、 分离, 得到如图 3所示的调制器结构。 l + ^ l + Z^ l + ^ From (4), it is known that this modulator cannot normally shape the mismatch noise E D (z) of the multi-bit feedback DAC23. According to the formula (3), two transfer functions L in the analog loop filter 21 shown in Fig. 2 are used. Separation, resulting in a modulator structure as shown in FIG.

ii)第二步, 转移传递函数  Ii) the second step, transfer transfer function

把如图 3所示的滤波器 32转移到数字电路一侧, 就得到了如图 1所 示的数字噪声整形多位 Delta-Sigma调制器(注意: 在调制器设计实现过 程中,为节省功耗和面积,一些类型的数字环路滤波器 12可能需要等价变 换)。  The filter 32 shown in FIG. 3 is transferred to the side of the digital circuit, and a digital noise shaping multi-bit Delta-Sigma modulator as shown in FIG. 1 is obtained (Note: in the process of implementing the modulator design, in order to save power Consumption and area, some types of digital loop filter 12 may require equivalent conversion).

由此可见, 该方法可以快捷地构造数字噪声整形多位 Delta-Sigma调 制器。 通过观察可以发现, 在这个构造过程中, 唯一发生变化的是: 滤波 器 32与多位反馈 DAC34的位置互相对调, 这必然导致失配噪声传递函数 NTFD发生变化。 根据上文所述可知, 数字噪声整形多位 Delta-Sigma调制 器输入输出关系为: It can be seen that the method can quickly construct a digital noise shaping multi-bit Delta-Sigma modulator. It can be observed from observation that the only change in this construction process is that the position of the filter 32 and the multi-bit feedback DAC 34 are mutually adjusted, which inevitably causes the mismatch noise transfer function NTF D to change. According to the above, the digital noise shaping multi-bit Delta-Sigma modulator input and output relationship is:

V(z)=-^U(z)+-^—EQ(z)--^—ED(z) ( 5 ) V(z)=-^U(z)+-^—E Q (z)--^—E D (z) ( 5 )

l + ^ l + Z^ l + ^  l + ^ l + Z^ l + ^

比较(4) (5) 两式可知, 数字噪声整形多位 Delta-Sigma调制器的 信号传递函数( STF )、 量化噪声传递函数( NTF0 = )与传统调 Comparison (4) (5) Two types show that the digital noise shaping multi-bit Delta-Sigma modulator signal transfer function (STF), quantization noise transfer function (NTF 0 = ) and traditional tuning

l + Z^ Q l + Z^ 制器保持一致, 但失配噪声传递函数从 NrFD= (注

Figure imgf000009_0001
l + Z^ Q l + Z^ The controller remains consistent, but the mismatch noise transfer function is from NrF D = (Note)
Figure imgf000009_0001

意噪声是随机的,可忽略正负号),并且等于量化噪声传递函数。由此可见, 数字噪声整形多位 Delta-Sigma 调制器不仅继承了传统调制器对量化噪 声的整形功能, 而且增加了对多位反馈 DAC失配噪声的整形功能, 所以, 该构造方法可以从传统调制器有效地构造数字噪声整形多位 De 11 a-S i gma 调制器。 综上, 上述构造方法, 是从传统的调制器(第一调制器) 出发, 来构 造本发明的调制器(第二调制器), 第一调制器包含模拟环路滤波器 21、 多位量化器 22、多位反馈 DAC23 ,模拟环路滤波器 21的一输入端接受模拟 信号输入, 输出端连接多位量化器 22的输入端, 多位量化器 22的输出端 输出多位数字信号, 并连接多位反馈 DAC23的输入端, 多位反馈 DAC23的 输出端连接模拟环路滤波器 21 的另一输入端, 所述构造方法包含如下步 骤: The noise is random, the sign can be ignored, and is equal to the quantization noise transfer function. It can be seen that the digital noise shaping multi-bit Delta-Sigma modulator not only inherits the shaping function of the quantization noise of the traditional modulator, but also increases the shaping function of the mismatch noise of the multi-bit feedback DAC. Therefore, the construction method can be traditionally The modulator effectively constructs a digital noise shaping multi-bit De 11 aS i gma modulator. In summary, the above construction method is to construct the modulator (second modulator) of the present invention from a conventional modulator (first modulator), the first modulator including the analog loop filter 21, multi-bit quantization The multi-bit feedback DAC 23, an input end of the analog loop filter 21 receives an analog signal input, the output end is connected to the input end of the multi-bit quantizer 22, and the output end of the multi-bit quantizer 22 outputs a multi-bit digital signal, and An input end of the multi-bit feedback DAC 23 is connected, and an output end of the multi-bit feedback DAC 23 is connected to the other input end of the analog loop filter 21, and the construction method comprises the following steps:

将模拟环路滤波器 21 分解为第一模拟滤波器 31 和第二模拟滤波器 32 , 增设模拟加法器 35 , 按如下方式调整器件连接: 模拟加法器 35的两 个输入端分别连接第一模拟滤波器 31和第二模拟滤波器 32的输出端, 输 出端连接多位量化器 33的输入端,第一模拟滤波器 31接受模拟信号输入, 第二模拟滤波器 32的输入端连接多位反馈数模转换器 34的输出端;  The analog loop filter 21 is decomposed into a first analog filter 31 and a second analog filter 32, and an analog adder 35 is added to adjust the device connection as follows: The two inputs of the analog adder 35 are respectively connected to the first analog The output ends of the filter 31 and the second analog filter 32 are connected to the input end of the multi-bit quantizer 33, the first analog filter 31 receives the analog signal input, and the input of the second analog filter 32 is connected to the multi-bit feedback. An output of the digital to analog converter 34;

将第二模拟滤波器 32调整为数字环路滤波器, 按如下方式调整器件 连接从而构造出第二调制器:数字环路滤波器的输入端连接多位量化器 33 的输出端,输出端连接多位反馈数模转换器 34的输入端,多位反馈数模转 换器 34的输出端连接所述加法器的一输入端。也就是说,把第二模拟滤波 器 32与多位反馈数模转换器 34相互对调位置, 于是, 第二模拟滤波器从 模拟域转移到数字域, 从而转变成为数字环路滤波器。  The second analog filter 32 is adjusted to a digital loop filter, and the device connection is adjusted as follows to construct a second modulator: the input of the digital loop filter is connected to the output of the multi-bit quantizer 33, and the output is connected. An input of the multi-bit feedback digital-to-analog converter 34 is coupled to an input of the adder. That is, the second analog filter 32 and the multi-bit feedback digital-to-analog converter 34 are mutually aligned, and then the second analog filter is transferred from the analog domain to the digital domain, thereby being converted into a digital loop filter.

第三方面, 如图 1所示的调制器中滤波器 11、 12可能包含具有累积 作用的单元, 比如: 积分器、 谐振器、 累加器等等, 当调制器工作时, 这 些单元的输出量将会极大增长, 然而调制器在电路实现时工作电压有限、 寄存器存储数值也有限, 如果不采取措施, 这种矛盾必然导致调制器工作 不稳定,进而崩溃。为了保证如图 1所示的数字噪声整形多位 De l ta-S i gma 调制器工作稳定,本发明提出一种数字噪声整形多位 De l ta-S i gma调制器 内部信号分流的方法。 该方法的基本思想是: 从数字滤波器中, 于输出量 极大增长的单元的输入端导出分流数字信号, 接着通过 DAC把它转换成相 应的模拟信号, 最后把这个模拟信号反馈到模拟滤波器的等价节点。 该方 法的基本原则是: 使被分流信号的传递函数在被分流前后保持一致。 该方 法的具体实施步骤是:  In a third aspect, the filters 11, 12 in the modulator shown in Figure 1 may contain units with cumulative effects, such as: integrators, resonators, accumulators, etc., when the modulator is operating, the output of these units It will increase greatly. However, the modulator has limited operating voltage and limited register storage value when the circuit is implemented. If no measures are taken, this contradiction will inevitably lead to unstable operation of the modulator and collapse. In order to ensure that the digital noise shaping multi-bit De ta-S i gma modulator shown in FIG. 1 works stably, the present invention proposes a digital noise shaping multi-bit De ta-S i gma modulator internal signal shunting method. The basic idea of the method is: From the digital filter, the shunt digital signal is derived from the input of the unit whose output is greatly increased, and then converted into a corresponding analog signal by the DAC, and finally the analog signal is fed back to the analog filter. Equivalent node of the device. The basic principle of the method is to: Make the transfer function of the shunt signal consistent before and after being shunted. The specific implementation steps of this method are:

i)第一步, 确定信号分流节点  i) First step, determine the signal shunt node

为表述方便, 以如图 4所示的调制器为例 (需要注意的是: 该信号分 流方法不限于该例, 其它调制器的内部信号分流方法可以根据此例类推) f\ - ^ '^. -7T ^ . ii^i *il ¾ ^iil v/ . ¾ 41 ^ if ^ ^S夂 4 ? i ¾ 位量化器 44、 多位反馈 DAC45和模拟加法器 46构成, 其中, 数字环路滤 波器 42内部, 某一具有累积作用的单元 43位于节点 47与节点 48之间, U(z)、 V(z)、 EQ(z)、 ED (z)分别表示调制器的输入模拟信号、 调制器的输出 数字信号、多位量化器 44的量化噪声和多位反馈 DAC45的失配噪声。通过 观察可以发现, 当调制器工作时,具有累积作用的单元 43的输出量将会极 大增长, 所以确定单元 43输入端的节点 47为信号分流节点。 For convenience of description, the modulator shown in FIG. 4 is taken as an example (note that the signal shunting method is not limited to this example, and the internal signal shunting method of other modulators can be analogized according to this example) f\ - ^ '^ -7T ^ . ii^i *il 3⁄4 ^iil v/ . 3⁄4 41 ^ if ^ ^S夂4 ? i 3⁄4 The bit quantizer 44, the multi-bit feedback DAC 45 and the analog adder 46 are constructed, wherein inside the digital loop filter 42, a certain unit 43 having an accumulation function is located between the node 47 and the node 48, U(z), V( z), E Q (z), E D (z) represent the input analog signal of the modulator, the output digital signal of the modulator, the quantization noise of the multi-bit quantizer 44, and the mismatch noise of the multi-bit feedback DAC 45, respectively. It can be observed by observation that when the modulator operates, the output of the unit 43 having the cumulative action will greatly increase, so the node 47 at the input of the determining unit 43 is the signal shunting node.

ii)第二步, 导出分流信号  Ii) The second step, exporting the shunt signal

为了导出分流信号, 需要在图 4的节点 47插入信号分流器, 得到如 图 5所示的调制器结构,信号分流器 54把^( 分解成 Vnl(z)和 Vn2(z) ,它 们之间存在如下关系: In order to derive the shunt signal, a signal shunt is required to be inserted at node 47 of Fig. 4 to obtain a modulator structure as shown in Fig. 5. The signal shunt 54 decomposes ^( into V nl (z) and V n2 (z), which There are the following relationships:

Vn(Z)=V z) + Vn2(z) (6) V n (Z)=V z) + V n2 (z) (6)

其中, Vnl(z)是被导出的分流信号, 它将被反馈到模拟滤波器 51的信 号馈入节点。 根据数字信号位数不同, 分流信号 Vnl(z)可以分成两大类, 第一类, Vnl(z)是 1位数字信号,仅包含这种分流信号的调制器归为 A类数 字噪声整形多位 Delta-Sigma调制器, 这类调制器不需要引入额外的 DEM 技术; 第二类, Vnl(z)是多位数字信号, 包含这种分流信号的调制器归为 B 类数字噪声整形多位 Delta-Sigma调制器, 这类调制器可能需要引入额外 的 DEM技术。 Where V nl (z) is the derived shunt signal that is fed back to the signal feed node of the analog filter 51. According to the number of digital signal bits, the shunt signal V nl (z) can be divided into two categories. In the first category, V nl (z) is a 1-bit digital signal, and the modulator containing only such shunt signal is classified as Class A digital noise. Plastic multi-bit Delta-Sigma modulator, this type of modulator does not need to introduce additional DEM technology; In the second category, V nl (z) is a multi-bit digital signal, and the modulator containing this shunt signal is classified as Class B digital noise. Shaped multi-bit Delta-Sigma modulators, such modulators may require the introduction of additional DEM technology.

iii)第三步, 信号类型转换  Iii) Step 3, signal type conversion

如图 5所示的分流信号 Vnl (z)属于数字信号, 在反馈到模拟滤波器 51 的信号馈入节点前, 需要把它转换成相应的模拟信号, 在 Vnl(z)后插入反 馈 DAC得到如图 6所示的调制器结构。 The shunt signal V nl (z) shown in FIG. 5 belongs to the digital signal, and before the signal fed back to the analog filter 51 is fed to the node, it needs to be converted into a corresponding analog signal, and the feedback is inserted after V nl (z). The DAC gets the modulator structure shown in Figure 6.

iv)第四步, 确定信号馈入节点  Iv) the fourth step, determine the signal feed node

在图 6 中, 假设 Vnl(z)信号被导出前传输路径 611 的传递函数为 TF2 (z) , Vnl(z)信号被导出后传输路径 612的传递函数为 TF z) , 根据上文 信号分流方法的基本原则, 使 TF z -TF z)成立的前提下, 可以在模拟 滤波器 601 中找到节点 610, 它就是分流信号的馈入节点, 在图 6的节点 610插入加法器, 得到如图 7所示的调制器结构。 In FIG. 6, it is assumed that the transfer function of the transmission path 611 before the V nl (z) signal is derived is TF 2 (z), and the transfer function of the transmission path 612 after the V nl (z) signal is derived is TF z) , according to Under the premise that the TF z -TF z) is established, the node 610 can be found in the analog filter 601, which is the feed node of the shunt signal, and the adder is inserted at the node 610 of FIG. A modulator structure as shown in Fig. 7 is obtained.

V)第五步, 闭合分流信号反馈回路  V) Step 5, closing the shunt signal feedback loop

在图 7中, 把反馈 DAC709的输出端连接到加法器 703的负输入端, 得到如图 8所示的调制器结构, 它是经过信号分流优化的数字噪声整形多 位 Delta- Sigma调制器, 内部包含一个分流反馈支路。 内有多个输出量极大增长的单元, 就需要多个分流反馈支路。 通过分流反 馈支路的设置, 使得调制器的工作更加稳定。 In FIG. 7, the output of the feedback DAC 709 is connected to the negative input of the adder 703 to obtain a modulator structure as shown in FIG. 8, which is a digital noise shaping multi-bit Delta-Sigma modulator optimized by signal shunting. The interior contains a shunt feedback branch. There are multiple units with greatly increased output, which requires multiple shunt feedback branches. The operation of the modulator is made more stable by the setting of the shunt feedback branch.

如上文所述, 针对多位 Del ta-S igma调制器的反馈 DAC非线性问题, 本发明的 A类数字噪声整形多位 Del ta-S igma调制器不需要引入 DEM技术, 它与级联双量化器结构的调制器相比,可以对量化噪声和多位反馈 DAC 的 失配噪声进行同阶整形, 并且不存在量化噪声和失配噪声被级间耦合系数 放大的问题。 本发明的 B类数字噪声整形多位 De 11 a-S i gma调制器可能需 要引入 DEM技术, 但它与现有的 DEM技术相比, 可以减少反馈到调制器输 入端的 DAC位数, 一方面, 筒化了该反馈 DAC的电路结构; 另一方面, 提 高了该反馈 DAC单位元件间的匹配精度, 为采用 1阶失配噪声整形的 DEM 技术(比如: DWA技术等等)创造了条件, 这可以进一步降低电路复杂度, 既减轻数字电路产生的噪声, 又节省功耗和面积。  As described above, for the feedback DAC nonlinearity problem of a multi-bit Delta-Sigma modulator, the Class A digital noise shaping multi-bit Delta-Sigma modulator of the present invention does not need to introduce DEM technology, and it is cascaded with Compared with the modulator of the quantizer structure, the quantization noise and the mismatch noise of the multi-bit feedback DAC can be shaped in the same order, and there is no problem that the quantization noise and the mismatch noise are amplified by the interstage coupling coefficient. The Class B digital noise shaping multi-bit De 11 aS i gma modulator of the present invention may need to introduce DEM technology, but it can reduce the number of DACs fed back to the input of the modulator compared with the existing DEM technology. The circuit structure of the feedback DAC is improved; on the other hand, the matching precision between the unit components of the feedback DAC is improved, and conditions are created for DEM technology (such as DWA technology, etc.) using 1st order mismatch noise shaping, which can Further reducing circuit complexity, both reducing the noise generated by digital circuits, but also saving power and area.

本发明的调制器的主要特点是:  The main features of the modulator of the present invention are:

与传统的多位调制器不同, 该调制器中多位量化器与多位反馈 DAC之 间插入了一个数字环路滤波器, 多位反馈 DAC输出信号的反馈节点从调制 器的输入端转移到多位量化器的输入端, 形成由多位量化器、 数字环路滤 波器和多位反馈 DAC构成的反馈环路,使量化噪声 EQ (z)和失配噪声 ED (z) 的注入节点处于等价位置, 在数字环路滤波器的作用下, 这些噪声同时受 到整形(据此称这种调制器为 "数字噪声整形多位 Del ta-S igma调制器" ), 解决了多位 Del ta-S igma 调制器中的多位反馈 DAC 的非线性问题, 作为 Del ta-S igma 模数转换器中的一个核心部件, 可应用于高速、 高精度的模 数转换。  Unlike conventional multi-bit modulators, a digital loop filter is inserted between the multi-bit quantizer and the multi-bit feedback DAC in the modulator. The feedback node of the multi-bit feedback DAC output signal is transferred from the input of the modulator to The input of the multi-bit quantizer forms a feedback loop composed of a multi-bit quantizer, a digital loop filter and a multi-bit feedback DAC, so that the injection nodes of the quantization noise EQ (z) and the mismatch noise ED (z) are at Equivalent position, under the action of the digital loop filter, these noises are simultaneously shaped (according to this modulation as "digital noise shaping multi-bit Delta-Sigma modulator"), solving multi-bit Delta The nonlinear problem of the multi-bit feedback DAC in the -Sigma modulator, as a core component of the Delta-Sigma analog-to-digital converter, can be applied to high-speed, high-precision analog-to-digital conversion.

此外, 为设计实现上述数字噪声整形多位 Del ta-S i gma调制器, 本发 明也提出了其设计方法, 即从传统 Del ta-S igma调制器构造数字噪声整形 多位 De l ta-S igma 调制器的构造方法,以及为使该调制器工作更稳定而采 取的信号分流方法。  In addition, in order to design and implement the above-mentioned digital noise shaping multi-bit Delta-S i gma modulator, the present invention also proposes a design method thereof, that is, constructing digital noise shaping multi-bit De l ta-S from a conventional Delta-Sigma modulator. The construction of the igma modulator and the signal shunting method taken to make the modulator work more stable.

下面结合一个应用实例对本发明作进一步说明。 为了说明的条理性, 本实施例首先从传统调制器构造四阶低通数字噪声整形多位 De 11 a-S i gma 调制器; 其次, 对该调制器进行内部信号分流; 最后, 说明该调制器的工 作原理, 并给出该调制器的性能仿真结果。  The present invention will be further described below in conjunction with an application example. For illustrative purposes, this embodiment first constructs a fourth-order low-pass digital noise shaping multi-bit De 11 aS i gma modulator from a conventional modulator; secondly, internal signal shunting is performed on the modulator; finally, the modulator is illustrated The working principle, and the performance simulation results of the modulator are given.

传统的四阶氐通多位 Del ta-S igma调制器如图 9所示, 居上文所述 的构造数字噪声整形多位 De 11 a-S i gma调制器的方法, 通过结构变换可以 路滤波器 912包含的两个传递函数 L。、 分离,得到如图 10所示的调制器 结构; 第二步, 把如图 10所示的滤波器 1018转移到数字电路一侧, 得到 如图 11所示的调制器结构,这就是本实施例需要说明的四阶低通数字噪声 整形多位 De 11 a- S i gma调制器原始结构。 The conventional fourth-order pass-through multi-bit Delta-Sigma modulator is shown in FIG. 9, and the method for constructing a digital noise shaping multi-bit De 11 aS i gma modulator described above can be implemented by structural transformation. The path filter 912 contains two transfer functions L. Separating, the modulator structure shown in FIG. 10 is obtained; in the second step, the filter 1018 shown in FIG. 10 is transferred to the side of the digital circuit to obtain a modulator structure as shown in FIG. 11, which is the implementation. The fourth-order low-pass digital noise shaping multi-bit De 11 a-S i gma modulator original structure to be explained.

由如图 11 所示的调制器可知, 模拟滤波器 1109 和数字环路滤波器 1118都由积分器构成, 并且积分器之间还以串联方式连接在一起, 由于积 分器具有累积作用, 当调制器开始工作时, 这些模拟积分器输出电压的幅 度将会极大增加, 数字积分器输出数值的绝对值也将会极大膨胀, 尤其是 后级积分器的输出量将会爆炸式增长, 根据上文所述的调制器内部信号分 流方法, 通过信号分流可以避免这种情况发生。 第一步, 通过观察确定数 字积分器 1110、 1111、 1112和 1113之前的节点 1122、 1124、 1126 和 1128 为信号分流节点; 第二步, 分别在节点 1122、 1124、 1126 和 1128处插入 信号分流器, 得到图 12所示的调制器结构, 其中信号分流器 1218、 1219、 1220和 1221把各自的输入信号 V ( 、 v\z) ^ V "( 和 V 进行分解, 得到 被导出的分流信号分别是 ¼( 、 ¼'( 、 ( 和 ( , 这些信号满足以下关 系:  As can be seen from the modulator shown in Fig. 11, both the analog filter 1109 and the digital loop filter 1118 are composed of integrators, and the integrators are also connected in series, since the integrator has a cumulative effect, when modulation When the device starts to work, the amplitude of the output voltage of these analog integrators will increase greatly, and the absolute value of the output value of the digital integrator will also expand greatly, especially the output of the post-integrator will explode, according to The modulator internal signal shunting method described above can avoid this by signal shunting. In the first step, it is observed that the nodes 1122, 1124, 1126, and 1128 before the digital integrators 1110, 1111, 1112, and 1113 are signal shunt nodes; and in the second step, the signal shunts are inserted at the nodes 1122, 1124, 1126, and 1128, respectively. The modulator structure shown in Fig. 12 is obtained, in which the signal splitters 1218, 1219, 1220 and 1221 decompose the respective input signals V ( , v\z) ^ V "( and V to obtain the derived shunt signal They are 1⁄4( , 1⁄4'( , , and ( , these signals satisfy the following relationship:

V(z)=V1(z) + V2(z) V(z)=V 1 (z) + V 2 (z)

V z) = V;(z) + V2(z) ( ? ) V z) = V; (z) + V 2 (z) ( ? )

V z) =V;(z) + V;(z)  V z) =V;(z) + V;(z)

V" z) =V;(z) + V;{z) 第三步, 如图 12所示的被导出信号 ( 、 v;(z) , 和 ( 都是数 字信号,在反馈到模拟滤波器 1209的信号馈入节点前,需要把它们转换成 相应的模拟信号, 在 ¼ω、 ν;(ζ) , νω和 ( 后插入反馈 DAC得到如图 V" z) = V; (z) + V; {z) The third step, as shown in Figure 12, the derived signals ( , v; (z) , and ( are all digital signals, fed back to the analog filter Before the signals of 1209 are fed into the node, they need to be converted into corresponding analog signals, which are shown in Figure 1⁄4ω, ν;(ζ), νω and (after inserting the feedback DAC)

13所示的调制器结构;第四步,在图 13中,通过观察可知,分流信号 ¼ω、 ( 、 ( 和 V' ( 流过路径 1334、 1335、 1336和 1337到达加法器 1329 前的传递函数与被分流前的 "负的传递函数" 保持一致, 因此, 如图 13 所示的节点 1330、 1331、 1332 和 1333正是对应的分流信号馈入节点, 在 这些节点插入加法器得到如图 14所示的调制器结构; 第五步,在图 14中, 把反馈 DAC1425、 1426、 1427和 1428的输出端分别连接到加法器 1429、 1430、 1431和 1432的负输入端, 得到如图 15所示的调制器结构, 它是经 过信号分流优化的四阶低通数字噪声整形多位 Delta-Sigma调制器,至此, 整个调制器的内部信号分流过程结束。 如图 15 所示, 四阶低通数字噪声整形多位 Delta-Sigma调制器由模 拟滤波器 1509、 数字环路滤波器 1522、 多位量化器 1523、 多位反馈 DAC 1524、 分流信号反馈 DAC (1525、 1526、 1527、 1528)、 和模拟加法器 1533 构成。 其中,模拟滤波器 1509采用分布式前馈结构, 由四个级联的模拟积 分器(1501、 1502、 1503、 1504)、 四个具有一定增益系数( "1"、 1505、 1506、 1507)的前馈支路、 前馈模拟加法器 1508 和四个分流信号馈入加法器 (1529、 1530、 1531、 1532)构成; 数字环路滤波器 1522也采用分布式前馈 结构, 由四个级联的数字积分器(1510、 1511、 1512、 1513)、 三个具有一 定增益系数(1514、 1515、 1516)的前馈支路、前馈数字加法器 1517和四个 信号分流器(1518、 1519、 1520、 1521)构成, U (z)表示调制器的输入模拟 信号, V(z)表示调制器的输出数字信号, EQ(z)表示多位量化器 1523的量 化噪声, ED(z)表示多位反馈 DAC1524的失配噪声。 模拟滤波器 1509用于 把输入模拟信号 U(z)预调制成 (^)4[/(z)信号,数字环路滤波器 1522用于 整形量化噪声 EQ(z)、 失配噪声 ED(z)和预调制信号 (^)4[/( , 多位量化 器 1523用于把模拟加法器 1533输出的模拟信号转换成相应的多位数字信 号,多位反馈 DAC1524用于把数字环路滤波器 1522输出的多位数字信号转 换成相应的模拟信号, 模拟加法器 1533用于模拟滤波器 1509与多位反馈 DAC1524输出信号的求和, 信号分流器 1518、 1519、 1520、 1521、 分流信 号反馈 DAC1525、 1526、 1527、 1528和分流信号馈入加法器 1529、 1530、 1531、 1532用于信号分流与反馈。 该调制器正常工作时, 首先, 输入模拟 信号 u(z)被模拟滤波器 1509预调制成 (^)4[/( 信号, 接着, (^)4 ω 信号、 量化噪声 EQ(z)和失配噪声 ED (z)—起注入包含有数字环路滤波器 1522的反馈环路, 最后, 这些信号都被数字环路滤波器 1522整形后从调 制器输出。 根据图 15, 经过推导可得: The modulator structure shown in Fig. 13; the fourth step, in Fig. 13, shows that the shunt signals 1⁄4ω, ( , ( and V' (the transfer functions before the paths 1334, 1335, 1336, and 1337 flow to the adder 1329) are observed. Consistent with the "negative transfer function" before being shunted, therefore, nodes 1330, 1331, 1332, and 1333 as shown in Figure 13 are the corresponding shunt signal feed nodes, and the adders are inserted at these nodes to obtain Figure 14 The modulator structure shown; in the fifth step, in Figure 14, the outputs of the feedback DACs 1425, 1426, 1427, and 1428 are connected to the negative inputs of the adders 1429, 1430, 1431, and 1432, respectively, as shown in FIG. The illustrated modulator structure, which is a fourth-order low-pass digital noise shaping multi-bit Delta-Sigma modulator optimized by signal shunting, ends the internal signal shunting process of the entire modulator. As shown in Figure 15, the fourth-order low-pass digital noise shaping multi-bit Delta-Sigma modulator consists of an analog filter 1509, a digital loop filter 1522, a multi-bit quantizer 1523, a multi-bit feedback DAC 1524, and a shunt signal feedback DAC ( 1525, 1526, 1527, 1528), and analog adder 1533. Among them, the analog filter 1509 adopts a distributed feedforward structure, consisting of four cascaded analog integrators (1501, 1502, 1503, 1504) and four with certain gain coefficients ("1", 1505, 1506, 1507). The feedforward branch, feedforward analog adder 1508 and four shunt signals are fed into the adders (1529, 1530, 1531, 1532); the digital loop filter 1522 also uses a distributed feedforward structure, consisting of four cascades Digital integrator (1510, 1511, 1512, 1513), three feedforward branches with a certain gain factor (1514, 1515, 1516), feedforward digital adder 1517 and four signal splitters (1518, 1519, 1520, 1521), U (z) represents the input analog signal of the modulator, V (z) represents the output digital signal of the modulator, and E Q (z) represents the quantization noise of the multi-bit quantizer 1523, E D (z) Indicates the mismatch noise of the multi-bit feedback DAC1524. The analog filter 1509 is used to pre-modulate the input analog signal U(z) into a (^)4[/( z ) signal, and the digital loop filter 1522 is used to shape the quantization noise E Q (z), mismatch noise E D (z) and pre-modulation signal (^) 4 [/(, multi-bit quantizer 1523 is used to convert the analog signal output from the analog adder 1533 into a corresponding multi-bit digital signal, and the multi-bit feedback DAC 1524 is used to digitally loop The multi-bit digital signal outputted by the filter 1522 is converted into a corresponding analog signal, and the analog adder 1533 is used to sum the output signals of the analog filter 1509 and the multi-bit feedback DAC 1524, the signal splitter 1518, 1519, 1520, 1521, the shunt signal Feedback DACs 1525, 1526, 1527, 1528 and shunt signals are fed to adders 1529, 1530, 1531, 1532 for signal shunting and feedback. When the modulator is operating normally, first, the input analog signal u(z) is analog filter 1509. Pre-modulation into (^) 4 [/(signal, then, (^) 4 ω signal, quantization noise E Q (z), and mismatch noise E D (z) - injection of feedback containing digital loop filter 1522 Loop, finally, these signals are all digital loop filter 1522 After the shape is output from the modulator. According to Figure 15, after derivation, it can be obtained:

V(z) = U(z) + (l-Z-1)4EQ(z)-(l-Z-1)4ED(z) ( 8 ) V(z) = U(z) + (lZ- 1 ) 4 E Q (z)-(lZ- 1 ) 4 E D (z) ( 8 )

由(8)式可知, 该调制器具有 4阶噪声整形低通性能, 输入信号 U(z) 可以直接通过该调制器, 而量化噪声 EQ(z)和失配噪声 ED(z)则同时受到 4 阶整形。 为了更加直观地理解该调制器的噪声整形功能, 可以通过建模、 直 者塞该 SNDR (Siena 1 o Noi s +Di st.ort. i on Ra io) ^ ife. 根据图 15 , 利用 Ma tLab S imuL ink建立相应的调制器模型, 该模型的关键 参数如下: It can be seen from equation (8) that the modulator has a fourth-order noise shaping low-pass performance, and the input signal U(z) can pass directly through the modulator, while the quantization noise E Q (z) and the mismatch noise E D (z) At the same time, it is subject to 4th order shaping. In order to understand the noise shaping function of the modulator more intuitively, the SNDR (Siena 1 o Noi s + Di st.ort. i on Ra io) ^ ife can be modeled. According to Figure 15, the corresponding modulator model is established by using Ma tLab S imuL ink. The key parameters of the model are as follows:

a)多位量化器 1523采用 5位理想模型;  a) Multi-bit quantizer 1523 uses a 5-bit ideal model;

b)多位反馈 DAC1524采用 5位非理想模型,该 DAC单位元件间的失配 为 1 %;  b) Multi-bit feedback The DAC1524 uses a 5-bit non-ideal model with a 1% mismatch between the DAC unit components;

c)分流信号反馈 DAC1525、 1526、 1527、 1528均采用一位模型; d)输入信号频率为 129394. 53125HZ;  c) shunt signal feedback DAC1525, 1526, 1527, 1528 use a one-bit model; d) the input signal frequency is 129394. 53125HZ;

e)信号带宽为 1MHZ;  e) the signal bandwidth is 1MHZ;

0过采样率为 20。  0 oversampling rate is 20.

经过仿真可以得到如图 16所示的调制器输出信号 SNDR最大时的频谱 图及如图 17所示的调制器输出信号 SNDR与输入信号幅度的关系曲线。 为 了下文表述方便, 预先定义三个筒称, 把采用理想多位反馈 DAC的理想调 制器筒称为 "理想调制器";把采用非理想多位反馈 DAC的传统调制器筒称 为 "非理想调制器"; 把采用非理想多位反馈 DAC 的数字噪声整形多位 De l ta- S i gma调制器筒称为 "非理想数字噪声整形调制器"。 在图 16中, 虚线、 实细线和实粗线分别表示 "理想调制器"、 "非理想调制器" 和 "非 理想数字噪声整形调制器" 的输出信号频谱, 对比这三者可知, 在 "非理 想调制器" 频谱中, 噪声本底升高, 带内有明显的 3次和 5次谐波, 导致 最大 SNDR急剧下降到 72. 8dB, 并且低频部分噪声呈现水平形状, 这些表 明传统调制器对多位反馈 DAC的失配噪声 ED (z)没有整形功能。但是,在"非 理想数字噪声整形调制器" 的频谱中, 噪声本底几乎和 "理想调制器" 的 重叠,最大 SNDR保持在 117. 8dB ("理想调制器"的最大 SNDR 为 116. 3dB) , 并且噪声以 80dB/十倍频的斜率上升, 这些表明本发明的数字噪声整形多 位 De l ta-S i gma调制器可以对量化噪声 EQ (z)和多位反馈 DAC失配噪声 ED (z) 同时进行良好的整形 (此例为四阶噪声整形)。 在图 17中, 虚线、 实细线 和实粗线分别表示 "理想调制器"、 "非理想调制器" 和 "非理想数字噪声 整形调制器"的输出信号 SNDR与输入信号幅度的关系曲线,对比这三者可 知, 几乎在整个输入信号幅度的变化范围, "非理想数字噪声整形调制器" 输出信号的 SNDR大约比 "非理想调制器"输出信号的 SNDR高 40dB , 并且 "非理想数字噪声整形调制器"输出信号的 SNDR 几乎等于 "理想调制器" 输出信号的 SNDR,这些表明本发明的数字噪声整形多位 De l ta-S i gma调制 器具有强健的稳定性。 总之, 在本实施例中, 通过理论分析和系统仿真,

Figure imgf000015_0001
且具有良好的噪声整形能力, 这种调制器可以有效地解决多位After simulation, a spectrum diagram of the modulator output signal SNDR as shown in FIG. 16 and a relationship between the modulator output signal SNDR and the input signal amplitude as shown in FIG. 17 can be obtained. For the convenience of the following description, three cartridges are pre-defined, and the ideal modulator cylinder with an ideal multi-bit feedback DAC is called an "ideal modulator"; the conventional modulator cylinder with a non-ideal multi-bit feedback DAC is called "non-ideal". Modulator"; A digital noise shaping multi-bit De ta-S i gma modulator cylinder with a non-ideal multi-bit feedback DAC is referred to as a "non-ideal digital noise shaping modulator." In Figure 16, the dashed line, the solid thin line, and the solid thick line represent the output signal spectrum of the "ideal modulator", "non-ideal modulator", and "non-ideal digital noise shaping modulator", respectively. In the "non-ideal modulator" spectrum, the noise floor is raised, and there are significant 3rd and 5th harmonics in the band, causing the maximum SNDR to drop sharply to 72.8dB, and the low-frequency part of the noise exhibits a horizontal shape, which indicates the traditional modulation. The mismatch noise E D (z) of the multi-bit feedback DAC has no shaping function. However, in the spectrum of the "non-ideal digital noise shaping modulator", the noise floor is almost overlapped with the "ideal modulator", and the maximum SNDR is maintained at 117. 8dB (the maximum SNDR of the "ideal modulator" is 116. 3dB). And the noise rises at a slope of 80dB/decade, which indicates that the digital noise shaping multi-bit De ta-S i gma modulator of the present invention can perform quantization noise E Q (z) and multi-bit feedback DAC mismatch noise E D (z) performs good shaping at the same time (this example is fourth-order noise shaping). In FIG. 17, the dotted line, the solid thin line, and the solid thick line respectively represent the relationship between the output signal SNDR of the "ideal modulator", "non-ideal modulator", and "non-ideal digital noise shaping modulator" and the input signal amplitude, Comparing the three, the SNDR of the "non-ideal digital noise shaping modulator" output signal is about 40 dB higher than the SNDR of the "non-ideal modulator" output signal, and the "non-ideal digital noise" is almost the entire range of the input signal amplitude. The shaped modulator's SNDR of the output signal is almost equal to the SNDR of the "ideal modulator" output signal, which indicates that the digital noise shaping multi-bit De ta-S i gma modulator of the present invention has robust stability. In short, in this embodiment, through theoretical analysis and system simulation,
Figure imgf000015_0001
And has good noise shaping ability, this modulator can effectively solve multiple bits

Del ta-S igma 调制器的反馈 DAC非线性问题。 Feedback from the Del ta-S igma modulator DAC nonlinearity problem.

以上内容是结合具体的实施方式对本发明所作的进一步详细说明, 不 能认定本发明的具体实施只局限于这些说明。 对于本发明所属技术领域的 普通技术人员来说, 在不脱离本发明构思的前提下, 还可以做出若干筒单 推演或替换, 都应当视为属于本发明的保护范围。  The above is a further detailed description of the present invention in connection with the specific embodiments, and the specific embodiments of the present invention are not limited to the description. It will be apparent to those skilled in the art that the present invention can be made without departing from the spirit and scope of the invention.

Claims

权 利 要 求 书 Claim 1. 一种调制器, 用于模数转换, 其特征在于, 包括模拟滤波器、 模拟加法器、 多位量化器、 数字环路滤波器、 多位反馈数模转换器, 所述 模拟滤波器用于对输入模拟信号进行预调制, 并输出到所述模拟加法器的 一个输入端, 所述模拟加法器用于模拟信号求和, 并输出到所述多位量化 器, 所述多位量化器用于将模拟信号和转换为多位数字信号输出; 所述数 字环路滤波器用于对多位量化器输出的多位数字信号滤波, 并输出到所述 多位反馈数模转换器, 所述多位反馈数模转换器用于将滤波后的多位数字 信号转换为反馈模拟信号, 并输出到所述模拟加法器的另一输入端。 A modulator for analog-to-digital conversion, comprising: an analog filter, an analog adder, a multi-bit quantizer, a digital loop filter, a multi-bit feedback digital-to-analog converter, and the analog filter The input analog signal is pre-modulated and output to an input of the analog adder, the analog adder is used for analog signal summation, and output to the multi-bit quantizer, the multi-bit quantizer is used Converting the analog signal to a multi-bit digital signal output; the digital loop filter is configured to filter the multi-bit digital signal output by the multi-bit quantizer and output to the multi-bit feedback digital-to-analog converter, the multi-bit The feedback digital-to-analog converter is configured to convert the filtered multi-bit digital signal into a feedback analog signal and output to another input of the analog adder. 2. 如权利要求 1所述的调制器, 其特征在于, 所述调制器还包括 至少一条分流反馈支路, 每一所述分流反馈支路输入端连接于所述数字环 路滤波器中的一个信号分流节点, 输出端连接于所述模拟滤波器中的一个 对应的分流信号馈入节点, 每一所述分流反馈支路从输入端到输出端依次 设置有信号分流器、 分流反馈数模转换器、 加法器。  2. The modulator of claim 1, wherein the modulator further comprises at least one shunt feedback branch, each of the shunt feedback branch inputs being coupled to the digital loop filter a signal shunt node, the output end is connected to a corresponding shunt signal feeding node of the analog filter, and each of the shunt feedback branches is provided with a signal shunt and a shunt feedback digital mode from the input end to the output end. Converter, adder. 3. 如权利要求 2所述的调制器, 其特征在于, 每一所述分流反馈 支路的输入分流信号为 1位数字信号或多位数字信号。  3. The modulator according to claim 2, wherein the input shunt signal of each of the shunt feedback branches is a 1-bit digital signal or a multi-bit digital signal. 4. 如权利要求 1-3任一所述的调制器, 其特征在于, 所述调制器 为多位 Del ta- S igma调制器。  The modulator according to any one of claims 1 to 3, wherein the modulator is a multi-bit Del ta- sig modulator. 5. 一种模数转换器, 其特征在于, 包含如权利要求 1-4任一所述 的调制器。  An analog to digital converter comprising the modulator according to any one of claims 1-4. 6. —种调制器的构造方法, 用于从第一调制器构造第二调制器, 其特征在于, 所述第一调制器包含模拟环路滤波器、 多位量化器、 多位反 馈数模转换器, 所述模拟环路滤波器的一输入端接受模拟信号输入, 输出 端连接所述多位量化器的输入端, 所述多位量化器的输出端输出多位数字 信号, 并连接所述多位反馈数模转换器的输入端, 所述多位反馈数模转换 器的输出端连接所述模拟环路滤波器的另一输入端, 所述构造方法包含如 下步骤: 6. A method of constructing a modulator for constructing a second modulator from a first modulator, wherein the first modulator comprises an analog loop filter, a multi-bit quantizer, and a multi-bit feedback digital mode a converter, an input end of the analog loop filter receives an analog signal input, an output end is connected to an input end of the multi-bit quantizer, and an output end of the multi-bit quantizer outputs a multi-bit digital signal, and is connected An input end of the multi-bit feedback digital-to-analog converter, wherein an output end of the multi-bit feedback digital-to-analog converter is connected to another input end of the analog loop filter, and the constructing method includes Next steps: 将所述模拟环路滤波器分解为第一模拟滤波器和第二模拟滤波器, 增 设模拟加法器, 按如下方式调整器件连接: 所述模拟加法器的两个输入端 分别连接所述第一模拟滤波器和第二模拟滤波器的输出端, 输出端连接所 述多位量化器的输入端, 所述第一模拟滤波器接受模拟信号输入, 所述第 二模拟滤波器的输入端连接所述多位反馈数模转换器的输出端;  Decomposing the analog loop filter into a first analog filter and a second analog filter, adding an analog adder, adjusting device connections as follows: two inputs of the analog adder are respectively connected to the first An output end of the analog filter and the second analog filter, the output end is connected to the input end of the multi-bit quantizer, the first analog filter accepts an analog signal input, and the input end of the second analog filter is connected The output of the multi-bit feedback digital-to-analog converter; 将第二模拟滤波器调整为数字环路滤波器, 按如下方式调整器件连接 从而构造出第二调制器: 所述数字环路滤波器的输入端连接所述多位量化 器的输出端, 输出端连接所述多位反馈数模转换器的输入端, 所述多位反 馈数模转换器的输出端连接所述加法器的一输入端。  Adjusting the second analog filter to a digital loop filter, adjusting the device connection as follows to construct a second modulator: the input of the digital loop filter is connected to the output of the multi-bit quantizer, and the output The terminal is connected to an input end of the multi-bit feedback digital-to-analog converter, and an output end of the multi-bit feedback digital-to-analog converter is connected to an input end of the adder. 7. —种调制器的信号分流方法, 其特征在于, 所述调制器用于模 数转换, 包括模拟滤波器、 模拟加法器、 多位量化器、 数字环路滤波器、 多位反馈数模转换器, 所述模拟滤波器用于对输入模拟信号进行预调制, 并输出到所述模拟加法器的一个输入端, 所述模拟加法器用于模拟信号求 和, 并输出到所述多位量化器, 所述多位量化器用于将模拟信号和转换为 多位数字信号输出; 所述数字环路滤波器用于对多位量化器输出的多位数 字信号滤波, 并输出到所述多位反馈数模转换器, 所述多位反馈数模转换 器用于将滤波后的多位数字信号转换为反馈模拟信号, 并输出到所述模拟 加法器的另一输入端; 所述信号分流方法包括如下步骤:  7. A signal shunting method for a modulator, characterized in that the modulator is used for analog to digital conversion, including an analog filter, an analog adder, a multi-bit quantizer, a digital loop filter, and a multi-bit feedback digital-to-analog conversion The analog filter is configured to pre-modulate an input analog signal and output it to an input of the analog adder, the analog adder is used for summing analog signals, and outputting to the multi-bit quantizer, The multi-bit quantizer is configured to convert an analog signal and a multi-bit digital signal output; the digital loop filter is configured to filter a multi-bit digital signal output by the multi-bit quantizer, and output the multi-bit feedback digital mode a converter, the multi-bit feedback digital-to-analog converter is configured to convert the filtered multi-bit digital signal into a feedback analog signal, and output to another input end of the analog adder; the signal shunting method includes the following steps: 确定所述数字环路滤波器中的至少一个信号分流节点;  Determining at least one signal shunt node of the digital loop filter; 设置至少一条分流反馈支路, 每一所述分流反馈支路的输入端连接于 一个所述信号分流节点, 并从输入端依次设置信号分流器、 分流反馈数模 转换器、 加法器;  And providing at least one shunt feedback branch, wherein the input end of each of the shunt feedback branches is connected to one of the signal shunt nodes, and a signal shunt, a shunt feedback digital-to-analog converter, and an adder are sequentially disposed from the input end; 将每一所述分流反馈支路的加法器插入到所述模拟滤波器的一个对应 的分流信号馈入节点。  An adder of each of the shunt feedback branches is inserted into a corresponding shunt signal feed node of the analog filter. 8. 如权利要求 7所述的信号分流方法, 其特征在于, 每一所述分 右 ^ 夂^ X Ύ 4ι 1 λχι !^ - ^ /^粉 ^ ^^τ  8. The signal shunting method according to claim 7, wherein each of said parts is right ^ 夂^ X Ύ 4ι 1 λχι !^ - ^ /^ powder ^ ^^τ
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