[go: up one dir, main page]

WO2011036841A1 - Dispositif semiconducteur et procédé pour sa fabrication - Google Patents

Dispositif semiconducteur et procédé pour sa fabrication Download PDF

Info

Publication number
WO2011036841A1
WO2011036841A1 PCT/JP2010/004821 JP2010004821W WO2011036841A1 WO 2011036841 A1 WO2011036841 A1 WO 2011036841A1 JP 2010004821 W JP2010004821 W JP 2010004821W WO 2011036841 A1 WO2011036841 A1 WO 2011036841A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
semiconductor device
insulating film
dielectric constant
high dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2010/004821
Other languages
English (en)
Japanese (ja)
Inventor
竹岡慎治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Publication of WO2011036841A1 publication Critical patent/WO2011036841A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a cap film containing a metal that changes a threshold voltage of a MIS (Metal Insulator Semiconductor) transistor and a manufacturing method thereof.
  • MIS Metal Insulator Semiconductor
  • a silicon oxide film or a silicon oxynitride film is used as the gate insulating film.
  • EOT Equivalent Oxide Thickness
  • the gate leakage current increases, causing a problem that the power consumption of the circuit increases.
  • a transistor having a high dielectric constant film and a metal gate electrode a metal gate electrode is not a silicon electrode but a gate electrode made of a metal material such as titanium nitride or tantalum nitride
  • One of the problems in realizing a transistor having a high dielectric constant film and a metal gate electrode is control of the threshold voltage of the transistor.
  • the work function of the silicon electrode is adjusted by implanting impurity ions, thereby realizing a threshold voltage suitable for each of the N-type FET and the P-type FET. That is, for an N-type FET, the work function of the silicon electrode is reduced by injecting an N-type impurity such as arsenic or phosphorus into the silicon electrode.
  • an N-type FET For a P-type FET, boron or the like is used for the silicon electrode.
  • the work function of the silicon electrode is increased by implanting P-type impurities.
  • the metal gate electrode cannot control the work function by implanting impurity ions. Therefore, when a metal gate electrode is used as the gate electrode, control of the threshold voltage of the transistor is a big problem.
  • the threshold voltage is described as an absolute value in order to uniformly express the change in the threshold voltage in the N-type FET and the P-type FET.
  • the threshold voltage decreases (decreases) or the threshold voltage decreases”. Is described as "the threshold voltage increases or the threshold voltage increases”.
  • Non-Patent Document 1 discloses a method for controlling a threshold voltage in a transistor having a high dielectric constant film and a metal gate electrode.
  • a transistor having a high dielectric constant film and a metal gate electrode In the transistor disclosed in Non-Patent Document 1, an oxide film and a high dielectric constant film are sequentially formed on an element formation region, and this transistor has an electric dipole at the interface between the oxide film and the high dielectric constant film.
  • a metal oxide film (cap film) to be generated is provided.
  • FIG. 8 is a plan view of a conventional semiconductor device having a cap film.
  • 9A is a cross-sectional view taken along the line IXA-IXA shown in FIG. 8
  • FIG. 9B is a cross-sectional view taken along the line IXB-IXB shown in FIG. 8 and 9A
  • NFET indicates a region where an N-type MIS transistor is formed
  • STI indicates an element isolation region.
  • S”, “D”, and “G” indicate a source region, a drain region, and a gate region, respectively
  • W” and “L” indicate a gate width and a gate length, respectively. Yes.
  • a trench 701 is formed in a silicon substrate 700.
  • An element isolation insulating film 703 is formed in the trench 701 via a base insulating film (for example, a silicon oxide film) 702, and an element isolation region STI (Shallow ⁇ ⁇ Trench Isolation) is formed by the base insulating film 702 and the element isolation insulating film 703. Is configured.
  • a portion of the silicon substrate 700 surrounded by the element isolation region STI is an element formation region 700a, and a gate insulating film 707 and a gate electrode 710 are sequentially provided on the element formation region 700a.
  • a silicon oxide film 704, a hafnium oxide film 705, and a cap film 706 are sequentially provided on the element formation region 700a.
  • a TiN film 708 and a polysilicon film 709 are formed in the gate insulating film 707. They are provided in order.
  • a sidewall 712 is provided on the side surface of the gate electrode 710.
  • an extension region 711 is formed below the side of the gate electrode 710, and a source / drain region 713 is formed below the side of the sidewall 712.
  • Non-Patent Document 1 if a lanthanum oxide film is used as a cap film, the threshold voltage of the N-type FET can be lowered by about 400 mV, and if an aluminum oxide film is used as the cap film, the threshold voltage of the P-type FET is lowered by about 300 mV. It can be done.
  • FIG. 10 is a graph schematically showing the evaluation results of the narrow channel characteristics of a conventional N-type MIS transistor.
  • the threshold voltage When the cap film was not formed, as shown by the line 91 in FIG. 10, there was almost no variation in the threshold voltage with respect to the gate width.
  • the cap film when the cap film is formed, as shown by the line 92 in FIG. 10, when the gate width is wide, the threshold voltage hardly fluctuates with respect to the gate width, but when the gate width is narrow, the gate width is small. The threshold voltage increased as it narrowed. Specifically, when the gate width is wide (when the gate width is 10 ⁇ m, for example), if a lanthanum oxide film having a film thickness of 1 nm is formed on a hafnium oxide film having a film thickness of 2 nm, the threshold voltage is 500 mV.
  • the threshold voltage increased as the gate width narrowed, and the threshold voltage increased as high as 200 mV or more ( ⁇ 2 ⁇ 200 mV) when the gate width narrowed to about 0.1 ⁇ m. That is, when the gate width is narrowed, the effect of lowering the threshold voltage by lanthanum is greatly reduced from 500 mV to 300 mV or less (degradation of narrow channel characteristics, dependence of threshold voltage on gate width).
  • the present invention has been made in view of the above points, and an object of the present invention is to provide a transistor capable of suppressing degradation of narrow channel characteristics and a method of manufacturing the same.
  • the cap film is formed not only on the element formation region but also on the base insulating film (the base insulating film is formed on the sidewall of the trench when the element isolation region is formed).
  • the first factor is that when the cap film is formed, the cap film is thinned due to coverage deterioration in a portion of the element isolation region that is in contact with the element formation region (the edge portion of the transistor).
  • the second factor is that when the high dielectric constant film is formed, the high dielectric constant film becomes thicker due to the loading effect at the edge portion of the transistor.
  • the third factor is that the metal applied to the cap film diffuses into the metal gate electrode during the heat treatment because the stress applied to the cap film is different between the central portion of the transistor and the edge portion of the transistor.
  • the effect of the cap film is reduced only at the edge of the transistor.
  • the gate width is wide, the influence of the edge portion of the transistor on the entire transistor is small. Therefore, if a cap film is formed over the element formation region, the threshold voltage of the transistor can be reduced.
  • the gate width is narrow, the influence of the edge portion of the transistor on the entire transistor is large, and thus the reduction in the effect of the cap film at the edge portion of the transistor cannot be ignored, and therefore the threshold voltage of the transistor increases.
  • a cap film containing lanthanum or aluminum is formed on the base insulating film.
  • the film thickness of the cap film can be made thicker than before only at the edge portion of the transistor. Accordingly, it is possible to prevent a reduction in the effect of the cap film at the edge portion of the transistor. Therefore, the threshold voltage can be made substantially the same at the edge portion of the transistor and the central portion of the transistor, so that deterioration of the narrow channel characteristic can be suppressed.
  • a semiconductor device in a trench formed in a semiconductor substrate, and includes an element isolation region surrounding the element formation region, and a gate provided on the element formation region and having a high dielectric constant film.
  • An insulating film and a gate electrode provided on the gate insulating film are provided.
  • the element isolation region has a base insulating film containing oxygen formed on the sidewall of the trench.
  • the high dielectric constant film has a first portion formed on the upper surface in the element formation region and a second portion formed on the upper side surface in the element formation region via a base insulating film.
  • a first cap film containing a metal that changes the threshold voltage of the MIS transistor is provided between the second portion of the high dielectric constant film and the base insulating film.
  • the first cap film is provided at the edge portion of the transistor. Therefore, the effect of the cap film at the edge portion of the transistor can be improved.
  • the element isolation region further includes an element isolation insulating film formed in the trench via the base insulating film, and the first region is between the base insulating film and the element isolation insulating film.
  • the cap film is provided.
  • the gate electrode is formed on the upper side surface in the element formation region via the second portion of the high dielectric constant film.
  • the gate insulating film includes an oxygen-containing film formed on the element formation region, a first portion in the high dielectric constant film formed on the oxygen-containing film, and a high dielectric constant film. It is preferable to have a second cap film formed on the first portion and containing a metal. Thereby, the threshold voltage of the transistor can be set to a desired value.
  • the second cap film is also formed on the second portion of the high dielectric constant film.
  • the film thickness of the second cap film formed on the second portion of the high dielectric constant film is the same as that of the second cap film formed on the first portion of the high dielectric constant film. Thinner than film thickness.
  • the oxygen-containing film is a silicon oxide film or a silicon oxynitride film
  • the base insulating film is a silicon oxide film or a silicon oxynitride film.
  • the metal impurity concentration in the second portion of the high dielectric constant film is equal to or higher than the metal impurity concentration in the first portion of the high dielectric constant film.
  • the MIS transistor is an N-channel MIS transistor, and the metal is at least one selected from lanthanum, dysprosium, scandium, erbium, magnesium, and strontium.
  • the MIS transistor is a P-channel MIS transistor and the metal is aluminum.
  • the high dielectric constant film is either a hafnium oxide film, a hafnium silicon oxide film, a hafnium silicon oxide film, a zirconium oxide film, or a hafnium zirconium oxide film.
  • the gate electrode is a single layer film made of any one of a titanium nitride film, a tantalum nitride film, a tantalum carbide film, and a tantalum nitride carbide film, or a laminated film made of two or more.
  • a recess is formed on the upper surface of the edge portion adjacent to the element formation region in the element isolation region, and the second portion of the high dielectric constant film is provided on the inner surface of the recess.
  • the concave portion is formed on the upper surface of the edge portion, the first cap film can be provided on the edge portion of the transistor.
  • the base insulating film contains a metal.
  • the method for manufacturing a semiconductor device includes a step (a) of forming a trench in a semiconductor substrate so as to surround an element formation region, and then providing a base insulating film containing oxygen on the sidewall of the trench; (B) providing a cap film containing a metal that changes the threshold voltage of the MIS transistor, and after the step (b), an element isolation insulating film is provided in the trench via the base insulating film, A step (c) of forming an element isolation region having an element isolation insulating film, a step (d) of providing a gate insulating film having a high dielectric constant film on the element formation region after the step (c), and gate insulation And (e) providing a gate electrode on the film.
  • a high dielectric constant film is formed on the upper side surface in the element formation region via a base insulating film and a cap film.
  • a step (f) of diffusing metal from the cap film to the base insulating film is provided after the step (b).
  • FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.
  • 2A to 2C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
  • 3A to 3C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
  • 4A and 4B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
  • 5A and 5B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
  • 6A is a cross-sectional view taken along the line VIA-VIA shown in FIG. 1, and FIG.
  • FIG. 6B is a cross-sectional view taken along the line VIB-VIB shown in FIG.
  • FIG. 7 is a graph schematically showing the evaluation results of the narrow channel characteristics.
  • FIG. 8 is a plan view of a conventional semiconductor device having a cap film.
  • 9A is a cross-sectional view taken along line IXA-IXA shown in FIG. 8
  • FIG. 9B is a cross-sectional view taken along line IXB-IXB shown in FIG.
  • FIG. 10 is a graph schematically showing another evaluation result of the narrow channel characteristics.
  • FIG. 1 is a plan view of the semiconductor device according to the present embodiment.
  • 2A to 5B are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of steps.
  • 2 (a) to 4 (b) are cross-sectional views taken along the line VIA-VIA shown in FIG. 1
  • FIGS. 5 (a) and 5 (b) are cross-sectional views taken along the line VIB-VIB shown in FIG.
  • “NFET” indicates a region where an N-type MIS transistor is formed
  • STI indicates an element isolation region.
  • FIG. 1 a method for manufacturing a semiconductor device including an N-type MIS transistor and its structure are shown.
  • S”, “D”, and “G” indicate a source region, a drain region, and a gate region, respectively
  • “W” and “L” indicate a gate width and a gate length, respectively.
  • A is a portion in contact with the element formation region in the element isolation region STI (referred to as an “edge portion of the N-type FET” in the present embodiment).
  • a silicon oxide film 101 of, eg, a 10 nm-thickness is formed on a semiconductor substrate (hereinafter referred to as “substrate”) 100 made of, eg, silicon, by thermal oxidation.
  • substrate e.g. silicon
  • a silicon nitride film 102 of, eg, a 70 nm-thickness is formed on the silicon oxide film 101.
  • resist film not shown
  • an opening is formed in a portion of the resist film that becomes the element isolation region STI by using a photolithography technique.
  • a resist pattern 103 is formed on the silicon nitride film 102 so as to expose the silicon nitride film 102 in a portion serving as the element isolation region STI.
  • the silicon nitride film 102, the silicon oxide film 101, and the substrate 100 are etched using the resist pattern 103 (see FIG. 2A) as a mask.
  • a trench 104 having a depth of, for example, 300 nm is formed in the substrate 100.
  • the resist pattern 103 is removed, and then heat treatment is performed in an oxygen gas and hydrogen gas atmosphere.
  • a base insulating film 105 made of, for example, a silicon oxide film having a thickness of 2 nm is formed on the sidewall and the bottom surface of the trench 104 (step (a)).
  • the top surface and side surface of the silicon nitride film 102, the side surface of the silicon oxide film 101, and the base insulating film 105 are formed using, for example, an ALD (Atomic Layer Deposition) method.
  • a first cap film (cap film) 106 made of a lanthanum oxide film having a thickness of 1 nm is formed (step (b)).
  • heat treatment is performed in a nitrogen gas atmosphere at, for example, 800 ° C. for 30 seconds.
  • the lanthanum in the first cap film 106 diffuses into the base insulating film 105 (step (f)).
  • lanthanum exists in the base insulating film 105.
  • silicon having a film thickness of, for example, 500 nm is formed on the entire surface of the substrate 100 so as to embed the trench 104 by using, for example, plasma CVD (Chemical Vapor Deposition) or thermal CVD.
  • An oxide film (not shown) is formed.
  • CMP Chemical Mechanical Polishing
  • the surface on the substrate 100 is planarized, and the element isolation insulating film 107 made of a silicon oxide film is formed in the trench 104 on the side wall and the bottom surface of the trench 104 via the base insulating film 105 and the first cap film 106. Formed on top. That is, the first cap film 106 is sandwiched between the base insulating film 105 and the element isolation insulating film 107 in the trench 104.
  • the element isolation insulating film 107, the first cap film 106, and the base insulating film 105 form an element isolation region STI (step (c)), and a portion of the substrate 100 surrounded by the element isolation region STI is formed as an element. It becomes area
  • the silicon nitride film 102 on the silicon oxide film 101 and the silicon oxide film 101 in the first cap film 106 are etched by etching using a chemical solution such as phosphoric acid. Remove the existing part.
  • impurity ions 108 are implanted into the substrate 100 using the resist pattern as a mask.
  • a P-type impurity such as boron may be used as the impurity ions 108.
  • a P-type well (not shown) is formed and the threshold voltage of the channel region is adjusted.
  • annealing is performed at 1000 ° C. for 1 minute in a nitrogen atmosphere in order to diffuse and activate impurities (P-type impurities) implanted into the substrate 100.
  • the silicon oxide film 101 is removed by etching using a chemical solution such as hydrofluoric acid.
  • a chemical solution such as hydrofluoric acid.
  • the wet etching rate of the silicon oxide film formed in the trench 104 is higher than the wet etching rate of the silicon oxide film 101 formed by the thermal oxidation method. Therefore, a recess 107 a is formed on the upper surface of the element isolation insulating film 107 at the edge portion of the N-type FET.
  • a portion of the first cap film 106 formed on the upper side wall (upper side surface in the element formation region) 104a of the trench is exposed.
  • an oxygen-containing film 109 made of, for example, a silicon oxide film having a thickness of 1 nm is formed on the element formation region 100a.
  • a high dielectric constant made of, for example, a 2 nm-thickness HfO 2 film (hafnium oxide film) is formed on the upper surface of the oxygen-containing film 109, the inner surface of the recess 107a, and the upper surface of the element isolation region STI by, for example, ALD.
  • a film 110 is formed.
  • the first cap film 106 is sandwiched between the portion (second portion) 110 b formed on the upper side surface 104 a in the element formation region of the high dielectric constant film 110 and the base insulating film 105.
  • the base insulating film 105 contains lanthanum. For these reasons, since lanthanum exists at the interface between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, an electric dipole is generated at this interface. Therefore, the threshold voltage can be reduced by the first cap film 106 at the edge portion of the N-type FET.
  • a second cap film 111 made of, for example, a lanthanum oxide film having a thickness of 1 nm is formed on the upper surface of the high dielectric constant film 110. Therefore, the second cap film 111 is formed not only on the upper surface of the portion (first portion) 110a formed on the upper surface of the oxygen-containing film 109 in the high dielectric constant film 110 but also on the second dielectric layer 110 of the high dielectric constant film 110. Also formed on the upper surface of the second portion 110b. Note that the film thickness of the portion of the second cap film 111 formed on the second portion 110b of the high dielectric constant film 110 is that of the high dielectric constant film 110 of the second cap film 111 due to coverage deterioration.
  • TiN film (titanium nitride film) 113 having a thickness of, for example, 10 nm is formed on the upper surface of the second cap film 111, and a polysilicon film 114 having a thickness of, for example, 80 nm is formed on the upper surface of the TiN film 113. .
  • a gate insulating film 112 formed by sequentially stacking the oxygen-containing film 109, the first portion 110a of the high dielectric constant film 110, and the second cap film 111 is formed on the upper surface of the element formation region 100a.
  • a gate electrode 115 formed by sequentially laminating the TiN film 113 and the polysilicon film 114 is formed on the upper surface of the gate insulating film 112 (Step (e)).
  • the gate insulating film 112 is also formed on the upper side surface 104a in the element formation region, and the gate electrode 115 is formed of the gate insulating film 112 (the first layer in the high dielectric constant film 110). 2 is also formed on the upper side surface 104a in the element formation region via the second portion 110b).
  • a resist (not shown) opened in a desired region is formed on the upper surface of the substrate 100.
  • N-type impurities such as arsenic ions or phosphorus ions are implanted using the resist and the gate electrode 115 as a mask.
  • the implantation energy is, for example, 2 to 5 keV, and the dose amount is, for example, 1 ⁇ 10 15 to 1 ⁇ 10 16 / cm 2 .
  • an N-type extension region 116 is formed below the side of the gate electrode 115 in the element formation region 100a. Thereafter, the resist is removed.
  • a resist (not shown) opened in a desired region is formed on the upper surface of the substrate 100.
  • N-type impurities such as arsenic ions or phosphorus ions are ion-implanted using the resist, the gate electrode 115 and the sidewall spacer 117 as a mask.
  • the implantation energy is, for example, 30 keV, and the dose amount is, for example, 1 ⁇ 10 16 / cm 2 .
  • an N-type source / drain region 118 is formed below the side wall spacer 117 in the element formation region. Thereafter, the resist is removed.
  • the semiconductor device according to this embodiment is manufactured.
  • lanthanum in the second cap film 111 diffuses to the interface between the high dielectric constant film 110 and the oxygen-containing film 109. Thereby, since an electric dipole is generated at the interface, the threshold voltage of the N-type FET can be reduced.
  • lanthanum in the first cap film 106 diffuses into the second portion 110b of the high dielectric constant film 110.
  • the lanthanum in the second cap film 111 is only diffused into the first portion 110a of the high dielectric constant film 110, but the second portion 110b of the high dielectric constant film 110 is diffused into the second portion 110b.
  • the lanthanum concentration in the second portion 110b of the high dielectric constant film 110 is equal to or higher than the lanthanum concentration in the first portion 110a of the high dielectric constant film 110.
  • FIGS. 1 and 6A to 7 are cross-sectional views taken along the line VIA-VIA shown in FIG. 1, and FIG. 6B is a cross-sectional view taken along the line VIB-VIB shown in FIG.
  • FIG. 7 is a graph schematically showing the evaluation results of the narrow channel characteristics.
  • a trench 104 is formed in the substrate 100.
  • a base insulating film 105 and a first cap film 106 are sequentially formed on the sidewall and the bottom surface of the trench 104, and the element is interposed in the trench 104 via the base insulating film 105 and the first cap film 106.
  • An isolation insulating film 107 is formed.
  • the base insulating film 105, the first cap film 106, and the element isolation insulating film 107 constitute an element isolation region STI, and a portion of the substrate 100 surrounded by the element isolation region STI is an element formation region 100a.
  • a gate insulating film 112 and a gate electrode 115 are sequentially formed on the element formation region 100a.
  • an oxygen-containing film 109, a high dielectric constant film 110, and a second cap film 111 are sequentially formed on the element formation region 100 a, and at the interface between the oxygen-containing film 109 and the high dielectric constant film 110.
  • a TiN film 113 and a polysilicon film 114 are sequentially formed on the gate insulating film 112.
  • the high dielectric constant film 110 is formed not only on the element formation region 100 a but also on the element isolation region STI. Specifically, in the element formation region via the base insulating film 105 and the first cap film 106. It is also provided on the upper side surface 104a (second portion 110b). Therefore, the first cap film 106 is sandwiched between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110 on the upper side surface 104a in the element formation region. Similarly, the second cap film 111, the TiN film 113, and the polysilicon film 114 are formed not only on the element formation region 100a but also on the element isolation region STI.
  • a sidewall spacer 117 is formed on the side surface of the gate electrode 115, and an N-type extension region 116 is formed below the side of the gate electrode 115 in the element formation region 100a.
  • An N-type source / drain region 118 is formed below the side wall spacer 117.
  • the first cap film 106 is sandwiched between the base insulating film 105 and the element isolation insulating film 107 in the trench 104, and the base is formed on the upper side surface 104a in the element formation region. It is sandwiched between the insulating film 105 and the second portion 110 b of the high dielectric constant film 110.
  • the base insulating film 105 contains lanthanum, particularly in the vicinity of the interface with the first cap film 106. For these reasons, since an electric dipole is generated at the interface between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, the threshold voltage is applied by the first cap film 106 at the edge portion A of the N-type FET. Can be reduced. Therefore, in this embodiment, as shown by the line 61 in FIG. 7, it is possible to suppress a decrease in narrow channel characteristics.
  • the threshold voltage can be reduced by the first cap film 106 at the edge portion A of the N-type FET. Therefore, even when the thickness of the second cap film 111 is reduced at the edge portion A of the N-type FET when the second cap film 111 is formed (coverage deterioration), it is possible to suppress a decrease in narrow channel characteristics. . Furthermore, even when the high dielectric constant film 110 is formed and the thickness of the high dielectric constant film 110 becomes thicker at the edge portion A of the N-type FET (loading effect), it is possible to suppress a decrease in narrow channel characteristics. In addition, even if lanthanum in the second cap film 111 diffuses into the gate electrode 115 during the heat treatment, it is possible to suppress a decrease in narrow channel characteristics.
  • this embodiment may have the following configuration.
  • the silicon nitride film 102, the silicon nitride film 102, and the silicon oxide film 101 are positioned so that the etching end faces of the silicon nitride film 102 and the silicon oxide film 101 are about 5 nm from the etching end face of the substrate 100. It is preferable to etch the silicon oxide film 101 and the substrate 100. Thereby, in the process of forming the base insulating film 105 on the side wall and the bottom surface of the trench 104, which is the next process, the corner at the upper end of the side wall of the trench 104 can be rounded off. Thereby, it is possible to avoid the concentration of the electric field at the upper end of the sidewall of the trench 104.
  • the structure of the base insulating film 105, and the structure of the first cap film 106 lanthanum forms the base insulating film 105 until the first cap film 106 is completely removed. May diffuse.
  • the boundary between the base insulating film 105 and the first cap film 106 does not exist on the upper side surface 104a in the element formation region.
  • the first cap film 106 is not formed on the base insulating film 105, and instead, the base insulating film 105 is the second portion of the high dielectric constant film 110. Lanthanum is contained in the vicinity of the interface with 110b.
  • the first cap film 106 may be removed after lanthanum is diffused from the first cap film 106 to the base insulating film 105.
  • the heat treatment in FIG. 2 (c) may be omitted.
  • the lanthanum in the first cap film 106 diffuses into the base insulating film 105 by the heat treatment in FIG. 3B or the heat treatment in FIGS. 4B and 5B.
  • FIG. 2C the degradation of the narrow channel characteristics can be suppressed even when the first cap film 106 is removed after the heat treatment. Therefore, it is preferable to perform heat treatment in FIG.
  • the second cap film 111 is completely removed depending on the conditions of the heat treatment, the configuration of the high dielectric constant film 110, and the configuration of the second cap film 111.
  • Lanthanum may diffuse to the lower part of the high dielectric constant film 110 or the upper part of the oxygen-containing film 109.
  • the second cap film 111 is not formed on the high dielectric constant film 110, and instead, the interface between the oxygen-containing film 109 and the high dielectric constant film 110.
  • the second cap film 111 is replaced with the oxygen-containing film 109 and the high dielectric constant film 110. What is necessary is just to form between.
  • the base insulating film 105 is not limited to a silicon oxide film, and may be a silicon oxynitride film, for example. If the base insulating film 105 contains oxygen, the first cap film 106 can be used to suppress degradation of the narrow channel characteristics.
  • the film thickness of the base insulating film 105 is not limited to 2 nm, and may be in the range of about 1 to 10 nm. When the thickness of the base insulating film 105 is in the range of about 0.5 to 15 nm, it is possible to suppress the degradation of narrow channel characteristics.
  • the first cap film 106 only needs to contain a metal that can reduce the threshold voltage of the N-type FET.
  • a metal that can reduce the threshold voltage of the N-type FET.
  • Examples of such a metal include dysprosium (Dy), scandium (Sc), erbium (Er), magnesium (Mg), and strontium (Sr) in addition to lanthanum. Therefore, the first cap film 106 is not limited to the lanthanum oxide film, and may be a film made of any one of the above metals, or an oxide film of any one of the above metals. It may be a film containing any two or more of the metals, or a film containing an oxide of any two or more of the metals. good.
  • the film thickness of the first cap film 106 is not limited to 1 nm. It is preferable to adjust the film thickness of the first cap film 106 in accordance with the amount of decrease in the threshold voltage at the edge portion A of the N-type FET. That is, when it is assumed that the threshold voltage decrease amount at the edge portion A of the N-type FET is small (for example, when the gate width is not so narrow), the thickness of the first cap film 106 is reduced (for example, 0.5 nm), and when the reduction amount of the threshold voltage at the edge portion A of the N-type FET is assumed to be large (for example, when the gate width is narrow), the thickness of the first cap film 106 is increased.
  • a film may be formed (for example, 2 nm).
  • the first cap film 106 may be formed only on the upper side surface 104 a in the element formation region with the base insulating film 105 interposed therebetween.
  • the high dielectric constant film 110 may include only the first portion 110a and the second portion 110b.
  • the high dielectric constant film 110 may be made of a material having a higher dielectric constant than silicon oxide, silicon nitride, and silicon oxynitride. Specifically, a metal oxide, metal oxynitride having a dielectric constant of 8 or more, A silicate or a nitrogen-containing silicate may be used. Therefore, the high dielectric constant film 110 is not limited to the HfO 2 film, but is an HfSiO film (hafnium silicon oxide film), an HfSiON film (hafnium silicon oxide film), a ZrO 2 film (zirconium oxide film), or an HfZrO film (hafnium film). Zirconium oxide film) or the like.
  • the second cap film 111 is not limited to a lanthanum oxide film, and any film that can be used as the first cap film 106 may be used. Further, the first cap film 106 and the second cap film 111 may be made of the same material or different materials.
  • the gate insulating film 112 may not contain lanthanum. Even if the gate insulating film 112 does not contain lanthanum, if the first cap film 106 is formed between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, Degradation of narrow channel characteristics can be suppressed.
  • any one single layer film or two layers of TaN film (tantalum nitride film), TaC film (tantalum carbide film), TaCN (tantalum nitride carbide film), etc. More than one type of laminated film may be used. Further, the gate electrode 115 may not have the polysilicon film 114.
  • a P-type pocket region may be formed below the N-type extension region 116 in the element formation region 100a. Further, a silicide layer made of NiSi having a thickness of, for example, 20 nm may be formed on the upper surface of the gate electrode 115 and the upper surface of the N-type source / drain region 118.
  • the conductivity type of the transistor may be P-type.
  • the semiconductor device according to the present embodiment includes a P-type FET, the conductivity types in the above description are opposite to each other, and the first and second cap films 106 and 111 are aluminum films or aluminum oxide films. is there.
  • an N-type FET and a P-type FET may be formed with the element isolation region STI interposed therebetween.
  • the present invention is useful, for example, for a transistor having a high dielectric constant film.
  • substrate substrate (semiconductor substrate) 100a Element formation region 101 Silicon oxide film 102 Silicon nitride film 103 resist pattern 104 trench 104a Upper side in element formation region 105 Underlying insulating film 106 First cap membrane 107 Element isolation insulating film 107a recess 109 Oxygen-containing membrane 110 High dielectric constant film 110a first part 110b second part 111 Second cap membrane 112 Gate insulation film 113 TiN film 114 Polysilicon film 115 Gate electrode 116 N-type extension area 117 Sidewall spacer 118 N-type source / drain region STI element isolation region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne un dispositif semiconducteur, une région d'isolation d'élément (STI) étant aménagée dans une tranchée (104) formée sur un substrat semiconducteur (100) et comportant un film (105) d'isolation de base formé sur la paroi latérale de la tranchée (104). Un film (112) d'isolation de grille est formé sur une région (100a) de formation d'élément, le film (112) d'isolation de grille comprenant un film (110) à haute constante diélectrique. La première partie (110a) du film (110) à haute constante diélectrique est formée sur la surface supérieure de la région (100a) de formation d'élément et la deuxième partie (110b) du film (110) à haute constante diélectrique est formée sur la surface latérale supérieure (104a) de la région de formation d'élément, le film (105) d'isolation de base étant intercalé entre celles-ci. Un premier film (106) de couverture, contenant un métal qui modifie la tension seuil d'un transistor MIS, est placé entre la deuxième partie (110b) et le film (105) d'isolation de base.
PCT/JP2010/004821 2009-09-28 2010-07-29 Dispositif semiconducteur et procédé pour sa fabrication Ceased WO2011036841A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-223028 2009-09-28
JP2009223028A JP2011071431A (ja) 2009-09-28 2009-09-28 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
WO2011036841A1 true WO2011036841A1 (fr) 2011-03-31

Family

ID=43795611

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/004821 Ceased WO2011036841A1 (fr) 2009-09-28 2010-07-29 Dispositif semiconducteur et procédé pour sa fabrication

Country Status (2)

Country Link
JP (1) JP2011071431A (fr)
WO (1) WO2011036841A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2535924A1 (fr) * 2011-06-16 2012-12-19 STMicroelectronics (Crolles 2) SAS Circuit integre comprenant une tranchée d'isolement et procédé correspondant
US9087872B2 (en) 2011-07-27 2015-07-21 Stmicroelectronics (Crolles 2) Sas Method for forming an insulating trench in a semiconductor substrate and structure, especially CMOS image sensor, obtained by said method
CN117690954A (zh) * 2024-02-01 2024-03-12 合肥晶合集成电路股份有限公司 一种半导体器件及其制作方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8343865B2 (en) * 2010-01-21 2013-01-01 Renesas Electronics Corporation Semiconductor device having dual work function metal
US10510855B2 (en) 2017-11-14 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor layout to reduce kink effect
DE102018114750A1 (de) 2017-11-14 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor-layout zum reduzieren des kink-effekts
US10468410B2 (en) 2017-11-15 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Metal gate modulation to improve kink effect
US10734398B2 (en) 2018-08-29 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Flash memory structure with enhanced floating gate
US11239313B2 (en) 2018-10-30 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated chip and method of forming thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01138730A (ja) * 1987-11-25 1989-05-31 Fujitsu Ltd 半導体装置
JP2001160623A (ja) * 1999-12-02 2001-06-12 Nec Ic Microcomput Syst Ltd 半導体装置とその製造方法
JP2006269789A (ja) * 2005-03-24 2006-10-05 Toshiba Corp 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01138730A (ja) * 1987-11-25 1989-05-31 Fujitsu Ltd 半導体装置
JP2001160623A (ja) * 1999-12-02 2001-06-12 Nec Ic Microcomput Syst Ltd 半導体装置とその製造方法
JP2006269789A (ja) * 2005-03-24 2006-10-05 Toshiba Corp 半導体装置及びその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2535924A1 (fr) * 2011-06-16 2012-12-19 STMicroelectronics (Crolles 2) SAS Circuit integre comprenant une tranchée d'isolement et procédé correspondant
FR2976726A1 (fr) * 2011-06-16 2012-12-21 St Microelectronics Crolles 2 Circuit integre comprenant une tranchee d'isolement et procede correspondant
US8829622B2 (en) 2011-06-16 2014-09-09 Stmicroelectronics (Crolles 2) Sas Integrated circuit comprising an isolating trench and corresponding method
US9117876B2 (en) 2011-06-16 2015-08-25 Stmicroelectronics (Crolles 2) Sas Integrated circuit comprising an isolating trench and corresponding method
US9087872B2 (en) 2011-07-27 2015-07-21 Stmicroelectronics (Crolles 2) Sas Method for forming an insulating trench in a semiconductor substrate and structure, especially CMOS image sensor, obtained by said method
CN117690954A (zh) * 2024-02-01 2024-03-12 合肥晶合集成电路股份有限公司 一种半导体器件及其制作方法
CN117690954B (zh) * 2024-02-01 2024-05-07 合肥晶合集成电路股份有限公司 一种半导体器件及其制作方法

Also Published As

Publication number Publication date
JP2011071431A (ja) 2011-04-07

Similar Documents

Publication Publication Date Title
JP5442332B2 (ja) 半導体装置およびその製造方法
JP5235784B2 (ja) 半導体装置
TWI446457B (zh) 橫向擴散金氧半電晶體及其製造方法
US8183641B2 (en) Semiconductor device and method for manufacturing same
JP5427148B2 (ja) 半導体装置
US20130260549A1 (en) Replacement gate with reduced gate leakage current
WO2011036841A1 (fr) Dispositif semiconducteur et procédé pour sa fabrication
TWI469262B (zh) 半導體裝置之製造方法及半導體裝置
US9059315B2 (en) Concurrently forming nFET and pFET gate dielectric layers
US9196706B2 (en) Method for manufacturing P-type MOSFET
CN102549755A (zh) 具有氧扩散阻挡层的半导体器件及其制造方法
US20120045876A1 (en) Method for manufacturing a semiconductor device
JP2011249402A (ja) 半導体装置およびその製造方法
US9029225B2 (en) Method for manufacturing N-type MOSFET
JP4005055B2 (ja) 半導体装置およびその製造方法
JP4040602B2 (ja) 半導体装置
US20140035058A1 (en) Semiconductor Devices and Methods of Manufacturing the Same
JP5444176B2 (ja) 半導体装置
JP2011054872A (ja) 半導体装置及びその製造方法
US20100123200A1 (en) Semiconductor device and method of manufacturing the same
US10403553B2 (en) Manufacturing method for dual work-function metal gates
JP4828982B2 (ja) 半導体装置の製造方法
JP2012099549A (ja) 半導体装置の製造方法
KR20100038976A (ko) 질소가 도핑된 게이트 절연막을 포함하는 반도체 소자 및 그 제조방법
WO2009101824A1 (fr) Transistor à effet de champ mis et son procédé de fabrication, et dispositif à semi-conducteur et son procédé de fabrication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10818522

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10818522

Country of ref document: EP

Kind code of ref document: A1