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WO2011098549A1 - Procédé de texturation sur côté unique - Google Patents

Procédé de texturation sur côté unique Download PDF

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Publication number
WO2011098549A1
WO2011098549A1 PCT/EP2011/052009 EP2011052009W WO2011098549A1 WO 2011098549 A1 WO2011098549 A1 WO 2011098549A1 EP 2011052009 W EP2011052009 W EP 2011052009W WO 2011098549 A1 WO2011098549 A1 WO 2011098549A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
providing
etching
adhesive layer
texturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2011/052009
Other languages
English (en)
Inventor
Victor Prajapati
Joachim John
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Katholieke Universiteit Leuven, Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Katholieke Universiteit Leuven
Priority to US13/576,925 priority Critical patent/US8969216B2/en
Priority to EP11702997.5A priority patent/EP2534698B1/fr
Priority to CN201180009272.2A priority patent/CN102822990B/zh
Publication of WO2011098549A1 publication Critical patent/WO2011098549A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a method for single side texturing of crystalline semiconductor substrates, such as e.g. crystalline silicon substrates.
  • one side e.g. the front side or front surface
  • the other side e.g. the rear side
  • the front side is textured to substantially reduce light reflection such that a substantial amount of the incident light is captured by the photovoltaic cell.
  • the rear side is polished such that it can act as a mirror for reflecting light (e.g. infrared light) that passes through the substrate without being absorbed. The light reflected at the rear side can pass a second time through the substrate, thereby increasing the chances of being absorbed and creating charge carriers.
  • the front silicon surface is generally textured by means of wet chemical etching.
  • alkaline based solutions such as KOH/IPA or NaOH/IPA (IPA: Isopropyl alcohol) based solutions are used for texturing monocrystalline silicon substrates.
  • IPA Isopropyl alcohol
  • HF/HN0 3 mixtures are often used for texturing.
  • a saw damage removal (SDR) step is performed, typically removing a silicon layer of about 10 micrometer thickness at both sides of the wafers.
  • both sides are textured by wet etching, thereby removing typically about 5 micrometer of silicon at both sides of the wafers.
  • the rear side of the wafers is polished using a one-side polishing process, e.g. a 'floating wafer' process wherein only the rear side of the wafers is submerged in an etching solution.
  • a one-side polishing process e.g. a 'floating wafer' process wherein only the rear side of the wafers is submerged in an etching solution.
  • Such a process sequence results in a reduction of the silicon wafer thickness with typically 40 micrometer. This means that for industrial silicon wafer thicknesses of 180 micrometer, the silicon loss is more that 20%.
  • the wet processing is rather time consuming and hinders high throughput processing that is required for cost effective photovoltaic cell processing.
  • the silicon loss can be reduced by providing a masking layer, e.g. a dielectric layer, at the rear side of the substrate after saw damage removal and before the texturing step.
  • a masking layer e.g. a dielectric layer
  • the reduction of the silicon wafer thickness can be limited to typically 25 micrometer.
  • it requires an additional process step for providing the masking layer.
  • plasma texturing dry etching
  • dry etching dry etching
  • embodiments of the present invention provide a method for single side texturing of a crystalline semiconductor substrate, the method comprising: providing a substrate, for example a semiconductor substrate such as a crystalline semiconductor substrate comprising a first surface and a second surface opposite to one another with respect to the substrate; providing a masking layer with a random pattern on the first surface of the substrate; and etching the substrate in a polishing solution, thereby texturing the first surface of the substrate and polishing the second surface opposite to the first surface in a single wet etching step.
  • the substrate e.g. crystalline semiconductor substrate can for example be a crystalline silicon substrate.
  • a method according to embodiments of the present invention it is fast in view of the polishing step of the second surface and the texturing step of the first surface being carried out in a single step.
  • a method according to embodiments of the present invention may for example be less time consuming than prior art methods, thus allowing a higher throughput and more cost effective photovoltaic cell processing.
  • Providing a semiconductor substrate may comprise providing a substrate, e.g. a semiconductor substrate, having a non-polished or rough first and/or second surface.
  • the substrate may be an as-cut silicon wafer, obtained for example by wire sawing the substrate from an ingot.
  • This has the advantage that pre-processing of the substrates is reduced or not required at all.
  • a short prior art texturing step could be performed first, for example using KOH/IPA as used in prior art texturing processes, such that the initially polished surfaces become rough.
  • the prior art texturing step can last just long enough to create some surface roughness. It does not need to last so long as to provide a good surface texturing as required e.g. for photovoltaic cells.
  • a method according to embodiments of the present invention can be performed, leading to a polished rear surface and a textured front surface without the need for providing a masking layer at the rear side of the substrate before performing the texturing step according to embodiments of the present invention.
  • Providing a masking layer with a random pattern on the first surface can comprise providing an adhesive layer on the first surface and subsequently removing the adhesive layer, thereby leaving randomly distributed traces of the adhesive layer on the first surface.
  • the adhesive layer may for example be an organic adhesive layer.
  • the adhesive layer may be an adhesive tape. This way of working is very simple and not very time consuming.
  • the adhesive layer may then for example be provided from a roll-to-roll sheet. Removing the adhesive layer from the first surface of the substrate may comprise leaving traces of the adhesive layer on the first surface of the substrate. These traces may be left in a random pattern. In particular embodiments, where the first surface already shows some roughness, the random pattern may be correlated to the roughness of the substrate.
  • providing a masking layer with a random pattern can comprise spraying a masking layer on the first surface.
  • providing a masking layer with a random pattern can comprise providing the masking layer by means of a roller. Also any other method for providing a masking layer with a random pattern known by a person skilled in the art and suitable for obtaining the desired features may be used.
  • Providing an adhesive layer on the first surface of the substrate may comprise providing the adhesive layer on the first surface of the substrate at room temperature.
  • Etching the substrate in a polishing solution can for example comprise etching the substrate in an alkaline solution such as a NaOH based polishing solution or a KOH based polishing solution, for example a NaOH:H20 or a KOH:H20 solution.
  • the NaOH concentration or the KOH concentration may be in the range between 5% and 45%, e.g. in the range between 10% and 40%, for example in the range between 15% and 30%.
  • Etching the substrate in a polishing solution may be performed at a temperature between 60°C and 95°C, for example between 70°C and 90°C.
  • Etching the substrate in a polishing solution may be performed with an etching time between 1 minute and 45 minutes, for example between 2 minutes and 30 minutes, for example between 2 minutes and 10 minutes.
  • the etching step results in a polished rear side. Due to the presence of a random masking layer at the front side of the substrate, the etching step results in a textured front side, e.g. a randomly textured front side. As etching times are not extremely long, removal of substrate material due to etching is limited, and the thickness of the substrate may be reduced with less than 20% during the etching step, e.g. with less than 10%. Hence thinner wafers can be used to start from, leading to reduction of material consumption.
  • the present invention provides a single side textured substrate manufactured in accordance with a method according to embodiments of the first aspect of the present invention.
  • the present invention also provides a photovoltaic cell comprising a single side textured substrate according to embodiments of the present invention.
  • FIG. 1 schematically illustrates a method according to an embodiment of the present invention.
  • FIG. 2 shows the reflectivity measured at textured silicon surfaces obtained by different texturing methods.
  • FIG. 3 shows the short-circuit current density J sc of a photovoltaic cell fabricated on a single side textured substrate using different texturing methods.
  • FIG. 4 shows the open-circuit voltage V oc of a photovoltaic cell fabricated on a single side textured substrate using different texturing methods.
  • FIG. 5 shows the Fill Factor FF of a photovoltaic cell fabricated on a single side textured substrate using different texturing methods.
  • FIG. 6 shows the energy conversion efficiency E ff of a photovoltaic cell fabricated on a single side textured substrate using different texturing methods.
  • the term "comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof.
  • the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B.
  • the front surface, front side, first surface or first side of a photovoltaic cell is the surface or side adapted for being oriented towards a light source and thus for receiving illumination.
  • the back surface, back side, rear surface, rear side, second surface or second side of a photovoltaic cell is the surface or side, with respect to a substrate forming the photovoltaic cell, opposite to the front surface.
  • the back surface, back side, rear surface, rear side, second surface or second side is the surface or side of the photovoltaic cell adapted for reflecting light that passes through the substrate without being absorbed.
  • the front surface, front side, first surface or first side of a photovoltaic cell substrate is the surface or side of the substrate adapted for being oriented towards a light source.
  • the back surface, back side, rear surface, rear side, second surface or second side of a photovoltaic cell substrate is the surface or side opposed to the front surface of the substrate.
  • Embodiments of the present invention provide a method for texturing a first surface of a substrate, e.g. a semiconductor substrate such as for example a silicon substrate and polishing a second surface of the substrate, the second surface being opposite to the first surface.
  • the method according to embodiments of the present invention is based on a wet etching process. It is an advantage of a method according to embodiments of the present invention that the amount of substrate material, e.g. semiconductor material such as for example silicon removed is smaller than in prior art wet-etching based methods for front side texturing and rear side polishing. Furthermore, the method of the present invention is less time consuming than prior art methods, thus allowing a higher throughput and more cost effective photovoltaic cell processing.
  • a method for single side texturing of a crystalline semiconductor substrate, such as a crystalline silicon substrate comprises: providing a crystalline semiconductor substrate, e.g. a crystalline silicon substrate; providing a masking layer with a random pattern at a first surface of the semiconductor substrate; and etching the substrate in a polishing solution, thereby texturing the first surface of the substrate and polishing a second surface opposite to the first surface in a single etching step.
  • Providing a crystalline semiconductor substrate may comprise providing a semiconductor substrate having a non-polished or rough first surface.
  • the substrate may be an as-cut silicon wafer.
  • Providing a masking layer with a random pattern can comprise providing an adhesive layer on the first surface and subsequently removing the adhesive layer, thereby leaving randomly distributed traces of the adhesive layer on the first surface.
  • providing a masking layer with a random pattern can comprise spraying a masking layer on the first surface. Any other method known by a person skilled in the art for providing a random masking layer may be used.
  • Etching the wafer in a polishing solution can for example comprise etching the wafer in an alkaline polishing solution such as a NaOH based polishing solution or a KOH based polishing solution.
  • a substrate 10 such as a semiconductor substrate e.g. a silicon wafer 10, is provided, having a first surface 12 and a second surface 14 opposite to the first surface 12 with respect to the substrate.
  • the first surface 12 and the second surface 14 may be rough, non-polished surfaces.
  • a semiconductor, e.g. silicon, as-cut wafer can be used, obtained e.g. by wire sawing from a semiconductor, e.g. silicon, ingot.
  • the surface of such an as-cut semiconductor, e.g. silicon, wafer is rough and contaminated with impurities, e.g. metal impurities from the slurry and the metal wire used during the wafering step (wire sawing).
  • a masking layer is provided on the first surface 12 of the substrate 10.
  • the masking layer may be an adhesive layer 20 such as for example an organic adhesive layer or an adhesive tape, which is provided on the first surface 12 of the substrate, e.g. of the rough silicon wafer 10.
  • the masking layer, e.g. adhesive layer 20 may be provided at room temperature. It is an advantage of using such an adhesive layer 20 (e.g. an adhesive tape) that it can be provided fast and at low cost.
  • an adhesive layer can be provided on the wafer from a roll-to-roll sheet, the wafer e.g. being held by vacuum. The roll of adhesive could provide sufficient pressure to obtain good coverage of the wafer surface.
  • the masking layer is provided with a random pattern.
  • the masking layer was an adhesive layer
  • the adhesive layer is removed, thereby leaving traces 21 of the adhesive layer on the first surface 12 of the substrate, e.g. the as cut silicon wafer 10.
  • These traces form an irregular or random pattern, e.g. correlated to the roughness of the rough substrate, e.g. the as-cut silicon surface.
  • a roll-to-roll process can be used for providing and shortly afterwards removing the adhesive layer.
  • a polishing solution such as for example an alkaline polishing solution, e.g. a solution comprising NaOH or KOH.
  • a NaOH:H 2 0 or a KOH:H 2 0 solution can be used wherein the NaOH concentration or the KOH concentration is in the range between 5% and 45%, e.g. in the range between 10% and 40%, e.g. in the range between 15% and 30%.
  • the etching temperature can for example be in the range between 60 Q C and 95 Q C, for example between 70 Q C and 90 Q C.
  • the etching time can for example be in the range between 1 minute and 45 minutes, e.g. in the range between 2 minutes and 30 minutes, e.g.
  • etching step may at the same time also results in removal of the random mask.
  • 20 weight% of NaOH or KOH in H 2 0 can be used, at a temperature of 80 Q C and with an etching time of 5 minutes.
  • Other etching solutions and etching parameters known to a person skilled in the art can be used. Due to the masking effect of the patterned masking layer, e.g. the remaining traces at the first surface 12 of the substrate, e.g. silicon wafer 10, this etching step results in a textured front surface, as illustrated in FIG. 1(c). Due to the absence of such patterned masking layer, e.g. traces at the second surface 14 of the wafer 10, the second surface 14 is polished and saw damage may be reduced or even completely removed. In addition, the etching step may at the same time also results in removal of the random mask.
  • the process of embodiments of the present invention can lead to a substantial reduction of the processing time with more than 50%, e.g. more than 70%, due to a combination of saw damage removal, front surface texturing and rear surface polishing in a single wet etching step.
  • the amount of substrate material, e.g. silicon, removed can be reduced with typically 50% as compared to the amount of substrate material, e.g. silicon, removed in prior art processes.
  • substrate material e.g. silicon
  • the natural roughness of an as-cut wafer can be used for the distribution of the masking material on one side.
  • the roughness allows the masking effect to be localized.
  • the proposed technique has been applied on 20 Cz-Si (156 cm 2 ) wafers.
  • the wafers have been processed using an advanced industrial process flow for high efficiency photovoltaic cells.
  • the Cz wafers had a resistivity of 1 Ohm-cm and a starting thickness of 150 micrometer.
  • Square wafers of 12.5 cm x 12.5 cm were used (substrate area 156 cm 2 ).
  • the as-cut wafers were heated to 50 Q C, and an organic masking material was provided on a first surface of the wafers.
  • a pressure roll was applied to ensure adequate coverage.
  • the adhesive was removed at room temperature.
  • a wet etching step was performed in a 1:5 NaOH:H 2 0 etching solution, at 80 Q C, for 4.5 minutes. This wet etching step removes saw damage and contaminants, and at the same time provides front side texturing and rear side polishing of the wafers.
  • the wet etching step removes the traces of organic masking material.
  • a reflectance curve for differently textured semiconductor surfaces can be measured, for comparison reasons.
  • the measured reflectance curve for differently textured monocrystalline silicon surfaces is depicted in FIG. 2.
  • the reflectance at a textured surface obtained with a process of embodiments of the present invention (upper curve, 'new') is compared with the reflectance at a surface textured using a random pyramid process as described in the state of the art, based on etching in a KOH/IPA solution (lower curve ' P' in FIG. 2), and with the reflectance at a surface textured using an industrial process provided by RENA (middle curve 'RENA' in FIG. 2).
  • the results shown for the silicon surfaces textured with a method according to an embodiment of the present invention are based on measurements on 20 different wafers, with 9 measurement points on each wafer.
  • the ' P' and 'RENA' results are based on measurements on 2 wafers each, with 9 measurement points per wafer.
  • the larger spread in the reflectance for wafers textured according to a method according to embodiments of the present invention as compared to the 'RP' and 'RENA' wafers may be related to a non-uniform coverage of the wafer by the adhesive providing the random mask.
  • the wafers were neutralized, in the example described in a hydrochloric solution.
  • the wafers were cleaned and an emitter was formed on the front side, in the example described for example by using a standard 60 ohm/sq POCI 3 based diffusion process.
  • the rear surface was then passivated, in the example described with a local AI-BSF (Back Surface Field) and a dielectric Si0 2 /SiN stack.
  • An antireflection coating in the example described for example a SiN antireflection coating, was provided at the front side, for example by means of PECVD SiN.
  • Laser ablation of a dot array pattern was performed on the rear side for providing vias through the dielectric stack.
  • Aluminum was deposited at the rear side for forming rear side metal/semiconductor contacts and a silver paste was screen printed on the front side for forming front side metal/semiconductor contacts.
  • a co-firing step was performed in a belt furnace to ensure ohmic contacts on the front side as well as a local BSF in the open areas of the dielectric stack.
  • FIGS. 3 to 6 Cell results are depicted in FIGS. 3 to 6.
  • the short-circuit current density J sc (FIG.3), the open- circuit voltage V oc (FIG.4), the Fill Factor FF (FIG.5) and the energy conversion efficiency E ff (FIG.6) are shown for cells textured using a method according to embodiments of the present invention and for cells textured using a prior art random pyramid process ('RP').
  • the short circuit current density J sc of the photovoltaic cells textured using a method according to embodiments of the present invention is equivalent or slightly better than the short circuit current density J sc of the cells textured with prior art methods.
  • the good Fill Factor FF and the good open circuit voltage V oc obtained for the cells textured according to embodiments of the present invention show that good contacts are obtained as well as a good surface passivation.
  • An average energy conversion efficiency Eff of 17.5% was achieved, with a top efficiency of 18.4%.
  • FIG. 3 to FIG. 6 also the student's t-test results are illustrated for both test groups (prior art devices and devices according to embodiments of the present invention).
  • the student's t-test is a way to show whether to sets of data are statistically different or not. In the results shown, the circles lie on top of each other, meaning that there is a 95% chance that the difference between the two sets of data is negligible.
  • the method according to embodiments of the present invention and the prior art method yield statistically the same results.

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Abstract

La présente invention concerne un procédé de texturation sur côté unique d'un substrat à semi-conducteur cristallin (10). Ledit procédé consiste : à fournir un substrat (10), par exemple un substrat à semi-conducteur, qui comprend une première surface (12) et une seconde surface (14) l'une en face de l'autre par rapport au substrat (10) ; à fournir une couche de masquage (21), qui possède un motif aléatoire, sur la première surface (12) du substrat (10) ; et à graver le substrat (10) dans une solution de polissage, pour ainsi texturer la première surface (12) du substrat (10) et polir la seconde surface (14) dans une étape unique de gravure à l'état humide.
PCT/EP2011/052009 2010-02-11 2011-02-11 Procédé de texturation sur côté unique Ceased WO2011098549A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US13/576,925 US8969216B2 (en) 2010-02-11 2011-02-11 Method for single side texturing
EP11702997.5A EP2534698B1 (fr) 2010-02-11 2011-02-11 Procédé de texturation sur côté unique
CN201180009272.2A CN102822990B (zh) 2010-02-11 2011-02-11 单侧纹理化的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30344510P 2010-02-11 2010-02-11
US61/303,445 2010-02-11

Publications (1)

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WO2011098549A1 true WO2011098549A1 (fr) 2011-08-18

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US (1) US8969216B2 (fr)
EP (1) EP2534698B1 (fr)
CN (1) CN102822990B (fr)
TW (1) TWI523088B (fr)
WO (1) WO2011098549A1 (fr)

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WO2013087071A1 (fr) * 2011-12-15 2013-06-20 Rena Gmbh Procédé de gravure lisse unilatérale d'un substrat silicium
WO2016012405A1 (fr) * 2014-07-21 2016-01-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Procédé et dispositif pour structurer les faces supérieure et inférieure d'un substrat semi-conducteur
DE102017206455A1 (de) * 2017-04-13 2018-10-18 Rct Solutions Gmbh Verfahren und Vorrichtung zur chemischen Bearbeitung eines Halbleiter-Substrats

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CN107887459B (zh) * 2017-10-30 2019-09-03 扬州协鑫光伏科技有限公司 单面湿法黑硅硅片
CN107863398B (zh) * 2017-10-30 2019-09-03 扬州协鑫光伏科技有限公司 单面湿法黑硅硅片的制备方法
CN112838140B (zh) * 2019-11-22 2022-05-31 阜宁阿特斯阳光电力科技有限公司 多晶硅太阳能电池及制备方法以及制备其绒面结构的方法
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Publication number Priority date Publication date Assignee Title
WO2013087071A1 (fr) * 2011-12-15 2013-06-20 Rena Gmbh Procédé de gravure lisse unilatérale d'un substrat silicium
WO2016012405A1 (fr) * 2014-07-21 2016-01-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Procédé et dispositif pour structurer les faces supérieure et inférieure d'un substrat semi-conducteur
DE102017206455A1 (de) * 2017-04-13 2018-10-18 Rct Solutions Gmbh Verfahren und Vorrichtung zur chemischen Bearbeitung eines Halbleiter-Substrats

Also Published As

Publication number Publication date
CN102822990A (zh) 2012-12-12
CN102822990B (zh) 2016-03-09
TWI523088B (zh) 2016-02-21
US8969216B2 (en) 2015-03-03
EP2534698A1 (fr) 2012-12-19
EP2534698B1 (fr) 2019-08-28
TW201135827A (en) 2011-10-16
US20120295446A1 (en) 2012-11-22

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