WO2011081130A1 - Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method - Google Patents
Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method Download PDFInfo
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- WO2011081130A1 WO2011081130A1 PCT/JP2010/073530 JP2010073530W WO2011081130A1 WO 2011081130 A1 WO2011081130 A1 WO 2011081130A1 JP 2010073530 W JP2010073530 W JP 2010073530W WO 2011081130 A1 WO2011081130 A1 WO 2011081130A1
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- insulating film
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- the present invention relates to a semiconductor wafer, a semiconductor device, and a semiconductor device manufacturing method using a semiconductor substrate covered with an insulating film.
- the present invention relates to a semiconductor wafer, a semiconductor device, and a method for manufacturing the semiconductor device that prevent peeling of an insulating film in a dicing process.
- BGA ball grid array
- a BGA type semiconductor package cuts a wafer substrate on which a circuit is formed and mounts the semiconductor chip on a substrate called an interposer to complete the package.
- an interposer In addition to the need for a patterned interposer, individual semiconductors A process of individually mounting the chip on the interposer is necessary. For this reason, a dedicated material or manufacturing apparatus has to be used, and there is a drawback that the cost is increased.
- CSP manufacturing method
- a semiconductor wafer is formed in the final process.
- a semiconductor device having a package structure can be obtained by cutting to a predetermined chip size (see, for example, Patent Document 1). Therefore, since the package structure is collectively formed on the wafer-like semiconductor substrate, an interposer is not required as in the prior art, and since processing is performed in the wafer state, a dedicated apparatus is not required. For this reason, the manufacturing efficiency is high and the cost disadvantage is reduced.
- a semiconductor device obtained from a semiconductor wafer by wafer level CSP is obtained by performing package processing on the entire surface of the wafer and then dicing into individual pieces. Therefore, the size of the singulated chip itself becomes a packaged semiconductor device, and a semiconductor device having a minimum projected area with respect to the mounting substrate can be obtained. Further, the wiring distance is shorter than that of the conventional package, and the parasitic capacitance of the wiring is also small.
- a scribe line region is cut using a dicing blade.
- control is performed such as adjusting the rotational speed of the dicing blade, the dicing speed (relative speed between the wafer and the dicing blade), and the like.
- a wafer level CSP using a through-electrode (Through-Silicon Via, TSV) has been proposed.
- the through electrode is an alternative to conventional wire bonding, and is used as an electrode by filling a through hole formed perpendicularly to the inside of a semiconductor device with a conductive metal.
- the through electrode technology can greatly reduce the wiring distance as compared with the conventional method of connecting by wire bonding, and thus contributes to higher speed, power saving, and downsizing of the semiconductor device.
- FIG. 7A is a view showing a cross section of a conventional semiconductor wafer 100.
- a circuit element 103 is provided on a first surface 102a of a wafer-like semiconductor substrate 102 made of Si (silicon), and penetrates from the second surface 102b of the semiconductor substrate 102 to the first surface 102a.
- a through-hole 107 is provided.
- An insulating film 105 is formed on the inner surface of the through hole 107 and at least the second surface side 102 b of the semiconductor substrate 102.
- a wiring 106 is formed on the insulating film 105.
- the insulating film 105, the wiring 106, and the through hole 107 constitute a through electrode 120.
- Reference numeral 104 denotes an electrode pad that is electrically connected to the through electrode 120, and is covered with a passivation layer 108.
- Reference numeral 109 denotes a protective layer covering the circuit element region on the second surface side 102 b of the semiconductor substrate 102.
- the above semiconductor elements are bonded to a supporting substrate 110 made of glass by an adhesive layer 111.
- Reference numeral 115 denotes a dicing tape for holding the semiconductor device 100 in the dicing process.
- a first scribe line region R10 is provided on the first surface side 102a of the semiconductor substrate 102, and a second scribe line is provided on the second surface side 102b in order to prevent the protective layer 109 from being involved in the dicing process.
- a region R11 is provided.
- the protective layer 109 is removed along the scribe line L, and a groove 130 is formed in advance along the scribe line L, thereby facilitating dicing and dicing.
- the circuit element 103 is prevented from being damaged in the process.
- FIG. 7B is a cross-sectional view showing a state in which the dicing blade B is inserted during the dicing process of the semiconductor wafer 100 having the above configuration.
- FIG. 7B when dicing is performed on the conventional semiconductor wafer 100, since the insulating film 105 exists in the second scribe line region R11, when the dicing blade B contacts the insulating film 105, the insulating film 105 is insulated. There was a problem that peeling of the film 105 (indicated by reference numeral C1) occurred.
- FIG. 8 is a top view of the vicinity of a dicing line after the conventional semiconductor wafer 100 is diced by the dicing blade B.
- FIG. 8 is a top view of the vicinity of a dicing line after the conventional semiconductor wafer 100 is diced by the dicing blade B.
- the peeling of the insulating film 105 occurs from the dicing line L in the direction in which the through electrode 120 and the circuit element are formed. As shown in FIGS. 7B and 8, the insulating film 105 is peeled off from the upper surface in the vicinity of the dicing line L. Further, the insulating film 105 on the inner surface of the through hole 107 may be peeled off. Further, the peeling of the insulating film 105 reaches the circuit element region, which causes a defect in the semiconductor device 100. As a result, the semiconductor substrate 102 may be chipped near the dicing blade B as the insulating film 105 is peeled off.
- the present invention has been made in view of such circumstances, and provides a semiconductor wafer, a semiconductor device, and a method for manufacturing the semiconductor device that can prevent the insulating film constituting the semiconductor wafer from peeling off in the dicing process. Objective.
- the present invention adopts the following configuration.
- a first surface on which a plurality of circuit elements and a first scribe line region provided between the plurality of circuit elements are formed is opposite to the first surface.
- a semiconductor wafer comprising: a semiconductor substrate having a second surface on the side; an insulating film formed on the second surface side of the semiconductor substrate; and a wiring formed on the insulating film,
- a second scribe line region that is a region where the insulating film is not formed is provided along the first scribe line region on the second surface side of the substrate.
- a recess may be formed on the second surface of the semiconductor substrate along the second scribe line region.
- a through hole penetrating from the second surface to the first surface may be formed in the semiconductor substrate; and the insulating film may be formed on an inner surface of the through hole.
- the circuit element may be an optical element, and a transparent substrate may be bonded to the first surface on which the circuit element is formed.
- a semiconductor device is a semiconductor device formed by cutting a semiconductor wafer along a scribe line, the first surface on which circuit elements are formed, and the first surface, Comprises a semiconductor substrate having a second surface on the opposite side, an insulating film formed on the second surface side of the semiconductor substrate, and a wiring formed on the insulating film, the insulating film comprising: It is located inside the cutting surface formed by cutting along the scribe line.
- a method for manufacturing a semiconductor device provides a semiconductor substrate in which a plurality of circuit elements are formed on a first surface side and a first scribe line region is provided between the plurality of circuit elements.
- an insulating film removing step for removing the insulating film exposed to the second scribe line region, and a dicing step for cutting the semiconductor wafer from the second surface side along the scribe line are provided.
- the insulating film removing step may be performed, and a recess may be formed on the second surface of the semiconductor substrate along the second scribe line region.
- the method for manufacturing a semiconductor device may further include a through hole forming step of forming a through hole penetrating from the second surface of the semiconductor substrate to the first surface of the semiconductor substrate; The insulating film may be formed on the inner surface of the through hole and on the second surface side of the semiconductor substrate.
- the method for manufacturing a semiconductor device further includes a step of adhering a support substrate to the first surface side of the semiconductor substrate; in the dicing step, the semiconductor substrate and the support substrate are diced in one step. May be.
- the first scribe line region is provided on the first surface side of the semiconductor substrate constituting the semiconductor wafer, and the insulating film formed on the second surface side of the semiconductor substrate has the first A second scribe line region, which is a region where the insulating film is separated, is provided along one scribe line region. Therefore, an effect that the peeling of the insulating film in the dicing process can be prevented can be obtained.
- the insulating film ends on the first surface side and the second surface side of the semiconductor substrate are separated from the end portions of the semiconductor device.
- it is not affected by the stress generated at the end portion of the semiconductor substrate by dicing, so that the defect that the insulating film peels can be reduced.
- even when an external stress is generated in the end portion of the semiconductor device it can be prevented that the insulating film is affected.
- a protective layer that individually covers a region where a circuit element is formed is formed on the second surface side of the semiconductor substrate, and a second scribe line region is provided between the protective layers.
- a protective layer forming step; and an insulating film removing step of removing the insulating film exposed to the second scribe line region after forming the protective layer Therefore, an effect that the peeling of the insulating film in the dicing process can be prevented can be obtained.
- FIG. 1 is a plan view of a semiconductor wafer according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along line AA in FIG. It is sectional drawing which shows the modification of the semiconductor wafer which concerns on 1st embodiment of this invention. It is sectional drawing which shows the dicing process of the semiconductor wafer before the dicing concerning this invention. It is sectional drawing which shows the dicing process of the semiconductor wafer in the dicing which concerns on this invention. It is sectional drawing of the semiconductor device separated into pieces by dicing. It is sectional drawing explaining the removal process of an insulating film. It is sectional drawing explaining the removal process of the insulating film after FIG. 5A.
- FIG. 5B It is sectional drawing explaining the removal process of the insulating film after FIG. 5B. It is a fragmentary sectional view of a semiconductor wafer concerning a second embodiment of the present invention. It is sectional drawing which shows the dicing process of the semiconductor wafer before the conventional dicing. It is sectional drawing which shows the dicing process of the semiconductor wafer in the conventional dicing. It is a top view at the time of dicing the conventional semiconductor wafer.
- FIG. 1 is a plan view showing a semiconductor wafer according to a first embodiment of the present invention, and shows a semiconductor wafer 1 before being separated into semiconductor devices.
- 2A is a cross-sectional view taken along the line AA in FIG. 1, and shows the periphery of the scribe line L.
- FIG. 1 the semiconductor wafer 1 according to the first embodiment of the present invention is cut into pieces into a plurality of semiconductor devices by cutting along a predetermined scribe line L.
- a circuit element 3 is formed in a region defined by the scribe line L on the semiconductor wafer 1.
- a through electrode 20 is formed in the region of the circuit element 3.
- reference numeral 1 is a semiconductor wafer
- reference numeral 2 is a semiconductor substrate
- reference numeral 3 is a circuit element
- reference numeral 4 is an electrode pad
- reference numeral 5 is an insulating film
- reference numeral 6 is a wiring
- reference numeral 7 is a through hole
- reference numeral 8 is a passivation layer.
- Reference numeral 9 denotes a protective layer
- reference numeral 10 denotes a support substrate
- reference numeral 11 denotes an adhesive layer.
- the through electrode 20 includes the insulating film 5, the wiring 6, and the through hole 7.
- the semiconductor substrate 2 provided with the through electrodes 20 and the like is bonded to the support substrate 10 by the adhesive layer 11.
- An electrode pad 4 is provided on the first surface side 2 a of the semiconductor substrate 2.
- a through hole 7 is formed from the second surface 2 b of the semiconductor substrate 2 to the first surface 2 a of the semiconductor substrate 2 where the electrode pads 4 are provided. The surface on which the electrode pad 4 is provided is protected by the passivation layer 8.
- An insulating film 5 is provided on both surfaces (first surface and second surface) of the semiconductor substrate 2 and the inner surface of the through hole 7.
- the insulating film 5 is, for example, SiO 2 , SiN, or a resin film.
- wiring 6 is formed on the insulating film 5 on the inner surface of the through hole 7 and on the second surface side 2 b of the semiconductor substrate 2.
- the wiring 6 is electrically connected to the electrode pad 4.
- the second surface 2 b of the semiconductor wafer 2 is covered with a protective layer 9.
- the protective layer 9 is not always necessary, and the through electrode 20 and the wiring 6 may be exposed.
- the semiconductor substrate 2 is, for example, a semiconductor substrate such as silicon or GaAs.
- the support substrate 10 is a substrate formed of a material different from that of the semiconductor substrate 2, and a material whose thermal expansion coefficient is close to that of the semiconductor substrate 2 is desirable.
- an adhesive made of a material having electrical insulation is used.
- the adhesive forming the adhesive layer 11 for example, polyimide resin, epoxy resin, benzocyclobutane (BCB) resin, silicone resin, acrylic resin, and the like are desirable.
- the semiconductor substrate 2 may be a transparent substrate or an opaque substrate.
- the adhesive layer 11 may be a transparent resin layer or an opaque resin layer. The semiconductor substrate 2 and the adhesive layer 11 can be appropriately selected according to the properties of the circuit element 3 provided on the semiconductor substrate 2.
- the circuit element 3 is, for example, a semiconductor functional element such as a memory, an IC, an imaging element, and a MEMS element.
- the wiring 6 is a wiring layer formed of a conductor (such as various metals or alloys) such as Cu, Al, Ni, Ag, Pb, Sn, Au, Co, Cr, Ti, TiW.
- the formation method of the circuit element 3 as a wiring layer is not specifically limited, For example, sputtering method, a vapor deposition method, a plating method etc., or the combination of these 2 or more methods is mentioned.
- the circuit element 3 as the wiring layer may be a single conductor layer or a laminate of multiple conductor layers.
- a photolithography technique is suitably used for patterning the wiring layer.
- the circuit element 3 may be, for example, a light emitting type or a light receiving type optical element.
- the circuit element 3 may be an element that receives light from the support substrate 10 and changes the optical signal into an electrical signal. Further, the circuit element 3 may be a light emitter that emits light by itself.
- the circuit element 3 is an optical element, a transparent glass substrate or a transparent resin substrate can be selected as the support substrate 10.
- the adhesive layer 11 is also preferably transparent.
- the adhesive layer 11 may be formed of a resin whose refractive index is close to that of the support substrate 10.
- the support substrate 10 is made of glass (refractive index: about 1.5)
- a silicone resin reffractive index: about 1.4 to 1.5
- an acrylic resin reffractive index: about 1.5
- an epoxy resin about 1.5 to 1.6
- the transparent adhesive layer 11 is employed, but the present embodiment is not limited to this.
- an opaque resin can be selected as the adhesive layer 11.
- the adhesive layer 11 is not formed in a portion corresponding to the formation region of the circuit element 3. Therefore, light can freely enter or exit through the region where the adhesive layer 11 is not formed.
- a support substrate 10 is provided on the first surface 2a on which the circuit element 3 is formed. Therefore, when the circuit element 3 is an optical element, the protection of the support substrate 10 can prevent the optical element from being affected by dust or the like.
- Reference symbol L is a scribe line referred to when the semiconductor wafer 1 is diced.
- a first scribe line region R ⁇ b> 1 is provided on the first surface side 2 a of the semiconductor substrate 2.
- the scribe line region is for separating the region into individual semiconductor devices by cutting the region with a dicing blade.
- the symbol R1 indicates the width of the first scribe line region.
- the insulating film 5 On the first surface side 2 a of the semiconductor substrate 2, the insulating film 5 has a region separated along the scribe line L by the width of the first scribe line region R 1. That is, the insulating film 5 is not provided in the first scribe line region R1 on the first surface side 2a. Further, the center line of the first scribe line region R1 coincides with the scribe line L.
- a second scribe line region R2 having a slightly larger width than the first scribe line region R1 is provided on the second surface side 2b of the semiconductor substrate 2.
- the protective layer 9 is not formed along the scribe line L. That is, in the present embodiment, the width R1 of the first scribe line region and the width R2 of the second scribe line region satisfy the relationship R1 ⁇ R2.
- the peeling of the insulating film occurs on both surfaces (first surface and second surface) of the semiconductor substrate. Among them, since the first surface of the semiconductor substrate is covered with an adhesive layer and the second surface of the semiconductor substrate is exposed to the outside, the insulating film is more easily peeled off on the second surface than the first surface. .
- the width of the second scribe line region R2 is relatively wide (R1 ⁇ R2), so that the peeling of the insulating film on the second surface can be reliably ensured.
- the insulating film 5 formed on the second surface side 2b of the semiconductor substrate 2 also includes a region separated along the scribe line L. The separation width is the same as that of the second scribe line region R2. That is, the insulating film 5 is not provided in the second scribe line region R2 on the second surface side 2b. Further, the center line of the second scribe line region R2 coincides with the scribe line region L. That is, the center line of the first scribe line region R1 and the center line of the second scribe line region R2 are coincident.
- a recess 13 is provided in the semiconductor substrate 2 in the second scribe line region R2.
- the recess 13 is a part where the surface of the semiconductor substrate 2 is scraped over a predetermined depth with respect to the second surface 2 b of the semiconductor substrate 2.
- the semiconductor substrate 2 is provided with a step with respect to the second surface 2b, and the semiconductor substrate 2 is thinner than the other regions. Since the thickness of the semiconductor substrate in the region to be cut becomes thinner as the height of the step becomes larger, dicing can be easily performed. As a result, chipping defects during dicing can be reduced.
- the semiconductor substrate is usually shaved to reduce its thickness, and then the through hole is formed.
- the second surface is shaved.
- the surface of the second surface has defects in the crystal lattice or fine cracks. Therefore, conventionally, when the insulating film is diced together with the second surface of the semiconductor substrate by the dicing blade B, there is a problem that the insulating film formed on the second surface is easily peeled off.
- the insulating film is not formed in the second scribe line region R2, dicing can be performed more easily. Furthermore, it is possible to reliably prevent the insulating film from peeling off.
- the through electrode is usually formed at a corner of the circuit element.
- the through hole of the through electrode is formed in a region near the scribe line L. Therefore, in the conventional semiconductor wafer 100, the through hole is easily affected by dicing along the scribe line L. Therefore, when dicing along the scribe line L, the insulating film 105 formed on the second surface 102a of the semiconductor substrate 102 is easily peeled off. As the insulating film 105 is peeled off, the insulating film formed inside the through hole may be peeled off. Furthermore, since the crystal lattice on the second surface has defects or fine cracks, the semiconductor substrate in the part of the insulating film 105 that has been peeled off may be lost.
- the insulating film 5 is not provided in the second scribe line region R2 on the second surface side 2b of the semiconductor substrate 2 according to the present embodiment. Therefore, peeling of the insulating film 5 on the second surface side 2b can be reliably prevented. As a result, peeling of the insulating film 5 inside the through hole can be surely prevented. Furthermore, since the semiconductor substrate is thinned by the recess 13 in the scribe line region R2, dicing can be easily performed. Accordingly, the semiconductor substrate can be prevented from being chipped. Furthermore, when the circuit element is an optical element, it is necessary to increase the formation area of the circuit element in order to ensure the characteristics of the optical element. In this case, the formation region of the through electrode 20 comes closer to the scribe line L side (outside).
- the insulating film, the through hole, and the like are more easily affected by dicing.
- the circuit element is an optical element, it is possible to reliably prevent the insulating film from peeling while securing a sufficient formation area.
- disconnects the semiconductor wafer 2 along the scribe line L and separates into pieces is demonstrated.
- the dicing process of the semiconductor wafer 1 is performed by attaching the dicing tape 15 to the front surface of the first side of the semiconductor wafer (opposite the dicing surface) and fixing the entire semiconductor wafer 1 to a frame (not shown).
- the dicing tape 15 for example, a UV tape whose viscosity is changed by irradiating ultraviolet rays can be used.
- the semiconductor wafer 1 is cut along the scribe line L using the dicing blade B.
- the dicing tape 15 loses its adhesive force by irradiating ultraviolet rays or the like, and then removes the semiconductor device from the dicing tape 15.
- the second scribe line region R ⁇ b> 2 has a width that is slightly larger than the width of the dicing blade B. That is, the protective layer 9 and the insulating film 5 are separated from the end face of the dicing blade B by a predetermined dimension.
- the width of the scribe line region R2 is preferably about 140 ⁇ m with respect to the width of the dicing blade B of 70 ⁇ m.
- the width of the first scribe line region R1 is preferably 100 ⁇ m.
- a semiconductor device 50 as shown in FIG. 4 can be manufactured.
- the end portions of the insulating films formed on both surfaces of the semiconductor substrate constituting the semiconductor device are separated from the end portion 50a of the semiconductor device by a predetermined distance.
- the distance D1 between the end portion of the insulating film 5 formed on the first surface side 2a of the semiconductor substrate 2 and the end surface 50a of the semiconductor device 50 is 15 ⁇ m.
- the distance D2 between the end of the insulating film 5 formed on the second surface side 2b of the semiconductor substrate 2 and the end surface 50a of the semiconductor device 50 is 35 ⁇ m.
- FIGS. 5A, 5B, and 5C are partial cross-sectional views of the semiconductor wafer 1 according to the first embodiment of the present invention, in particular, an enlarged view of a portion where the second scribe line region R2 is provided.
- a protective layer 9a having a thickness T1 is formed.
- the thickness T1 of the protective layer 9a is appropriately determined according to the finally desired thickness of the protective layer 9.
- the protective layer 9a having such a shape can be manufactured by a photolithography technique using a photosensitive resin.
- the protective layer 9a having such a shape can also be manufactured by pattern-etching a non-photosensitive resin.
- etching is performed on the second surface (dicing surface) of the semiconductor wafer 1.
- This etching is performed by introducing a CF etching gas as a reaction gas and generating plasma.
- a CF etching gas as a reaction gas and generating plasma.
- scum generated during the formation of the protective layer 9a is removed, and the protective layer 9a, the insulating film 5, and the semiconductor substrate 2 are etched to a predetermined thickness by etching.
- 5B shows the surface of the protective layer 9a before etching.
- the protective layer 9a formed by the process shown in FIG. 5A is etched, and at the same time, the insulating film 5 and the semiconductor substrate 2 are etched.
- a scribe line region R2 is formed.
- the protective layer 9 and the insulating film 5 are not formed along the scribe line region L, and a recess 13 in which a step portion is provided with respect to the semiconductor substrate 2 is formed.
- the semiconductor wafer 1 according to the first embodiment of the present invention is characterized in that the second scribe line region R2 having the above-described configuration is provided.
- the semiconductor wafer 1 according to the first embodiment of the present invention since the recess 13 is provided in the second scribe line region R2, the thickness of the semiconductor substrate 2 in the second scribe line region R2 is reduced. Further, chipping defects of the semiconductor substrate 2 in the dicing process can be reduced.
- the semiconductor substrate and the support substrate are formed of different materials to form a composite substrate.
- the composite substrate in order to dice a composite substrate formed of different materials, it has been necessary to select a rotation speed of a dicing blade, a raw material, or the like according to the material, so that it is very difficult to perform dicing in one step.
- the composite substrate by forming the recess 13, the composite substrate can be diced in one step, and can be diced more easily and in a short time.
- FIG. 6 is a partial sectional view showing a semiconductor wafer according to the second embodiment of the present invention, and corresponds to FIG. 2 of the first embodiment.
- the second embodiment differs from the first embodiment in the widths of the first scribe line region and the second scribe line region.
- the semiconductor wafer 1b according to the second embodiment can be manufactured by substantially the same manufacturing method as the semiconductor wafer 1 according to the first embodiment.
- the semiconductor wafer 1b according to the second embodiment performs cutting along the scribe line region R2b provided on the second surface side 2b.
- the positioning of the dicing blade is facilitated, and a problem that the dicing blade comes off the scribe line region R1b on the first surface side 2a and contacts the insulating film 5 during dicing can be avoided.
- the width R1 of the first scribe line region and the width R2 of the second scribe line region satisfy the relationship R1> R2. As shown in FIG.
- the first surface 2a when dicing with the dicing blade B, the first surface 2a is not visible.
- the width R2 of the second scribe line region is smaller than the width R1 of the first scribe line region, dicing on the first surface can be ensured in the first scribe line region. Therefore, in addition to the effect in the first embodiment, the dicing range on the first surface is shifted, and the influence on the insulating film on the first surface can be reliably prevented.
- the present invention can be widely applied to semiconductor devices including an insulating film on a substrate and a through electrode separated by a dicing process.
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Abstract
Description
本発明は、絶縁膜で被覆された半導体基板を用いた半導体ウエハ及び半導体装置並びに半導体装置の製造方法に関する。特に、ダイシング工程における絶縁膜の剥がれを防ぐ半導体ウエハ及び半導体装置並びに半導体装置の製造方法に関する。
本願は、2009年12月28日に、日本に出願された特願2009-296880号に基づき優先権を主張し、その内容をここに援用する。
The present invention relates to a semiconductor wafer, a semiconductor device, and a semiconductor device manufacturing method using a semiconductor substrate covered with an insulating film. In particular, the present invention relates to a semiconductor wafer, a semiconductor device, and a method for manufacturing the semiconductor device that prevent peeling of an insulating film in a dicing process.
This application claims priority based on Japanese Patent Application No. 2009-296880 filed in Japan on December 28, 2009, the contents of which are incorporated herein by reference.
従来、例えば、シリコンチップを樹脂により封止した、いわゆるデュアル・インライン・パッケージ(Dual Inline Package、DIP)やクァド・フラット・パッケージ(Quad Flat Package、QFP)のような半導体パッケージでは、樹脂パッケージの側面部又は周辺部に金属リードを配置した周辺端子配置型が主流であった。 Conventionally, for example, in a semiconductor package such as a so-called dual inline package (DIP) or quad flat package (QFP) in which a silicon chip is sealed with a resin, the side surface of the resin package is used. Peripheral terminal arrangement type in which metal leads are arranged in the part or the peripheral part has been the mainstream.
これに対し、近年広く普及している半導体パッケージ構造として、たとえばボールグリットアレイ(Ball Grid Array、BGA)タイプがある。このBGAタイプは、パッケージの平坦な表面に半田バンプと呼ばれる電極を二次元的に配置した構造を有しているため、DIPやQFPと比較して高密度な実装が可能となる。このため、BGAタイプはコンピュータのCPUやメモリなどのパッケージとして使われている。BGAタイプの半導体パッケージは、そのパッケージサイズがチップサイズよりも大きい。しかしながら、BGAタイプのパッケージのうち、ほとんどチップサイズに近い大きさにまで小型化したパッケージは、チップスケールパッケージ(Chip Scale Package、CSP)と呼ばれ、電子機器の小型軽量化に大きく貢献している。 On the other hand, as a semiconductor package structure widely spread in recent years, for example, there is a ball grid array (BGA) type. Since this BGA type has a structure in which electrodes called solder bumps are two-dimensionally arranged on the flat surface of the package, it can be mounted at a higher density than DIP or QFP. For this reason, the BGA type is used as a package for a CPU and a memory of a computer. The package size of the BGA type semiconductor package is larger than the chip size. However, among BGA type packages, a package that is downsized to almost the size of the chip is called a chip scale package (CSP), and greatly contributes to the reduction in size and weight of electronic devices. .
BGAタイプの半導体パッケージは、回路を形成したウエハ基板を切断し、その半導体チップをインターポーザと呼ばれる基板に搭載してパッケージを完成させるもので、パターニングされたインターポーザが必要である上に、個々に半導体チップを個別にインターポーザに実装する工程が必要である。このため、専用の材料や製造装置を用いなければならず、コストが高くなるという欠点があった。 A BGA type semiconductor package cuts a wafer substrate on which a circuit is formed and mounts the semiconductor chip on a substrate called an interposer to complete the package. In addition to the need for a patterned interposer, individual semiconductors A process of individually mounting the chip on the interposer is necessary. For this reason, a dedicated material or manufacturing apparatus has to be used, and there is a drawback that the cost is increased.
これに対し、CSP、特に「ウエハレベルCSP」と呼ばれる製法においては、このウエハ基板上に、絶縁樹脂層、再配線層、封止樹脂層、はんだバンプ等を形成し、最終工程において半導体ウエハを所定のチップ寸法に切断することでパッケージ構造を具備した半導体装置を得ることができる(例えば、特許文献1参照)。したがって、パッケージ構造をウエハ状の半導体基板上に一括形成するため、従来のようにインターポーザを必要とせず、またウエハ状態で加工するので専用の装置を必要としない。このため製造効率が高く、コスト面の不利は低減している。 On the other hand, in the manufacturing method called CSP, especially “wafer level CSP”, an insulating resin layer, a rewiring layer, a sealing resin layer, a solder bump, etc. are formed on this wafer substrate, and a semiconductor wafer is formed in the final process. A semiconductor device having a package structure can be obtained by cutting to a predetermined chip size (see, for example, Patent Document 1). Therefore, since the package structure is collectively formed on the wafer-like semiconductor substrate, an interposer is not required as in the prior art, and since processing is performed in the wafer state, a dedicated apparatus is not required. For this reason, the manufacturing efficiency is high and the cost disadvantage is reduced.
ウエハレベルCSPによる半導体ウエハより得られる半導体装置は、ウエハ全面にパッケージ加工を施した後にダイシングして個片化することにより得られる。従って、個片化したチップそのものの大きさが、パッケージの施された半導体装置となり、実装基板に対して最小投影面積を有する半導体装置を得ることが可能となる。また、配線距離が従来のパッケージよりも短く、配線の寄生容量も小さい。 A semiconductor device obtained from a semiconductor wafer by wafer level CSP is obtained by performing package processing on the entire surface of the wafer and then dicing into individual pieces. Therefore, the size of the singulated chip itself becomes a packaged semiconductor device, and a semiconductor device having a minimum projected area with respect to the mounting substrate can be obtained. Further, the wiring distance is shorter than that of the conventional package, and the parasitic capacitance of the wiring is also small.
上記ウエハレベルCSPを採用した半導体装置の製造工程のうち、半導体ウエハを個片化するダイシング工程では、ダイシングブレードを用いて、スクライブライン領域を切削する。ダイシング時には、回路素子内部に機械的欠陥が生じるのを防ぐために、ダイシングブレードの回転速度や、ダイシング速度(ウエハとダイシングブレードの相対速度)等を調整するなどの制御が行われる。 Among the semiconductor device manufacturing processes employing the wafer level CSP, in a dicing process for separating a semiconductor wafer, a scribe line region is cut using a dicing blade. At the time of dicing, in order to prevent mechanical defects from occurring inside the circuit element, control is performed such as adjusting the rotational speed of the dicing blade, the dicing speed (relative speed between the wafer and the dicing blade), and the like.
また、半導体装置のさらなる小型化を実現する技術として、貫通電極(Through-Silicon Via、TSV)を用いたウエハレベルCSPが提案されている。貫通電極は従来のワイヤーボンディングに代わるものであり、半導体装置の内部に垂直に形成した貫通孔を、導電性を有する金属で充填することによって、電極として利用するものである。貫通電極の技術は、ワイヤーボンディングによって接続する従来の手法と比較して、配線距離を大幅に短縮できるため、半導体装置の高速化、省電力化、小型化に寄与する。
これら優れた特徴は、現在急速に進んでいる実装の高密度化や、情報処理速度の高速化が実現できるという点において非常に優位である。
In addition, as a technique for realizing further miniaturization of a semiconductor device, a wafer level CSP using a through-electrode (Through-Silicon Via, TSV) has been proposed. The through electrode is an alternative to conventional wire bonding, and is used as an electrode by filling a through hole formed perpendicularly to the inside of a semiconductor device with a conductive metal. The through electrode technology can greatly reduce the wiring distance as compared with the conventional method of connecting by wire bonding, and thus contributes to higher speed, power saving, and downsizing of the semiconductor device.
These excellent features are extremely advantageous in that high-density mounting and high-speed information processing can be realized, which are currently progressing rapidly.
従来の貫通電極を用いた半導体ウエハとしては、例えば特許文献2に記載されたものがある。図7Aは、従来の半導体ウエハ100の断面を示す図である。
従来の半導体ウエハ100は、Si(シリコン)からなるウエハ状の半導体基板102の第一面102aに回路素子103が設けられているとともに、半導体基板102の第二面102bから第一面102aに貫通する貫通孔107が設けられている。貫通孔107の内面及び半導体基板102の少なくとも第二面側102bには、絶縁膜105が形成されている。絶縁膜105上には配線106が形成されている。この絶縁膜105と、配線106と、貫通孔107とにより貫通電極120を構成している。
As a semiconductor wafer using a conventional through electrode, for example, there is one described in
In the
符号104は、前記貫通電極120と電気的に接続される電極パッドであり、パッシベーション層108によって被覆されている。符号109は、半導体基板102の第二面側102bにおいて、回路素子領域を被覆する保護層である。以上の半導体素子が、接着層111によってガラスからなる支持基板110に接合されている。
符号115は、ダイシング工程において、半導体装置100を保持するためのダイシングテープである。
半導体基板102の第一面側102aには、第一スクライブライン領域R10が設けられており、第二面側102bには、ダイシング工程において、保護層109を巻き込むのを防ぐため、第二スクライブライン領域R11が設けられている。第二スクライブライン領域R11においては、前記保護層109がスクライブラインLに沿って除去されているとともに、予めスクライブラインLに沿った溝130が形成されており、これにより、ダイシングを容易にし、ダイシング工程における回路素子103の破損を防ぐ構成となっている。
A first scribe line region R10 is provided on the
図7Bは、上記構成の半導体ウエハ100のダイシング工程の際、ダイシングブレードBが挿入された状態を示す断面図である。
図7Bに示すように、従来の半導体ウエハ100に対してダイシングを行う場合、第二スクライブライン領域R11に絶縁膜105が存在しているため、ダイシングブレードBが絶縁膜105に接触した際、絶縁膜105の剥がれ(符号C1で示す)が生じる不具合があった。
図8は、従来の半導体ウエハ100をダイシングブレードBによってダイシングした後の、ダイシングライン付近の上面図である。絶縁膜105の剥がれは、ダイシングラインLから、貫通電極120や回路素子が形成されている方向へ生じる。図7B及び図8に示したように、ダイシングラインL付近の上面で、絶縁膜105が剥がれている。さらに、貫通孔107の内面における絶縁膜105が剥がれることもある。さらに、絶縁膜105の剥がれが回路素子の領域に達することで、半導体装置100に不良が発生する原因となる。ひいては、絶縁膜105の剥がれに伴って、ダイシングブレードBの付近で、半導体基板102に欠けが生じる場合もある。
FIG. 7B is a cross-sectional view showing a state in which the dicing blade B is inserted during the dicing process of the
As shown in FIG. 7B, when dicing is performed on the
FIG. 8 is a top view of the vicinity of a dicing line after the
この発明は、このような事情を考慮してなされたもので、ダイシング工程における半導体ウエハを構成する絶縁膜の剥がれを防ぐことを可能にする半導体ウエハ及び半導体装置並びに半導体装置の製造方法の提供を目的とする。 The present invention has been made in view of such circumstances, and provides a semiconductor wafer, a semiconductor device, and a method for manufacturing the semiconductor device that can prevent the insulating film constituting the semiconductor wafer from peeling off in the dicing process. Objective.
上記の課題を解決するために、本発明は以下の構成を採用する。
(1)本発明の一態様に係る半導体ウエハは、複数の回路素子及び前記複数の回路素子間に設けられた第一スクライブライン領域が形成された第一面と、前記第一面とは反対側の第二面とを有する半導体基板と、前記半導体基板の前記第二面側に形成された絶縁膜と、前記絶縁膜上に形成された配線とを備えた半導体ウエハであって、前記半導体基板の前記第二面側には、前記第一スクライブライン領域に沿って前記絶縁膜が形成されていない領域である第二スクライブライン領域が設けられている。
(2)前記半導体ウエハにおいて、前記第二スクライブライン領域に沿って、前記半導体基板の前記第二面に凹部が形成されてもよい。
(3)前記半導体基板に前記第二面から前記第一面まで貫通する貫通孔が形成され;前記貫通孔の内面に前記絶縁膜が形成されてもよい。
(4)前記回路素子は光学素子であって、前記回路素子が形成された前記第一面に透明基板が接着されてもよい。
In order to solve the above problems, the present invention adopts the following configuration.
(1) In the semiconductor wafer according to one aspect of the present invention, a first surface on which a plurality of circuit elements and a first scribe line region provided between the plurality of circuit elements are formed is opposite to the first surface. A semiconductor wafer comprising: a semiconductor substrate having a second surface on the side; an insulating film formed on the second surface side of the semiconductor substrate; and a wiring formed on the insulating film, A second scribe line region that is a region where the insulating film is not formed is provided along the first scribe line region on the second surface side of the substrate.
(2) In the semiconductor wafer, a recess may be formed on the second surface of the semiconductor substrate along the second scribe line region.
(3) A through hole penetrating from the second surface to the first surface may be formed in the semiconductor substrate; and the insulating film may be formed on an inner surface of the through hole.
(4) The circuit element may be an optical element, and a transparent substrate may be bonded to the first surface on which the circuit element is formed.
(5)本発明の一態様に係る半導体装置は、半導体ウエハをスクライブラインに沿って切削して形成された半導体装置であって、回路素子が形成された第一面と、前記第一面とは反対側の第二面とを有する半導体基板と、前記半導体基板の前記第二面側に形成された絶縁膜と、前記絶縁膜上に形成された配線とを備え、前記絶縁膜は、前記スクライブラインに沿う切削によって形成された切削面より内側に位置している。 (5) A semiconductor device according to an aspect of the present invention is a semiconductor device formed by cutting a semiconductor wafer along a scribe line, the first surface on which circuit elements are formed, and the first surface, Comprises a semiconductor substrate having a second surface on the opposite side, an insulating film formed on the second surface side of the semiconductor substrate, and a wiring formed on the insulating film, the insulating film comprising: It is located inside the cutting surface formed by cutting along the scribe line.
(6)本発明の一態様に係る半導体装置の製造方法は、第一面側に複数の回路素子が形成され、前記複数の回路素子間に第一スクライブライン領域が設けられた半導体基板を準備する半導体基板準備工程と、前記貫通孔の内面及び前記半導体基板の前記第二面側に絶縁膜を形成する絶縁膜形成工程と、前記絶縁膜上に配線を形成する配線形成工程と、前記半導体基板の前記第二面側に、前記回路素子が形成された領域を個々に被覆する保護層を形成し、前記保護層間に第二スクライブライン領域を設ける保護層形成工程と、前記保護層を形成した後に、前記第二スクライブライン領域に露呈した前記絶縁膜を除去する絶縁膜除去工程と、前記半導体ウエハをスクライブラインに沿って前記第二面側から切削するダイシング工程と、を備える。
(7)前記半導体装置の製造方法において、前記絶縁膜除去工程を行うとともに、前記第二スクライブライン領域に沿って前記半導体基板の前記第二面に凹部を形成してもよい。
(8)前記半導体装置の製造方法において、前記半導体基板の前記第二面から前記半導体基板の前記第一面まで貫通する貫通孔を形成する貫通孔形成工程をさらに備え;前記絶縁膜形成工程において、前記貫通孔の内面及び前記半導体基板の前記第二面側に前記絶縁膜を形成してもよい。
(9)前記半導体装置の製造方法において、前記半導体基板の前記第一面側に、支持基板を粘着する工程をさらに備え;前記ダイシング工程において、前記半導体基板と前記支持基板とをワンステップでダイシングしてもよい。
(6) A method for manufacturing a semiconductor device according to one embodiment of the present invention provides a semiconductor substrate in which a plurality of circuit elements are formed on a first surface side and a first scribe line region is provided between the plurality of circuit elements. A semiconductor substrate preparing step, an insulating film forming step of forming an insulating film on an inner surface of the through hole and the second surface side of the semiconductor substrate, a wiring forming step of forming a wiring on the insulating film, and the semiconductor Forming a protective layer for individually covering the area where the circuit elements are formed on the second surface side of the substrate, and forming a second scribe line area between the protective layers; and forming the protective layer Then, an insulating film removing step for removing the insulating film exposed to the second scribe line region, and a dicing step for cutting the semiconductor wafer from the second surface side along the scribe line are provided.
(7) In the manufacturing method of the semiconductor device, the insulating film removing step may be performed, and a recess may be formed on the second surface of the semiconductor substrate along the second scribe line region.
(8) The method for manufacturing a semiconductor device may further include a through hole forming step of forming a through hole penetrating from the second surface of the semiconductor substrate to the first surface of the semiconductor substrate; The insulating film may be formed on the inner surface of the through hole and on the second surface side of the semiconductor substrate.
(9) The method for manufacturing a semiconductor device further includes a step of adhering a support substrate to the first surface side of the semiconductor substrate; in the dicing step, the semiconductor substrate and the support substrate are diced in one step. May be.
上記本発明の態様に係る半導体ウエハによれば、半導体ウエハを構成する半導体基板の第一面側に第一スクライブライン領域を設け、半導体基板の第二面側に形成された絶縁膜に、第一スクライブライン領域に沿って絶縁膜が離間した領域である第二スクライブライン領域を設けた。従って、ダイシング工程における絶縁膜の剥がれを防ぐことができるという効果が得られる。 According to the semiconductor wafer according to the aspect of the present invention, the first scribe line region is provided on the first surface side of the semiconductor substrate constituting the semiconductor wafer, and the insulating film formed on the second surface side of the semiconductor substrate has the first A second scribe line region, which is a region where the insulating film is separated, is provided along one scribe line region. Therefore, an effect that the peeling of the insulating film in the dicing process can be prevented can be obtained.
上記本発明の態様に係る半導体装置によれば、半導体基板の第一面側及び第二面側それぞれの絶縁膜端部が、半導体装置の端部より離間した構成となっているため、絶縁膜がダイシングによって半導体基板の端部に生じた応力の影響を受けず、よって、絶縁膜が剥れる不良を低減できる。また、半導体装置の端部に外部応力が生じた際も、絶縁膜にその影響が及ぶことを防ぐことができる。 According to the semiconductor device according to the aspect of the present invention, the insulating film ends on the first surface side and the second surface side of the semiconductor substrate are separated from the end portions of the semiconductor device. However, it is not affected by the stress generated at the end portion of the semiconductor substrate by dicing, so that the defect that the insulating film peels can be reduced. In addition, even when an external stress is generated in the end portion of the semiconductor device, it can be prevented that the insulating film is affected.
上記本発明の態様に係る半導体装置の製造方法は、半導体基板の第二面側に回路素子が形成された領域を個々に被覆する保護層を形成し、保護層間に第二スクライブライン領域を設ける保護層形成工程と、保護層を形成した後に、第二スクライブライン領域に露呈した絶縁膜を除去する絶縁膜除去工程とを備えている。従って、ダイシング工程における絶縁膜の剥がれを防ぐことができるという効果が得られる。 In the method of manufacturing a semiconductor device according to the aspect of the present invention, a protective layer that individually covers a region where a circuit element is formed is formed on the second surface side of the semiconductor substrate, and a second scribe line region is provided between the protective layers. A protective layer forming step; and an insulating film removing step of removing the insulating film exposed to the second scribe line region after forming the protective layer. Therefore, an effect that the peeling of the insulating film in the dicing process can be prevented can be obtained.
<第一実施形態>
以下、図面を参照して、本発明の実施形態を詳細に説明する。
図1は、本発明の第一実施形態に係る半導体ウエハを示す平面図であり、半導体装置に個片化される前の半導体ウエハ1を示すものである。図2Aは、図1のA-A線に沿う断面図であり、スクライブラインL周辺を示すものである。
図1に示すように、本発明の第一実施形態に係る半導体ウエハ1は、所定のスクライブラインLに沿って切断されることで、複数の半導体装置へと個片化される。半導体ウエハ1上のスクライブラインLによって画定された領域に、回路素子3が形成されている。また、回路素子3の領域に貫通電極20が形成されている。
<First embodiment>
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a plan view showing a semiconductor wafer according to a first embodiment of the present invention, and shows a
As shown in FIG. 1, the
図2Aにおいて、符号1は半導体ウエハ、符号2は半導体基板、符号3は回路素子、符号4は電極パッド、符号5は絶縁膜、符号6は配線、符号7は貫通孔、符号8はパッシベーション層、符号9は保護層、符号10は支持基板、符号11は接着層を示している。貫通電極20は、絶縁膜5と、配線6と、貫通孔7とから構成されている。
2A,
この半導体ウエハ1では、図2Aに示すように、貫通電極20等が設けられている半導体基板2が、接着層11によって支持基板10に接合されている。
半導体基板2の第一面側2aには、電極パッド4が設けられている。半導体基板2の電極パッド4が設けられた部分には、半導体基板2の第二面2bから第一面2aにわたって貫通孔7が形成されている。また、電極パッド4が設けられている面は、パッシベーション層8によって保護されている。
In this
An
また、半導体基板2の両面(第1面及び第二面)および貫通孔7の内面には絶縁膜5が設けられている。絶縁膜5は、例えばSiO2、SiN、又は樹脂膜である。さらに、絶縁膜5の上であって、貫通孔7内面及び半導体基板2の第二面側2bには、配線6が形成されている。この配線6は、電極パッド4と電気的に接続されている。
そして、半導体ウエハ2の第二面2bは、保護層9で被覆されている。なお、保護層9は必ずしも必要ではなく、貫通電極20や配線6を露出する形態としてもよい。
An insulating
The
半導体基板2は、例えば、シリコンやGaAs等の半導体基板である。
支持基板10は、半導体基板2と異なる材料から形成された基板であって、その熱膨張率が半導体基板2に近い材料が望ましい。
接着層11を構成する接着剤としては、電気絶縁性を有する材料からなるものが用いられる。接着層11をなす接着剤としては、例えばポリイミド樹脂、エポキシ樹脂、ベンゾシクロブタン(BCB)樹脂、シリコーン樹脂、アクリル樹脂などが望ましい。
この半導体基板2は、透明な基板であってもよく、不透明な基板であってもよい。なお、この接着層11は、透明な樹脂層であってもよく、不透明な樹脂層であってもよい。これら半導体基板2及び接着層11は、半導体基板2に設けられた回路素子3の性質に応じて、適宜選択することができる。
The
The
As the adhesive constituting the
The
回路素子3は、例えばメモリ、IC、撮像素子、MEMS素子などの半導体機能素子などである。前記配線6は、Cu、Al、Ni、Ag、Pb、Sn、Au、Co、Cr、Ti、TiW等の導体(各種の金属や合金等)から形成された配線層である。配線層としての回路素子3の形成方法は、特に限定されるものではなく、例えばスパッタリング法、蒸着法、めっき法等、あるいはこれらの2つ以上の方法の組み合わせが挙げられる。また、配線層としての回路素子3は、単層の導体層でも、多層の導体層を積層したものでもよい。また、配線層のパターニングには、フォトリソグラフィ技術が好適に用いられる。
回路素子3は、例えば、発光タイプまたは受光タイプの光学素子であってもよい。例えば、回路素子3は、支持基板10からの光を受光して、この光信号を電気信号に変更する素子であってもよい。さらに、回路素子3は、自ら発光する発光体であってもよい。
回路素子3が光学素子である場合、前記支持基板10として、透明なガラス基板又は透明な樹脂基板を選択することができる。さらに、接着層11も透明であることが好ましい。
なお、回路素子3が光学素子である場合、接着層11は、その光学的特性が前記支持基板10と近い樹脂を選択することがよい。その一例として、例えば接着層11は、その屈折率が支持基板10の屈折率と近い樹脂で形成されることが挙げられる。具体的に、例えば支持基板10がガラス(屈折率:約1.5)である場合には、ガラスの屈折率に近い接着層11としてシリコーン樹脂(屈折率:約1.4~1.5)を選択することができる。その他、アクリル樹脂(屈折率:約1.5)やエポキシ樹脂(約1.5~1.6)を選択することができる。本実施形態において、透明な接着層11を採用しているが、本実施形態はこれのみに限定されない。例えば、接着層11として、不透明な樹脂を選択することができる。この場合、図2Bに示すように、回路素子3の形成領域に対応する部分において、接着層11が形成されていない。従って、接着層11が形成されていない領域を介して、光が自由に入射又は出射することができる。
本実施形態において、回路素子3が形成されている第一面2aには支持基板10が設けられている。従って、回路素子3が光学素子である場合、この支持基板10の保護によって、光学素子が埃などの影響を受けることを防ぐことができる。
The
The
When the
When the
In the present embodiment, a
符号Lは、半導体ウエハ1をダイシング加工する際の参照されるスクライブラインである。
半導体基板2の第一面側2aには、第一スクライブライン領域R1が設けられている。スクライブライン領域とは、この領域をダイシングブレードで切削することによって、個々の半導体装置に分離するためのものである。図2Aおいて符号R1は、第一スクライブライン領域の幅を示すものである。半導体基板2の第一面側2aにおいて、絶縁膜5は、スクライブラインLに沿って第一スクライブライン領域R1の幅だけ離間した領域を有している。つまり、第一面側2aにおいて、第一スクライブライン領域R1には絶縁膜5が設けられていない。また、第一スクライブライン領域R1の中心線は、スクライブラインLと一致している。
Reference symbol L is a scribe line referred to when the
A first scribe line region R <b> 1 is provided on the
半導体基板2の第二面側2bには、第一スクライブライン領域R1と比較して、やや大なる幅を有する第二スクライブライン領域R2が設けられている。第二スクライブライン領域R2においては、スクライブラインLに沿って保護層9は形成されていない。すなわち、本実施形態において、第一スクライブライン領域の幅R1と、第二スクライブライン領域の幅R2とは、R1<R2との関係を満たす。
通常、絶縁膜の剥がれは、半導体基板の両面(第一面及び第二面)で生じる。その中、半導体基板の第一面は接着層に覆われ、半導体基板の第二面は外部に露出されているので、前記第一面に比べて、第二面において絶縁膜の剥がれが生じ易い。本実施形態において、第二スクライブライン領域R2の幅を相対的に広く(R1<R2)することで、第二面における絶縁膜の剥がれを確実に確保することができる。
本発明の第一実施形態に係る半導体ウエハ1は、半導体基板2の第二面側2bに形成されている絶縁膜5も、スクライブラインLに沿って離間した領域を備えている。離間幅は第二スクライブライン領域R2と同一である。つまり、第二面側2bにおいて、第二スクライブライン領域R2には絶縁膜5が設けられていない。
また、第二スクライブライン領域R2の中心線は、スクライブライン領域Lと一致している。すなわち、第一スクライブライン領域R1の中心線と、第二スクライブライン領域R2の中心線は、一致している。
On the
Usually, the peeling of the insulating film occurs on both surfaces (first surface and second surface) of the semiconductor substrate. Among them, since the first surface of the semiconductor substrate is covered with an adhesive layer and the second surface of the semiconductor substrate is exposed to the outside, the insulating film is more easily peeled off on the second surface than the first surface. . In this embodiment, the width of the second scribe line region R2 is relatively wide (R1 <R2), so that the peeling of the insulating film on the second surface can be reliably ensured.
In the
Further, the center line of the second scribe line region R2 coincides with the scribe line region L. That is, the center line of the first scribe line region R1 and the center line of the second scribe line region R2 are coincident.
さらに、第二スクライブライン領域R2においては、半導体基板2に凹部13が設けられている。凹部13は、半導体基板2の第二面2bに対して、所定深さに亘って半導体基板2の表面が削られた部位である。つまり、第二スクライブライン領域R2において、半導体基板2には第二面2bに対して段差が設けられており、半導体基板2は他の領域と比較して、基板厚さが薄くなっている。
段差の高さが大きくなるほど、切削する領域における半導体基板厚さが薄くなるので、容易にダイシングすることができる。ひいては、ダイシング時におけるチッピング不良を低減することができる。
半導体基板に貫通孔を形成する際に、通常半導体基板を削ってその厚みを薄くした上で、貫通孔を形成する。その際に、半導体基板の第一面には様々な回路素子が形成されているので、第二面を削る。しかしながら、第二面の表面には、結晶の格子に欠陥があるか又は細かいクラックがある。従って、従来において、ダイシングブレードBにより、半導体基板の第二面と共に絶縁膜をダイシングする際に、この第二面に形成された絶縁膜が剥がれ易いという問題があった。
しかしながら、本実施形態では、第二スクライブライン領域R2に絶縁膜が形成されていないため、ダイシングをより簡単に行うことができる。さらに、絶縁膜の剥がれを確実に防ぐことができる。
なお、貫通電極は、通常回路素子の隅部に形成されている。すなわち、貫通電極の貫通孔は、スクライブラインLの近い領域に形成されている。従って、従来の半導体ウエハ100において、貫通孔は、スクライブラインLに沿うダイシングの影響を受け易い。従って、スクライブラインLに沿ってダイシングする際に、半導体基板102の第二面102aに形成された絶縁膜105が剥がれ易くなる。絶縁膜105の剥がれに伴って、貫通孔の内部に形成された絶縁膜が剥がれる可能性がある。さらに、第二面の結晶の格子に欠陥があるか又は細かいクラックがあるので、剥がれた絶縁膜105の部分における半導体基板が欠ける場合もある。
しかしながら、本実施形態に係る半導体基板2の第二面側2bにおいて、第二スクライブライン領域R2には絶縁膜5が設けられていない。従って、第二面側2bにおける絶縁膜5の剥がれを確実に防ぐことができる。ひいては、貫通孔の内部における絶縁膜5の剥がれを確実に防ぐことができる。さらに、スクライブライン領域R2は、凹部13により半導体基板が薄肉化されているので、容易にダイシングを行うことができる。したがって、半導体基板が欠けることを防ぐことができる。
さらに、回路素子が光学素子である場合、光学素子の特性を確保するために、回路素子の形成面積をより大きくする必要がある。この場合、貫通電極20の形成領域がスクライブラインL側(外側)により近付くことになる。従って、従来の半導体ウエハ100においては、絶縁膜及び貫通孔などが、ダイシングによる影響をより一層受け易くなる。一方、本実施形態によれば、回路素子が光学素子であっても、十分な形成面積を確保しながら、絶縁膜の剥がれを確実に防ぐことができる。
Furthermore, a
Since the thickness of the semiconductor substrate in the region to be cut becomes thinner as the height of the step becomes larger, dicing can be easily performed. As a result, chipping defects during dicing can be reduced.
When forming a through hole in a semiconductor substrate, the semiconductor substrate is usually shaved to reduce its thickness, and then the through hole is formed. At this time, since various circuit elements are formed on the first surface of the semiconductor substrate, the second surface is shaved. However, the surface of the second surface has defects in the crystal lattice or fine cracks. Therefore, conventionally, when the insulating film is diced together with the second surface of the semiconductor substrate by the dicing blade B, there is a problem that the insulating film formed on the second surface is easily peeled off.
However, in this embodiment, since the insulating film is not formed in the second scribe line region R2, dicing can be performed more easily. Furthermore, it is possible to reliably prevent the insulating film from peeling off.
The through electrode is usually formed at a corner of the circuit element. That is, the through hole of the through electrode is formed in a region near the scribe line L. Therefore, in the
However, the insulating
Furthermore, when the circuit element is an optical element, it is necessary to increase the formation area of the circuit element in order to ensure the characteristics of the optical element. In this case, the formation region of the through
次に、図3A及び図3Bを参照して、半導体ウエハ2をスクライブラインLに沿って切断し個片化するダイシング工程について説明する。
半導体ウエハ1のダイシング工程においては、半導体ウエハの第一面側(ダイシング面の反対側)の前面にダイシングテープ15に貼り付け、半導体ウエハ1全体をフレーム(図示せず)に固定して行う。ダイシングテープ15としては、例えば、紫外線を照射することによって粘性が変化するUVテープを使用することができる。
Next, with reference to FIG. 3A and FIG. 3B, the dicing process which cut | disconnects the
The dicing process of the
次に、ダイシングブレードBを用いて、スクライブラインLに沿って半導体ウエハ1を切削する。
半導体ウエハ1を切断することによって、半導体ウエハ1は個々の半導体装置に分離される。ダイシングテープ15は、紫外線を照射するなどして、その粘着力を失わせた上で、半導体装置をダイシングテープ15から取り外す。
図3Bに示したように、第二スクライブライン領域R2は、ダイシングブレードBの幅に対して、やや大なる幅を有している。つまり、ダイシングブレードBの端面に対して、保護層9及び絶縁膜5は、所定寸法離間している。具体的には、ダイシングブレードBの幅70μmに対して、スクライブライン領域R2の幅を140μm程度とすることが好ましい。
また、第一スクライブライン領域R1に関しては、その幅を100μmとすることが好ましい。
Next, the
By cutting the
As shown in FIG. 3B, the second scribe line region R <b> 2 has a width that is slightly larger than the width of the dicing blade B. That is, the
The width of the first scribe line region R1 is preferably 100 μm.
以上の工程を経て、図4に示すような、半導体装置50を製作することができる。図4に示したように、半導体装置を構成する半導体基板の両面に形成されている絶縁膜の端部は、半導体装置の端部50aに対して、所定距離を隔てて離間している。
具体的には、半導体基板2の第一面側2aに形成されている絶縁膜5の端部と半導体装置50の端面50aとの距離D1は15μmである。また、半導体基板2の第二面側2bに形成されている絶縁膜5の端部と半導体装置50の端面50aとの距離D2は35μmである。
Through the above steps, a
Specifically, the distance D1 between the end portion of the insulating
次に、図5A、図5B、及び図5Cを参照して、本発明の第一実施形態に係る第二スクライブライン領域R2の形成方法について説明する。図5A~図5Cは、本発明の第一実施形態に係る半導体ウエハ1の部分断面図であり、特に、第二スクライブライン領域R2が設けられている箇所を拡大した図である。
Next, a method for forming the second scribe line region R2 according to the first embodiment of the present invention will be described with reference to FIGS. 5A, 5B, and 5C. 5A to 5C are partial cross-sectional views of the
第二スクライブライン領域R2の形成にあたっては、まず、図5Aに示したように、厚さT1を有する保護層9aを形成する。保護層9aの厚さT1は、最終的に所望する保護層9の厚みに応じて適宜決定される。このような形状の保護層9aは、感光性樹脂を用いたフォトリソグラフィ技術で製作できる。このような形状の保護層9aは、非感光性樹脂をパターンエッチングすることでも製作できる。
In forming the second scribe line region R2, first, as shown in FIG. 5A, a
次に、図5Bに示すように、半導体ウエハ1の第二面(ダイシング面)に対してエッチングを行う。このエッチングは、反応ガスとしてCF系のエッチングガスを導入してプラズマを発生させて行う。この工程は、前記保護層9aの形成の際に発生したスカムを除去すると共に、保護層9a、絶縁膜5、及び半導体基板2をエッチングにより所定厚さに亘って削るものである。図5Bの二点差線がエッチング前の保護層9aの表面を示すものである。
このエッチングによって、図5Aに示した工程によって形成された保護層9aがエッチングされると同時に、絶縁膜5及び半導体基板2がエッチングされる。
Next, as shown in FIG. 5B, etching is performed on the second surface (dicing surface) of the
By this etching, the
最終的に、図5Cに示すように、スクライブライン領域R2が形成される。スクライブライン領域R2においては、スクライブライン領域Lに沿って保護層9及び絶縁膜5が形成されておらず、かつ、半導体基板2に対して段差部が設けられた凹部13が形成される。
Finally, as shown in FIG. 5C, a scribe line region R2 is formed. In the scribe line region R <b> 2, the
本発明の第一実施形態に係る半導体ウエハ1は、上記したような構成の第二スクライブライン領域R2を設けたことが特徴である。第二スクライブライン領域R2において、絶縁膜5を設けない構成としたことによって、ダイシング工程において、絶縁膜5が剥がれる不具合を低減することができる。
さらに、本発明の第一実施形態に係る半導体ウエハ1によれば、第二スクライブライン領域R2に凹部13を設けたことによって、第二スクライブライン領域R2における半導体基板2の厚さが薄くなるため、ダイシング工程における半導体基板2のチッピング不良を低減することができる。
通常、半導体基板と支持基板とは互いに異なる材料から形成されて、複合基板を形成する。従来、異なる材料から形成された複合基板をダイシングするために、ダイシングブレードの回転速度や、素材などを材料に応じて選択する必要があったため、ワンステップでダイシングすることは非常に難しかった。しかしながら、本実施形態において、凹部13を形成することで、ワンステップで複合基板をダイシングすることができ、より簡単且つ短時間でダイシングすることができる。
The
Furthermore, according to the
Usually, the semiconductor substrate and the support substrate are formed of different materials to form a composite substrate. Conventionally, in order to dice a composite substrate formed of different materials, it has been necessary to select a rotation speed of a dicing blade, a raw material, or the like according to the material, so that it is very difficult to perform dicing in one step. However, in the present embodiment, by forming the
<第二実施形態>
図6は、本発明の第二実施形態に係る半導体ウエハを示す部分断面図であり、第一実施形態の図2に対応する図である。
第二実施形態は、第一実施形態と比較して、第一スクライブライン領域、及び第二スクライブライン領域の幅が異なっている。
<Second embodiment>
FIG. 6 is a partial sectional view showing a semiconductor wafer according to the second embodiment of the present invention, and corresponds to FIG. 2 of the first embodiment.
The second embodiment differs from the first embodiment in the widths of the first scribe line region and the second scribe line region.
第二実施形態に係る半導体ウエハ1bは、第一実施形態に係る半導体ウエハ1と略同様の製造方法で製作することができる。
第二実施形態に係る半導体ウエハ1bは、ダイシング工程において、第二面側2bに設けられたスクライブライン領域R2bに沿って切削を行う。これにより、ダイシングブレードの位置決めが容易になり、ダイシングの際、ダイシングブレードが第一面側2aのスクライブライン領域R1bから外れて、絶縁膜5と接触する不具合を回避することができる。
本実施形態において、第一スクライブライン領域の幅R1と、第二スクライブライン領域の幅R2とは、R1>R2との関係を満たす。図6に示したように、ダイシングブレードBによるダイシングを行う際に、第一面2aは見えない。しかしながら、第二スクライブライン領域の幅R2が第一スクライブライン領域の幅R1より狭いので、第一面におけるダイシングを、第一スクライブライン領域内に確保することができる。従って、第一実施形態における効果に加えて、第一面におけるダイシング範囲がずれて、第一面における絶縁膜への影響を確実に防ぐことができる。
The
In the dicing process, the
In the present embodiment, the width R1 of the first scribe line region and the width R2 of the second scribe line region satisfy the relationship R1> R2. As shown in FIG. 6, when dicing with the dicing blade B, the
本発明は、基板上に絶縁膜を備え、ダイシング工程によって分離される貫通電極を備えた半導体装置に広く適用可能である。 The present invention can be widely applied to semiconductor devices including an insulating film on a substrate and a through electrode separated by a dicing process.
1 半導体ウエハ
2 半導体基板
3 回路素子
4 電極パッド
5 絶縁膜
6 配線
7 貫通孔
8 パッシベーション層
9 保護層
10 支持基板
11 接着層
13 凹部
15 ダイシングテープ
20 貫通電極
50 半導体装置
DESCRIPTION OF
Claims (9)
前記半導体基板の前記第二面側に形成された絶縁膜と;
前記絶縁膜上に形成された配線と;
を備えた半導体ウエハであって、
前記半導体基板の前記第二面側には、前記第一スクライブライン領域に沿って前記絶縁膜が形成されていない領域である第二スクライブライン領域が設けられていることを特徴とする半導体ウエハ。 A semiconductor substrate having a first surface on which a plurality of circuit elements and a first scribe line region provided between the plurality of circuit elements are formed; and a second surface opposite to the first surface;
An insulating film formed on the second surface side of the semiconductor substrate;
A wiring formed on the insulating film;
A semiconductor wafer comprising:
A semiconductor wafer, wherein a second scribe line region, which is a region where the insulating film is not formed, is provided along the first scribe line region on the second surface side of the semiconductor substrate.
前記貫通孔の内面に、前記絶縁膜が形成されていることを特徴とする請求項1又は2に記載の半導体ウエハ。 A through-hole penetrating from the second surface to the first surface is formed in the semiconductor substrate;
The semiconductor wafer according to claim 1, wherein the insulating film is formed on an inner surface of the through hole.
前記回路素子が形成された前記第一面に透明基板が接着されていることを特徴とする請求項1又は2に記載の半導体ウエハ。 The circuit element is an optical element,
The semiconductor wafer according to claim 1, wherein a transparent substrate is bonded to the first surface on which the circuit element is formed.
回路素子が形成された第一面と、前記第一面とは反対側の第二面とを有する半導体基板と;
前記半導体基板の前記第二面側に形成された絶縁膜と;
前記絶縁膜上に形成された配線と;を備え、
前記絶縁膜は、前記スクライブラインに沿う切削によって形成された切削面より内側に位置していることを特徴とする半導体装置。 A semiconductor device formed by cutting a semiconductor wafer along a scribe line,
A semiconductor substrate having a first surface on which circuit elements are formed and a second surface opposite to the first surface;
An insulating film formed on the second surface side of the semiconductor substrate;
Wiring formed on the insulating film; and
The semiconductor device according to claim 1, wherein the insulating film is located inside a cutting surface formed by cutting along the scribe line.
前記半導体基板の前記第二面側に絶縁膜を形成する絶縁膜形成工程と;
前記絶縁膜上に配線を形成する配線形成工程と;
前記半導体基板の前記第二面側に、前記回路素子が形成された領域を個々に被覆する保護層を形成し、前記保護層間に第二スクライブライン領域を設ける保護層形成工程と;
前記保護層を形成した後に、前記第二スクライブライン領域に露呈した前記絶縁膜を除去する絶縁膜除去工程と;
前記半導体ウエハを前記第二面側から切削するダイシング工程と;
を備える半導体装置の製造方法。 A semiconductor substrate preparation step of preparing a semiconductor substrate in which a plurality of circuit elements are formed on the first surface side and a first scribe line region is provided between the plurality of circuit elements;
An insulating film forming step of forming an insulating film on the second surface side of the semiconductor substrate;
A wiring forming step of forming a wiring on the insulating film;
Forming a protective layer individually covering the area where the circuit elements are formed on the second surface side of the semiconductor substrate, and providing a second scribe line area between the protective layers;
An insulating film removing step of removing the insulating film exposed to the second scribe line region after forming the protective layer;
A dicing step of cutting the semiconductor wafer from the second surface side;
A method for manufacturing a semiconductor device comprising:
前記絶縁膜形成工程において、前記貫通孔の内面及び前記半導体基板の前記第二面側に前記絶縁膜を形成する;ことを特徴とする請求項6又は7に記載の半導体装置の製造方法。 A through hole forming step of forming a through hole penetrating from the second surface of the semiconductor substrate to the first surface of the semiconductor substrate;
8. The method of manufacturing a semiconductor device according to claim 6, wherein in the insulating film forming step, the insulating film is formed on an inner surface of the through hole and on the second surface side of the semiconductor substrate.
前記ダイシング工程において、前記半導体基板と前記支持基板とをワンステップでダイシングする;ことを特徴とする請求項6又は7に記載の半導体装置の製造方法。 A step of adhering a support substrate to the first surface side of the semiconductor substrate;
8. The method of manufacturing a semiconductor device according to claim 6, wherein in the dicing step, the semiconductor substrate and the support substrate are diced in one step.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009-296880 | 2009-12-28 | ||
| JP2009296880A JP2013065582A (en) | 2009-12-28 | 2009-12-28 | Semiconductor wafer, semiconductor device and semiconductor device manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2011081130A1 true WO2011081130A1 (en) | 2011-07-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2010/073530 Ceased WO2011081130A1 (en) | 2009-12-28 | 2010-12-27 | Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method |
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| Country | Link |
|---|---|
| JP (1) | JP2013065582A (en) |
| TW (1) | TW201135825A (en) |
| WO (1) | WO2011081130A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013053923A (en) * | 2011-09-05 | 2013-03-21 | Lasertec Corp | Thickness measuring device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11244863B2 (en) * | 2018-05-28 | 2022-02-08 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor apparatus |
| JP2022047357A (en) * | 2020-09-11 | 2022-03-24 | キオクシア株式会社 | Semiconductor device and manufacturing method for the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006030230A (en) * | 2004-07-12 | 2006-02-02 | Sanyo Electric Co Ltd | Manufacturing method of semiconductor device |
| JP2008270520A (en) * | 2007-04-20 | 2008-11-06 | Sharp Corp | Light receiving element for blue laser and method for manufacturing the same, optical pickup device and electronic apparatus |
-
2009
- 2009-12-28 JP JP2009296880A patent/JP2013065582A/en active Pending
-
2010
- 2010-12-27 WO PCT/JP2010/073530 patent/WO2011081130A1/en not_active Ceased
- 2010-12-28 TW TW099146284A patent/TW201135825A/en unknown
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006030230A (en) * | 2004-07-12 | 2006-02-02 | Sanyo Electric Co Ltd | Manufacturing method of semiconductor device |
| JP2008270520A (en) * | 2007-04-20 | 2008-11-06 | Sharp Corp | Light receiving element for blue laser and method for manufacturing the same, optical pickup device and electronic apparatus |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013053923A (en) * | 2011-09-05 | 2013-03-21 | Lasertec Corp | Thickness measuring device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013065582A (en) | 2013-04-11 |
| TW201135825A (en) | 2011-10-16 |
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