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WO2011070745A1 - Dispositif d'imagerie à semi-conducteur et dispositif d'imagerie - Google Patents

Dispositif d'imagerie à semi-conducteur et dispositif d'imagerie Download PDF

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Publication number
WO2011070745A1
WO2011070745A1 PCT/JP2010/006974 JP2010006974W WO2011070745A1 WO 2011070745 A1 WO2011070745 A1 WO 2011070745A1 JP 2010006974 W JP2010006974 W JP 2010006974W WO 2011070745 A1 WO2011070745 A1 WO 2011070745A1
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Prior art keywords
transistor
pixel
imaging device
solid
state imaging
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Ceased
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PCT/JP2010/006974
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English (en)
Japanese (ja)
Inventor
邦彦 原
誠之 松長
善久 南
洋之 林下
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/42—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors

Definitions

  • the present invention relates to a solid-state imaging device and an imaging device in which pixels that photoelectrically convert incident light are two-dimensionally arranged on a semiconductor substrate.
  • MOS type image sensors solid-state imaging devices
  • DSLR digital single lens reflex cameras
  • MOS type image sensors solid-state imaging devices
  • DSLR digital single lens reflex cameras
  • the MOS type image sensor needs to have high image quality not only in the all-pixel readout mode for still image shooting but also in the pixel mixing mode for moving image recording.
  • Patent Document 1 there is one disclosed in Patent Document 1.
  • FIG. 20 is a diagram showing an overall configuration of the solid-state imaging device described in Patent Document 1.
  • This solid-state imaging device includes an imaging region 201 and a pixel readout circuit 100.
  • the imaging region 201 is arranged in a matrix and includes a plurality of unit cells 202 that photoelectrically convert incident light, and vertical signal lines 101 and 102 that are provided corresponding to the columns of the unit cells 202.
  • the unit cell 202 includes a photodiode 211, an amplification transistor 215, a reset switch 214, and a row selection switch 216.
  • the pixel readout circuit 100 includes a current source 103, a ground connection switch 104, a load transistor 105, and a power supply connection switch 106.
  • the ground connection switch 104 is turned off, the row selection switch 216 of the unit cell 202 in the selected row is turned on, and the power connection switch 106 is turned on.
  • the current source 103 is connected to either the source terminal or the drain terminal on the row selection switch 216 side of the amplification transistor 215 of the selected unit cell 202 via the vertical signal line 101, and the row selection switch 216 side A power source is connected to the other of the source terminal and the drain terminal on the opposite side via a vertical signal line 102.
  • the amplification transistor 215 of the unit cell 202 and the current source 103 form a source follower amplifier, and the signal of the selected unit cell 202 is read from the pixel output line 107.
  • the ground connection switch 104 is turned on, the row selection switch 216 of the unit cell 202 of the selected row is turned on, and the power connection switch 106 is turned off.
  • the ground is connected to either the source terminal or the drain terminal on the row selection switch 216 side of the amplification transistor 215 of the selected unit cell 202 via the vertical signal line 101, and opposite to the row selection switch 216 side.
  • a load transistor 105 is connected to one of the source terminal and the drain terminal on the side through a vertical signal line 102.
  • a common source amplifier is formed by the amplification transistor 215 and the load transistor 105 of the unit cell 202, and if the row selection switches 216 of two rows are simultaneously turned on, the signals of the upper and lower unit cells 202 arranged in the column direction are mixed.
  • the mixed signal is obtained from the pixel output line 108. If the mixed signal is read by sequentially turning on the row selection switch 216 two rows at a time, the mixed signal of the entire imaging region 201 is read.
  • the solid-state imaging device of FIG. 20 when the solid-state imaging device of FIG. 20 is driven in the pixel mixing mode, the operating current varies according to the signal level of the mixed signal. As a result, the power supply provided in common for all the pixel readout circuits 100 is shaken, and the captured image (pixel mixed image) obtained by the mixed signal is deteriorated.
  • an object of the present invention is to provide a solid-state imaging device and an imaging device capable of obtaining a high-quality image even when driven in a pixel mixing mode.
  • a solid-state imaging device includes a pixel that generates a signal corresponding to an amount of received light, a floating diffusion that accumulates the signal of the pixel, and a source that is the floating diffusion.
  • a plurality of unit cells arranged in a two-dimensional manner and corresponding to the column of pixels, and corresponding to the reset transistor connected to each other and amplifying transistors whose gates are connected to the floating diffusion A vertical signal line that is connected to a source of the amplification transistor of the unit cell including the pixel of the column and transmits a signal of the pixel of the corresponding column; and when the signal of the pixel is output to the vertical signal line
  • a pixel current source that supplies current to the signal line, a drain of the reset transistor, and a drain of the amplification transistor.
  • a pixel power supply line connected to IN and between the source of the amplification transistor and the vertical signal line, or between the drain of the amplification transistor and the pixel power supply line, and the pixel is connected to the vertical signal line. And an element that functions as a resistor when the above signal is output.
  • the element functioning as the resistor may be a transistor.
  • the on-resistance of the transistor functioning as the resistor may be larger than that of the reset transistor or the amplification transistor.
  • the solid-state imaging device of the present invention it is possible to obtain a high-quality image even when driven in the pixel mixing mode, and it is easy to realize a DSLR having a high-quality still image shooting function and a moving image recording function. The effect of becoming is obtained.
  • FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing a detailed configuration of the column circuit of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram illustrating a detailed configuration of the multiplexer and its periphery in the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 5 is a diagram illustrating a detailed configuration of the row selection circuit of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 3
  • FIG. 6 is a diagram illustrating the timing of each control signal supplied to the unit cell and the column circuit when the solid-state imaging device according to the first embodiment of the present invention is in the all-pixel readout mode.
  • FIG. 7 is a diagram illustrating the timing of each control signal supplied to the unit cell and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 8 is a diagram illustrating a relationship between the FD potential Vfd and the pixel SF output Vo when the solid-state imaging device according to the first embodiment of the present invention is in the all-pixel readout mode.
  • FIG. 9 is a diagram illustrating a relationship between the FD potential Vfd and the pixel SF output Vo when the solid-state imaging device according to the first embodiment of the present invention is in the pixel mixture mode.
  • FIG. 10 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 11 is a diagram illustrating a detailed configuration of the row selection circuit of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 12 is a diagram illustrating another detailed configuration of the row selection circuit of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 13 is a circuit diagram illustrating a detailed configuration of the imaging region of the solid-state imaging device according to the third embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing a detailed configuration of the imaging region of the solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 11 is a diagram illustrating a detailed configuration of the row selection circuit
  • FIG. 14 is a diagram illustrating the timing of each control signal supplied to the unit cell and the column circuit in the all-pixel readout mode of the solid-state imaging device according to the third embodiment of the present invention.
  • FIG. 15 is a diagram illustrating timings of control signals supplied to the unit cell and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels of the solid-state imaging device according to the third embodiment of the present invention.
  • FIG. 16 is a circuit diagram illustrating a detailed configuration of the imaging region of the solid-state imaging device according to the fourth embodiment of the present invention.
  • FIG. 17 is a diagram illustrating an overall configuration of a solid-state imaging device according to the fifth embodiment of the present invention.
  • FIG. 18 is a diagram illustrating a detailed configuration of the column ADC of the solid-state imaging device according to the fifth embodiment of the present invention.
  • FIG. 19 is a timing chart for explaining the AD conversion operation of the column ADC of the solid-state imaging device according to the fifth embodiment of the present invention.
  • FIG. 20 is a diagram illustrating an overall configuration of the solid-state imaging device described in Patent Document 1.
  • FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram illustrating a detailed configuration of the imaging region 1 of the solid-state imaging device.
  • This solid-state imaging device includes an imaging region 1, a row selection circuit 3, a pixel current source circuit 4, a clamp circuit 5, a sample hold (S / H) circuit 6, a multiplexer (MUX) 7, a column selection circuit 8, a control unit 9, and
  • the output amplifier 10 is configured.
  • the imaging region 1 is provided corresponding to a column of a plurality of unit cells 2 and pixels (light receiving units) 11 arranged in a two-dimensional shape (matrix) on a semiconductor substrate, and includes a unit 11 including pixels 11 of the corresponding column.
  • a vertical signal line 19 connected to the source terminal of the amplification transistor of the cell 2 and transmitting the output signal from the pixel 11 of the corresponding column in the column direction (vertical direction), and the drain terminal of the reset transistor 14 of the unit cell 2
  • a pixel power line 17 connected to the drain terminal of the amplifying transistor 15 and supplying an initial voltage to the unit cell 2.
  • FIG. 1 shows an example in which 6 ⁇ 4 unit cells 2 are two-dimensionally arranged, the actual number of unit cells 2 is several million or more.
  • the row selection circuit 3 is provided for each horizontal row of the unit cells 2 and is common to a plurality of unit cells 2 in the same row, that is, a row selection signal SEL [n], a reset signal RST [n], and a transfer signal. It is connected to three control lines for supplying TRAN [n] (n is a natural number of 1 or more).
  • the row selection circuit 3 resets (initializes), reads (reads), and selects a line (row selection) for each unit cell 2 in the imaging region 1 in units of rows of the unit cell 2 via these control lines.
  • the pixel 11 to be controlled and to output a signal to the vertical signal line 19 is selected in units of rows.
  • the pixel current source circuit 4 is configured such that basic units provided corresponding to each column of the pixels 11 are arranged in an array in the row direction (horizontal direction), and the signal of the pixel 11 is output to the vertical signal line 19. A current supplied to the vertical signal line 19 is sometimes generated and supplied.
  • the clamp circuit 5 is configured such that basic units provided corresponding to the respective columns of the pixels 11 are arranged in an array in the row direction, and the unit cell 2 is output from the output signal of the unit cell 2 in the row unit from the vertical signal line 19. The fixed pattern noise component generated in step 1 is removed.
  • the S / H circuit 6 includes basic units provided corresponding to the respective columns of the pixels 11 arranged in an array in the row direction, and holds the output signal of the unit cell 2 in units of rows from the clamp circuit 5. .
  • the MUX 7 is configured such that basic units provided corresponding to each column of the pixels 11 are arranged in an array in the row direction, and switches connection between each basic unit of the S / H circuit 6 and the output amplifier 10.
  • the column selection circuit 8 is connected to the MUX 7 via a control line and controls the operation of the MUX 7. In other words, the column selection circuit 8 sequentially selects the column of the pixels 11 that outputs the output signal from the clamp circuit 5 to the output amplifier 10, that is, the basic unit of the S / H circuit 6.
  • the output amplifier 10 receives the output signal from the S / H circuit 6 via the MUX 7, amplifies the received output signal, and outputs it to the outside of the chip.
  • the control unit 9 supplies a drive signal for driving the row selection circuit 3 to the row selection circuit 3 in accordance with the drive mode.
  • the unit cell 2 photoelectrically converts incident light to generate a signal charge corresponding to the amount of received light, accumulates and outputs the generated signal charge, and accumulates and accumulates the signal charge generated by the pixel 11.
  • a floating diffusion (FD) 13 for outputting a signal charge as a voltage signal, and a reset for initializing the FD 13 so that the source terminal is connected to the FD 13 and the voltage indicated by the FD 13 becomes an initial voltage (here, VDD).
  • the transistor 14, the transfer transistor 12 inserted between the pixel 11 and the FD 13 and supplying the signal charge output from the pixel 11 to the FD 13, and the gate terminal thereof are connected to the FD 13, and follow the voltage indicated by the FD 13.
  • an amplifying transistor 15 for outputting to the vertical signal line 19.
  • the unit cell 2 outputs a reset voltage obtained by amplifying the voltage of the FD 13 when the FD 13 is initialized and a read voltage obtained by amplifying the voltage of the FD 13 when the signal charge of the pixel 11 is read to the FD 13 to the vertical signal line 19. To do.
  • the unit cell 2 is further inserted between the source terminal of the amplification transistor 15 and the vertical signal line 19, and when the row selection signal SEL [n] is received at the gate terminal from the row selection circuit 3 via the control line.
  • the row selection transistor 16 that connects the output (source terminal) of the amplification transistor 15 to the vertical signal line 19, and the source terminal of the amplification transistor 15 and the row selection transistor 16 (vertical signal line 19) are serially connected to the amplification transistor 15.
  • a resistance element 61 that can ensure a desired operating range of the FD 13 in the pixel mixture mode.
  • the resistance element 61 is formed of a wiring composed of a diffusion region, a metal wiring, a polysilicon wiring, a contact, and the like.
  • An example of the pixel 11 is a photodiode having a buried structure.
  • the resistance element 61 functions as a resistance when the signal of the pixel 11 is output to the vertical signal line 19.
  • the unit cell 2 in FIG. 2 has a structure including a pixel, a transfer transistor, an FD, a reset transistor, and an amplification transistor, that is, a so-called one-pixel one-cell structure.
  • the unit cell 2 includes a plurality of pixels, and may have a structure in which any one or all of the FD, the reset transistor, and the amplification transistor are shared within the unit cell, that is, a so-called multi-pixel 1-cell structure. Absent.
  • the pixel 11 can have a structure formed on the surface of the semiconductor substrate, that is, on the same side as the surface on which the gate terminal and the wiring of the transistor are formed. Furthermore, the structure of a so-called back-side illumination type image sensor (back-side illumination type solid-state imaging device) in which the pixels 11 are formed on the back side of the semiconductor substrate, that is, the side on which the gate terminal and the wiring of the transistor are formed. It can also be used.
  • back-side illumination type image sensor back-side illumination type solid-state imaging device
  • FIG. 3 is a diagram showing a detailed configuration of the column circuit.
  • the column circuit processes signals output from the pixels 11 in the same column, and includes a basic unit 4 a of the pixel current source circuit 4, a basic unit 5 a of the clamp circuit 5, and a basic unit 6 a of the S / H circuit 6. Composed.
  • the column circuit temporarily holds a pixel signal indicating a difference between the reset voltage and the read voltage output to the vertical signal line 19 for each pixel 11 or for each unit cell 2, and then outputs a pixel signal indicating the difference to the MUX 7. .
  • the basic unit 4a of the pixel current source circuit 4 is supplied with a current source bias voltage 21 at its gate terminal, and from the current source transistor 20 that supplies current to the amplifying transistor 15 when a signal is read from the unit cell 2 to the vertical signal line 19. Become.
  • the basic unit 5a of the clamp circuit 5 includes a clamp capacitor 23 having a capacitance value Ccl for obtaining a pixel signal, a sampling transistor 22 to which a sampling signal is supplied to the gate terminal, and the S / H circuit 6 opposite to the clamp capacitor 23. It comprises a clamp voltage input terminal 25 for setting the terminal potential on the pixel current source circuit 4 side to the clamp potential (VCL) and a clamp transistor 24 to which a clamp signal is supplied to the gate terminal.
  • VCL clamp potential
  • the basic unit 6 a of the S / H circuit 6 includes an S / H capacitor 27 having a capacitance value Csh for temporarily holding a pixel signal, an S / H capacitor input signal supplied to the gate terminal, and a pixel in the S / H capacitor 27.
  • An S / H capacitor input transistor 26 for inputting a signal is included.
  • FIG. 4 is a diagram showing a detailed configuration of the MUX 7 and its surroundings.
  • the basic unit 7 a of the MUX 7 includes a column selection transistor 28 disposed between the basic unit 6 a of the S / H circuit 6 and the horizontal common signal line 29.
  • the column selection transistor 28 sequentially outputs the pixel signal held in each basic unit 6 a of the S / H circuit 6 to the horizontal common signal line 29 in response to the column selection signal H [n] supplied to the gate terminal.
  • the pixel signal supplied to the output amplifier 10 via the horizontal common signal line 29 is amplified and then output to the outside of the chip.
  • FIG. 5 is a diagram showing a detailed configuration of the row selection circuit 3.
  • the row selection circuit 3 includes an address decoder 31 and a plurality of row selection logic circuits 32 provided corresponding to each row of the unit cell 2.
  • a Hi voltage is output to a predetermined row selection logic circuit 32 according to the address signal ADR supplied from the control unit 9, and a write enable signal is output to the flip-flop 33 of the predetermined row selection logic circuit 32. Entered.
  • the Hi voltage is set in the flip-flop 33 to which the write enable signal is input, and the unit cell 2 in the row connected to the flip-flop 33 via the AND gate 34 is selected.
  • the control pulses SEL_s, TRAN_s, and RST_s are input in the selected state, the row selection signal SEL [n], the reset signal RST [n], and the transfer signal TRAN [ n].
  • the driving of the unit cell 2 is completed, the value of each flip-flop 33 is reset to the Lo voltage, and the row selection is released.
  • the solid-state imaging device of the present embodiment has an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function. Next, the signal reading operation will be described for each mode.
  • FIG. 6 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the all-pixel readout mode in the solid-state imaging device of the present embodiment.
  • Vfd the potential of the FD 13
  • the threshold voltage of the amplification transistor 15 is Vth
  • the resistance value of the resistance element 61 is R
  • the current value of the pixel current source circuit 4 Is Vfdrst-Vth-RI (precisely Vfdrst-Vth-RI- ⁇ , where ⁇ is omitted) is output to the vertical signal line 19 as a reset voltage.
  • the reset voltage Vfdrst ⁇ Vth ⁇ RI is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in an on state.
  • both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistor 12 is off and the row selection transistor 16 is on, and Vfdrst-Vfdsig-Vth-RI is output to the vertical signal line 19 as a read voltage.
  • the input of the clamp capacitor 23 changes by Vfdsig.
  • the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a voltage corresponding to the pixel signal, and at timing t5, the row selection signal SEL [1] and the S / H capacitor input signal. Becomes the Lo voltage, and this pixel signal is accumulated in the S / H capacitor 27.
  • the pixel signals for one row are held in the S / H circuit 6.
  • the column selection signal H [1] becomes the Hi voltage, and the column selection transistor 28 in the first column is turned on.
  • the pixel signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and is output to the outside of the chip via the output amplifier 10.
  • the column selection signal H [2] becomes the Hi voltage, and the column selection transistor 28 in the second column is turned on.
  • the pixel signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • pixel signals for one row are sequentially output to the outside of the chip.
  • FIG. 7 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels in the solid-state imaging device of the present embodiment.
  • the row selection signals SEL [1] and SEL [2] are both Hi voltage, and the unit cells 2 in the first and second rows are selected.
  • two address decoders 31 of the row selection circuit 3 This can be achieved by sequentially supplying the address signal ADR, sequentially inputting the write enable signal to the flip-flop 33 of the row selection logic circuit 32, and sequentially setting the Hi voltage (also for the transfer signals TRAN [1] and TRAN [2]). The same).
  • Vfdrst ⁇ Vth ⁇ RI / 2 is output to the vertical signal line 19 as a reset voltage (more precisely, Vfdrst -Vth-RI / 2- ⁇ , where ⁇ is omitted). Further, the reset voltage Vfdrst ⁇ Vth is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in the ON state.
  • both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistors 12 are turned on for the unit cells 2 in the first and second rows, so that the signal charges accumulated in the pixels 11 of the unit cells 2 in the first and second rows are transferred to the FD 13.
  • the FD potentials Vfd1 and Vfd2 of the unit cells 2 in the first row and the second row are reduced by the voltages Vfdsig1 and Vfdsig2 corresponding to the signal charge amounts to Vfdrst ⁇ Vfdsig1 and Vfdrst ⁇ Vfdsig2.
  • Vfdrst ⁇ Vfdsig ⁇ Vth -RI / 2 is output to the vertical signal line 19 as a read voltage.
  • This read voltage corresponds to the mixed signal of the unit cells 2 in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 23 also changes by Vfdsig.
  • the clamp transistor 24 since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) of the unit cells 2 in the first and second rows.
  • the row selection signals SEL [1] and SEL [2] and the S / H capacitor input signal become Lo voltage and are stored in the S / H capacitor 27.
  • the S / H capacitor input signal and the column selection signals H [1] and H [2] are set to the Hi voltage, and the column selection transistors 28 in the first column and the second column are turned on.
  • the average signal of the S / H capacitor 27 in the first column and the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the column selection signals H [3] and H [4] become Hi voltage, and the column selection transistors 28 in the third and fourth columns are turned on.
  • an average signal of the S / H capacitors 27 in the third column and the S / H capacitors 27 in the fourth column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the average signal of the pixel signals of the S / H capacitors 27 in each column is sequentially output outside the chip.
  • FIG. 8 is a diagram showing the relationship between Vfd and pixel SF output Vo at timing t4 in the all-pixel readout mode (FIG. 6).
  • the relationship between Vfd and Vo is expressed by equations (1) and (2).
  • Vo Vfd ⁇ Vth ⁇ RI ⁇ (I / a) (1)
  • a (1/2) ⁇ (W / L) ⁇ ⁇ eff ⁇ Cox (2)
  • Vth, W, L, ⁇ eff, and Cox indicate the threshold voltage, gate width, gate length, carrier mobility, and gate oxide film thickness of the amplification transistor 15, and I indicates the current value of the pixel current source circuit 4. Show. Strictly speaking, when Vo changes, the source-substrate potential of the amplification transistor 15 changes and Vth also changes. Here, Vth is treated as a fixed value.
  • Vo shows a linear characteristic that becomes a value obtained by subtracting a fixed value from Vfd.
  • Vfd is at the initial value Vfdrst at the timing t2, and the signal charge of the pixel 11 is transferred at the timing t3 to reduce the potential.
  • a pixel signal is detected by detecting the difference in the output potential of the pixel SF with respect to the two values of Vfd by a column circuit.
  • FIG. 9 is a diagram showing the relationship between the FD potential Vfd1 of the unit cell 2 in the first row and the FD potential Vfd2 of the unit cell 2 in the second row and the pixel SF output Vo when mixing signals of two vertical pixels. is there.
  • ⁇ V RI + (2- ⁇ 2) ⁇ ⁇ (I / a) (4)
  • the resistance element 61 serially inserted into the amplification transistor 15 can ensure a desired operating range in the signal mixing of a plurality of pixels arranged vertically.
  • a desired operating range of the FD 13 can be secured by the resistance element 61 even when signals output from the unit cells 2 are mixed by the vertical signal line 19.
  • fluctuations in the operating current during signal readout can be suppressed in both the all-pixel readout mode and the pixel mixture mode, so that a high-quality image can be obtained.
  • the unit cell 2 in FIG. 2 has a configuration using four transistors, that is, an amplification transistor, a transfer transistor, a reset transistor, and a row selection transistor, but includes only three transistors, an amplification transistor, a transfer transistor, and a reset transistor. But it doesn't matter.
  • the row selection of the unit cell 2 is executed by setting a low potential to the Vfd of the unit cell 2 in the row where reading is not performed.
  • the overall configuration of the solid-state imaging device according to the second embodiment of the present invention is the same as the overall configuration of the solid-state imaging device according to the first embodiment shown in FIG.
  • FIG. 10 is a circuit diagram illustrating a detailed configuration of the imaging region 1 of the solid-state imaging device according to the second embodiment.
  • the difference between this circuit and the circuit of the imaging region 1 of the first embodiment shown in FIG. 2 is that there is no resistance that is serially connected to the amplification transistor 15, and the on-resistance of the row selection transistor 16 is different from that of the unit cell 2. It is larger than the transistor (reset transistor 14 or amplification transistor 15).
  • FIG. 11 is a diagram showing a detailed configuration of the row selection circuit 3.
  • VDDL is supplied as a power source of the AND gate 34 that generates the row selection signal SEL [n].
  • VDDL is set to a voltage lower than the power supply of other circuits. Either the Hi voltage or the Lo voltage lower than the Hi voltage is supplied to the gate terminals of the reset transistor 14 and the row selection transistor 16 by the row selection signal SEL.
  • the Hi voltage supplied to the gate terminal of the row selection transistor 16 is Since the voltage is lower than the Hi voltage supplied to the gate terminal of the reset transistor 14, the on-resistance of the row selection transistor 16 when the row selection transistor 16 is turned on becomes a relatively large value.
  • the solid-state imaging device of the present embodiment has an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function. Next, the signal reading operation will be described for each mode.
  • the timing of each control signal supplied to the unit cell 2 and the column circuit in the all-pixel readout mode in the solid-state imaging device of the present embodiment is the same as the timing of the first embodiment shown in FIG.
  • Vfdrst-Vth-RI (exactly Vfdrst-Vth-RI- ⁇ , where ⁇ is omitted) Is output to the vertical signal line 19 as a reset voltage.
  • the reset voltage Vfdrst ⁇ Vth ⁇ RI is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in an on state.
  • both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistor 12 is off and the row selection transistor 16 is on, and Vfdrst-Vfdsig-Vth-RI is output to the vertical signal line 19 as a read voltage.
  • the input of the clamp capacitor 23 changes by Vfdsig.
  • the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a voltage corresponding to the pixel signal, and at timing t5, the row selection signal SEL [1] and the S / H capacitor input signal. Becomes the Lo voltage, and this pixel signal is accumulated in the S / H capacitor 27.
  • the pixel signals for one row are held in the S / H circuit 6.
  • the column selection signal H [1] becomes the Hi voltage, and the column selection transistor 28 in the first column is turned on.
  • the pixel signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and is output to the outside of the chip via the output amplifier 10.
  • the column selection signal H [2] becomes the Hi voltage, and the column selection transistor 28 in the second column is turned on.
  • the pixel signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • pixel signals for one row are sequentially output to the outside of the chip.
  • each control signal supplied to the unit cell 2 and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels in the solid-state imaging device of this embodiment is the same as the timing of the first embodiment shown in FIG. is there.
  • the row selection signals SEL [1] and SEL [2] are both Hi voltage, and the unit cells 2 in the first and second rows are selected.
  • two address decoders 31 of the row selection circuit 3 This can be achieved by sequentially supplying the address signal ADR, sequentially inputting the write enable signal to the flip-flop 33 of the row selection logic circuit 32, and sequentially setting the Hi voltage (also for the transfer signals TRAN [1] and TRAN [2]). The same).
  • the row selection transistor 16 is in the on state, but the on-resistance becomes a magnitude R that cannot be ignored because the gate potential is low, and Vfdrst ⁇ Vth ⁇ RI / 2. (To be precise, Vfdrst ⁇ Vth ⁇ RI / 2 ⁇ , where ⁇ is omitted) is output to the vertical signal line 19 as a reset voltage. Further, the reset voltage Vfdrst ⁇ Vth ⁇ RI / 2 is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in the ON state. On the other hand, the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistors 12 are turned on for the unit cells 2 in the first and second rows, so that the signal charges accumulated in the pixels 11 of the unit cells 2 in the first and second rows are transferred to the FD 13.
  • the FD potentials Vfd1 and Vfd2 of the unit cells 2 in the first row and the second row are reduced by the voltages Vfdsig1 and Vfdsig2 corresponding to the signal charge amounts to Vfdrst ⁇ Vfdsig1 and Vfdrst ⁇ Vfdsig2.
  • Vfdrst ⁇ Vfdsig ⁇ Vth -RI / 2 is output to the vertical signal line 19 as a read voltage.
  • This read voltage corresponds to the mixed signal of the unit cells 2 in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 23 also changes by Vfdsig.
  • the clamp transistor 24 since the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) of the unit cells 2 in the first and second rows.
  • the row selection signals SEL [1] and SEL [2] and the S / H capacitor input signal become Lo voltage and are stored in the S / H capacitor 27.
  • the S / H capacitor input signal and the column selection signals H [1] and H [2] are set to the Hi voltage, and the column selection transistors 28 in the first column and the second column are turned on.
  • the average signal of the S / H capacitor 27 in the first column and the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the column selection signals H [3] and H [4] become Hi voltage, and the column selection transistors 28 in the third and fourth columns are turned on.
  • an average signal of the S / H capacitors 27 in the third column and the S / H capacitors 27 in the fourth column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the average signal of the pixel signals of the S / H capacitors 27 in each column is sequentially output outside the chip.
  • pixel signals in which signals of 2 vertical pixels and 2 horizontal pixels are mixed are sequentially output to the outside of the chip.
  • FD range ⁇ V in this pixel mixture mode is expressed by equation (4) as in the first embodiment. It can be seen that the operating range of the FD 13 can be secured by the on-resistance R generated by reducing the Hi voltage of the gate potential of the row selection transistor 16.
  • a resistance element is not provided separately, but the row selection transistor 16 functions as a resistor connected in series with the amplification transistor 15. Therefore, not only the signal mixing operation with the fluctuation of the operating current can be realized, but also the resistor element and the row selection transistor 16 can be realized by one device, and the circuit area of the unit cell 2 can be reduced and the sensitivity can be improved. There is also an advantage of being.
  • the gate width of the row selection transistor 16 is made smaller than the gate width of the amplification transistor 15, and the threshold voltage of the row selection transistor 16 is set to the threshold of the amplification transistor 15. There is also a method of adjusting larger than the value voltage. Further, the gate length of the row selection transistor 16 is made larger than the minimum value allowed in the process. For example, the gate length of the row selection transistor 16 is made larger than the minimum gate length of the transistors constituting the row selection circuit 3. The on-resistance of the selection transistor 16 can be increased.
  • FIG. 1 the configuration of another row selection circuit 3 for reducing the Hi voltage of the gate potential of the row selection transistor 16 is shown in FIG.
  • the output of the variable power source 62 having a variable output voltage is supplied as the power source of the AND gate 34 that generates the row selection signal SEL [n] for supplying the Hi voltage to the gate terminal of the row selection transistor 16.
  • the output of the variable power source 62 is a high voltage in the all-pixel reading mode and a low voltage in the pixel mixing mode.
  • the solid-state imaging device of the second embodiment is characterized in that the row selection transistor 16 functions as a resistance element, and the gate potential of the row selection transistor 16 is set low in order to clarify the effect of the feature.
  • the gate potential of the row selection transistor 16 is not adjusted, the on-resistance of the row selection transistor 16 exists, and in an application where the FD operation range ⁇ V may be relatively narrow, fluctuations in the operating current are suppressed even without this Hi voltage adjustment.
  • the pixel signal mixing operation in the state can be realized. In this case, a separate power source is unnecessary, and the configuration of the entire chip is simplified.
  • the gate width of the row selection transistor 16 is made smaller than that of the amplification transistor 15, and the gate length of the row selection transistor 16 is made larger than the minimum value allowed in the process.
  • the method of adjusting the threshold voltage of the row selection transistor 16 is also effective.
  • FIG. 13 is a circuit diagram showing a detailed configuration of the imaging region 1.
  • the resistance element 61 and the row selection transistor 16 function as an element that functions as a resistor connected in series with the amplification transistor 15.
  • a resistance transistor 63 whose gate terminal is connected to the pixel power supply line 17 and whose on-resistance is larger than the other transistors (reset transistor 14 or amplification transistor 15) constituting the unit cell 2 is serially connected to the amplification transistor 15.
  • the output VDDCEL of the pixel power supply generation circuit 73 is supplied to the pixel power supply line 17 connected to the drain terminals of the reset transistor 14 and the amplification transistor 15.
  • the row selection operation of the unit cell 2 is realized by turning on and off the row selection transistor 16, but here, the Vfd of all the rows of the unselected unit cell 2 is obtained.
  • the row selection operation of the unit cell 2 is realized by setting it low.
  • VDDCEL is switched between a low potential for non-selection and a high pixel potential (VDD) for signal readout.
  • the solid-state imaging device of the present embodiment has an all-pixel readout mode that can be used for camera still photography and a pixel mixture mode that can be used for a moving image recording function. Next, the signal reading operation will be described for each mode.
  • FIG. 14 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the all-pixel readout mode in the solid-state imaging device of the present embodiment.
  • the transfer transistor 12 is in the OFF state
  • the VDDCEL is in the Hi voltage (VDD) state
  • the reset transistor 14 is in the ON state
  • the gate potential VDDCEL of the resistance transistor 63 is a Hi voltage. Accordingly, since the resistance transistor 63 is in the on state, assuming that the threshold voltage of the amplification transistor 15 is Vth, the on-resistance of the resistance transistor 63 is R, and the current value of the pixel current source circuit 4 is I, Vfdrst ⁇ Vth -RI (precisely Vfdrst-Vth-RI- ⁇ , where ⁇ is omitted) is output to the vertical signal line 19 as a reset voltage. Further, the reset voltage Vfdrst ⁇ Vth ⁇ RI is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in an on state. On the other hand, both the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistor 12 is off and the resistance transistor 63 is on, and Vfdrst-Vfdsig-Vth-RI is output to the vertical signal line 19 as a read voltage.
  • the input of the clamp capacitor 23 changes by Vfdsig.
  • the clamp transistor 24 is in the OFF state, the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, a voltage corresponding to the pixel signal.
  • the S / H capacitance input signal becomes the Lo voltage, and this pixel signal is Accumulated in the S / H capacity 27.
  • the pixel signals for one row are held in the S / H circuit 6.
  • VDDCEL is at the Lo voltage and the reset transistor 14 is in the ON state, so that Vfd is set to a low potential, and the unit cell 2 in the row where the signal reading is completed returns to the non-selected state.
  • the column selection signal H [1] becomes the Hi voltage, and the column selection transistor 28 in the first column is turned on.
  • the pixel signal of the S / H capacitor 27 in the first column is output to the horizontal common signal line 29 and is output to the outside of the chip via the output amplifier 10.
  • the column selection signal H [2] becomes the Hi voltage, and the column selection transistor 28 in the second column is turned on.
  • the pixel signal of the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • pixel signals for one row are sequentially output to the outside of the chip.
  • FIG. 15 is a diagram showing the timing of each control signal supplied to the unit cell 2 and the column circuit in the pixel mixing mode of two vertical pixels and two horizontal pixels in the solid-state imaging device of the present embodiment.
  • VDDCEL is in the Hi voltage state
  • the two address signals ADR are sequentially supplied to the address decoder 31 of the row selection circuit 3, and the row selection logic circuit. This can be achieved by sequentially setting the 32 flip-flops 33 to the selected state (the same applies to the transfer signals TRAN [1] and TRAN [2]).
  • the gate potential VDDCEL of the resistance transistor 63 is the Hi voltage for the unit cells 2 in the first row and the second row. Accordingly, since the resistance transistor 63 is in the ON state, Vfdrst ⁇ Vth ⁇ RI / 2 (precisely Vfdrst ⁇ Vth ⁇ RI / 2 ⁇ , where ⁇ is omitted) is used as the reset voltage as the vertical signal line 19. Is output. Further, the reset voltage Vfdrst ⁇ Vth ⁇ RI / 2 is output to one terminal of the clamp capacitor 23 because the sampling transistor 22 is in the ON state. On the other hand, the clamp signal and the S / H capacitor input signal are Hi voltages, and the potential of the other terminal of the clamp capacitor 23 and the S / H capacitor 27 is set to VCL.
  • the transfer transistors 12 are turned on for the unit cells 2 in the first and second rows, so that the signal charges accumulated in the pixels 11 of the unit cells 2 in the first and second rows are transferred to the FD 13.
  • the FD potentials Vfd1 and Vfd2 of the unit cells 2 in the first row and the second row are reduced by the voltages Vfdsig1 and Vfdsig2 corresponding to the signal charge amounts to Vfdrst ⁇ Vfdsig1 and Vfdrst ⁇ Vfdsig2.
  • Vfdrst ⁇ Vfdsig ⁇ Vth-RI / 2 is output to the vertical signal line 19 as a read voltage.
  • This read voltage corresponds to the mixed signal of the unit cells 2 in the first and second rows. Due to the potential change of the vertical signal line 19, the input of the clamp capacitor 23 also changes by Vfdsig.
  • the potential of the other terminal of the clamp capacitor 23, that is, the potential of the S / H capacitor 27 changes by Vfdsig ⁇ Ccl / (Ccl + Csh).
  • This potential change is a voltage corresponding to the difference between the reset voltage and the read voltage in the vertical signal line 19, that is, an averaged pixel signal (vertical pixel mixed signal) of the unit cells 2 in the first and second rows.
  • the S / H capacitor input signal becomes Lo voltage and is stored in the S / H capacitor 27.
  • VDDCEL is the Lo voltage and the reset transistors 14 of the unit cells 2 in the first row and the second row are in the ON state, Vfd is set to a low potential, Return to unselected state.
  • the S / H capacitor input signal and the column selection signals H [1] and H [2] are set to the Hi voltage, and the column selection transistors 28 in the first column and the second column are turned on.
  • the average signal of the S / H capacitor 27 in the first column and the S / H capacitor 27 in the second column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the column selection signals H [3] and H [4] become Hi voltage, and the column selection transistors 28 in the third and fourth columns are turned on.
  • an average signal of the S / H capacitors 27 in the third column and the S / H capacitors 27 in the fourth column is output to the horizontal common signal line 29 and output to the outside of the chip via the output amplifier 10.
  • the average signal of the pixel signals of the S / H capacitors 27 in each column is sequentially output outside the chip.
  • FD range ⁇ V in this pixel mixture mode is expressed by equation (4) as in the first and second embodiments.
  • a transistor corresponding to the row selection transistor 16 of the first and second embodiments that is, as a transistor for selecting the unit cell 2
  • a resistance transistor 63 is provided, and the operating range of the FD 13 is increased by the on-resistance R of the resistance transistor 63. It can be seen that it can be secured.
  • the solid-state imaging device of the present embodiment not only can a signal mixing operation with suppressed fluctuations in operating current be realized, but also a transistor that functions as a resistor compared to the solid-state imaging device of the second embodiment. This eliminates the need for a signal line to be supplied to the gate terminal, and therefore has an advantage of being suitable for reducing the circuit area and the aperture ratio of the unit cell 2.
  • FIG. 16 is a circuit diagram showing a detailed configuration of the imaging region 1.
  • ⁇ V bRI + (2- ⁇ 2) ⁇ ⁇ (I / a) (5)
  • FIG. 17 is a diagram illustrating an overall configuration of a solid-state imaging device according to the fifth embodiment of the present invention.
  • This solid-state imaging device includes an imaging region 1, a row selection circuit 3, a pixel current source circuit 4, a clamp circuit 5, a sample hold (S / H) circuit 6, a column ADC 44, a digital mixer 45, and a control unit 9. .
  • the column ADC 44 is configured such that basic units provided corresponding to the respective columns of the pixels 11 are arranged in an array in the row direction, and converts the row-unit analog pixel signals held in the S / H circuit 6 into digital signals. To do.
  • the digital mixer 45 is configured such that basic units provided corresponding to each column of the pixels 11 are arranged in an array in the row direction, and mixes output data (digital signal) of the column ADC 44.
  • the detailed configuration of the unit cell 2, the pixel current source circuit 4, the clamp circuit 5, the S / H circuit 6, and the row selection circuit 3 is the same as that of the solid-state imaging device of the first embodiment.
  • FIG. 18 is a diagram showing a detailed configuration of the column ADC 44.
  • the column ADC 44 includes a plurality of basic units 44 a and a column ADC input terminal 46, a ramp waveform generation circuit 48, and a counter 50.
  • the basic unit 44 a of the column ADC 44 includes a comparator 47 and a latch 49.
  • the comparator 47 receives the pixel signal from the S / H circuit 6 input from the column ADC input terminal 46, compares the input pixel signal with the ramp waveform of the ramp waveform generation circuit 48, and the ramp waveform is When it is lower than the pixel signal, the Hi voltage is output.
  • the latch 49 receives the output (counter value) of the counter 50, and writes the output of the counter 50 when the latch signal from the counter 50 is switched from the Hi voltage to the Lo voltage.
  • the counter 50 counts up in synchronization with the ramp waveform generated by the ramp waveform generation circuit 48.
  • a pixel signal is input to the column ADC 44, the ramp waveform is set to the minimum value of the pixel signal, and the counter 50 is set to 0. At this time, since the ramp waveform is at a lower level than the pixel signal, the latch signal is at the Hi voltage.
  • the ramp waveform level starts to rise.
  • the rising slope is set to reach the maximum value of the pixel signal at timing t3.
  • the counter 50 also counts up in synchronization with the ramp waveform rise.
  • the latch signal is switched to the Lo voltage, and the counter value at that time is written in the latch 49.
  • the digital value written in the latch 49 is a value corresponding to the pixel signal.
  • the solid-state imaging device includes an all-pixel readout mode and a pixel mixture mode, similarly to the solid-state imaging device according to the first embodiment. Next, the signal reading operation in each mode will be described.
  • the unit cells 2 for one row are selected, and pixel signals for one row are read from the unit cells 2 and held in the S / H circuit 6.
  • the pixel signals for one row are read from the S / H circuit 6 to the column ADC 44 and are digitally converted by the column ADC 44.
  • the mixed pixel signal is read from the S / H circuit 6 to the column ADC 44 and is digitally converted by the column ADC 44.
  • digital signals are simultaneously read out from the basic units 44 a of the column ADCs 44 in a plurality of columns to the digital mixer 45 and mixed by the digital mixer 45.
  • the mixed digital signals are sequentially output to the outside of the chip via the output unit (not shown).
  • the solid-state imaging device As described above, according to the solid-state imaging device according to the present embodiment, a digital output solid-state imaging device having a pixel mixing function suitable for high image quality while suppressing fluctuations in operating current can be realized.
  • the MUX 7, the output amplifier 10, and the analog front end portion that performs AD conversion in the subsequent stage are wide-band circuits for a high data transfer rate. become. For this reason, there exists a subject that the noise from the outside tends to mix.
  • the solid-state imaging device has an advantage that the resistance to the disturbance noise is greatly improved since the signal is digitized by the column circuit. This also leads to easy creation of a camera substrate using a solid-state imaging device.
  • the present invention is not limited to this embodiment.
  • the present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.
  • the solid-state imaging device of the above embodiment includes a lens that collects external light on the solid-state imaging device, an image signal processing device that processes a signal from the solid-state imaging device, and a signal processed by the image signal processing device. It can be used in an imaging apparatus that includes an image storage device for storing and has a still image shooting function and a moving image shooting function with a lower resolution and a higher frame rate than a still image.
  • each transistor constituting the solid-state imaging device is an n-channel type MOS transistor, but may be a p-channel type MOS transistor.
  • the present invention is useful as a solid-state imaging device and an imaging device, and particularly useful as an image sensor for an imaging device that requires high image quality and high functionality such as a digital single-lens reflex camera and a high-end compact camera.

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  • Multimedia (AREA)
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  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention concerne un dispositif d'imagerie et un dispositif d'imagerie à semi-conducteur qui peuvent obtenir des images de haute qualité lorsqu'ils fonctionnent en mode mélange de pixels. Lesdits dispositifs sont équipés : d'une pluralité de cellules unitaires (2) qui sont disposées dans une matrice bidimensionnelle et qui ont chacune un pixel (11), un FD (13), un transistor de réinitialisation (14) et un transistor d'amplification (15) ; d'une ligne de signal vertical (19) qui est prévue en correspondance avec une colonne de pixels (11), qui se connecte aux sources des transistors d'amplification (15) des cellules unitaires (2) contenant la colonne de pixels correspondante (11) et qui transmet les signaux de la colonne de pixels correspondante (11) ; d'un circuit de source de courant de pixel (4) qui fournit un courant à la ligne de signal vertical (19) lorsque le signal d'un pixel est sorti de la ligne de signal vertical (19) ; une ligne de source de tension de pixel (17) qui est connectée aux drains des transistors d'amplification (15) et aux drains des transistors de réinitialisation (14) ; et d'un élément résistif (61) inséré entre la source du transistor d'amplification (15) et la ligne de signal vertical (19).
PCT/JP2010/006974 2009-12-09 2010-11-30 Dispositif d'imagerie à semi-conducteur et dispositif d'imagerie Ceased WO2011070745A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023182811A (ja) * 2016-12-30 2023-12-26 ソニー アドバンスト ビジュアル センシング アーゲー 動的ビジョンセンサアーキテクチャ

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Publication number Priority date Publication date Assignee Title
JP2005218139A (ja) * 2005-04-04 2005-08-11 Canon Inc 固体撮像装置、それを用いた固体撮像システム、及び信号転送装置
JP2008271159A (ja) * 2007-04-19 2008-11-06 Matsushita Electric Ind Co Ltd 固体撮像装置
JP2009010787A (ja) * 2007-06-28 2009-01-15 Panasonic Corp 固体撮像装置およびその駆動方法、撮像装置
JP2010136110A (ja) * 2008-12-04 2010-06-17 Canon Inc 固体撮像装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005218139A (ja) * 2005-04-04 2005-08-11 Canon Inc 固体撮像装置、それを用いた固体撮像システム、及び信号転送装置
JP2008271159A (ja) * 2007-04-19 2008-11-06 Matsushita Electric Ind Co Ltd 固体撮像装置
JP2009010787A (ja) * 2007-06-28 2009-01-15 Panasonic Corp 固体撮像装置およびその駆動方法、撮像装置
JP2010136110A (ja) * 2008-12-04 2010-06-17 Canon Inc 固体撮像装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023182811A (ja) * 2016-12-30 2023-12-26 ソニー アドバンスト ビジュアル センシング アーゲー 動的ビジョンセンサアーキテクチャ
JP7717132B2 (ja) 2016-12-30 2025-08-01 ソニー アドバンスト ビジュアル センシング アーゲー 動的ビジョンセンサアーキテクチャ

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