WO2011070164A1 - Reconfigurable boolean cells having a criss-crossed nanowire matrix - Google Patents

Abstract

The invention relates to a reconfigurable logic cell including: a plurality of data inputs and a plurality of configuration inputs, the cell consisting of a matrix of crossed nanowires, the matrix including transistors each of which is formed at the crossing of two nanowires, the cell being provided to carry out at least one Boolean logic function of the logic inputs thereof, the Boolean logic function applied being selectable on the basis of the configuration of said configuration inputs.

Description

 RECONFIGURABLE BOOLEAN CELLS WITH INTERCONNECTED NANOWIL MATRIX

TECHNICAL AREA

The present invention relates to the field of logic circuits, and in particular to reconfigurable logic circuits.

 It relates to a reconfigurable logic cell, capable of implementing a large number of different logical functions, which has a small footprint, and whose addressing is facilitated.

PRIOR ART

It is known to implement reconfigurable Boolean logic cells, that is to say cells performing one or more Boolean logic functions that can be modified, depending on how these cells are controlled or programmed.

 One embodiment of such a cell type using nano-based components has been disclosed in O'Connor et al., CNTFET Modeling and Reconfigurable Logic-Circuit Design, IEEE Transactions on Circuits and Systems, Vol. 54, No. 11, pp. 2365-2379, November 2007.

In this document, the reconfigurable logic cell was produced using DG CNT-FET type technology transistors, that is to say double-gate transistors whose channel is made using nanoparticles. carbon tubes. Such transistors may alternatively play the role of N-type transistors and P-type transistors. The logic cell described in this document is capable of carrying out 14 elementary logic functions.

 The implementation of such a cell raises problems of manufacturing complexity and tolerance to manufacturing defects.

 Such a cell is also limited in the number of Boolean logic functions that it is likely to achieve.

 FIGS. 1A-1B give another example of logic cell 2 called "nano-block" and which makes it possible to perform a Boolean function with three inputs, three outputs, as well as its complementary function.

 The internal architecture of a nano-Block (FIG. 1B) comprises a network 4 called MLA (MLA for "Molecular Logic Array" or "molecular logical network") made from intersecting nano-wires at the intersection of which is located a programmable molecular diode acting as a configurable switch according to the function to be performed.

 An MLA network 6 configured to perform NAND and ET functions is given by way of example in FIG.

Because of the use of programmable diodes, such a structure requires a point-by-point control of each diode of the network. The implementation of a device comprising a plurality of such cells poses problems of addressing complexity.

 The nanoblocks can be assembled into a group so as to form a group 12 commonly called a "cluster", within which each nanoblock is connected to its four closest neighbors. A set of nano-block clusters forms a module called "nano-fabric" (Figure 3).

 Another architecture called nano-PLA

(PLA for "Programmable Logical Array") was presented in DeHon, et al. : "Nanowire-based sublithographic programmable logic arrays" Proceedings of the 2004 ACM / SIGDA 12th International Symposium on Field Programmable Treat Arrays. This architecture is formed of nanowires for making and interconnecting nanoscale cells, the logic being realized by programmable diodes at the intersection of the nanowires.

 This type of architecture has even been proposed in 3 dimensions, as described for example in the document: "3D Nanowire-Based Programmable Logic" by DeHon et al., Nano-Networks and Workshops NanoNet 06, pp. 1-5, Sept. 2006.

A programmable diode architecture forms a plane of OR or addressable functions by the nano-son interconnections, each nano-wire at the output of the plane can be programmed to perform the OR logic function of its inputs. A disadvantage of such an architecture resides, because of the voltage loss across each diode, in that it is difficult to achieve several levels of logic in cascade. In addition, the fact of using a logic based solely on the OR function makes incomplete the set of logical operations that can be performed.

 Such an architecture also poses problems addressing, restoration of logic signals, manufacturing, and programming difficulty.

 There is the problem of finding a new reconfigurable logic cell architecture, which has a small footprint, is capable of performing a large number of logical functions, and can be addressed easily.

STATEMENT OF THE INVENTION

The present invention relates to a logic cell comprising:

 a plurality of data inputs and

a plurality of configuration inputs, the cell being designed to perform at least one Boolean logic function of its logic inputs, the applied Boolean logic function being modifiable as a function of the configuration of said configuration inputs. Thus, the logic cell according to the invention is said to be "reconfigurable" or to have a "reconfigurable" function, as a function of the configuration signals that it receives. The cell is further formed of a matrix of intersecting nanowires, the matrix comprising transistors formed at the intersection of two nanowires. The matrix may be formed of a plurality of nano-wires parallel to each other, and orthogonal to another plurality of nano-wires parallel to each other.

 More particularly, the present invention provides a logic cell comprising:

 a plurality of data inputs;

 a plurality of inputs of different configurations of the data inputs, the cell being designed to perform at least one Boolean logic function of its logic inputs, the applied Boolean logic function being parameterized as a function of the value of said configuration inputs;

 a crossed nano-son matrix comprising a first plurality of first nano-wires perpendicular to a second plurality of second nano-wires, wherein a subset of the second nano-wires is connected to the data inputs, the other sub-set of the set of second nanowires being connected to the configuration inputs; and

 transistors formed at certain crossings of two nano-wires, each transistor being controllable by a signal transiting on a second nano-wire.

Such a cell can make it possible to perform a number of important Boolean logic functions while maintaining a small footprint. Such a cell can be addressed and interconnected more easily than cells according to the prior art.

 According to a feature, each first nano-wire is connected to at least a second nano-wire by a transistor controllable by a signal from a configuration input.

 In another feature, at least one first nano-wire is connected to at least one second nanowire by a transistor controllable by a signal from a data input.

 Advantageously, the logic cell further comprises two third nano-wires perpendicular to said first plurality of first nano-wires, a transistor being formed at each intersection between a first nano-son and a third nano-son.

 A plurality of the transistors may form a first block performing a NAND function, while another plurality of the transistors may form a second block performing a NAND function. More particularly, the transistors connected to the first and second nano-wires forming a first block performing a NAND function, the transistors connected to the first and third nano-son forming a second block performing a NAND function.

Advantageously, the logic cell further comprises a fourth plurality of nano-wires parallel to said first plurality of nano-wires, and in which at least one so-called inversion transistor is formed at the intersection of a fourth nano-wire and a second nano-son, the fourth nano-son accommodating the transistor considered being further connected to another second nano-son to provide, on the other second nano-son, an inverse signal of the signal transiting on the second nano-son son controlling the transistor considered.

 A plurality of transistors in the array may form an inverter and / or follower block. More particularly, the transistors connected to the second and fourth nano-wires form an inverter or inverter / follower block.

 The configuration signals may be binary signals.

According to one possibility, the logic cell may comprise K (with K> 1) data inputs and M (with M> 1) configuration signals. In this case, the logic cell may be provided to perform at least one function on 2 ^{M out} of 2 possible functions.

 According to one implementation possibility, the logic cell may comprise 2 data inputs and 4 configuration signals, the cell being designed to perform 16 different Boolean functions.

 According to one particular implementation, the cell can be implemented in dynamic logic, and comprise one or more of said transistors located between at least one pre-charge transistor controlled by a pre-charge signal and at least one evaluation transistor controlled by an evaluation signal.

According to one possibility, the nano-wires may all be doped according to a doping of the same type, by for example, N-type doping, the transistors being N-type transistors.

 The invention further relates to a microelectronic device comprising a plurality of cells as defined above.

 This device may furthermore comprise at least one storage element connected to one or more of said cells, said storage element being formed of another matrix of crossed nano-wires, the matrix comprising transistors formed at the intersection of two nano-wires. .

 According to one possibility, said other matrix of said storage block may be located in the same plane as the nanowire matrix (s) of the cells interconnected with each other.

 The invention also provides a method for producing a logic cell as defined above.

 The invention provides a method of manufacturing a cell as defined above, wherein the formation of the interwoven nano-son matrix comprises steps of:

 depositing, on a support, a first set of parallel nanowires coated with an insulating layer,

 partial removal of the insulating layer,

depositing, on said first set, a second set of parallel nanowires coated with an insulating layer, the nano-wires of the first set being orthogonal to the nano-wires of the first set. BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which:

 FIGS. 1A-1B illustrate an example of a logic block according to the prior art of the type called "nano-block",

 FIG. 2 illustrates an example of a network of a type called "MLA" forming a 2-input NAND gate,

 FIG. 3 illustrates an example of a device according to the prior art, comprising several logic blocks of "nano-block" type,

 FIG. 4 illustrates a version in dynamic logic of an example of a logic cell according to the invention with intersecting nano-wire matrix,

 FIG. 5 illustrates a static version of an example of a logic cell according to the invention with intersecting nano-son matrix and comprising NWFET transistors at the intersection between certain nanowires,

 FIG. 6 illustrates another example of a logic cell according to the invention, with intersecting nanowire matrix and comprising NWFET type N transistors at certain intersections of the matrix,

FIG. 7 illustrates an example of arrangement of interconnect metal tracks of a logic cell according to the invention, with intersecting nano-son matrix,

 FIG. 8 illustrates an example of an array arrangement of logic cells according to the invention, with intersecting nano-wire matrix,

 FIG. 9 illustrates an example of arrangement of interconnecting metal tracks of an array of logic cells according to the invention;

 FIG. 10 illustrates an exemplary matrix arrangement of an array of logic cells according to the invention,

 FIGS. 11A-11B illustrate an exemplary storage element of a device comprising an array of logic cells according to the invention, while FIG. 11C illustrates a dynamic logic implementation of such an element;

 FIGS. 12A-12B and 13 illustrate an example of operation in dynamic logic,

 FIGS. 14A-14F, 15A-15B, and 16A-16F illustrate an exemplary method for producing a matrix of crossed nanowires intended to be integrated in a logic cell according to the invention.

 Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.

The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable. DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

An example of a logic cell according to the invention, with a reconfigurable Boolean logic function, will now be described.

 The cell according to the invention is capable of producing N logical functions (with N an integer greater than 2) different Booleans. Thus a Boolean function selected from N functions can be applied to the data inputs of the cell.

 The selection of this function depends on cell configuration entries. The Boolean function implemented by the cell is set according to the value of its configuration entries.

 According to one example, a cell with 2 data inputs, 4 configuration inputs, is capable of implementing 16 different functions.

 The different functions that this example cell is able to implement, according to its configuration entries, are given in the table below.

FUNCTION binary code carried out on signals of two data inputs A configuration dcba and B

 0000 (0) A + B

0001 (1) 1

0010 (2) A + B

0011 (3) I 0100 (4) A

 0101 (5) 1. B

0110 (6) A + B

0111 (7) B

 1000 (8) B

1001 (9) 0

1010 (10) A. B

1011 (11) 1 + B

1100 (12) A.B

1101 (13) ^~ ΣB

1110 (14) A®B

1111 (15) A®B

Such a cell may be implemented so as to comprise, for example, 4 configuration signals Vb [d], Vb [c], Vb [b], Vb [a], 4 inverted configuration signals Vb [d], Vb [c], Vb [b], Vb [a] as well as two data signals A and B, and two complementary data signals A and B.

The configuration signals, which make it possible to determine the function performed on the data signals, may be binary signals, for example derived from a memory or an external microelectronic device. The microelectronic device for transmitting the configuration signals may for example be made in MOS technology. At the output, a binary Y signal resulting from the desired function is obtained, as well as its complementary Y.

 In the case where this cell is implemented in dynamic logic, at least one precharge transistor Tpre and at least one evaluation transistor Teva may be provided on either side of transistors of the cell (FIGS. 12A-12B).

 In order to implement the dynamic logic version, non-overlapping Seva, Spre clock signals may be provided respectively for controlling the pre-charge (timing Cpre in FIG. 13) and evaluation phases (Ceva chronogram on the figure 13).

 An example of a cell implemented in dynamic logic is given in FIG.

 The cell is formed of a plurality of nano-wires parallel to each other, the nano-wires being perpendicular to other nano-wires of another plurality of nano-wires parallel to each other.

 The intersecting nano-wires form a grid or a mesh or a matrix.

 Transistors are provided at some crossings of the matrix.

 With such an arrangement of nano-wires associated with transistors, it is possible to perform any elementary function of combinatorial logic.

Such an arrangement can also make it possible to make the addressing of a cell, and a interconnection of cells in a network easier than in the devices according to the prior art.

 The transistors may be made of NWFET (NWFET) technology, that is to say comprise a channel portion formed of at least one nanowire and whose conduction is controlled by a gate. . The operation of the nano-son FET transistors as implemented in a logic cell according to the invention can be based on the principle of the divider bridge, the value of the channel resistances of the FET transistors depending on the voltage applied to their gate .

 To reduce the number of nano-wires of the matrix and the multiple need for external signals, a version of the cell in static logic can be provided (Figure 5).

 In the static version of the cell, some transistors, particularly those on which the clock signals are applied, are removed and replaced by pull resistors. The pull resistors can be realized using NWFET components for which the grid voltage is kept constant.

 With such a device, it is possible to invert the outputs Y and Y, by switching the potential applied to polarization lines 51 and 52 biased respectively to a ground potential GND and a supply potential Vdd.

Means provided to deliver a first potential equal for example to GND or Vdd to a line of polarization 51 and to deliver a second potential equal for example to Vdd or GND different from the first potential to another polarization line 52, depending on a selection signal can be so provided.

These means may be in the form of a multiplexer controlled by a selection signal with an input at a logic level ^λ 1 'and another input at a logic level ^λ 0' and two outputs connected respectively to the first polarization line and to the second polarization line.

 According to one variant, these means may be in the form of a set of switching transistors controlled by a selection signal and its complement.

 According to one possibility, the cell can be implemented using a matrix of nanowires of the same doping, the transistors of the matrix being of the same type.

 In the example of FIG. 6, the cell is formed of a plurality of nano-wires 101, a plurality of nano-wires being parallel to each other and perpendicular to another plurality of nano-wires. At certain crossings between nano-wires are made NWFET transistors 102 of type N.

In this example, the cell comprises at least one block 110 performing an inverter and / or follower function, at least one block 120 performing a NAND function, and at least one other block 130 performing a NAND function. The inversion / follower stage 1 1 0, makes it possible to remedy the needs of connectors in the form of nanowires.

 A bias line at a potential Vdd, a ground line GND, means for applying a first pair of clock signals Hpre of pre-load phase control and Heva of control evaluation phases of the horizontal lines of the matrix during evaluation phases, means for applying a second pair of pre-charge phase control Vpre clock signals and evaluation Veva of vertical matrix line evaluation phases during evaluation phases , are also provided.

An example of an arrangement of interconnecting metal lines of such a cell is given in FIG. The dimensions of this cell can be for example of the order of 0. 05 ym ² for the active part 1 05, and for example of the order of 0. 2 9 ym ² in total, including the area occupied by the interconnections.

 A cell as described above can be arranged in a network of interconnected cells.

 In the example of FIG. 8, 1 6 cells 100i, 10012,..., 10021,..., 10022,..., 10031,..., 1004 of an array of cells are represented.

Interconnection means 150 1, 150 ₂ , I 503, formed at a different level or at another stage than logic cells 100 0, 100 12, ..., 10021, ..., 10022, 10031, 1004 reconfigurable are provided. Storage elements, for example in the form of flip-flops 1 60 i, I6O2, I6O3, 1 60 _4, may be provided for outputting the data signals to the logic cells.

 An example of an interconnection of 100 n, 10012,..., 10021,..., 10022, 10031, 10044 interconnecting metallic lines arranged at a stage higher than that of the matrix is given on FIG. figure 9.

 In FIG. 10, an example of a device comprising a matrix network of m * n (with m> 1 and n> 1) cells of the type of that described previously with reference to FIG. 6 is represented.

 A matrix network arrangement makes it possible to limit the interconnection complexity and to limit the space requirement.

 The cells may be associated with memory elements, among which are configuration memories and data memories.

 The configuration memories can be non-volatile and placed in so-called back-end levels immediately above the reconfigurable logic cells.

 As for the data memories, they can be arranged as close to the logical structure as possible and preferably in the same plane as the logic cells.

It is thus possible to provide storage elements in a technology identical to that of the logic cells described above. Storage elements, the dimensions of which are close to the logic cells formed of a nano-son crossing matrix, can be provided.

 An exemplary block diagram of a storage element is given in Figure 11A. This element can be in the form of a flip-flop D and comprises an inverter 210, as well as means 221, 222, 231, 232 forming NAND gates.

 The structure of such a storage element is given in FIG. 11B.

 The structure is formed of nano-son intersecting perpendicular to each other, realizing a matrix of the form of a grid or a mesh.

 At certain intersection points of the grid or the mesh are formed NWFET type transistors. The transistors are arranged to form at least one block 210 forming at least one inverter, at least one other block 220 forming NAND functions, and at least one other block 230 forming NAND functions.

 Since the storage element is also formed of nano-wires, it can be integrated at the same level in the same plane as the logic cell or cells according to the invention. This can facilitate the connections between this storage element and the logic cells.

 A dynamic version by cascade of synchronization stages, can also be provided.

To implement a dynamic version of the given storage element example 12A, buffers 241, 242, 243, as well as non-overlapping and out-of-phase clock signals can be provided (FIG. 11C).

 In either of the examples of cells that have just been given, the FET transistors are created from nano-son crossings.

 Nano-son perpendicular to each other, which may have the same doping, and form a matrix or a mesh, are made to manufacture a logic cell according to the invention.

 The manufacture of nanowires can be carried out for example on a substrate by CVD ("CVD" for "Chemical Vapor Deposition") using gold particles as catalyst.

When the nano-son made are semi ^¬ conductors, can be carried out doping in situ, for example an N-type doping during growth of the latter, for example by including dopants in a flow Silane when nano-son made are based on Si.

 The formed nano-wires may for example have a critical dimension or a diameter of between 1 nanometer and 100 nanometers, for example of the order of 3 nanometers.

 Thereafter, thermal oxidation can be performed to form an oxide layer 303 around the nano-wires 302.

Nano-wires 302 can be detached from the substrate on which they were formed and then deposited on a support 300, so as to be arranged parallel to the support 300 (Figures 14A and 16A).

 The support 300 may for example be formed of a semiconductor substrate covered with an insulating layer, obtained for example by oxidation.

 A first set 301 of parallel nanowires 302, for example by a Langmuir-Blodgett type fluidic alignment method and as described for example in the document "An introduction to ultrathin organic films: from Langmuir Blodgett to self assembly", Academy Press, 1991 can be realized (Figures 15A-15B).

 Partial removal of the oxide layer 303 is then performed on and on each side of the nanowires (FIGS. 14B and 16B).

 The nanowires can then be modified to include areas having semiconductor behavior and areas having conductive behavior.

 For this, a metallization of certain portions of the nano-son can be carried out, for example by deposition of Ni or Pt on the nano-son 302.

 During the deposition, certain parts of the nano-wires 302 can be protected by means of masking, for example based on resin.

Then, this masking is removed for example by a commonly known method of "lift off". Then, thermal annealing, to form NiSi or PtSi zones is performed. An alternation of conductive zones 306 and semiconductor zones 307 can thus be implemented along nano-wires 302 (FIGS. 14C and 16C).

 Then, a second set 311 of nanowires is deposited on the first set, so that the nano-wires of the first set 301 are orthogonal to the nano-wires of the second set 311 (FIGS. 14D and 16D).

 The second set 311 of nanowires 312 may have been obtained using a method similar to that used to form the first set 301 of nano-son 302.

 A semiconductor oxide layer 313 formed around the nano-wires 312 of the second assembly 311 has a controlled thickness to maintain the nano-wires 312 spaced at a controlled spacing.

 Partial removal of the oxide layer 313 is then performed on and on each side of the nano-wires 312 of the second set. Insulating areas beneath the nano-wires of the second set can be retained and subsequently serve as grid dielectric areas.

Then, a metallization of certain portions of some nano-son 312a of the second set 311 of nano-son 312 can be carried out, for example first by depositing Ni or Pt on the nano-son, while others nano-son 312b are protected by a masking 315, for example based on resin. Then, the masking 315 is removed. An annealing step is then carried out in order to form NiSi or PtSi zones on the nanowires (Figure 16E).

 An alternation of conductive zones 316 and semiconductor zones 317 is implemented along the nano-wires (FIG. 14E).

 At certain intersections between nanowires of the two sets, when conductive zones 317 have been formed between nanowires, these conductive zones can act as transistor gates.

 Contact metal areas 320 are then made (FIGS. 14F and 16F).

 Metal interconnection areas of the type shown in FIGS. 8 and 10 can then be realized.

 In FIG. 16F, a NWFET transistor structure is shown and comprises a gate 336 formed of a metallized nano-wire 312a resting on an oxide layer acting as a gate dielectric 335, the gate dielectric resting on a semiconductor region of another nano-wire 302 acting as channel 332. Metallized zones of nano-wire 302 located on either side of channel 332 respectively form a source region 331 and a drain region 333.

Claims

1. Logic cell (100) comprising  a plurality of data inputs (A, B)  a plurality of configuration inputs (Vb [a], Vb [b], Vb [c], Vb [d]) different from the data inputs, the cell being adapted to perform at least one Boolean logic function of its logic inputs, the Boolean logic function applied being parameterized according to the value of said configuration entries;  a crossed nano-son matrix (101) comprising a first plurality of first nano-wires perpendicular to a second plurality of second nano-wires, wherein a subset of the second nano-wires is connected to the data inputs; another subset of the second nanowires being connected to the configuration inputs; and  transistors formed at certain crossings of two nanowires, each transistor being controllable by a signal transiting on a second nano-wire. The logic cell according to claim 1, wherein each first nanowire is connected to at least a second nano-son by a transistor controllable by a signal from a configuration input (Vb [a], Vb [b] , Vb [c], Vb [d]). The logic cell of claim 2, wherein at least a first nano-son is connected to at least a second nano-son by a transistor controllable by a signal from a data input (A, B). The logic cell of claim 1, further comprising two third nano-wires (51, 52) perpendicular to said first plurality of first nano-wires, a transistor being formed at each crossing between a first nano-wire and a third nano -son . 5. The cell of claim 4, wherein the transistors connected to the first and second nano-son form a first block (120) performing a NAND function, the transistors connected to the first and third nano-son forming a second block (130). performing a NAND function. The logic cell according to any of the preceding claims, further comprising a fourth plurality of nano-wires parallel to said first plurality of nano-wires, and wherein at least one inverting transistor is formed at the crossover of a fourth nano-son and a second nano-son, the fourth nano-son hosting the transistor considered being further connected to another second nano-son to provide, on this other second nano-son, a signal reverse signal transiting on the second nano-son controlling the transistor considered. 7. The cell of claim 6, wherein the transistors connected to the second and fourth nano-son form an inverter block (110) or inverter / follower. The logic cell of any one of the preceding claims, wherein the configuration signals are binary. A logic cell according to any one of the preceding claims, wherein the logic cell comprises K (with K> 1) data inputs and M (with M> 1) configuration signals, the logic cell being adapted to perform minus one function on 2 ^M out of 2 functions. 10. Logic cell according to the claim 9, comprising two data inputs and four configuration signals, the cell being arranged to perform sixteen different Boolean functions. The logic cell according to any of the preceding claims, wherein the cell is a dynamic logic cell, one or more of said transistors being located between a pre-charge transistor (Tpre) controlled by a pre-charge signal (Hpre). , Vpre) and a transistor of evaluation (Teva) controlled by at least one evaluation signal (Heva, Veva). 12. Cell according to any one of the preceding claims, said nano-son having an N-type doping, the transistors being N-type transistors. 13. Microelectronic device comprising a plurality of cells according to any one of claims 1 to 12, interconnected between them. The microelectronic device according to claim 13, further comprising at least one storage element connected to one or more of said cells, said storage element being formed of another matrix of crossed nano-wires, the matrix comprising transistors formed at crossing of two nano-wires. 15. Microelectronic device according to claim 14, said other matrix of said storage block being located in the same plane as the nano-son matrix (s) of the interconnected cells. 16. The method of manufacturing a cell according to one of claims 1 to 12, wherein the formation of the interwoven nano-son matrix comprises steps of: depositing, on a support, a first set of parallel nanowires coated with an insulating layer,  - Partial removal of the insulating layer - Deposit on said first set of a second set of parallel nanowires coated with an insulating layer, the nano-son of the first set being orthogonal to the nano-son of the first set.