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WO2010137169A1 - Dispositif de mémoire non volatile à semi-conducteur, et procédé pour écrire dans celui-ci - Google Patents

Dispositif de mémoire non volatile à semi-conducteur, et procédé pour écrire dans celui-ci Download PDF

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Publication number
WO2010137169A1
WO2010137169A1 PCT/JP2009/059900 JP2009059900W WO2010137169A1 WO 2010137169 A1 WO2010137169 A1 WO 2010137169A1 JP 2009059900 W JP2009059900 W JP 2009059900W WO 2010137169 A1 WO2010137169 A1 WO 2010137169A1
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WIPO (PCT)
Prior art keywords
memory cell
transistor
source
potential
voltage
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English (en)
Japanese (ja)
Inventor
智史 鳥井
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Priority to PCT/JP2009/059900 priority Critical patent/WO2010137169A1/fr
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Definitions

  • the present invention relates to a nonvolatile semiconductor memory device and a writing method thereof.
  • nonvolatile semiconductor memory devices have been used. Since the nonvolatile semiconductor memory device does not need a refresh process for rewriting the written information at a constant cycle, unlike the volatile semiconductor memory device, even if power is not supplied to the nonvolatile semiconductor memory device, The written state is maintained.
  • FIG. 1 shows a memory cell array of a nonvolatile semiconductor memory device according to a conventional example.
  • FIG. 2 is a diagram for explaining writing to the nonvolatile semiconductor memory device of FIG.
  • a plurality of memory cells MC each having a memory cell transistor MT and a selection transistor ST are arranged in a matrix.
  • the memory cell transistor MT and the selection transistor ST are NMOS transistors.
  • the memory cell transistor MT is formed by sequentially stacking a tunnel insulating film TI, a floating gate FG, and a control gate CG on the substrate SUB.
  • the select transistor ST is formed by stacking a gate insulating film GI and a select gate SG on the substrate SUB.
  • FIG. 1 and FIG. 2 show the voltage of each signal line when writing is performed to the selected cell MC (SELECT) in the erased state in the memory cell array.
  • the write selection voltage 6V is applied to the control gate CG of the memory cell transistor MT of the selected cell MC (SELECT) by the first word line WL1.
  • the voltage Vcc is applied to the select gate SG of the select transistor ST of the selected cell MC (SELECT) by the second word line WL2.
  • a voltage of 5.5 V is applied to the source of the memory cell transistor MT of the selected cell MC (SELECT) through the source line SL.
  • the drain of the selection transistor ST of the selection cell MC (SELECT) is grounded by the bit line BL.
  • a source line SL connected to the source of the memory cell transistor MT of the selected cell MC (SELECT) and a non-selected cell MC (SL) whose sources are commonly connected are arranged.
  • the non-selected cell MC (SL) is in a write state
  • the floating gate FG of the memory cell transistor MT of the non-selected cell MC (SL) is in a state where electrons are injected.
  • control gate CG of the memory cell transistor MT of the unselected cell MC is commonly connected to the control gate CG of the memory cell transistor MT of the selected cell MC (SELECT). Absent.
  • the control gate CG of the non-selected cell MC (SL) is connected to the first word line WL1 different from the line connected to the selected cell MC (SELECT) .
  • the select gate SG of the selection transistor ST of the non-selected cell MC is connected to a second word line WL2 different from the line connected to the selected cell MC (SELECT) .
  • the control gate CG of the memory cell transistor MT of the non-selected cell MC (SL) is grounded by the first word line WL1.
  • the select gate SG of the select transistor ST of the non-selected cell MC (SL) is grounded by the second word line WL2. Further, the drain of the selection transistor ST of the non-selected cell MC (SL) is grounded by the bit line BL.
  • the voltage Vcc is applied to the bit line BL of the memory cell in the column adjacent to the selected cell MC (SELECT) .
  • the memory cell transistor MT of the unselected cell MC (SL) commonly connected to the source line SL has the control gate CG grounded, and the source is positively connected by the source line SL. A voltage of 5.5V is applied.
  • a high negative voltage is applied to the surface of the substrate SUB near the gate by the floating gate FG into which electrons e ⁇ are injected.
  • a high positive voltage is applied to the surface of the substrate SUB near the source by the source line SL.
  • the potential of the source diffusion layer is sufficiently higher than the gate potential.
  • the expansion of the depletion layer that tends to extend from the source diffusion layer is suppressed by the gate potential.
  • electron e ⁇ / hole h + pairs may be generated. Then, as shown in FIG. 3, some holes h + with sufficient energy may become hot holes and be trapped by the tunnel insulating film TI across the potential energy barrier.
  • a defect may occur in which the unselected cell MC (SL) changes from the erased state to the written state.
  • a technique for preventing a failure from occurring in the storage state of an unselected cell is disclosed.
  • a nonvolatile semiconductor memory device including a memory cell having a memory cell transistor and a selection transistor a method for preventing the storage state of a non-selected cell from changing at the time of writing to the selected cell is still disclosed.
  • a selection transistor that is an NMOS transistor and a memory cell transistor that is an NMOS transistor connected to the selection transistor are provided.
  • a memory cell array having a plurality of memory cells arranged in a matrix, and a first word line extending in the row direction commonly connecting the control gates of the plurality of memory cell transistors existing in the same row, A second word line extending in the row direction commonly connecting select gates of the plurality of selection transistors existing in a row, and sources of the plurality of memory cell transistors existing in two adjacent rows or two columns.
  • the source line connected to the source of the memory cell transistor of the selected memory cell is connected in common, and the source of the memory cell transistor of the selected memory cell is connected.
  • a positive voltage is applied to the control gates of the memory cell transistors of the memory cells that are not commonly connected to the first word line connected to the control gate.
  • a selection transistor that is an NMOS transistor and a memory cell that is an NMOS transistor connected to the selection transistor
  • a second word line extending in the row direction commonly connecting select gates of the plurality of selection transistors present in the same row, and a plurality of the memory cell transistors existing in two rows or two columns adjacent to each other
  • the source line and the source to be connected are connected in common, and the first word line connected to the control gate of the memory transistor of the selected memory cell is not commonly connected to the control gate.
  • a positive voltage is applied to the control
  • a change in the storage state of the non-selected cell is prevented when writing to the selected cell.
  • FIG. 2 is a diagram for explaining writing to the memory cell array of FIG. 1. It is a figure from which an electron escapes from the floating gate of a non-selected cell. It is a figure by which an electron is inject
  • 1 is a circuit diagram illustrating a nonvolatile semiconductor memory device according to a first embodiment.
  • FIG. It is a figure explaining a 1st row decoder. It is a figure explaining a positive voltage generation circuit.
  • 1 is a plan view showing a memory cell array of a nonvolatile semiconductor memory device according to a first embodiment.
  • FIG. 1 is a plan view showing a memory cell array of a nonvolatile semiconductor memory device according to a first embodiment.
  • FIG. 9 is a cross-sectional view taken along the line AA ′ of FIG.
  • FIG. 9 is a sectional view taken along the line BB ′ of FIG.
  • FIG. 9 is a cross-sectional view taken along the line CC ′ of FIG.
  • 3 is a time chart illustrating a writing method of the nonvolatile semiconductor memory device according to the first embodiment. It is a circuit diagram which shows the non-volatile semiconductor memory device of 2nd Embodiment.
  • FIG. 6 is a process cross-sectional view (part 1) illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment; FIG.
  • FIG. 6 is a process cross-sectional view (part 2) illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment
  • FIG. 9 is a process cross-sectional view (part 3) illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment
  • FIG. 9 is a process cross-sectional view (part 4) illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment
  • FIG. 9 is a process cross-sectional view (part 5) illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment
  • FIG. 6 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the nonvolatile semiconductor memory device in the first embodiment.
  • FIG. 5 is a circuit diagram showing the nonvolatile semiconductor memory device of this embodiment.
  • a memory cell MC is formed by a select transistor ST and a memory cell transistor MT connected to the select transistor ST.
  • the source of the selection transistor ST is connected to the drain of the memory cell transistor MT. More specifically, the source of the selection transistor ST and the drain of the memory cell transistor MT are integrally formed by one impurity diffusion layer.
  • the memory cell transistor MT and the selection transistor ST are NMOS transistors.
  • the plurality of memory cells MC are arranged in a matrix.
  • a memory cell array 10 is formed by a plurality of memory cells MC arranged in a matrix.
  • the memory cell array 10 has a first word line WL1 extending in the row direction commonly connecting control gates of a plurality of memory cell transistors MT existing in the same row.
  • the first word line WL1 is connected to the first row decoder Dr1.
  • the first row decoder Dr1 is for controlling the potentials of the plurality of first word lines WL1 that commonly connect the control gates of the memory cell transistors MT.
  • the memory cell array 10 includes a second word line WL2 extending in the row direction for commonly connecting select gates of a plurality of select transistors ST existing in the same row.
  • the memory cell array 10 has a bit line BL extending in the column direction commonly connecting the drains of a plurality of select transistors ST present in the same column.
  • the first word line WL1 and the second word line WL2 are provided so as to intersect the bit line BL.
  • the first word line WL1 and the second word line WL2 are provided in parallel.
  • the nonvolatile semiconductor memory device of this embodiment includes a plurality of sets of the first word lines WL1 and the second word lines WL2 extending in the row direction and a plurality of bit lines BL extending in the column direction.
  • the memory cell MC is disposed at the intersection of each set of the first word line WL1 and the second word line WL2 and the bit line BL.
  • the memory cell array 10 has a source line SL for commonly connecting the sources of a plurality of memory cell transistors MT existing in two adjacent rows.
  • the source line SL extends in the row direction by commonly connecting the sources of a plurality of memory cell transistors MT existing in the same row.
  • a plurality of memory cells MCn are arranged in the nth row of the memory cell array 10.
  • a plurality of memory cells MCn + 1 are arranged in the n + 1th row of the memory cell array 10.
  • a plurality of memory cells MC n + 2 are arranged in the ( n + 2) th row of the memory cell array 10.
  • a plurality of memory cells MC n + 3 are arranged in the ( n + 3) th row of the memory cell array 10.
  • a plurality of memory cells MC n + m are arranged in the ( n + m) th row of the memory cell array 10.
  • the source of the memory cell transistor MT of the n- th row memory cell MC n and the source of the memory cell transistor MT of the n + 1-th row memory cell MC n + 1 are connected by a common source line SL.
  • the source of the memory cell transistor MT of the memory cell MC n + 2 in the n + 2 row and the source of the memory cell transistor MT of the memory cell MC n + 3 in the n + 3 row are connected by a common source line SL. Yes.
  • the source line SL and the bit line BL are provided so as to intersect.
  • the nonvolatile semiconductor memory device of this embodiment prevents a change in the storage state of a non-selected cell that is not selected for writing when writing to a memory cell selected for writing.
  • the memory cell MC (SELECT) is selected as the memory cell to be written.
  • the memory cell MC (SELECT) selected for writing is hereinafter also referred to as a selected cell MC (SELECT) .
  • the source line SL connected to the source of the memory cell transistors MT of the selected cell MC (SELECT)
  • the write voltage Vsl is applied.
  • non-selected cells MC SL
  • non-selected cells MC that are not selected for writing are connected as source cells SL connected to the source of the memory cell transistor MT of the selected cell MC (SELECT).
  • SELECT the source of the memory cell transistor MT of the selected cell MC
  • ADJACENT There is a selected cell MC (ADJACENT) .
  • the memory cell transistor MT of the non-selected cells MC (SL), the first word line WL1 and the control gate to be connected to the control gate of the memory cell transistors MT of the selected cell MC (SELECT) is not commonly connected.
  • the memory cell transistor MT of the non-selected cell MC is commonly connected to the first word line WL1 connected to the control gate of the memory cell transistor MT of the selected cell MC (SELECT) .
  • a write selection voltage which is a positive voltage is applied to the control gate of the memory cell transistor MT of the selected cell MC (SELECT) , and the memory cell transistor MT is turned on. .
  • the write selection voltage is applied to the control gate of the memory cell transistor MT of the non-selected cell MC (ADJACENT) by the same first word line WL1.
  • the source line SL connected to the source of the memory cell transistor MT of the selected cell MC (SELECT) and the non-selected cell MC (SL) connected in common are connected. Similarly, changes in the memory state are prevented.
  • the nonvolatile semiconductor memory device of this embodiment has a positive voltage generation circuit ViG for applying a positive voltage Vi to the control gate of the memory cell transistor MT of the non-selected cell MC (SL) .
  • the nonvolatile semiconductor memory device of this embodiment has a control circuit CC to which the positive voltage Vi generated by the positive voltage generation circuit ViG is supplied.
  • the positive voltage generation circuit ViG supplies the generated positive voltage Vi to the first row decoder Dr1 via the control circuit CC.
  • the timing at which the positive voltage Vi is supplied to the first row decoder Dr1 by the positive voltage generation circuit ViG is controlled by the control circuit CC.
  • the first row decoder Dr1 applies the positive voltage Vi supplied from the positive voltage generation circuit ViG to the control gate of the memory cell transistor MT of the non-selected cell MC (SL) via the first word line WL1. .
  • the selection transistor ST of the non-selected cell MC (SL) is turned off.
  • the selection transistor ST even if the memory cell transistor MT of the non-selected cell MC (SL) to which the positive voltage Vi is applied is turned on, writing to the memory cell transistor MT is prevented. .
  • the positive voltage Vi applied to the control gate of the memory cell transistor MT which is an NMOS transistor is a voltage in a direction in which an inversion layer is generated on the silicon surface below the control gate with respect to the well (see reference numeral 26 in FIG. 9).
  • the value of the positive voltage Vi when not less than the threshold value for the memory cell transistors MT of the memory cells MC in the erased state to the ON state, the selected cell MC (SELECT) is written, the non-selected cells MC (SL) Is preferable for sufficiently preventing the generation of electron e--hole h + pairs due to band-to-band tunneling.
  • the value of the positive voltage Vi may be the value of the power supply voltage Vcc.
  • the power supply voltage Vcc is supplied to the control circuit CC without using the positive voltage generation circuit, and the power supply voltage Vcc is supplied from the control circuit CC to the first row decoder Dr1.
  • the value of the positive voltage Vi may be a value of a verification voltage used for verifying the write state of the memory cell transistor MT in which the write has been performed.
  • the potential of the first word line WL1 is set to the verification voltage (verification voltage) by the first row decoder Dr1 without using the positive voltage generation circuit and the control circuit CC.
  • the first row decoder Dr1 has a multi-stage inverter.
  • the final-stage inverter Inv-F is connected to the first word line WL1.
  • FIG. 6 shows only the final-stage inverter Inv-F connected to one first word line WL1, but actually, the final-stage inverter Inv-F connected to each first word line WL1 is shown.
  • An inverter Inv-F is arranged.
  • the write selection voltage Vpp is applied to one end of the final stage inverter Inv-F. Further, the positive voltage Vi or 0 V (ground) is applied to the other end of the inverter Inv-F at the final stage by the control circuit CC.
  • the control circuit CC supplies a positive voltage Vi or 0 V to the other end of each final stage inverter Inv-F.
  • the final-stage inverter Inv-F is connected to the final-stage inverter Inv-F via the node A.
  • the inverter Inv-preF outputs a low-level signal via the node A to the final-stage inverter Inv-F connected to the selected cell MC selected for writing.
  • the inverter Inv-preF outputs a high-level signal via the node A to the final-stage inverter Inv-F connected to the unselected cell MC that is not selected for writing.
  • the final-stage inverter Inv-F to which a low level signal is input from the node A, sets the potential of the first word line WL1 to be connected to the write selection voltage Vpp.
  • the final-stage inverter Inv-F that receives a high-level signal from the node A sets the potential of the first word line WL1 to be connected to the positive voltage Vi or 0 V (ground).
  • the inverter Inv-F in the final stage switches the potential of the first word line WL1 to the write selection voltage Vpp, the positive voltage Vi, or 0V.
  • the write selection voltage Vpp is applied to the control gate CG of the memory cell transistor MT of the selected cell MC selected for writing.
  • a positive voltage Vi or 0 V is applied to the control gate CG of the memory cell transistor MT of the unselected cell MC that is not selected for writing.
  • FIG. 7 is a diagram for explaining the positive voltage generation circuit ViG.
  • the positive voltage generation circuit ViG includes resistors R1 and R2 that divide the input write selection voltage Vpp, PMOS transistors MP1 and MP2, and NMOS transistors MN1 to MN3.
  • the positive voltage generation circuit ViG outputs a positive voltage Vi.
  • the input write selection voltage Vpp is divided by the dividing resistors R1 and R2, and the reference potential Vdiv is determined.
  • the reference potential Vdiv determines the gate voltage Vgs (MP1) of the PMOS transistor MP1.
  • the PMOS transistor MP1 supplies a drain current Ids (MP1) corresponding to the gate voltage Vgs (MP1) to the NMOS transistors MN1 and MN2.
  • the NMOS transistors MN1 and MN2 generate the gate voltage Vgs (MN3) of the NMOS transistor MN3 determined by the drain current Ids (MP1).
  • the NMOS transistor MN3 is supplied with the drain current Ids (MN3) determined by the gate voltage Vgs (MN3) from the PMOS transistor MP2.
  • the PMOS transistor MP2 outputs its gate voltage Vgs (MP2) determined by the drain current Ids (MN3) as a positive voltage Vi.
  • the positive voltage Vi generated by the positive voltage generation circuit ViG is supplied to the first row decoder Dr1 via the control circuit CC.
  • control circuit CC will be described in further detail below.
  • the value of the voltage supplied to the first row decoder Dr1 at the time of writing to the selected cell differs depending on the type of the memory cell MC connected to the inverter Inv-F at the final stage for supplying power.
  • the control circuit CC supplies the positive voltage Vi to the final-stage inverter Inv-F.
  • control circuit CC supplies the positive voltage Vi to the final stage inverter Inv-F.
  • control circuit CC supplies 0 V to the final stage inverter Inv-F.
  • the first row decoder Dr1 is formed by a high voltage circuit (high voltage circuit).
  • a high voltage circuit is a circuit having a relatively low operating speed and a relatively high breakdown voltage.
  • a gate insulating film (not shown) of a transistor (not shown) of the high voltage circuit is formed relatively thick in order to ensure a sufficient breakdown voltage. For this reason, the operation speed of the transistor of the high voltage circuit is lower than that of the transistor of the low voltage circuit.
  • the high voltage circuit is used for the first row decoder Dr1 because the first word decoder 1 is used when information is written in the memory cell transistor MT or when information written in the memory cell transistor MT is erased. This is because a high voltage needs to be applied to the line WL1.
  • the plurality of second word lines WL2 that commonly connect the select gates of the select transistors ST are connected to the second row decoder Dr2.
  • the second row decoder Dr2 is for controlling the potentials of the plurality of second word lines WL2 that commonly connect the select gates of the select transistors ST.
  • the second row decoder Dr2 is formed by a low voltage circuit (low withstand voltage circuit). The reason why the low voltage circuit is used for the second row decoder Dr2 in this embodiment is that it is not necessary to apply a high voltage to the select gate of the select transistor ST, but it is important to operate the select transistor ST at high speed. This is because of this. In the present embodiment, since a low voltage circuit is used for the second row decoder 18, the select transistor ST can be operated at a relatively high speed, and thus a non-volatile semiconductor memory device having a high read speed is provided. Is possible.
  • a plurality of bit lines BL commonly connecting the drains of the selection transistors ST are connected to the column decoder Dc.
  • the column decoder Dc is for controlling the potentials of a plurality of bit lines BL that commonly connect the drains of the selection transistors ST.
  • a sense amplifier SA for detecting a current flowing through the bit line BL is connected to the column decoder Dc.
  • the column decoder Dc is formed by a low voltage circuit that operates at a relatively low voltage.
  • the low voltage circuit is a circuit that can operate at high speed while having a relatively low withstand voltage.
  • a gate insulating film (not shown) of a transistor (not shown) of the low voltage circuit is formed relatively thin.
  • the transistors of the low voltage circuit used in the column decoder Dc can operate at a relatively high speed.
  • the reason why the low voltage circuit is used for the column decoder Dc in the present embodiment is that it is not necessary to apply a high voltage to the drain of the selection transistor ST, while the selection transistor is read when information written in the memory cell transistor MT is read. This is because it is necessary to operate the ST at high speed.
  • the select transistor ST since a low voltage circuit is used for the column decoder Dc, the select transistor ST can be operated at a relatively high speed, and as a result, it is possible to provide a nonvolatile semiconductor memory device with a high read speed. Become.
  • a plurality of source lines SL that commonly connect the sources of the memory cell transistors MT are connected to the third row decoder Dr3.
  • the third row decoder Dr3 is for controlling the potentials of the plurality of source lines SL that commonly connect the sources of the memory cell transistors MT.
  • the third row decoder Dr3 is formed by a high voltage circuit (high voltage circuit). The reason why the high voltage circuit is used for the third row decoder Dr3 in the present embodiment is that a high voltage needs to be applied to the source line SL when information is written to the memory cell transistor MT. As will be described later, when reading information written in the memory cell transistor MT, the source line SL is always grounded.
  • FIG. 8 is a plan view of the memory cell array of the nonvolatile semiconductor memory device according to the present embodiment.
  • FIG. 9 is a cross-sectional view taken along the line AA ′ of FIG. 10 is a cross-sectional view taken along the line BB ′ of FIG.
  • FIG. 11 is a sectional view taken along the line CC ′ of FIG.
  • An element isolation region 22 that defines an element region 21 is formed in the semiconductor substrate 20.
  • the semiconductor substrate 20 for example, a P-type silicon substrate is used.
  • the element isolation region 22 is formed by, for example, an STI (Shallow Trench Isolation) method.
  • N-type buried diffusion layer 24 is formed in the semiconductor substrate 20 on which the element isolation region 22 is formed.
  • the upper portion of the N type buried diffusion layer 24 is a P type well 26.
  • a floating gate 30a is formed on the semiconductor substrate 20 via a tunnel insulating film 28a.
  • the floating gate 30 a is electrically isolated for each element region 21.
  • a control gate 34a is formed on the floating gate 30a via an insulating film 32a.
  • the control gates 34a of the memory cell transistors MT existing in the same row are commonly connected.
  • the first word line WL1 that commonly connects the control gates 34a via the insulating film 32 is formed on the floating gate 30.
  • a select gate 30b of the select transistor ST is formed on the semiconductor substrate 20 in parallel with the floating gate 30a.
  • the select gates 30b of the select transistors ST existing in the same row are connected in common.
  • the second word line WL2 that commonly connects the select gates 30b is formed on the semiconductor substrate 20 via the gate insulating film 28b.
  • the thickness of the gate insulating film 28b of the selection transistor ST is equal to the thickness of the tunnel insulating film 28a of the memory cell transistor MT.
  • a polysilicon layer 34b is formed on the select gate 30b via an insulating film 32b.
  • N-type impurity diffusion layers 36a, 36b, and 36c are formed in the semiconductor substrate 20 on both sides of the floating gate 30a and in the semiconductor substrate 20 on both sides of the select gate 30b.
  • the impurity diffusion layer 36b that forms the drain of the memory cell transistor MT and the impurity diffusion layer 36b that forms the source of the selection transistor ST are formed of the same impurity diffusion layer 36b.
  • a sidewall insulating film 37 is formed on the side wall portion of the stacked body having the floating gate 30a and the control gate 34a.
  • a sidewall insulating film 37 is formed on the side wall portion of the stacked body having the select gate 30b and the polysilicon layer 34b.
  • silicide layers 38a to 38d made of, for example, cobalt silicide are respectively provided. Is formed.
  • the silicide layer 38a on the source electrode 36a functions as a source electrode.
  • the silicide layer 38c on the drain electrode 36c functions as a drain electrode.
  • the memory cell transistor MT having the floating gate 30a, the control gate 34a, and the source / drain diffusion layers 36a and 36b is formed.
  • a select transistor ST having a select gate 30b and source / drain diffusion layers 36b and 36c is formed.
  • the selection transistor ST is an NMOS transistor.
  • an NMOS transistor having a higher operation speed than the PMOS transistor is used as the selection transistor, which can contribute to an improvement in the operation speed.
  • an interlayer insulating film 40 formed of a silicon nitride film (not shown) and a silicon oxide film (not shown) is formed on the semiconductor substrate 20 on which the memory cell transistor MT and the select transistor ST are formed.
  • contact holes 42 reaching the source electrode 38a and the drain electrode 38b are formed.
  • a conductor plug 44 made of, for example, tungsten is embedded in the contact hole 42.
  • a wiring (first metal wiring layer) 46 is formed on the interlayer insulating film 40 in which the conductor plugs 44 are embedded.
  • An interlayer insulating film 48 is formed on the interlayer insulating film 40 on which the wiring 46 is formed.
  • a contact hole 50 reaching the wiring 46 is formed in the interlayer insulating film 48.
  • a conductor plug 52 made of, for example, tungsten is embedded in the contact hole 50.
  • a wiring (second metal wiring layer) 54 is formed on the interlayer insulating film 48 in which the conductor plug 52 is embedded.
  • An interlayer insulating film 56 is formed on the interlayer insulating film 48 on which the wiring 54 is formed.
  • a conductor plug 60 made of, for example, tungsten is embedded in the contact hole 58.
  • a wiring (third metal wiring layer) 62 is formed on the interlayer insulating film 56 in which the conductor plug 60 is embedded.
  • the memory cell array 10 (see FIG. 5) of the nonvolatile semiconductor memory device according to the present embodiment is formed.
  • FIG. 12 is a diagram illustrating a writing method, a reading method, and an erasing method of the nonvolatile semiconductor memory device according to the present embodiment.
  • F indicates floating.
  • the parentheses indicate the potential of the non-selected line.
  • the address of the memory cell (selected cell) MC (SELECT) to be selected is determined.
  • the potential of the second word line WL2 (SELECT) connected to the selected cell MC (SELECT ) is set to Vcc (first potential) by the second row decoder Dr2.
  • the potential of the second word line WL2 other than the selected second word line WL2 (SELECT) is set to 0 V (grounded) by the second row decoder Dr2. ).
  • the potential of the selected bit line BL (SELECT) connected to the drain of the selection transistor ST of the selected cell MC (SELECT) is set to 0 V (ground) by the column decoder Dc.
  • the potentials of the non-selected bit lines BL other than the selected bit line BL are set to Vcc (second potential) by the column decoder Dc.
  • the potential of the first word line WL1 (SELECT) connected to the selected cell MC (SELECT) is set to the positive voltage Vi by the first row decoder Dr1. Further, the potential of the first word line WL1 (ADJACENT) (adjacent WL1) connected to the non-selected cell MC (SL) is set to the positive voltage Vi by the first row decoder Dr1.
  • the final next stage inverter Inv-preF in the first row decoder Dr1 in the write selection standby state always outputs a high level signal to the final stage inverter Inv-F via the node A. Therefore, when the control circuit CC outputs the positive voltage Vi to the first row decoder Dr1 in the write selection standby state, the final-stage inverter Inv-F causes the first word lines WL1 (SELECT) and WL1 (ADJACENT ) Is a positive voltage Vi.
  • the positive voltage Vi is applied by the first row decoder Dr1 to the control gates of the memory cell transistors MT of the selected cell MC (SELECT) and the non-selected cell MC (SL) .
  • the potential of the first word line WL1 connected to the other non-selected cells MC is set to 0 V by the first row decoder Dr1.
  • the potential of the first word line WL1 (SELECT) connected to the selected cell MC (SELECT ) is set to the write selection voltage Vpp (third potential) by the first row decoder Dr1.
  • Vpp write selection voltage
  • the potential of the selected first word line WL1 (SELECT) is higher than the potential of a selected source line SL (SELECT) described later.
  • the potential of the first word line WL1 (ADJACENT) connected to the non-selected cell MC (SL) remains the positive voltage Vi.
  • the potential of the source line SL (SELECT) connected to the selected cell MC is set to the write voltage Vsl by the third row decoder Dr3.
  • the write voltage Vsl can be set to, for example, 5.5V.
  • the potentials of the source lines SL other than the selected source line SL (SELECT) that is, the potentials of the unselected source lines SL are set to 0 V (ground).
  • the write voltage Vsl is applied to the memory cell transistors MT of the selected cell MC (SELECT) Is written.
  • the positive voltage Vi is applied to the control gate of the memory cell transistor MT of the non-selected cell MC (SL) for at least a predetermined time by the first row decoder Dr1.
  • the positive voltage Vi is applied at least 10 nsec before the application of the write voltage Vsl.
  • the selected cell MC (SELECT) When the selected cell MC (SELECT) is written, the memory state of the non-selected cell MC (SL) changes. It is preferable to prevent this. In this way, even when the write voltage Vsl rises, hot holes are reliably prevented from being captured by the tunnel insulating film TI with respect to the non-selected cell MC (SL) .
  • the time T1 between the start time of application of the positive voltage Vi and the start time of application of the write voltage Vsl is preferably 10 nsec to 1 ⁇ sec.
  • the positive voltage Vi may be applied for at least 10 nsec after the end of application of the write voltage Vsl.
  • the positive voltage Vi is applied between the bands in the unselected cell MC (SL) . This is preferable for preventing generation of electron e ⁇ / hole h + pairs due to tunneling. In this way, even when the write voltage Vsl falls, hot holes are reliably prevented from being trapped by the tunnel insulating film TI with respect to the non-selected cells MC (SL) .
  • the time T2 between the end of application of the positive voltage Vi and the end of application of the write voltage Vsl is preferably 10 nsec to 1 ⁇ sec.
  • the memory state is prevented from changing for the selected source line SL (SELECT) and the non-selected cell MC (SL) whose sources are connected in common. .
  • a positive voltage Vi is applied to the control gate of the memory cell transistor MT of the non-selected cell MC (SL) .
  • the memory cell transistor MT may be turned on.
  • the second word line WL2 potential of the non-selected and 0V since the selection transistors ST of the non-selected cells MC (SL) is in the off state, the memory cell transistor MT of the non-selected cells MC (SL) Is prevented from being written to.
  • each memory cell MC existing in the same row as the non-selected cells MC n and MC n + 1 not selected for writing, the potential of the source line SL to be connected is set to 0 V and the first connected memory cell MC is connected.
  • the potential of one word line WL1 is also set to 0V. Therefore, in these non-selected cells, there is no possibility of generating electron e--hole h + pairs due to band-to-band tunneling when writing to the selected cell MC (SELECT) . There is no fear of being captured by
  • the potential of each part is set as follows. That is, the potential of the bit line BL connected to the memory cell MCn to be selected is set to Vcc. On the other hand, the potentials of the bit lines BL other than the selected bit line are set to 0V. The potentials of the source lines SL are all 0V. The potential of the first word line WL1 is always Vcc during read standby. The potential of the second word line WL2 connected to the memory cell MCn to be selected is set to Vcc. On the other hand, the potentials of the second word lines WL2 other than the selected second word line WL2 are set to 0V. The potentials of the well Well (see reference numeral 26 in FIG.
  • the potential of the bit line BL is Information written in the memory cell transistor MT can be read only by controlling the potential of the second word line WL2.
  • the column decoder Dc for controlling the potential of the bit line BL is formed by the low voltage circuit as described above, the bit line BL is controlled at high speed.
  • the second row decoder Dr2 for controlling the potential of the second word line WL2 is formed by the low voltage circuit as described above, the second word line WL2 is controlled at high speed. Therefore, according to the present embodiment, information written in the memory cell transistor MT can be read at high speed.
  • the potential of each part is set as follows. That is, the potentials of the bit lines BL are all floating. The potentials of the source lines SL are all floating.
  • the potential of the first word line WL1 is set to, for example, ⁇ 9 V by the first row decoder Dr1.
  • the potential of the second word line WL2 is all floated by the second row decoder Dr2.
  • the potential of the well Well (see reference numeral 26 in FIG. 9) is, for example, + 9V.
  • nonvolatile semiconductor memory device of this embodiment it is possible to reliably prevent the storage state of the non-selected cell MC (SL) from changing when the selected cell MC (SELECT) is written.
  • the column decoder Dc for controlling the potential of the bit line BL that commonly connects the drains 36c of the selection transistors ST is formed by a low voltage circuit capable of high-speed operation.
  • the second row decoder Dr2 for controlling the potential of the second word line WL2 that commonly connects the select gates 30b of the select transistors ST is formed by a low voltage circuit capable of high speed operation.
  • the source line SL commonly connecting the sources 36a of the memory cell transistors MT is controlled by the column decoder Dc.
  • the bit line BL, the second word line WL2, and the source line can be controlled at high speed. That is, the information written in the memory cell transistor MT can be read at high speed.
  • the selection transistor ST is formed of an NMOS transistor, it is possible to contribute to an increase in operation speed as compared with the case where the selection transistor is formed of a PMOS transistor.
  • the areas of the memory cell array 10 can be reduced, and the nonvolatile semiconductor This can contribute to downsizing of the storage device.
  • the structure of the third row decoder Dr3 is simplified.
  • FIG. 14 is a circuit diagram showing the nonvolatile semiconductor memory device of this embodiment.
  • a memory cell MC is formed by a select transistor ST and a memory cell transistor MT connected to the select transistor ST.
  • the source of the selection transistor ST is connected to the drain of the memory cell transistor MT. More specifically, the source of the selection transistor ST and the drain of the memory cell transistor MT are integrally formed by one impurity diffusion layer.
  • the memory cell transistor MT and the selection transistor ST are NMOS transistors.
  • the plurality of memory cells MC are arranged in a matrix.
  • a memory cell array 10 is formed by a plurality of memory cells MC arranged in a matrix.
  • the memory cell array 10 has a first word line WL1 extending in the row direction commonly connecting control gates of a plurality of memory cell transistors MT existing in the same row.
  • the first word line WL1 is connected to the first row decoder Dr1.
  • the first row decoder Dr1 is for controlling the potentials of the plurality of first word lines WL1 that commonly connect the control gates of the memory cell transistors MT.
  • the memory cell array 10 includes a second word line WL2 extending in the row direction for commonly connecting select gates of a plurality of select transistors ST existing in the same row.
  • the memory cell array 10 has a bit line BL extending in the column direction commonly connecting the drains of a plurality of select transistors ST present in two adjacent columns. Further, the bit line BL commonly connects the drains of a plurality of memory cell transistors MT existing in the same column.
  • the memory cell array 10 has a source line SL that commonly connects sources of a plurality of memory cell transistors MT existing in two adjacent rows.
  • the source line SL extends in the column direction by commonly connecting sources of a plurality of memory cell transistors MT existing in two adjacent columns.
  • the source line SL commonly connects the sources of a plurality of memory cell transistors MT existing in the same column.
  • the source line SL and the bit line BL are alternately provided.
  • the source line SL and the bit line BL are provided in parallel.
  • the first word line WL1 and the second word line WL2 are provided so as to intersect the source line SL and the bit line BL.
  • the first word line WL1 and the second word line WL2 are provided in parallel.
  • the nonvolatile semiconductor memory device of this embodiment includes a plurality of sets of first word lines WL1 and second word lines WL2 extending in the row direction, a plurality of bit lines BL extending in the column direction, and a plurality of bit lines BL.
  • the memory cell MC is disposed at the intersection of each set of the first word line WL1 and the second word line WL2 and the bit line BL.
  • the structure of the memory cell array 10 of the nonvolatile semiconductor memory device according to the present embodiment is the same as the structure shown in FIGS.
  • FIGS. 8 to 11 are appropriately referred to.
  • the nonvolatile semiconductor memory device of this embodiment prevents a change in the storage state of a non-selected cell that is not selected for writing when writing to a memory cell selected for writing.
  • the memory cell MC (SELECT) is selected as the memory cell to be written.
  • the memory cell MC (SELECT) selected for writing is hereinafter also referred to as a selected cell MC (SELECT) .
  • the source line SL connected to the source of the memory cell transistors MT of the selected cell MC (SELECT)
  • the write voltage Vsl is applied.
  • non-selected cells MC SL
  • non-selected cells MC SELECT
  • source cells SL connected to the source of the memory cell transistor MT of the selected cell MC (SELECT).
  • SELECT source of the memory cell transistor MT of the selected cell MC
  • the memory cell transistor MT of the unselected cell MC (SL) is not commonly connected to the first word line WL1 connected to the control gate of the memory cell transistor MT of the selected cell MC (SELECT) .
  • the memory cell transistor MT of the non-selected cell MC is commonly connected to the first word line WL1 connected to the control gate of the memory cell transistor MT of the selected cell MC (SELECT) .
  • a write selection voltage which is a positive voltage is applied to the control gate of the memory cell transistor MT of the selected cell MC (SELECT) , and the memory cell transistor MT is turned on. Become.
  • the write selection voltage is applied to the control gate of the memory cell transistor MT of the non-selected cell MC (ADJACENT) by the same first word line WL1.
  • the source line SL connected to the source of the memory cell transistor MT of the selected cell MC (SELECT) and the non-selected cell MC (SL) connected in common are connected. Similarly, changes in the memory state are prevented.
  • the nonvolatile semiconductor memory device of this embodiment has a positive voltage generation circuit ViG for applying a positive voltage Vi to the control gate of the memory cell transistor MT of the non-selected cell MC (SL) .
  • the nonvolatile semiconductor memory device of this embodiment has a control circuit CC to which the positive voltage Vi generated by the positive voltage generation circuit ViG is supplied.
  • the positive voltage generation circuit ViG and the control circuit CC are the same as those in the first embodiment described above.
  • the positive voltage generation circuit ViG supplies the generated positive voltage Vi to the first row decoder Dr1 via the control circuit CC.
  • the timing at which the positive voltage Vi is supplied to the first row decoder Dr1 by the positive voltage generation circuit ViG is controlled by the control circuit CC.
  • the first row decoder Dr1 applies the positive voltage Vi supplied from the positive voltage generation circuit ViG to the control gate of the memory cell transistor MT of the non-selected cell MC (SL) via the first word line WL1. .
  • the potential of the source diffusion layer becomes higher than the gate potential so that the electron e ⁇ / hole h + pair is generated by the band-to-band tunneling. It is prevented. Accordingly, generation of electron e ⁇ / hole h + pairs due to band-to-band tunneling is suppressed, and hot holes are prevented from being trapped in the tunnel insulating film TI. Therefore, compared to the case where 0 V is applied to the control gate of the memory cell transistor MT of the unselected cell MC (SL) as described in the description of the prior art, in this embodiment, the well (see reference numeral 26 in FIG. 9). As a result, the reverse bias voltage of the control gate of the non-selected cell MC (SL) increases.
  • the selection transistor ST of the non-selected cell MC (SL) is turned off.
  • the selection transistor ST even if the memory cell transistor MT of the non-selected cell MC (SL) to which the positive voltage Vi is applied is turned on, writing to the memory cell transistor MT is prevented. .
  • the positive voltage Vi applied to the control gate of the memory cell transistor MT which is an NMOS transistor is a voltage in a direction in which an inversion layer is generated on the silicon surface below the control gate with respect to the well (see reference numeral 26 in FIG. 9).
  • the value of the positive voltage Vi when not less than the threshold value for the memory cell transistors MT of the memory cells MC in the erased state to the ON state, the selected cell MC (SELECT) is written, the non-selected cells MC (SL) This is preferable for reliably preventing the memory state from changing.
  • the value of the positive voltage Vi is the value of the power supply voltage Vcc or the value of the verification voltage used for verifying the writing state of the memory cell transistor MT in which writing has been performed, as in the first embodiment described above. There may be.
  • the first row decoder Dr1 is formed by a high voltage circuit (high voltage circuit).
  • a high voltage circuit is a circuit having a relatively low operating speed and a relatively high breakdown voltage.
  • a gate insulating film (not shown) of a transistor (not shown) of the high voltage circuit is formed relatively thick in order to ensure a sufficient breakdown voltage. For this reason, the operation speed of the transistor of the high voltage circuit is lower than that of the transistor of the low voltage circuit.
  • the high voltage circuit is used for the first row decoder Dr1 because the first word decoder 1 is used when information is written in the memory cell transistor MT or when information written in the memory cell transistor MT is erased. This is because a high voltage needs to be applied to the line WL1.
  • the plurality of second word lines WL2 that commonly connect the select gates of the select transistors ST are connected to the second row decoder Dr2.
  • the second row decoder Dr2 is for controlling the potentials of the plurality of second word lines WL2 that commonly connect the select gates of the select transistors ST.
  • the second row decoder Dr2 is formed by a low voltage circuit (low withstand voltage circuit). The reason why the low voltage circuit is used for the second row decoder Dr2 in this embodiment is that it is not necessary to apply a high voltage to the select gate of the select transistor ST, but it is important to operate the select transistor ST at high speed. This is because of this. In the present embodiment, since a low voltage circuit is used for the second row decoder 18, the select transistor ST can be operated at a relatively high speed, and thus a non-volatile semiconductor memory device having a high read speed is provided. Is possible.
  • the plurality of bit lines BL commonly connecting the drains of the selection transistors ST are connected to the first column decoder Dc1.
  • the column decoder Dc1 is for controlling the potentials of a plurality of bit lines BL that commonly connect the drains of the selection transistors ST.
  • the column decoder Dc1 also controls the potentials of the plurality of source lines SL that commonly connect the sources of the memory cell transistors MT when reading the information written in the memory cell transistors MT.
  • a sense amplifier SA for detecting a current flowing through the bit line BL is connected to the column decoder Dc1.
  • the column decoder Dc1 is formed by a low voltage circuit (low withstand voltage circuit) that operates at a relatively low voltage.
  • the low voltage circuit is a circuit that can operate at high speed while having a relatively low withstand voltage.
  • a gate insulating film (not shown) of a transistor (not shown) of the low voltage circuit is formed relatively thin. For this reason, the transistors of the low voltage circuit used in the column decoder Dc1 can operate at a relatively high speed.
  • the reason why the low voltage circuit is used for the column decoder Dc1 in this embodiment is that it is not necessary to apply a high voltage to the drain of the selection transistor ST, while the selection transistor is read when information written in the memory cell transistor MT is read. This is because it is necessary to operate the ST at high speed.
  • the select transistor ST can be operated at a relatively high speed, and as a result, it is possible to provide a nonvolatile semiconductor memory device with a high read speed. Become.
  • the plurality of source lines SL that commonly connect the sources of the memory cell transistors MT are connected to both the first column decoder Dc1 and the second column decoder Dc2.
  • the second column decoder Dc2 is for controlling the potentials of the plurality of source lines SL that commonly connect the sources of the memory cell transistors MT when writing information to the memory cell transistors MT.
  • the source line SL is controlled by the first column decoder Dc1.
  • the second column decoder Dc2 is formed by a high voltage circuit (high voltage circuit).
  • the reason why the high voltage circuit is used for the second column decoder Dc2 in this embodiment is that it is necessary to apply a high voltage to the source line SL when writing information to the memory cell transistor MT. As described above, when reading information written in the memory cell transistor MT, the source line SL is controlled by the first column decoder Dc1.
  • FIG. 15 is a diagram illustrating a writing method, a reading method, and an erasing method of the nonvolatile semiconductor memory device according to the present embodiment.
  • the parenthesis indicates the potential of the non-selected line.
  • F indicates floating.
  • FIG. 16 is a circuit diagram illustrating the writing method of the nonvolatile semiconductor memory device according to the present embodiment.
  • FIG. 17 is a time chart illustrating the writing method of the nonvolatile semiconductor memory device according to the present embodiment.
  • the address of the memory cell (selected cell) MC (SELECT) to be selected is determined.
  • the second word line WL2 connected to the selected cell MC (SELECT) (SELECT)
  • Vcc fourth potential
  • the potential of the second word line WL2 other than the selected second word line WL2 (SELECT)
  • the potential of the unselected second word line WL2 is set to 0 V (grounded) by the second row decoder Dr2. ).
  • the potential of the selected bit line BL (SELECT) connected to the drain of the selection transistor ST of the selected cell MC (SELECT) is set to 0 V by the first column decoder Dc1.
  • bit line (adjacent bit line) BL (ADJACENT) connected to the drain of the selection transistor ST of the adjacent cell MC (ADJACENT) adjacent to the selected cell MC (SELECT) is set to Vcc by the first column decoder Dc1. Set to (fifth potential).
  • adjacent bit line BL ADJACENT
  • to the selected bit line BL SELECT
  • the selected cell MC SELECT
  • memory cell transistors connected to the source source line of MT of (selected source line) SL (SELECT) It is located on the first side and is adjacent to the selected source line SL (SELECT) .
  • the selected source line SL (SELECT) is located on the first side of the selected bit line BL (SELECT), is adjacent to the selected bit line BL (SELECT). Further, the potentials of the bit lines BL other than the selected bit line BL (SELECT) and the adjacent bit line BL (ADJACENT) are set to 0 V (ground) by the first column decoder Dc1.
  • the potentials of all the first word lines WL1 are set to the positive voltage Vi by the first row decoder Dr1.
  • the final next stage inverter Inv-preF in the first row decoder Dr1 in the write selection standby state always outputs a high level signal to the final stage inverter Inv-F via the node A. Therefore, when the control circuit CC outputs the positive voltage Vi to the first row decoder Dr1 in the write selection standby state, all final stage inverters Inv-F set the potentials of all the first word lines WL1.
  • the positive voltage Vi is the positive voltage Vi.
  • the positive voltage Vi is applied by the first row decoder Dr1 to the control gates of the memory cell transistors MT of the non-selected cell MC (SL) and the non-selected cell MC (ADJACENT) .
  • the positive voltage Vi is also applied to the control gate of the memory cell transistor MT of the selected cell MC (SELECT) by the first row decoder Dr1.
  • the potential of the first word line WL1 (SELECT) connected to the selected cell MC (SELECT) is changed by the first row decoder Dr1 to the write selection voltage Vpp (sixth potential) which is a positive potential.
  • Vpp sixteenth potential
  • the write selection voltage Vpp can be set to 9V, for example.
  • the potential of the selected first word line WL1 (SELECT) is higher than the potential of a selected source line SL (SELECT) described later.
  • the potential of the first word line WL1 other than the selected first word line WL1 (SELECT) that is, the potential of the unselected first word line WL1 remains the positive voltage Vi.
  • the positive voltage Vi is applied to the control gates of the memory cell transistors MT of all unselected cells MC (SL) . Therefore, the first row recorder Dr1 sets the potentials of all the first word lines WL1 other than the selected first word line WL1 (SELECT) to the positive voltage Vi. That is, the positive voltage Vi is applied to the control gates of all the select transistors ST not connected to the selected first word line WL1 (SELECT) , including memory cells other than the non-selected cells MC (SL). .
  • the potential of the source line SL (SELECT) connected to the memory cell MC to be selected is set to the write voltage Vsl by the second column decoder Dc2.
  • the write voltage Vsl can be set to, for example, 5.5V.
  • the potential of the source line SL other than the selected source line SL (SELECT) is set as the floating F.
  • the write voltage Vsl is applied to the source of the memory cell transistor MT of the selected cell MC (SELECT) for a predetermined time, and the memory cell transistor MT of the selected cell MC (SELECT) is applied. Is written.
  • the positive voltage Vi is applied to the control gate of the memory cell transistor MT of the non-selected cell MC (SL) for at least a predetermined time by the first row decoder Dr1.
  • the positive voltage Vi is applied at least 10 nsec before the application of the write voltage Vsl.
  • the selected cell MC SELECT
  • the memory state of the non-selected cell MC SL
  • the time T1 between the start time of application of the positive voltage Vi and the start time of application of the write voltage Vsl is preferably 10 nsec to 1 ⁇ sec.
  • the positive voltage Vi can be applied for at least 10 nsec after the end of application of the write voltage Vsl.
  • the selected cell MC SELECT
  • the electrons e ⁇ / holes due to interband tunneling are applied. It is preferable for preventing the generation of h + pairs. In this way, even when the write voltage Vsl falls, generation of electron e ⁇ / hole h + pairs due to band-to-band tunneling is suppressed, and hot holes are surely captured by the tunnel insulating film TI. Is prevented.
  • the time T2 between the end of application of the positive voltage Vi and the end of application of the write voltage Vsl is preferably 10 nsec to 1 ⁇ sec.
  • the memory state is prevented from changing for the selected source line SL (SELECT) and the non-selected cell MC (SL) whose sources are connected in common. .
  • a positive voltage Vi is applied to the control gate of the memory cell transistor MT of the non-selected cell MC (SL) .
  • the memory cell transistor MT may be turned on.
  • the selection transistor ST of the non-selected cell MC (SL) is in the off state by setting the potential of the non-selected second word line WL2 to 0 V, the memory cell transistor MT of the non-selected cell MC (SL) Is prevented from being written to.
  • the potential of the adjacent bit line BL (ADJACENT) is set to Vcc for the following reason.
  • the potential of the connected source line SL is floating, and the potential of the connected first word line WL1 is a positive potential.
  • Vpp or positive voltage Vi is set.
  • FIG. 18 is a circuit diagram illustrating the read method of the nonvolatile semiconductor memory device according to the present embodiment.
  • FIG. 19 is a time chart illustrating the read method of the nonvolatile semiconductor memory device according to the present embodiment.
  • the address of the memory cell (selected cell) MC (SELECT) to be selected is determined.
  • the potential of the bit line (selected bit line) BL (SELECT) connected to the selected cell MC (SELECT) is set to Vcc by the first column decoder Dc1.
  • the potentials of the bit lines BL other than the selected bit line BL (SELECT) are made floating.
  • the potential of the source line (selected source line) SL (SELECT) connected to the selected cell MC (SELECT) is set to 0 V (ground) by the first column decoder Dc1. Note that the selected source line SL (SELECT) is located on the first side with respect to the selected bit line BL (SELECT) .
  • the potential of the source line (adjacent source line) SL (ADJACENT) connected to the memory cell (adjacent cell) MC (ADJACENT) adjacent to the selected cell MC (SELECT) is set to Vcc by the first column decoder Dc1. .
  • the adjacent source line SL (ADJACENT) is located on the second side opposite to the first side with respect to the selected bit line BL (SELECT) .
  • the drain of the selection transistor ST of the selected cell MC (SELECT) and the drain of the selection transistor ST of the adjacent cell MC (ADJACENT) are commonly connected by a selected bit line BL (SELECT) .
  • the potentials of the other source lines SL that is, the potentials of the source lines SL excluding the selected source line SL (SELECT) and the adjacent source line SL (SELECT) are floating. Further, the potentials of all the first word lines WL1 are always set to Vcc by the first row decoder Dr1 during the read standby. The potentials of the well Well (see reference numeral 26 in FIG. 9) are all 0V.
  • the selected bit line BL (SELECT) is connected to the sense amplifier SA.
  • the potential of the second word line WL2 (SELECT) connected to the selected cell MC (SELECT) is set to Vcc by the second row decoder Dr2.
  • the potentials of the plurality of second word lines WL2 excluding the selected second word line WL2 (SELECT) are set to 0 V by the second row decoder Dr2.
  • the memory cell transistors information MT of the selected cell MC (SELECT) is written, that is, in the case of the selected cell MC (SELECT) information of the memory cell transistor MT is "0"
  • the floating of the memory cell transistor MT Charges are accumulated in the gate 30a.
  • no current flows between the source diffusion layer 36a of the memory cell transistor MT and the drain diffusion layer 36c of the selection transistor ST, and the selected bit line (selected bit line) BL (SELECT) Current does not flow.
  • the potential of the selected bit line BL (SELECT) remains at Vcc.
  • the potential of the selected bit line BL (SELECT) is detected by the sense amplifier SA.
  • the potential of the selected bit line BL (SELECT) remains at Vcc, it is determined that the information of the memory cell transistor MT of the selected cell MC (SELECT) is “0” (see FIG. 19).
  • the potential of the first word line WL1 is always set to Vcc during read standby, the potential of the source line SL, the potential of the bit line BL, and the potential of the second word line WL2 are controlled. As a result, information written in the memory cell transistor MT can be read.
  • the first column decoder Dc1 for controlling the potential of the bit line BL is formed by the low voltage circuit as described above, the bit line BL is controlled at high speed. Further, when reading information written in the memory cell transistor MT, the potential of the source line SL is controlled by the first column decoder Dc1, and therefore the source line SL is also controlled at high speed.
  • the second row decoder Dr2 for controlling the potential of the second word line WL2 is formed by the low voltage circuit as described above, the second word line WL2 is also controlled at high speed. Therefore, according to the present embodiment, information written in the memory cell transistor MT of the selected cell MC (SELECT) can be read at high speed.
  • the source diffusion of the memory cell transistor MT is performed in the adjacent cell MC (ADJACENT) even though the adjacent cell MC (ADJACENT) is not selected.
  • An unintended current may flow between the layer 36a and the drain diffusion layer 36c of the selection transistor ST.
  • the selected cell MC regardless of whether or not current flows between the source diffusion layer 36a of the memory cell transistor MT and the drain diffusion layer 36c of the selection transistor ST, the selected bit line BL ( Current will flow through ( SELECT) .
  • the memory cell In the selected cell MC (SELECT) , even though no current flows between the source diffusion layer 36a of the memory cell transistor MT and the drain diffusion layer 36c of the selection transistor ST, in the adjacent cell MC (ADJACENT) , the memory cell When a current flows between the source diffusion layer 36a of the transistor MT and the drain diffusion layer 36c of the selection transistor ST, information on the memory cell transistor MT of the selection cell MC (SELECT) is erroneously determined.
  • the potential of the adjacent source line SL (ADJACENT) is set to Vcc.
  • an unintended current does not flow between the source diffusion layer 36a of the memory cell transistor MT and the drain diffusion layer 36c of the selection transistor ST.
  • the potential of each part is set as follows. That is, the potentials of the bit lines BL are all floating. The potentials of the source lines SL are all floating.
  • the potential of the first word line WL1 is set to, for example, ⁇ 9 V by the first row decoder Dr1.
  • the potential of the second word line WL2 is all floated by the second row decoder Dr2.
  • the potential of the well Well (see reference numeral 26 in FIG. 9) is, for example, + 9V.
  • nonvolatile semiconductor memory device of this embodiment it is possible to reliably prevent the storage state of the non-selected cell MC (SL) from changing when the selected cell MC (SELECT) is written.
  • the first column decoder Dc1 that controls the potential of the bit line BL that commonly connects the drains 36c of the selection transistors ST is formed by a low-voltage circuit capable of high-speed operation.
  • the second row decoder Dr2 for controlling the potential of the second word line WL2 that commonly connects the select gates 30b of the select transistors ST is formed by a low voltage circuit capable of high speed operation.
  • the source line SL commonly connecting the sources 36a of the memory cell transistors MT is controlled by the first column decoder Dc1.
  • the bit line BL, the second word line WL2, and the source line can be controlled at high speed. That is, the information written in the memory cell transistor MT can be read at high speed.
  • the selection transistor ST is formed of an NMOS transistor, it is possible to contribute to an increase in operating speed as compared with the case where the selection transistor is formed of a PMOS transistor.
  • the nonvolatile semiconductor memory device of each embodiment described above can be changed as appropriate without departing from the spirit of the present invention.
  • the above-described writing method of the nonvolatile semiconductor memory device is an example. If a positive voltage is applied to the control gate of the memory cell transistor MT of the non-selected memory cell (SL) along with the application of the write voltage Vsl, the order of operation of the potentials of other signal lines such as the first word line WL1. The writing may be performed by changing.
  • the nonvolatile semiconductor memory device of the second embodiment can be manufactured in the same manner.
  • FIGS. 29A, 29A, 30, 32, and 34 show the memory cell array region (core region) 2.
  • FIGS. 29A, 29A, 30, 32, and 34 correspond to the CC ′ cross section of FIG. 20 (a), 21 (a), 22 (a), 23 (a), 24 (a), 25 (a), 26 (a), 27 (a), and 28.
  • FIG. 29A, FIG. 29A, FIG. 30, FIG. 32 and FIG. 34 corresponds to the AA 'cross section of FIG. 20 (b), 21 (b), 22 (b), 23 (b), 24 (b), 25 (b), 26 (b), 27 (b), 28 FIG. 29B, FIG. 31, FIG. 33, and FIG. 35 show the peripheral circuit region 4.
  • 20 (b), 21 (b), 22 (b), 23 (b), 24 (b), 25 (b), 26 (b), 27 (b), 28 (B), FIG. 29 (b), FIG. 31, FIG. 33 and FIG. 35 the left side of the drawing shows the region 6 where the high voltage transistor is formed.
  • the left side of the region 6 where the high breakdown voltage transistor is formed shows the region 6N where the high breakdown voltage N channel transistor is formed, and the right side of the region 6 where the high breakdown voltage transistor is formed is the high breakdown voltage P channel.
  • a region 6P where a transistor is formed is shown. 20 (b), 21 (b), 22 (b), 23 (b), 24 (b), 25 (b), 26 (b), 27 (b), 28 (B), FIG. 29 (b), FIG. 31, FIG. 33, and FIG.
  • the left side of the paper 8 in the region 8 where the low voltage transistor is formed shows the region 8N where the low voltage N channel transistor is formed, and the right side of the paper 8 in the region 8 where the low voltage transistor is formed is the low voltage P channel.
  • a region 8P where a transistor is formed is shown.
  • the semiconductor substrate 20 is prepared.
  • a P-type silicon substrate is prepared as the semiconductor substrate 20.
  • thermal oxide film 64 having a film thickness of 15 nm is formed on the entire surface by, eg, thermal oxidation.
  • a silicon nitride film 66 having a thickness of 150 nm is formed on the entire surface by, eg, CVD.
  • a photoresist film (not shown) is formed on the entire surface by, eg, spin coating.
  • an opening (not shown) is formed in the photoresist film by using a photolithography technique.
  • the opening is for patterning the silicon nitride film 66.
  • the silicon nitride film 66 is patterned using the photoresist film as a mask. Thereby, a hard mask 66 made of a silicon nitride film is formed.
  • the semiconductor substrate 20 is etched by dry etching using the hard mask 66 as a mask. As a result, a groove 68 is formed in the semiconductor substrate 20 (see FIG. 20).
  • the depth of the groove 68 formed in the semiconductor substrate 20 is, for example, 400 nm from the surface of the semiconductor substrate 20.
  • the exposed portion of the semiconductor substrate 20 is oxidized by a thermal oxidation method. As a result, a silicon oxide film (not shown) is formed on the exposed portion of the semiconductor substrate 20.
  • a 700 nm-thickness silicon oxide film 22 is formed on the entire surface by high-density plasma CVD.
  • the silicon oxide film 22 is polished by CMP (Chemical Mechanical Polishing) until the surface of the silicon nitride film 66 is exposed.
  • CMP Chemical Mechanical Polishing
  • the heat treatment conditions are, for example, 900 ° C. and 30 minutes in a nitrogen atmosphere.
  • the silicon nitride film 66 is removed by wet etching.
  • a sacrificial oxide film 69 is grown on the surface of the semiconductor substrate 20 by a thermal oxidation method.
  • an N type buried diffusion layer 24 is formed by deeply implanting an N type dopant impurity into the memory cell array region 2.
  • the upper part of the buried diffusion layer 24 becomes a P-type well 26.
  • an N-type buried diffusion layer 24 is formed also by deeply implanting an N-type dopant impurity in the region 6N where the high breakdown voltage N-channel transistor is formed.
  • an N-type buried diffusion layer 70 is formed in a frame shape in the region 6N where the high breakdown voltage N-channel transistor is formed.
  • the frame-shaped buried diffusion layer 70 is formed so as to extend from the surface of the semiconductor substrate 20 to the peripheral portion of the buried diffusion layer 24.
  • a region surrounded by the buried diffusion layer 24 and the buried diffusion layer 70 is a P-type well 72P.
  • an N-type well 72N is formed by introducing an N-type dopant impurity into the region 6P where the high breakdown voltage P-channel transistor is formed.
  • channel doping is performed on the region 6N where the high breakdown voltage N-channel transistor is formed and the region 6P where the high breakdown voltage P-channel transistor is formed (not shown).
  • the sacrificial oxide film 69 present on the surface of the semiconductor substrate 20 is removed by etching.
  • a 10 nm thick tunnel insulating film 28 is formed on the entire surface by thermal oxidation.
  • a 90 nm-thickness polysilicon film 30 is formed on the entire surface by, eg, CVD.
  • a polysilicon film doped with impurities is formed.
  • the polysilicon film 30 existing in the peripheral circuit region 4 is removed by etching.
  • an insulating film (ONO film) 32 formed by sequentially laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed on the entire surface.
  • the insulating film 32 is for insulating the floating gate 30a and the control gate 34a.
  • a P-type well 74P is formed by introducing a P-type dopant impurity into a region 8N where a low-voltage N-channel transistor is to be formed.
  • an N-type well 74N is formed by introducing an N-type dopant impurity into the region 8P where the low-voltage P-channel transistor is formed.
  • channel doping is performed on the region 8N where the low voltage N-channel transistor is formed and the region 8P where the low voltage P-channel transistor is formed (not shown).
  • the insulating film (ONO film) 32 existing in the peripheral circuit region 4 is removed by etching.
  • a gate insulating film 76 of, eg, a 15 nm-thickness is formed on the entire surface by thermal oxidation.
  • the gate insulating film 76 present in the region 8 where the low voltage transistor is formed is removed by wet etching.
  • a gate insulating film 78 of, eg, a 3 nm-thickness is formed on the entire surface by thermal oxidation.
  • a gate insulating film having a film thickness of 3 nm is formed in the region 8 where the low voltage transistor is formed.
  • the thickness of the gate insulating film 76 is, for example, about 16 nm.
  • a polysilicon film 34 of, eg, a 180 nm-thickness is formed on the entire surface by, eg, CVD.
  • an antireflection film 80 is formed on the entire surface.
  • the antireflection film 80, the polysilicon film 34, the insulating film 32, and the polysilicon film 30 are dry-etched using a photolithography technique.
  • a stacked body including the floating gate 30a formed of polysilicon and the control gate 34a formed of polysilicon is formed in the memory cell array region 2.
  • a stacked body having a select gate 30b made of polysilicon and a polysilicon film 34b is formed in the memory cell array region 2.
  • the polysilicon film 34b is removed by etching (not shown).
  • a silicon oxide film (FIG. 27) is formed on the sidewall portion of the floating gate 30a, the sidewall portion of the control gate 34a, the sidewall portion of the select gate 30b, and the sidewall portion of the polysilicon film 34b by thermal oxidation. (Not shown).
  • a photoresist film (not shown) is formed on the entire surface by spin coating.
  • an opening (not shown) exposing the memory cell array region 2 is formed in the photoresist film.
  • N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask.
  • impurity diffusion layers 36a to 36c are formed in the semiconductor substrate 20 on both sides of the floating gate 30a and in the semiconductor substrate 20 on both sides of the select gate 30b. Thereafter, the photoresist film is peeled off.
  • the memory cell transistor MT having the floating gate 30a, the control gate 34a, and the source / drain diffusion layers 36a and 36b is formed. Further, the selection transistor ST having the control gate 30b and the source / drain diffusion layers 36b and 36c is formed.
  • a silicon oxide film 82 is formed on the sidewall portion of the floating gate 30a, the sidewall portion of the control gate 34b, the sidewall portion of the select gate 30b, and the sidewall portion of the polysilicon film 34b by thermal oxidation.
  • a 50 nm-thickness silicon nitride film 84 is formed by, eg, CVD.
  • the sidewall insulating film 84 formed from the silicon nitride film is formed by anisotropically etching the silicon nitride film 84 by dry etching. At this time, the antireflection film 80 is removed by etching.
  • the polysilicon film 34 in the region 6 where the high voltage transistor is formed and the region 8 where the low voltage transistor is formed are patterned.
  • the gate electrode 34c of the high breakdown voltage transistor formed of the polysilicon film 34 is formed.
  • the gate electrode 34d of the low voltage transistor formed of the polysilicon 34 is formed.
  • a photoresist film (not shown) is formed on the entire surface by spin coating.
  • an opening (not shown) exposing the region 6N where the high voltage N channel transistor is to be formed is formed in the photoresist film.
  • N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask.
  • an N-type low-concentration diffusion layer 86 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high breakdown voltage N-channel transistor. Thereafter, the photoresist film is peeled off.
  • a photoresist film (not shown) is formed on the entire surface by spin coating.
  • an opening (not shown) exposing the region 6P where the high voltage P channel transistor is to be formed is formed in the photoresist film.
  • a P-type dopant impurity is introduced into the semiconductor substrate 20.
  • a P-type low-concentration diffusion layer 88 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high breakdown voltage P-channel transistor. Thereafter, the photoresist film is peeled off.
  • a photoresist film (not shown) is formed on the entire surface by spin coating.
  • an opening (not shown) exposing the region 8N where the low-voltage N-channel transistor is to be formed is formed in the photoresist film.
  • N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask.
  • an N-type low-concentration diffusion layer 90 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage N-channel transistor. Thereafter, the photoresist film is peeled off.
  • a photoresist film (not shown) is formed on the entire surface by spin coating.
  • an opening (not shown) exposing the region 8P where the low voltage P-channel transistor is to be formed is formed in the photoresist film.
  • a P-type dopant impurity is introduced into the semiconductor substrate 20.
  • a P-type low-concentration diffusion layer 92 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage P-channel transistor. Thereafter, the photoresist film is peeled off.
  • a 100 nm-thickness silicon oxide film 93 is formed by, eg, CVD.
  • the silicon oxide film 93 is anisotropically etched by dry etching.
  • a sidewall insulating film 93 formed of a silicon oxide film is formed on the sidewall portion of the stacked body having the floating gate 30a and the control gate 34a (see FIG. 28).
  • a sidewall insulating film 93 made of a silicon oxide film is formed on the side wall portion of the stacked body having the select gate 30b and the polysilicon film 34b.
  • a sidewall insulating film 93 formed of a silicon oxide film is formed on the side wall portion of the gate electrode 34c.
  • a sidewall insulating film 93 formed of a silicon oxide film is formed on the side wall portion of the gate electrode 34d.
  • a photoresist film (not shown) is formed on the entire surface by spin coating.
  • an opening (not shown) exposing the region 6N where the high voltage N channel transistor is to be formed is formed in the photoresist film.
  • N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask.
  • an N-type high concentration diffusion layer 94 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high breakdown voltage N-channel transistor.
  • the N-type low-concentration diffusion layer 86 and the N-type high-concentration diffusion layer 94 form an N-type source / drain diffusion layer 96 having an LDD structure.
  • a high breakdown voltage N-channel transistor 110N having the gate electrode 34c and the source / drain diffusion layer 96 is formed.
  • the high breakdown voltage N-channel transistor 110N is used in a high voltage circuit (high breakdown voltage circuit). Thereafter, the photoresist film is peeled off.
  • a photoresist film (not shown) is formed on the entire surface by spin coating.
  • an opening (not shown) exposing the region 6P where the high voltage P channel transistor is to be formed is formed in the photoresist film.
  • a P-type dopant impurity is introduced into the semiconductor substrate 20.
  • a P-type high concentration diffusion layer 98 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high breakdown voltage P-channel transistor.
  • the P-type low-concentration diffusion layer 88 and the P-type high-concentration diffusion layer 98 form a P-type source / drain diffusion layer 100 having an LDD structure.
  • a high breakdown voltage P-channel transistor 110P having the gate electrode 34c and the source / drain diffusion layer 100 is formed.
  • the high breakdown voltage P-channel transistor 110P is used in a high voltage circuit (high breakdown voltage circuit). Thereafter, the photoresist film is peeled off.
  • a photoresist film (not shown) is formed on the entire surface by spin coating.
  • an opening (not shown) exposing the region 8N where the low-voltage N-channel transistor is to be formed is formed in the photoresist film.
  • N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask.
  • an N-type high concentration diffusion layer 102 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage N-channel transistor.
  • An N-type source / drain diffusion layer 104 having an LDD structure is formed by the N-type low-concentration diffusion layer 90 and the N-type high-concentration diffusion layer 102.
  • the low voltage N-channel transistor 112N having the gate electrode 34d and the source / drain diffusion layer 104 is formed.
  • the low voltage N-channel transistor 112N is used in a low voltage circuit. Thereafter, the photoresist film is peeled off.
  • a photoresist film (not shown) is formed on the entire surface by spin coating.
  • an opening (not shown) exposing the region 8P where the low voltage P-channel transistor is to be formed is formed in the photoresist film.
  • a P-type dopant impurity is introduced into the semiconductor substrate 20.
  • a P-type high concentration diffusion layer 106 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low voltage P-channel transistor.
  • the P-type low-concentration diffusion layer 92 and the P-type high-concentration diffusion layer 106 form a P-type source / drain diffusion layer 108 having an LDD structure.
  • the low voltage P-channel transistor 112P having the gate electrode 34d and the source / drain diffusion layer 108 is formed.
  • the low voltage P-channel transistor 112P is used in a low voltage circuit. Thereafter, the photoresist film is peeled off.
  • a cobalt film having a thickness of 10 nm is formed on the entire surface by, eg, sputtering.
  • heat treatment is performed to react silicon atoms on the surface of the semiconductor substrate 20 with cobalt atoms in the cobalt film. Further, the silicon atoms on the surface of the control gate 34a are reacted with the cobalt atoms in the cobalt film. Further, the silicon atoms on the surface of the polysilicon film 34b are reacted with the cobalt atoms in the cobalt film. Further, silicon atoms on the surfaces of the gate electrodes 34c and 34d are reacted with cobalt atoms in the cobalt film.
  • cobalt silicide films 38a and 38b are formed on the source / drain diffusion layers 36a and 36c (see FIG. 29).
  • a cobalt silicide film 38c is formed on the control gate 34a.
  • a cobalt silicide film 38d is formed on the polysilicon film 34b.
  • a cobalt silicide film 38e is formed on the source / drain diffusion layers 96, 100, 104, and 108.
  • a cobalt silicide film 38f is formed on the gate electrodes 34c and 34d.
  • the unreacted cobalt film is removed by etching.
  • the cobalt silicide film 38b formed on the drain diffusion layer 36c of the select transistor ST functions as a drain electrode.
  • the cobalt silicide film 38a formed on the source diffusion layer 36a of the memory cell transistor MT functions as a source electrode.
  • the cobalt silicide film 38e formed on the source / drain diffusion layers 96, 100 of the high voltage transistors 110N, 110P functions as a source / drain electrode.
  • the cobalt silicide film 38e formed on the source / drain diffusion layers 104 and 108 of the low voltage transistors 112N and 112P functions as a source / drain electrode.
  • a 100 nm-thickness silicon nitride film 114 is formed on the entire surface by, eg, CVD.
  • the silicon nitride film 114 functions as an etching stopper.
  • a 1.6 ⁇ m thick silicon oxide film 116 is formed on the entire surface by CVD.
  • the interlayer insulating film 40 formed of the silicon nitride film 114 and the silicon oxide film 116 is formed.
  • the surface of the interlayer insulating film 40 is planarized by CMP.
  • a contact hole 42 reaching the source / drain electrodes 38a and 38b, a contact hole 42 reaching the source / drain diffusion layer 38e, and a contact hole 42 reaching the cobalt silicide film 38f are formed by using a photolithography technique (FIG. 32, see FIG. 33).
  • a barrier layer (not shown) formed of a Ti film and a TiN film is formed on the entire surface by sputtering.
  • a 300 nm-thickness tungsten film 44 is formed on the entire surface by, eg, CVD.
  • the tungsten film 44 and the barrier film are polished by CMP until the surface of the interlayer insulating film 40 is exposed.
  • the conductor plug 44 made of, for example, tungsten is buried in the contact hole 42.
  • a laminated film 46 formed by sequentially laminating a Ti film, a TiN film, an Al film, a Ti film, and a TiN film is formed on the interlayer insulating film 40 in which the conductor plugs 44 are embedded, for example, by sputtering. .
  • the laminated film 46 is patterned using a photolithography technique. As a result, a wiring (first metal wiring layer) 46 formed from the laminated film is formed.
  • a 700 nm-thickness silicon oxide film 118 is formed by, for example, a high-density plasma CVD method.
  • a silicon oxide film 120 is formed by TEOSCVD.
  • the silicon oxide film 118 and the silicon oxide film 120 form an interlayer insulating film 48.
  • a contact hole 50 reaching the wiring 46 is formed in the interlayer insulating film 48 by using a photolithography technique.
  • a barrier layer (not shown) formed of a Ti film and a TiN film is formed on the entire surface by sputtering.
  • a 300 nm-thickness tungsten film 52 is formed on the entire surface by, eg, CVD.
  • the tungsten film 52 and the barrier film are polished by CMP until the surface of the interlayer insulating film 48 is exposed.
  • the conductor plug 52 made of, for example, tungsten is embedded in the contact hole 50.
  • a laminated film 54 formed by sequentially laminating a Ti film, a TiN film, an Al film, a Ti film, and a TiN film is formed on the interlayer insulating film 48 in which the conductor plugs 52 are embedded, for example, by sputtering. .
  • the laminated film 54 is patterned by using a photolithography technique. As a result, a wiring (second metal wiring layer) 54 formed from the laminated film is formed.
  • a silicon oxide film 122 is formed by, for example, a high density plasma CVD method.
  • a silicon oxide film 124 is formed by TEOSCVD.
  • An interlayer insulating film 56 is formed by the silicon oxide film 122 and the silicon oxide film 124.
  • a contact hole 58 reaching the wiring 54 is formed in the interlayer insulating film 56 by using a photolithography technique.
  • a barrier layer (not shown) formed of a Ti film and a TiN film is formed on the entire surface by sputtering.
  • a 300 nm-thickness tungsten film 60 is formed on the entire surface by, eg, CVD.
  • the tungsten film 60 and the barrier film are polished by CMP until the surface of the interlayer insulating film 56 is exposed.
  • a conductor plug 60 made of tungsten, for example, is buried in the contact hole 58.
  • a laminated film 62 is formed on the interlayer insulating film 56 in which the conductor plugs 60 are embedded, for example, by sputtering.
  • the laminated film 62 is patterned by using a photolithography technique. Thereby, a wiring (third metal wiring layer) 62 formed of the laminated film is formed.
  • a silicon oxide film 126 is formed by, for example, a high density plasma CVD method.
  • a silicon oxide film 128 is formed by TEOSCVD.
  • An interlayer insulating film 130 is formed by the silicon oxide film 126 and the silicon oxide film 128.
  • a contact hole 132 reaching the wiring 62 is formed in the interlayer insulating film 130 using a photolithography technique.
  • a barrier layer (not shown) formed of a Ti film and a TiN film is formed on the entire surface by sputtering.
  • a 300 nm-thickness tungsten film 134 is formed on the entire surface by, eg, CVD.
  • the tungsten film 134 and the barrier film are polished by CMP until the surface of the interlayer insulating film 130 is exposed.
  • a conductor plug (not shown) 134 made of, for example, tungsten is embedded in the contact hole 132.
  • a laminated film 136 is formed on the interlayer insulating film 130 in which the conductor plugs 134 are embedded, for example, by sputtering.
  • the laminated film 136 is patterned using a photolithography technique. Thereby, a wiring (fourth metal wiring layer) 136 formed from the laminated film is formed.
  • a silicon oxide film 138 is formed by, for example, a high density plasma CVD method.
  • a silicon oxide film 140 is formed by TEOSCVD.
  • the silicon oxide film 138 and the silicon oxide film 140 form an interlayer insulating film 142.
  • a contact hole 143 reaching the wiring 136 is formed in the interlayer insulating film 142 using a photolithography technique.
  • a barrier layer (not shown) formed of a Ti film and a TiN film is formed on the entire surface by sputtering.
  • a 300 nm-thickness tungsten film 146 is formed on the entire surface by, eg, CVD.
  • the tungsten film 146 and the barrier film are polished by CMP until the surface of the interlayer insulating film 142 is exposed.
  • the conductor plug 144 made of, for example, tungsten is embedded in the contact hole 143.
  • a laminated film 145 is formed on the interlayer insulating film 142 in which the conductor plugs 144 are embedded, for example, by sputtering.
  • the laminated film 145 is patterned using a photolithography technique. Thereby, a wiring (fifth metal wiring layer) 145 formed from the laminated film is formed.
  • a silicon oxide film 146 is formed by, for example, a high density plasma CVD method.
  • a silicon nitride film 148 having a thickness of 1 ⁇ m is formed by plasma CVD.
  • the nonvolatile semiconductor memory device according to the present embodiment is manufactured.
  • Memory cell array region 4 Peripheral circuit region 6 Region where high breakdown voltage transistor is formed 6N Region where high breakdown voltage N-channel transistor is formed 6P Region where high breakdown voltage P-channel transistor is formed 8 Region where low voltage transistor is formed 8N Low 8P region where voltage N channel transistor is formed 8P region where low voltage P channel transistor is formed 10 memory cell array 20 semiconductor substrate 21 element region 22 element isolation region 24 buried diffusion layer 26 well 28 tunnel insulating film 28a tunnel insulating film 28b gate insulating Film 30a floating gate 30b select gate 32a, 32b insulating film 34a control gate 34b polysilicon film 34c, 34d gate electrode 35 impurity diffusion layer 36a impurity diffusion layer, Source diffusion layer 36b impurity diffusion layer 36c impurity diffusion layer, drain diffusion layer 37 sidewall insulating film 38a silicide layer, source electrode 38b silicide layer, drain electrode 38c-38f silicide layer 40 interlayer insulating film 42 contact hole 44 conductor plug 46 wiring 48 Interlayer insulating film 50 Contact hole 52 Conductor plug 54 Wir

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention porte sur un dispositif de mémoire non volatile à semi-conducteur, qui comprend un groupement de cellules de mémoire (10) formées par groupement dans une matrice d'une pluralité de cellules de mémoire (MC) comprenant chacune un transistor de sélection (ST) jouant le rôle de transistor métal-oxyde-semi-conducteur à canal N (NMOS) et un transistor de cellule de mémoire (MT) jouant le rôle de transistor métal-oxyde-semi-conducteur à canal N connecté au transistor de sélection (ST), des premières lignes de mots (WL1) connectant chacune en commun les grilles d'une pluralité de transistors (MT) inclus dans une rangée identique, des secondes lignes de mots (WL2) connectant chacune en commun les grilles d'une pluralité de transistors de sélection (ST) inclus dans une rangée identique, et des lignes de source (SL) connectant chacune en commun les sources des transistors (MT) inclus dans deux rangées ou deux colonnes adjacentes. Lors de l'écriture dans le transistor (MT) d'une cellule sélectionnée (MC), une tension positive est appliquée à la grille du transistor (MT) d'une cellule de mémoire (MC) qui est connectée en commun à une ligne de source (SL) connectée à la source du transistor (MT) de la cellule sélectionnée (MC) et non connectée en commun à une première ligne de mots (WL1) connectée à la grille du transistor (MT) de la cellule sélectionnée (MC).
PCT/JP2009/059900 2009-05-29 2009-05-29 Dispositif de mémoire non volatile à semi-conducteur, et procédé pour écrire dans celui-ci Ceased WO2010137169A1 (fr)

Priority Applications (1)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152826A (en) * 1978-05-24 1979-12-01 Nec Corp Writing method of nonvolatile memory
WO2008041306A1 (fr) * 2006-09-29 2008-04-10 Fujitsu Microelectronics Limited Appareil à mémoire à semi-conducteur non volatile, procédé de lecture associé, procédé d'écriture associé et procédé d'effacement associé
JP2008226332A (ja) * 2007-03-12 2008-09-25 Renesas Technology Corp 不揮発性半導体記憶装置
JP2008310950A (ja) * 2008-07-07 2008-12-25 Renesas Technology Corp 半導体処理装置及びｉｃカード

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152826A (en) * 1978-05-24 1979-12-01 Nec Corp Writing method of nonvolatile memory
WO2008041306A1 (fr) * 2006-09-29 2008-04-10 Fujitsu Microelectronics Limited Appareil à mémoire à semi-conducteur non volatile, procédé de lecture associé, procédé d'écriture associé et procédé d'effacement associé
JP2008226332A (ja) * 2007-03-12 2008-09-25 Renesas Technology Corp 不揮発性半導体記憶装置
JP2008310950A (ja) * 2008-07-07 2008-12-25 Renesas Technology Corp 半導体処理装置及びｉｃカード

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