WO2010113059A1 - Device for characterizing current transients produced by ionizing particles interacting with a block of transistors in a logic gate - Google Patents

Abstract

Device for characterizing current transients produced by ionizing particles interacting with a block of transistors in a logic gate, which device comprises a memory block with capacitors and a synchronization block, the memory block being provided with means for replicating said current and sending the latter to a plurality of outputs each connected to a branch to a capacitor by means of an evaluation switch, the synchronization block being able to generate, at regular intervals, control signals for opening the switches such that, during a current transient, the charge variation of the different capacitors via the evaluation switches is initiated at regular intervals, the approximate temporal profile of the integral of the current transient being able to be characterized from the states of charge of the capacitors.

Description

 TRANSITORY CHARACTERIZATION DEVICE FOR

CURRENT PRODUCED BY INTERACTION OF PARTICLES

IONIZERS WITH A ONE DOOR TRANSISTOR BLOCK

LOGIC

The present invention relates to a device for capturing and experimentally measuring the transient effects produced by an SEE in a microelectronic circuit that can be implemented in any standard CMOS technology.

BACKGROUND OF THE INVENTION

Alpha particles or neutrons from cosmic radiation are ionizing particles that can generate ionization processes in integrated circuits.

The effect produced by one of these particles in an electronic device is called SEE (Single Event Effect). The trend of the microelectronic industry consisting of manufacturing smaller and smaller devices working with increasingly low voltages is causing the electrical charge necessary to produce an error in a given node of the circuit to be smaller and smaller.

Consequently, microelectronic devices are increasingly sensitive to the generation of transient pulses produced by SEEs. Although these effects are transient, they can have dire consequences in applications that require high reliability, such as those related to aeronautics, automotive or medical applications.

A frequent type of SEE is known as SEU

(Single Event Upset). A SEU is an error that occurs in the circuit caused by the electrical charge that is generated because of the loss of energy that an ionizing particle experiences when it hits a semiconductor crystal like silicon. If this load is large enough, you can change the logical state of a node that contains the information of the state of a memory element.

Another type of SEE is the SET (Single Event Transient). A SET takes place when a particle impacts a particular node of a combinational logic circuit, producing a transient disturbance of the voltage of that node. Such disturbance can lead to a false logical transition, which can be propagated through several stages of logical gates to be captured in the last room by a memory element giving rise to a SEU. Typically an SEE is generated by ionizing radiation present in the atmosphere from cosmic radiation such as neutrons or protons. The flow of these particles is higher in high areas of the atmosphere than at sea level, for example in the area destined for commercial aviation. Additionally, an SEE can be produced by alpha particles originated by the decay of uranium or thorium atoms, present in the form of traces in the encapsulation of integrated circuits. SEEs can also be generated in circuits that work in environments with the presence of radioactive materials or after the explosion of nuclear weapons.

So far, numerous techniques have been developed to mitigate the effect of SEEs, both in logic circuits and in memories (see, for example, US7319253, US2007 / 0109865, discussed below), which aim to increase the average time between failures that an electronic circuit presents when operating in its usual operating environment. Also known are previous works aimed at detect the specific moment in which a SEU occurs (US7109746, US2007 / 0162798, EP1758022) or measure the error rate due to SEEs in circuits working in normal operating conditions. In these jobs, high capacity SRAM memories are used and the number of memory locations that have changed logical status as a result of a SEU is detected. However, these techniques do not allow to determine the electrical characteristics that have caused said SEU. Another different problem is to determine the electrical characteristics produced by a SEE in a given node of the circuit, such as the current transients induced in said node.

Regarding this last problem, no device is known for this purpose. There are three reasons that hinder this task:

i. The appearance of an SEE is a random process, both in space and time. ii. The probability of said SEE occurring in the particular node to be analyzed is very low, even working in environments with high levels of ionizing radiation. iii. The short duration of the transitory phenomena produced. The duration and form of said transients depend on the characteristics of each event, especially the nature of the ionizing radiation, energy, distance between the point of interaction and the affected node, and / or the specific characteristics of the microelectronic technology involved. . In any case, transients of the order of a few tens of PS -such as those produced by alpha particles- can give rise to SEUs. These circumstances cause in practice to use computer simulation techniques to obtain information regarding the characteristics of these transients (US 2007/0096754). Some of the aforementioned background as well as other prior art documents related to the present invention are described below.

EP 1 906 526 describes the "use of moving average filters to detect transients due to radiation and correct their effects", so it is not necessary with this procedure to use redundant memories to detect changes in the circuit. However, it is a detection procedure that does not allow measuring or characterizing the currents caused by ionizing radiation.

In US 5 657 267 a dynamic RAM capable of detecting SEUs is described, in which redundant memories are used to be able to compare between different instants. However, it is a device based on comparison and that does not allow characterizing the currents produced in SEU or SET events. In addition, it also requires redundant memories.

In US 5 898 711 Al a procedure is described in which a plurality of SEU detectors are distributed, which operate by bit registers, and for whose application redundant armored registers are necessary to be able to make comparisons, and therefore, presents the same lacks as the previous one. In US 2007/0096754, already mentioned and considered as the closest antecedent of the invention, a method and a system for analyzing SEU 's in semiconductor devices is described, specifically in which a model is used to predict the response of a device semiconductor to a SEU. This procedure of Analysis includes simulating the impact of a particle on a node, determining whether it causes changes in the node and finally varying the charge of the particle to obtain a range of charge values that cause changes in the node. However, it is not based on the measurement of currents either and its effectiveness depends on simulation models, necessarily simplifiers, used.

Finally, in the article by Maya Gokhale and Paul Graham "Dynamic reconfiguration for management of radiation-induced faults in FPGAs" a dynamic reconfiguration system for the management of SEU in FPGA 's is described. This system includes the possibility of artificially inducing faults, which can be a known and controlled radiation exposure or a computer simulation, but it also does not allow to accurately characterize the SEU and SET events and the associated current transients. It is also based on the comparison between redundant memories. In view of the foregoing, the applicant of the present invention has considered it necessary to conceive a device and a method based on this capable of accurately characterizing SEU and SET in microelectronic devices, especially by measuring currents caused by these transients.

DESCRIPTION OF THE INVENTION

For this, the present invention proposes a device for characterizing current transients produced by interaction of ionizing particles with a block of transistors of a logic gate, which is characterized by the fact that it comprises a memory block with capacitors and a block of synchronism, the memory block being provided with means to replicate said current and send it to a plurality of outputs connected each to a branch to a capacitor by means of an evaluation switch, the synchronization block being able to generate control signals at regular intervals opening of the evaluation switches, so that during a current transient the load variation of the different capacitors through the evaluation switches starts at regular intervals, being possible to characterize from the capacitor charge states the approximate time profile of the current transient integral.

From the integral associated with each current transient it is possible to deduce the current and characterize the transient both quantitatively and qualitatively. In addition, the described structure can be replicated in parallel so that it is possible to have a system that operates continuously, that is, without dead times.

It is also possible to adapt the measurement accuracy by selecting the parameters of the synchronization block.

Preferably, each branch is connected to a common output node through a read switch, so that by means of control signals of the switches it is possible to discharge the capacitors and deduct the load stored in each one, to later obtain the mentioned integral .

More preferably, the device of the invention is provided with means for restoring the potential of the capacitors at a given voltage, so that the evaluation is always carried out therein. terms .

Even more preferably, the means for restoring the potential of the capacitors comprise two switches connected to the input and output of each of said evaluation switches.

Advantageously, the device comprises an amplifier arranged between each capacitor and the output node.

More advantageously, the memory block has the capacitors, and their associated switches, organized in two identical banks, so that they can be operated alternately in time, avoiding detection dead times.

Advantageously, the synchronization block comprises a string of monostable cells, an arrangement that allows sampling frequencies of the order of tens of Gigahertz to be obtained.

More advantageously, the synchronization block comprises two synchronization sub-blocks connected to each other and synchronized with the two capacitor banks, allowing the assembly to operate continuously.

Preferably, the device of the invention comprises a detection block configured to detect the start of a current transient, so that when a current transient is detected, it is possible to interrupt the evaluation periods, ie the periods in which they open The evaluation switches Advantageously, the detection block comprises a capacitor, a switch that connects the output of said transistor block of the logic gate to a branch to said capacitor and means for emitting a detection signal from a threshold value of charging said capacitor. This detection signal interrupts the evaluation phase of the memory block, especially to proceed to the reading of the capacitor charges. In this case, a detection dead time will necessarily occur to be able to "read" the capacitor charge, but the probability of two SEEs occurring in a row is extremely low, so it is a dead time that does not globally alter Detection efficiency More advantageously, the means for emitting a detection signal consist of a Schmitt trigger.

Preferably, the device of the invention comprises a control unit configured to control the synchronism generator block based on external setpoints and the signals emitted by the detection block. Specifically, depending on the external setpoints, the control unit allows operating in various modes, as will be explained later.

More preferably, the logic gate, the memory block, the synchronism block and the detection block are integrated in the same substrate, so that the connection between the different components is simplified, which in turn prevents the introduction of delays. , capacitive or inductive elements that would introduce uncontrolled signals into the reading of the transients.

Also, the device according to the invention provides a block of induced current generation, preferably a monostable connected to the base of a transistor, capable of supplying a current to said memory block for calibration.

In particular, when activating this component, a well-known current transient is generated and whose duration is of the order of an SEE, with which it is possible to verify the correct functioning of the device as well as calibrate it

Also, the device may comprise an attenuation block, located between the transistor block of the sampled logic gate and the memory block input.

Advantageously, each branch is connected to a common output node through a read switch, which allows a FISO evaluation and reading procedure (Fast in, Slow out) to be carried out. Preferably, the transistor block of a logic gate is made with CMOS technology, as well as all other components.

Finally, the invention relates to a method of characterizing current transients produced by interaction of ionizing particles with a CMOS logic gate, in which a device according to any of the preceding claims is used, comprising the steps of:

-replicate said current to send it to said outputs,

- open the different evaluation switches sequentially and at regular intervals, so that during a current transient the variation of charge of the different capacitors starts at regular intervals, being possible to characterize from the capacitor charge states the approximate time profile of the current transient integral.

BRIEF DESCRIPTION OF THE DRAWINGS

To better understand how much has been exposed, some drawings are attached in which, schematically and only by way of non-limiting example, a practical case of realization is represented. Figure 1 shows a diagram of the blocks that form the device of the invention.

Figure 2 shows a typical arrangement of the device for the generation of transient events.

Figure 3 shows a transistor circuit whose working point allows the exposure of events in a pMOS transistor (a), the exposure of events in an nMOS transistor (b). Figure 4 shows a scheme corresponding to the stage of induced generation of events.

Figure 5 shows a schematic of a stage (or block) of attenuation.

Figure 6 shows a transistor level scheme of the typical arrangement shown in Figure 2.

Figure 7 shows a diagram of the analog memory cell (or block) used.

Figure 8 shows a diagram explaining the sequence of preload and evaluation phases and the signals used to control the download time in an analog memory bank (memory block).

Figure 9 shows a diagram of the event detector block. Figure 10 shows a diagram of the synchronism block with which a sampling frequency sufficiently high is obtained for the adequate reconstruction of the transients produced.

Figure 11 illustrates the way in which the two sub-blocks of the synchronization block are connected to alternately supply the opening signals of the switches to the two banks in which the capacitors are organized with their associated switches (Also called memory cells) . DESCRIPTION OF A PREFERRED EMBODIMENT

The difficulties related to the detection of SETs have to do, on the one hand, with the random nature of the process, with the low probability that a particle will produce a transient in a given node of the circuit and with a priori ignorance of the duration and magnitude of the transitory to be produced. In order to have a system that is capable of measuring said phenomena, the present invention proposes a device formed by the blocks detailed in Figure 1.

The device is formed by an event generating block, a block intended to memorize the current transient produced by an event, an event detection block, a synchronization signal generation block that allows obtaining the high sampling frequencies required by the application and finally a control block. The device incorporates the necessary control signals so that the device can operate in standby mode, in continuous capture mode or in data reading mode. These three modes of operation are described below: - In standby mode, the status of the different system elements is initialized and left ready so that you can enter the continuous capture mode when the relevant signal is enabled.

- In continuous capture mode, the device is capable of detecting and memorizing a current transient produced in the event generating block, regardless of the moment at which said event occurs.

In data reading mode, it is possible to randomly access the memory block used to sample the transient

Event Generator Block

This block has several sensitive areas, capable of generating current transients as a result of interactions caused by ionizing radiation. In figure 2, a typical arrangement of the sensitive block of events is shown. In order for a transient event to occur, it is necessary that the sensitive zone, where the event occurs, is part of a transistor in a cut-off state, it is usual for said zone to be constituted by the drain of the transistor. Said transistor, in turn, is part of a logical gate. In this invention, the event generator block is obtained from a complementary CMOS logic inverter, although any other logic gate implemented by MOS transistors can be used. The modification to be made will depend on the region that we want to sensitize the passage of the ionizing particles:

Configuration P: so that the passage of the ionizing particle produces an effect generated in the drain of a pMOS transistor (Figure 3a), said transistor (or group of transistors) will be kept in a cut state by connecting its door to a high logic level, indicated as "1", or if applicable to the supply voltage. Likewise, the nMOS transistor block of the door will be replaced by an nMOS transistor with its drain and door connected to each other.

Configuration N: so that the passage of the ionizing particle produces an effect generated in the drain of an nMOS transistor, said transistor (or group of transistors) will be kept in a state of cut by connecting its door to a low logic level, indicated as "0", or if necessary to the ground voltage. Likewise, the gate's pMOS transistor block will be replaced by a single pMOS transistor with its drain and door connected to each other.

To increase the probability of capturing an event, the chosen configuration can be replicated N times by connecting the output nodes of several identical modified doors (nSET node of Figures 3 (a) and 3 (b)). The value of the number of sensors, N, will be chosen based on the parasitic capacity associated with the resulting output node since excessively high values of said capacity produce excessive attenuation and distortion in the generated transients.

The logic gate described in Figure 3 is completed with a stage of induced generation of events (Figure 4) formed by a monostable circuit connected to the MGE transistor gate (said transistor will be of type pMOS in configuration N and type nMOS in the configuration P). When activating the signal

Vmn, the monostable produces a transient event of known duration and amplitude on the measurement node

(nSET). This block allows to validate the correct functioning of the presented device node.

An additional second stage, in this case of attenuation (Figure 5) is obtained with the MAT transistor. MAT is a pMOS transistor in the P configuration or an nMOS transistor in the N configuration. This stage allows the maximum amplitude of the events produced to be attenuated in a controlled manner. The attenuation level on the node of interest is selected using the VAT signal voltage. This stage will be useful if the device is used under exposure to particles very energetic (this can happen in accelerated characterization processes that make use of particle accelerators).

Figure 6 shows an arrangement, corresponding to an N configuration, incorporating the logic gate with the sensitive nodes, the controlled generation stage and the attenuation stage.

In order to proceed with the sampling of the current transients induced in the nSET node of Figure 6, these are replicated by means of an output stage implemented for example, from current mirrors. In this way, possible SET effects produced in memory cells do not interfere with the measurement node. For the reasons discussed in the following section, since the memory is divided into two banks, two identical output stages are necessary connected to the nSET node.

As it is deduced, said block operates in static mode, so once polarized it will be enabled at all times to generate events produced by ionizing radiation.

Memory block

The memory block is intended to capture the transient produced in the event generator block. Said block is integrated in the same substrate as the generator block and is organized in two equal banks, each formed by M identical cells of analog memory. The division into two banks allows the system to work without downtime.

In order to capture the current transient produced in the generator block, it is necessary to sample the signal we want to memorize. To do this proposes to use a structure like the one described in figure 7. Assuming that the node n _c is initially polarized to a value V _nc (t = 0) = V _starts i, (for example V _starts i = V _dd in a configuration P ), a variable current in time and _{aco t tech} imi _e n _to (t) acting for a time t _D produces a partial discharge of the node n _c which in turn translates into a change in the value of the voltage in said knot:

nÁh>) ^~ 'initial ^~

To facilitate the reading process, each memory position has an output amplifier.

If we have a bank formed by M identical cells, varying the discharge time of each cell we obtain a different final voltage for each of the cells of the bank. If t _sampling is the sampling period of the current transient, assigning a discharge time of the first cell equal to Mt _Mues treo (MI) ^• t _Mues treo to the second cell and so on until the last, which present a download time equal to _sample , then, in the event that an event occurs, the sampled signal stored in memory will depend linearly on J iacontecimiento (t) dt. In this way, the transient iacontecimiento (t) can be obtained by numerically deriving the values captured in the memory block. Note that if no event occurs, the value of all cells is maintained in V _starts i. If the time elapsed between the moment at which the voltage of node n _c is set to the initial value and the moment at which an event occurs is considerable, it is possible that the resulting voltage V _nc (t) undergoes variations attributable to another type of usual physical processes in nanometric technologies, such as they are, for example, the appearance of leakage currents.

For this reason it is necessary to periodically refresh the initial voltage value of each of the memory cells. This results in when the device enters capture mode, the memory bank

(memory block) must operate by continuously alternating two different phases: in a first preload phase all the memory cells of the bank are initialized to a fixed voltage value (in our case V _dd ), in a second phase, the phase evaluation, the voltage established in the preload phase can vary depending on the value of the load / discharge current caused by the SET, a variation that in each cell will be modulated by the duration of its discharge time (Figure 7). Note that switches Ii and I2, controlled by the S _pc signal, will be used to activate the preload phase (S _pc = "1" in preload mode and "0" in evaluation mode). The switch I3, controlled by the signal S _m , has the mission of controlling the discharge time of each cell (each cell is understood as each branch of the memory block composed of the capacitor and the associated switches. Note that while the signal S _pc is the same for all the cells of a bank, the signal S _m varies for each cell.The arrangement presented in figure 7 and described in the preceding paragraphs corresponds to a configuration P. In the case of wanting to work with a configuration N, The capacitor C, would be located between n _c and V _dd , switches Ii and I2 would be connected between the input node and ground and between n _c and ground respectively.The preload would correspond to placing V _ir iiciai = OV. The transient produced in the Generator block will cause the node voltage to rise n _c . As in the situation described, the sampled signal stored in memory will continue to be a function l ineal of / iacontecimiento (t) dt.

When a bank is in its preload phase, it is not able to capture data, for this reason, so that the system can work in continuous acquisition mode, it is necessary to divide the memory block into two equal banks, so that the The synchronization block will ensure that while one bank is in the preload phase the other is in the evaluation phase and vice versa (Figure 8). The sequence of preload / evaluation processes will be active as long as the detector block does not detect the presence of an event, the characteristics of the detector block are presented in the following section. Alternatively, the process can be stopped by acting properly on the control unit. At the moment an event is detected, the procedure of the presented device is as follows:

-waiting the completion of the ongoing evaluation phases of the two memory banks -precharge processes are suspended, and

-the memory is accessible to reading mode. Thus 2M samples are captured corresponding to a transient duration t treo 2M- _Mues •

Externally, the memory location to be read can be indicated randomly. Said signal, properly decoded, is used to open the corresponding output switch, I ₄ (signal S ₀ represented in Figure I) ₁ so that the analog voltage corresponding to the chosen position is obtained at the output node.

To speed up the reading process, an independent exit is planned for each bank. Acceleration of the reading process is recommended if the sensor is implemented in nanometric technologies, so that it is possible to reduce effects produced by currents discharge parasites on the voltage value stored in the node n _c .

Event Detector Block

This block is connected directly to the output stage of the generator block. Its function is to determine the precise moment in which an event occurs in the generator block. This information is needed to decide when to stop the sequence of preload and evaluation phases of the memory block and enter its reading mode.

In this way, it is guaranteed that only the events produced in the generator block activate capture processes in the memory block. Those particles that affect positions other than the sensitive areas of the generator block, such as the incidence of a particle in a cell of the memory block, would create current transients that could possibly alter the final voltage of one or more memory cells ; However, these events, unable to be recognized by the detector block, would not stop the preload / evaluation process, so their effects would be restored after the subsequent preload phase.

A possible structure of the detector block is shown in Figure 9. Its structure is similar to the structure of the memory cell presented in Figure 7, with the difference that instead of an output amplifier, the node n _c is connected to a trigger of Schmitt, a circuit that allows greater immunity against interference that can generate false events.

This cell works with a discharge time equal to Mt _mu stereo- A capacitor capacity value C _{0 is used} , less than that used in the cells of memory, said value being adjusted in order to select the trigger threshold of the Schmitt trigger.

After each preload phase, the voltage of the node n _c is restored to V _dd (value equivalent to a logical "1") so that in the node n _out , a low logic level ("0") is obtained in principle. In the event of an event, the voltage of n _c drops rapidly to 0, therefore n _out switches from "0" to "1". When this happens, the new value is registered in a bistable element whose status is used to indicate that an event has been detected.

Being subject to the preload / evaluation processes, it is necessary to have two detection blocks, one for each memory bank.

Sync block

For proper sampling transients, the sampling period, t treo _Mues, must be sufficiently low. The synchronization block, on the one hand, generates the synchronization signals S _pc , _A and S _pc , _B used in the memory banks to control their preload and evaluation phases during operation in continuous capture mode, and by another periodically generate the set of sampling signals described in Figure 8, which are used to establish the download time of each of the cells of the memory bank.

Each monostable has an RST input that restores the logical level of node Q to "1", when input S _1n is activated to "1" the discharge of node Q up to "0" occurs and the load of Q _B of "0 "a" 1 ", a process that has a duration t _Q. If M monostable cells are chained in series so that the Q _B output of a monostable is connected to the S _1n input of the circuit Next (Figure 10), a block is obtained that generates a set of signals like the one described in Figure 8 with sampling ^~~ tς>.

The sampling time t _Mues threo can be suitably adjusted by selecting measures transistors of this block. Sampling times of 40 ps in a CMOS technology of 130 nm have been achieved in the device of the invention.

As can be seen, this block also works following a sequence of two phases that alternate, a tripping phase and a recovery or preload phase of all nodes Q to "1", so again, as illustrated in figure 11, the option of dividing the synchronism block into two sub-blocks is used so that when one sub-block is in trip mode generating the download time signals from one of the memory banks, the other block is in the recovery phase (phase that coincides with the preload phase of the memory bank assigned to said sub-block). In this case it is necessary condition to get trecuperacion ^ u "t _mue streo •

As can be deduced from Figure 11b, the trigger signal of the last cell of one of the sub-blocks is used to initiate the firing of the first cell of the other sub-block and starts the process of recovering its sub-block. . In this way when the device is in continuous capture mode, the synchronization signal generation process can continue indefinitely (the process stops when an event is detected).

Control unit

Finally, the control unit is a finite state machine that is responsible for generating the signals necessary to conveniently initiate the modes of wait, capture and read described in the preceding sections.

As a summary, to increase the capture efficiency, it is necessary that the device can work in continuous capture mode for long periods of time. For this, the invention uses a high-speed acquisition system in which a set of samples of the monitored transient are captured. The structure of said module, characterized by having a very fast capture time and a slower reading time, can therefore be considered as an adaptation to the problem of characterizing transient currents of a FISO structure (Fast-in Slow-Out) as those presented in US 1981/4271488 or EP0483945 Bl.

This part of the invention differs from the preceding ones in the sense that the memory has been organized into two linear banks of M cells each

(Bank A and Bank B), in order to get the system to work in a continuous mode and without downtime. The reading port of our memory has been conveniently adapted to be able to respond to current transients of the event to be captured and, finally, a protocol of control signals that govern the capture process has been established so that if event (t) is the current transient produced by the event, the acquisition acquisition system of the invention is actually a signal proportional to Ji _aco n _tec imi _e n _to (t) dt. The signals necessary for this are generated internally by a specific block based on a monostable chain.

Claims

1. Device for characterizing current transients (I) produced by interaction of ionizing particles with a transistor block of a logic gate (1), characterized by the fact that it comprises a memory block (2) with capacitors (C) and a synchronization block (3), the memory block (2) being provided with means to replicate said current (I) and send it to a plurality of outputs connected each to a branch (n _c ) towards a capacitor (C) by means of an evaluation switch (mi), the synchronism block (3) being able to generate at regular intervals ( _sampling ) opening control signals (S _mi ) of the evaluation switches (mi), so that during a current transient (I) the variation of the charge of the different capacitors (C) through the evaluation switches starts at regular intervals (t _sampling ), being possible to characterize from the states of charge of the densifiers (C) the approximate time profile of the current transient integral (I). 2. Device according to the preceding claim, wherein each branch (n _c ) is connected to a common output node (N) through a read switch (oi). 3. Device according to any of the preceding claims, provided with means for restoring the potential of the capacitors at a given voltage (V _dd ). 4. Device according to the preceding claim, wherein said means comprise two switches (PC) connected at the input and output of each of said evaluation switches (mi). 5. Device according to any of claims 2, 3 or 4, comprising an amplifier arranged between each capacitor (C) and the output node (N). 6. Device according to any of the preceding claims, the memory block (2) has the capacitors (C), and their associated switches (mi, pe), organized in two identical banks. 7. Device according to any one of the preceding claims, wherein the synchronization block (3) comprises a chain of monostable cells. Device according to any one of the preceding claims, in which the synchronization block (3) comprises two synchronization sub-blocks (A, B) connected to each other. 9. Device according to any of the preceding claims, comprising a detection block (4) configured to detect the start of a current transient (I). Device according to the preceding claim, wherein said detection block (4) comprises a capacitor (C _d ), a switch (mi) that connects the output of said transistor block of the logic gate (1) to a branch (n _c ) towards said capacitor (C _d ) and means for emitting a detection signal from a load threshold value of said capacitor (C _d ). 11. Device according to the preceding claim, wherein said means for emitting a detection signal consists of a Schmitt trigger. 12. Device according to any combination of the preceding claims, comprising a control unit (5) configured to control the synchronism generator block (3) based on external setpoints and the signals emitted by the detection block (4). 13. Device according to any of the preceding claims, wherein the logic gate (1), the memory block (2), the synchronism block (3) and the detection block (4) are integrated in the same substrate. 14. Device according to any of the claims, comprising a block of induced current generation (6) capable of supplying a current to said memory block (2) for calibration. 15. Device according to the preceding claim, wherein said current-induced generation block 6 comprises a monostable connected to the gate of a transistor. 16. Device according to any of the preceding claims, comprising an attenuation block (7) connected to the memory block input (2). 17. Device according to the preceding claim, wherein said attenuation block (7) is a transistor. 18. Device according to any of the preceding claims, wherein each branch (n _c ) is connected to a common output node (N) through a read switch (oi). 19. Device according to any of the preceding claims, wherein said transistor block of a logic gate (1) is made with CMOS technology. 20. Method for characterizing current transients (I) produced by interaction of ionizing particles with a CMOS logic gate (1), in which a device according to any of the preceding claims is used, comprising the steps of: -replicate said current (I) to send it to said outputs, -seed sequentially and at regular intervals (t _sampling ) the different evaluation switches (mi), so that during a current transient (I) the variation of charge of the different capacitors (C) starts at regular intervals (t _sample ), being possible to characterize from the charge states of the capacitors (C) the approximate temporal profile of the transient integral of current (I).