WO2010151340A1

WO2010151340A1 - Thin film solar module fabrication

Info

Publication number: WO2010151340A1
Application number: PCT/US2010/001837
Authority: WO
Inventors: Paul H.J. Beatty
Original assignee: SOL ARRAY LLC
Current assignee: SOL ARRAY LLC
Priority date: 2009-06-26
Filing date: 2010-06-26
Publication date: 2010-12-29
Anticipated expiration: 2011-12-26
Also published as: WO2010151340A8

Abstract

A method for fabricating a thin film solar cell comprising: depositing a first conductive layer to a substrate forming a bottom electrode; forming a semiconductor junction comprising a p-type semiconductor and an n-type semiconductor; depositing a second conductive layer forming a top electrode; determining a voltage measure for application to the semiconductor junction; placing the semiconductor junction in reverse bias mode by applying the voltage measure to the top electrode and the bottom electrode; applying the voltage measure below a predetermined breakdown value to increase efficiency of the solar cell.

Description

DESCRIPTION TITLE

THIN FILM SOLAR MODULE FABRICATION PRIORITY CLAIM

[0001] This application claims priority benefit from U.S. provisional application Ser. No. 61/220,577 filed on June 26, 2009, the entire disclosure of which is incorporated herein by reference for all purposes.

TECHNICAL FIELD

[0002] Embodiments of this invention relate to fabrication methods of solar cells and modules, and their performance.

BACKGROUND

[0003] Thin film solar cells promise lower cost, large area arrays of efficient electricity generation for public utility usage. In the case of copper indium gallium diselenide (CIGS) films, the theoretical maximum of efficiency of 25% is limited to about 19% at best, for various reasons. These include resistance paths, and also shunting of the p-n junction, particularly in modules having cells connected in series as a monolithic structure.

[0004] In Figure 1, a typical solar cell is shown in cross section with a bottom

Mo electrode, then a p-type CIGS layer followed by CdS, then undoped i-ZnO followed by a conducting n-doped ZnO:Al electrode. Actually, the n-type junction to create voltage arises from n-doping of the CIGS by Zn or Cd ions during annealing.

[0005] Shunting of the junction can occur by pin holes in the CIGS film due to removal of particulates in processing, and these holes are filled in by subsequent deposition of the top conductive material, n-ZnO:Al, a transparent oxide, used for the top electrode.

[0006] In prior art, the use of CdS and i-ZnO is for various purposes, including insulation of the pin holes. Modules of CIGS solar panels include exposed regions of Mo to enable series connection of adjacent cells with n- ZnO conducting material from the top of one cell to the Mo bottom electrode of the adjacent cell. Depositing i-ZnO before n-ZnO requires removal from the vacuum system and scribing of the CIGS layer covered with i-ZnO to expose the Mo. Scribing may not fully remove the thin layer of i-ZnO, and can also damage the underlying Mo electrode.

[0007] Cations of both Zn and Cd can dope the upper layer of the CIGS film to make it an n-type semiconductor, and hence form part of the photovoltaic p- n junction. However, such cations may also be added with just a solution of Cd salt, or with a source of zinc alone. Thus, CdS and i-ZnO may not be entirely successful to insulate the pin holes, and a complete layer of insulating CdS may be considered too toxic compared with using limited amounts of Cd salt, or even just zinc materials.

[0008] Particulates can arise from contamination of substrates before loading into vacuum chamber, or within the vacuum chamber. This can happen for evaporated films but particularly for sputtering. The advantage of sputtering thin films includes speed and cost effectiveness, compared to evaporation or use of wet processing. However, particles occur when CIGS films are deposited by sputtering from targets of pressed tiles, that is ones made by pressing powders such as the four elements Cu, In, Ga and Se. Alternatively, the target is an alloy of Cu, In, and Ga, in which case selenization of the films can be done after deposition such as with selenium vapor. Similar pin hole effects are known for sputtering ZnS and indium tin oxide, as well as many others¹.

[0009] Avoiding voids in the target tiles helps to reduce particle contamination, but even with hot pressing techniques the density is often not as high as necessary to avoid the creation of some residual particles. Another source of pin holes is from growth of the CIGS layer as influenced by the grain structure, adhesion and morphology of the underlying Mo electrode.

[00010] Moreover, the pinhole problem is worse as the thickness of the film decreases in relation to the size of the contaminating particle. On the other hand, there is a need to reduce CIGS thickness below a micron to reduce cost of materials, especially scarce indium. Also, as film thickness is reduced there is less chance of losing electrons and holes by their recombination.

[00011] Traditionally, the use of an insulating layer of i-ZnO before the conducting layer n-ZnO is beneficial in dealing with shunting pinholes in the CIGS layer. However, most work has been done by evaporating CIGS rather than the lower cost method of sputtering.

[00012] Also, given that i-ZnO is an insulator, its position under the top n-

ZnO:Al electrode would seem to be inappropriate for conduction of current. However, it is a relatively thin layer and diffusion occurs during annealing, so its insulating effect may decrease by some diffusion of the Al into it from the adjacent thicker top n-ZnO:Al electrode. This will need to occur at the top of the CIGS layer for the device to function, but may not be totally successful. It could also occur also at the bottom of pinholes in the CIGS layer, and at the top of the pin holes shorting out the p-n junction. So, to some extent, even when using i-ZnO and CdS there may be a conductive pathway through these pin holes, and also across the exposed faces of the p-n junction at the other end of the pin hole. In the absence of insulating buffer layers such as i-ZnO or CdS, this effect will be exaggerated.

SUMMARY

[00013] This invention relates particularly to improving the efficiency of CIGS solar cells and modules, wherever pin-holes can develop in the CIGS layer. This includes films deposited by sputtering, and where layers of CdS or i-ZnO are undesirable. The object is to remove short circuit paths between the top and bottom electrodes, and even paths across exposed areas of the p-n junctions at the top side of pin holes. In particular, this invention minimizes or eliminates the need for insulating films such as zinc oxide (i-ZnO) or cadmium sulfide (CdS), relying for doping effects on deposits of metals or salts of cadmium, zinc or other divalent cations followed by thermal annealing.

[00014] In one embodiment of the invention, there is a reverse bias voltage applied to the p-n junction. Sufficient voltage is applied to allow a high current density in the small pin holes filled with n-ZnO. Such voltage may be applied continuously or advantageously as pulses until the conductive pin holes are burnt out, much like electrical fuses. Proper pulse length and duty cycle can avoid propagation of pin holes causing film damage over a larger area.

[00015] Meanwhile, the p-n junction of the device remains intact as much less current is passed in the reverse bias mode of such a diode configuration.

[00016] This technique is similar to work on electroluminescent films using a sandwich of zinc sulfide between dielectric layers, although in this case there is no p-n junction. [00017] In other embodiments, an insulating layer is formed on the Mo electrode at the bottom of pin holes, or the Mo is removed by selective etching.

BRIEF DESCRIPTION OF DRAWINGS

[00018] FIG. 1 illustrates a cross section of a CIGS solar cell; and

[00019] FIG. 2 illustrates pinholes in the CIGS layer of the solar cell.

DESCRIPTION OF EMBODIMENTS

[00020] Figure 1 shows a cross section of a typical CIGS cell. (1) is a soda lime glass substrate with a thickness typically 1.0 mm. (2) is a thin film of molybdenum (Mo) about 0.35 microns thick. (3) is a thin film of CIGS about 0.5 to 1.5 microns thick, but typically 1.0 microns, and shows grain sizes of similar size. (4) is cadmium sulfide, CdS, 0.05 microns thick. (5) is intrinsic zinc oxide, i-ZnO, about 0.1 microns thick. (6) is conductive n-ZnO:Al, about 0.35 microns thick. (7) is nickel, about 0.05 microns thick as part of a top grid to strengthen the top contact conductivity. (8) is aluminum, about 3.0 microns thick, also as part of the top grid. (9) is a further layer of nickel, about 0.05 microns thick, to protect the aluminum. (10) is a cover glass of soda lime glass, about 1.0 mm thick. [00021] Figure 2 shows pin holes in the CIGS film layer. Numbers have the same designation as in Figure 1. Layers (4), (5) and (6) are shown amalgamated in the same order of deposition as in Figure 1. Item (6) is the conductive form of ZnO doped with Al. Item (5) is deposited as the undoped non conductive i-ZnO. (1 1) are pinholes

[00022] Embodiment 1. As shown in Figure 2, pin holes (1 1) can be present within the CIGS layer (3). These arise by inclusion of particulates such as dust or debris, from scribing the cell bottom electrode for series linkage. On removal from the vacuum chamber after deposition of the CIGS layer so that it also can be scribed, projecting particles can be removed and also during subsequent handling operations. Additional deposited films can fill these holes leading to a conductive pathway and lower device efficiency.

[00023] In particular, the additional films include conducting thin films of n-

ZnO (6) (0.35 microns) or other transparent conducting oxide. Certain diffusion of cations and anions can occur in annealing of all the deposited films to provide the p-n junction just below the top of the CIGS layer.

[00024] In prior art, reliance is placed on use of insulating films such as CdS

(4) and i-ZnO (5). In some cases, it is preferably to omit the CdS to simplify fabrication, avoid its environmental toxicity and avoid its greater absorption of lower wavelength sunlight. Usually, the CdS layer is applied using a chemical bath deposition (CBD) consisting of a heated solution of cadmium sulphate, ammonium hydroxide and thiourea. This procedure is quite different to the vacuum deposition in terms of its better coating of CIGs, being epitaxial, but on the other hand it is a time consuming wet process that can also dislodge particles in the CIGS to produce pinholes. Cadmium salt solutions are found to be as effective for doping the CIGS as layers of insulating CdS. Additionally, vacuum deposition of an extremely thin layer of cadmium metal may be sufficient for doping in combination with later annealing.

[00025] In prior art, the bottom of pinholes in the CIGS layer has CdS and then i-ZnO followed by n-ZnO. Annealing can convert the i-ZnO to n-type from its proximity to aluminum doped ZnO. This helps contact at the top electrode, but leads to some short circuiting of the bottom Mo (2) at pin holes in contact with the top n-ZnO electrode. [00026] Also, with thinner CdS, used to avoid absorption of lower wavelength sunlight, its insulating nature at the bottom of the pinholes may not be preserved, due to non uniformity of thickness and cracks.

[00027] Normally, the device operates by producing a low output voltage up to about 0.8 V open circuit. In the first embodiment of this invention, an external voltage is applied with positive polarity to the n-ZnO, and negative to the Mo bottom contact. This puts the p-n junction into reverse bias mode in which little current can flow up to a breakdown value.

[00028] Using a voltage below that of the breakdown value, but sufficient to generate enough current for fusion and disruption of the conductive pin hole pathways is the essence of this embodiment.

[00029] Calculations show that applying voltage below the likely breakdown voltage of a reverse biased CIGS p-n junction will be sufficient to melt and vaporize the n-ZnO in pin holes. This assumes a typical resistivity of 4 x 10^"4 Ohm cm, a maximum of 5 V, with pin hole diameter and length of 1.0 microns. For these conditions, resistance of the pin hole from top to bottom is about 2.5 Ohms, and power dissipated is about 8.1 x 10⁸ W per sq inch.

[00030] By comparison, thin film resistors can rise 0.04 deg C per W/sq inch.

Assuming a similar order of specific heat and film resistance, then the local confined temperature rise for the CIGS pinhole will be about 3.2 x 10⁸ deg C. Clearly, this would be more than sufficient to melt and vaporize the ZnO which has a melting point of 1975 degrees C. The essence here is in confinement of the power both spatially and temporally. Using pulses ensures that there is insufficient time for the heat to conduct fully into the surrounding area of film or Mo on glass beneath. Indeed, the Mo is thermally heat sunk from its intimate contact with the large mass of the glass substrate.

[00031] It is assumed also that there will be insufficient time for any field induced diffusion of ions in response to the reverse biased applied voltage. This ensures the doped junction regions remain intact.

[00032] Applied voltage can be from 2 to 10V, but more typically 4 volts.

Pulse lengths can be 5 microseconds to 100 microseconds, more typically 20 microseconds. Duty cycle can be from 10^~6 to 0.5 per cent, typically 7 x 10^"4 per cent.

[00033] This technique may be applied to improving prior art devices that use

CdS, i-ZnO or both, or with some alternative insulating layers. It may also be used preferably with doping of the CIGS layers by metal or metal salts, such as cadmium and zinc.

[00034] Embodiment 2. Another method to removing the effect of short circuit paths through conductive pin holes is to fill the holes selectively with an insulating material. Thus, the underlying bottom electrode can be treated as an anode in an electrolytic cell so as to form within the pin holes an insulating layer of oxide on the Mo by anodization. Indeed, processes are well known to those versed in the art for forming insulating oxides such as anodization of aluminum. Furthermore, the electric field will be higher in the pin holes due to geometric sharp edges, and also the Mo bottom contact being more conductive than the overlying layer of CIGS. This should help ensure the CIGS layer itself is not affected.

[00035] Thus, A.G. Gad-Allah² et al show very insulating films of molybdenum dioxide are formed in various 0.2 M salt solutions buffered to pH 9.3, at lmA/sq cm. Examples of salts include sodium halides, sulfate, nitrate, nitrite, oxalate, citrate, and acetate among others. This technique can be applied to the CIGS devices to insulate the pin holes.

[00036] Embodiment 3. In the third embodiment of this invention, Mo in the pinholes can be etched away selectively compared to the CIGS film.

[00037] Also, the methods shown here can apply to other thin film solar cells.

These include those using various compositions of copper, indium, gallium and selenium, and including substitution of some selenium by sulfur. Such compositions can be those without any gallium (CIS).

[00038] Other materials can be used for Mo anodization or etching, whatever is optimum and satisfies the essence of the relevant embodiments as understood by those skilled in the art. Equally clear to those skilled in the art, is applicability to materials other than those given in the examples quoted. Thus, the material absorbing sunlight could be other thin film material such as cadmium telluride, copper gallium selenide, copper indium gallium selenide/sulfide (selective substitution of selenium with sulfur). Likewise, the top and bottom electrodes could be other metals and semiconductors. Furthermore, other materials may be substituted for the doping effect of buffer layers of CdS and i-ZnO. The absorbing layer of CIGS or other materials may be deposited by any alternative means than sputtering such as by vacuum evaporation.

CITATION LIST

[00039] Non-Patent Literature

[00040] 1. D. Samsonov and J. Goreea, Particle growth in a sputtering discharge, Department of Physics and Astronomy, The University of Iowa, American Vacuum Society. (1999) 41] 2. A.G.Gad-Allah, H.A. ABD El-Rahman, J. Appl. Electrochemistry,

Vol. 18, (1988) pp. 312-313

Claims

Claim 1 A method for fabricating a thin film solar cell comprising: depositing a first conductive layer to a substrate forming a bottom electrode; forming a semiconductor junction comprising a p-type semiconductor and an n-type semiconductor; depositing a second conductive layer forming a top electrode; determining a voltage measure for application to the semiconductor junction; placing the semiconductor junction in reverse bias mode by applying the voltage measure to the top electrode and the bottom electrode; applying the voltage measure below a predetermined breakdown value to increase efficiency of the solar cell.

Claim 2 The method for fabricating a thin film solar cell of claim 1, wherein the voltage measure is between 2 volts and 10 volts.

Claim 3 The method for fabricating a thin film solar cell of claim 1, further comprising: determining a pulse length for application of the voltage measure.

Claim 4 The method for fabricating a thin film solar cell of claim 3, wherein the pulse length is between 5 microseconds and 100 microseconds. Claim 5 The method for fabricating a thin film solar cell of claim 1, further comprising: determining a duty cycle for application of the voltage measure.

Claim 6 The method for fabricating a thin film solar cell of claim 5, wherein the duty cycle is between .000001 percent and .5 percent.

Claim 7 The method for fabricating a thin film solar cell of claim 1, wherein the step of placing the semiconductor junction in reverse bias mode further comprises: applying a positively polarized voltage to the top electrode; and applying a negatively polarized voltage to the bottom electrode.

Claim 8 The method for fabricating a thin film solar cell of claim 1, further comprising: depositing an absorbent material layer above the bottom electrode wherein the bottom electrode is more conductive than the absorbent material layer.

Claim 9 The method for fabricating a thin film solar cell of claim 8, wherein the absorbent material layer comprises a chalcopyrite crystal structure and an optical bandgap, the optical bandgap being between 1.OeV and 1.7eV.

Claim 10 The method for fabricating a thin film solar cell of claim 9, wherein the absorbent material layer comprises a composition of Copper, Indium and Selenium (CIS). Claim 1 1 The method for fabricating a thin film solar cell of claim 9, wherein the absorbent material layer comprises a composition of Copper, Indium, Gallium and Selenium (CIGS).

Claim 12 The method for fabricating a thin film solar cell of claim 8, further comprising: depositing an insulating layer coupled to the absorbent material layer.

Claim 13 The method for fabricating a thin film solar cell of claim 9, wherein the insulating layer coupled to the absorbent material layer comprises a composition of CdS.

Claim 14 The method for fabricating a thin film solar cell of claim 9, wherein the insulating layer coupled to the absorbent material layer comprises a composition of i- ZnO.

Claim 15 A method for fabricating a thin film solar cell comprising: depositing a first conductive layer to a first substrate forming a bottom electrode; depositing an absorbent material layer above the bottom electrode wherein the bottom electrode is more conductive than the absorbent material layer; depositing an insulating layer coupled to the absorbent material layer; forming a semiconductor junction comprising a p-type semiconductor and an n-type semiconductor; depositing a second conductive layer forming a top electrode; forming an oxide based insulating layer through anodization to increase efficiency of the solar cell.

Claim 16 The method for fabricating a thin film solar cell of claim 15, further comprising: depositing the first conductive layer to the first substrate forming the bottom electrode wherein the first conductive layer includes a composition of Molybdenum; anodizing a metal layer to increase thickness of the oxide based insulating layer; forming, through annodization of the metal layer, the oxide based insulating layer on the composition of Molybdenum to selectively remove a plurality of pinholes in the absorbent material layer.

Claim 17 The method for fabricating a thin film solar cell of claim 16, wherein the metal layer is a composition of Aluminum.

Claim 18 A method for fabricating a thin film solar cell comprising: depositing the first conductive layer to the first substrate forming the bottom electrode wherein the first conductive layer includes a composition of

Molybdenum; depositing an absorbent material layer above the bottom electrode wherein the bottom electrode is more conductive than the absorbent material layer; depositing an insulating layer coupled to the absorbent material layer; forming a semiconductor junction comprising a p-type semiconductor and an n-type semiconductor; depositing a second conductive layer forming a top electrode selectively etching the composition of Molybdenum to increase efficiency of the solar cell.

Claim 19 The method for fabricating a thin film solar cell of claim 18, wherein the step of selectively etching, further comprises: using a mineral acid etchant with an etch mask.

Claim 20 The method for fabricating a thin film solar cell of claim 18, wherein the step of selectively etching, further comprises: reactive ion etching; and removing an oxide film produced from the selective etching.