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WO2010023756A1 - Processeur d’informations comprenant un processeur virtuel, procédé de traitement d’informations, et programme - Google Patents

Processeur d’informations comprenant un processeur virtuel, procédé de traitement d’informations, et programme Download PDF

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Publication number
WO2010023756A1
WO2010023756A1 PCT/JP2008/065561 JP2008065561W WO2010023756A1 WO 2010023756 A1 WO2010023756 A1 WO 2010023756A1 JP 2008065561 W JP2008065561 W JP 2008065561W WO 2010023756 A1 WO2010023756 A1 WO 2010023756A1
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WIPO (PCT)
Prior art keywords
real
processor
cpu
virtual
register
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Ceased
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PCT/JP2008/065561
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English (en)
Japanese (ja)
Inventor
正治 吉山
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to PCT/JP2008/065561 priority Critical patent/WO2010023756A1/fr
Publication of WO2010023756A1 publication Critical patent/WO2010023756A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources

Definitions

  • the disclosed technology relates to processor control in information processing.
  • an information system including an information processing device such as a server computer
  • some CPUs may fail in an information system including a plurality of CPUs, and the CPUs may be disconnected. In some cases, the CPU is replaced with a new CPU instead of the failed CPU.
  • the performance needs to be increased and the CPU may be increased.
  • change processing In order to notify the OS of the change result from the hardware and change the subsequent processing, various adjustment processes are required between the OS and the hardware.
  • B When the application program is operating in consideration of the configuration of the CPU, various adjustment processes are required between the application program and the OS in response to the CPU change notified from the OS to the application program.
  • the OS acquires hardware configuration information including the CPU at the time of booting. Further, the application program obtains its configuration information when it is activated. However, some OSs cannot acquire such configuration information during system operation. In such an information system, a system change is accompanied by a restart. Therefore, the operation in operation is stopped.
  • PRIMEPOWER / SPARC Enterprise registered trademark
  • the CPU requests the OS to take the CPU offline.
  • the OS takes the CPU offline.
  • OBP OpenBoot TM PROM
  • the OS when executing a DR (Dynamic Reconfiguration) function, the OS changes the process according to the hardware configuration change.
  • This function makes it possible to add a CPU and memory while the information system is operating. It can be said that these can be realized because the hardware and the OS are developed in a close relationship. This is largely due to the fact that the vendors developing the hardware and OS are the same. If this is not the case, for example, in the case of a server configured by providing the same hardware by a plurality of vendors and providing an OS by another vendor in such a system, adjustment of each hardware and the OS is required. Become. As such a system, an example in which an OS supplied from a vendor dedicated to the OS is incorporated to configure the system can be exemplified. A system incorporating an OS supplied as open source software also falls under this category.
  • the application program when the application program is operating in consideration of the number of CPUs, the application program must acquire the number of CPUs that can be acquired through the change of the CPU number notified from the OS or the API. If this dynamic change in the number of CPUs is not supported, it is necessary to restart the application program. If the application is not restarted, the application may malfunction, or sufficient performance may not be exhibited. If the OS does not support changing the number of CPUs, the application cannot be aware of the change at all.
  • OS or application program If the existing OS or application program is not compatible with the replaced CPU, the OS or application program must be updated to a version OS corresponding to the replaced CPU. As a result, OS and application update costs and operation verification costs are incurred in addition to the CPU replacement costs.
  • an object of the technology of the present disclosure is to provide a system that can minimize the influence on the OS or application program due to a change in the hardware configuration.
  • a storage device that stores firmware for forming a plurality of real processors and a virtual processor that is executed by any one of the real processors and includes any one or more of the plurality of real processors Is exemplified by an information processing apparatus comprising:
  • the real processor has a real register that manages the execution state of each process.
  • the virtual processor includes a configuration storage unit that stores the configuration of a real processor included in the virtual processor, an activation unit that accepts activation of a process, a virtual register that accepts activation and manages an execution state of a process being executed A real processor activation unit that copies the value of the virtual register to a real register of any real processor included in the virtual processor that has received the activation, and causes the real processor to execute processing managed by the virtual register.
  • the virtual processor once accepts the activation, and then activates the processing in any of the real processors included in the virtual processor. Therefore, the OS for starting the processor, the process managed by the OS, and the application program executed by the process need only be aware of the number of virtual processors, the virtual processor instruction set, and the like. Changes in the number of real processors and instruction sets included in the virtual processor may be absorbed by the processing of the virtual processor.
  • the influence on the OS or application program due to the change of the hardware configuration can be minimized.
  • FIG. 1 is a figure which illustrates the outline
  • FIG. is a figure which illustrates the procedure which dispatches a process. It is a figure which illustrates the process which monitors the error which generate
  • FIG. 1 illustrates an overview of the information system.
  • This information system includes a hardware layer having a plurality of real CPUs (also referred to as real processors), a firmware layer that combines one or a plurality of real CPUs to form a virtual CPU (also referred to as a virtual processor), and a virtual CPU.
  • a service processor that monitors an operating OS (operating system), an application program (hereinafter simply referred to as an application) executed under the management of the OS, and a hardware layer and manages a configuration of a virtual CPU in a firmware layer And a state monitoring device connected to the service processor and providing a user interface.
  • the hardware layer has the same configuration as that of a normal computer, and includes a plurality of real CPUs in this embodiment.
  • the real CPUs are exemplified by R-CPU1 to R-CPU5.
  • These real CPUs are processors that constitute a general computer, and are normally activated in accordance with an activation instruction from the OS, and a process managed by the OS is scheduled and assigned to execute information processing. However, in this information system, the real CPU is assigned a process to be executed through the virtual CPU.
  • the firmware layer forms a plurality of virtual CPUs.
  • V-CPU1 to V-CPU3 are illustrated as virtual CPUs.
  • the V-CPU 1 includes an R-CPU 1 and an R-CPU 2.
  • the V-CPU 2 includes an R-CPU 3 and an R-CPU 4. However, here, the R-CPU 4 is off-line and disconnected. Further, the V-CPU 3 includes an R-CPU 5.
  • the virtual CPU is an information processing function formed by firmware. Similarly to the conventional real CPU, the virtual CPU also accepts a startup command from the OS and executes information processing. However, the process of the virtual CPU is a virtual process on the firmware.
  • the firmware is a program stored in a ROM (Read Only Memory), a flash memory or the like.
  • the firmware includes a program (instruction sequence) and a register group that form a virtual CPU.
  • the processing of a virtual CPU is realized by one real CPU executing firmware.
  • a process realized by the real CPU executing the firmware is simply referred to as a virtual CPU process.
  • a list of real processors that constitute the virtual CPU is defined for the virtual CPU.
  • the register group of the virtual CPU includes, for example, a register indicating an execution state of a process to which processing is assigned, a register instructing execution of a process, a register instructing a next execution address when an interrupt occurs. included.
  • the virtual CPU is assigned a process according to the OS scheduling and receives a start command. Then, the virtual CPU reads a list of real CPUs constituting the virtual CPU, and assigns a process assigned to the virtual CPU to the real CPU according to a predetermined scheduling.
  • the scheduling procedure in which the virtual CPU assigns a process to a real CPU is the same as that of conventional OS scheduling, and there is no particular limitation.
  • the virtual CPU copies the contents of the register group of the process managed by itself to the register of the real CPU to which the process is assigned, and starts execution of the real processor.
  • the actual processor is activated.
  • a value is set in a specific activation register.
  • the head address of the instruction sequence is set in the program counter.
  • a virtual CPU that has been assigned and started a process from the OS passes the state of the process as it is to the real process and starts processing. In this way, assigning a process to the CPU and starting the process is also called dispatching.
  • the application and the OS are executed on the virtual CPU.
  • various hardware such as the type of CPU, the number of CPUs, and the operating frequency can be prepared as virtual hardware recognized by the OS.
  • This relationship is defined by a service processor (SVP) that is a system controller.
  • SVP service processor
  • the service processor provides a user interface and defines a relationship between the virtual CPU and the real CPU on the firmware according to the user operation. This defined relationship is also called mapping.
  • mapping This defined relationship is held in a register on the virtual CPU (actually, a rewritable ROM such as a flash memory or an EEPROM). This definition is, for example, the following information.
  • the meaning of the definition formula in the first row means that the V-CPU 1 that is a virtual CPU includes R-CPU 1 and R-CPU 2 that are real CPUs. The same applies to the second and third lines.
  • the service processor sets, for the OS, the type and number of virtual CPUs, and the location of each virtual CPU register (for example, the position in the address space). Thereby, on this information system, three virtual CPUs are defined for five real CPUs, and the OS recognizes them as a system including three CPUs.
  • the virtual CPU can also define the emulation of the real CPU architecture.
  • Architecture emulation is instruction set translation. That is, when the instruction set related to the CPU architecture is different between the virtual CPU and the real CPU, and the conversion from the instruction sequence of the virtual CPU to the instruction sequence of the real CPU is possible, the conversion table is Define it. In this conversion table, a virtual CPU instruction and a real CPU instruction are set in pairs. Then, when a virtual CPU instruction is given, the conversion table is searched using the virtual CPU instruction as a key to acquire the real CPU instruction.
  • SPARC Enterprise registered trademark
  • PRIMEPOWER registered trademark SPARC (registered trademark) 64V
  • the OS recognizes a fixed number of virtual CPUs defined on the firmware.
  • the OS is executed by any real CPU.
  • the OS dispatches the process to the real CPU (passes the process) in accordance with the OS mechanism for the application running on the OS.
  • the OS dispatches a process
  • a request for starting the process by the dispatch is once accepted by the virtual CPU.
  • the virtual CPU that has received the request from the OS further dispatches the process to each real CPU in the firmware.
  • the application is executed by the virtual CPU instead of the conventional real CPU.
  • the application recognizes a fixed number of virtual CPUs, the software including the OS and the application need not be aware of the change in the number of CPUs.
  • the number of software licenses is set based on a virtual CPU by contract, the number of licenses is fixed regardless of the number of actual CPUs. Therefore, it is possible to set a contract that does not cause a problem of an increase in the number of licenses.
  • the virtual CPU separates (degenerates) the real CPU where the error is detected, and the virtual CPU The CPU continues to operate. At this time, the failed information is notified to the service processor and stored in a log.
  • a real CPU is added to the virtual CPU to be added. This process is performed by an operator's operation through the service processor. Thereafter, for an application operating on the virtual CPU, the process is dispatched to each real CPU in the virtual CPU, and the process is continued.
  • the processing capacity of the virtual CPU is improved by adding the real CPU, and the processing capacity of the information system is improved while the number of CPUs recognized by the OS and application (in this case, the number of virtual CPUs) remains fixed.
  • FIG. 2 is a diagram illustrating the configuration of the server 1 according to the first embodiment.
  • the server 1 includes a processor group 11, a memory 12, an I / O 13, firmware 14, and a service processor 15.
  • the processor group 11 includes a plurality of real CPUs.
  • the plurality of real CPUs share a bus and are activated by being identified by the address of the activation register on the bus.
  • the memory 12 stores firmware 14 and defines a virtual CPU.
  • the virtual CPU is realized by executing a virtual CPU control program on the firmware 14 by any real CPU.
  • a real CPU that loads a virtual CPU control program on firmware may be set for each virtual CPU, for example.
  • an OS and an application are further executed on the virtual CPU.
  • the firmware 14 defines the relationship between the virtual CPU (V-CPU1 to V-CPU3) and the real CPU (R-CPU1 to R-CPU5), maintains the state of the real CPU corresponding to the virtual CPU, and changes from the virtual CPU to the real CPU. Dispatch function.
  • the service processor 15 has a function of setting the definition of the relationship between the virtual CPU and the real CPU in the firmware.
  • the service processor 15 is a computer including a CPU, a memory, and an external interface.
  • the service processor 15 in addition to the above, the following functions are also provided. (1) Partition settings (2) Status monitoring of server environment abnormalities, hardware abnormalities, etc. (3) Power supply control (4) Collecting logs This service processor 15 can be connected from the client 20 and on the client 20 Settings can be made through the user interface.
  • the client 20 is a personal computer, for example.
  • the I / O 13 is an interface to, for example, an external storage device (hard disk), an input / output device (network board, printer, scanner), other input devices (switch, keyboard), and the like.
  • an external storage device hard disk
  • an input / output device network board, printer, scanner
  • other input devices switch, keyboard
  • the client 20 connects to the service processor 15 and defines a virtual CPU on the firmware 14.
  • the defined contents are stored in a definition table (corresponding to the configuration management unit) on the memory 12.
  • FIG. 3 and Figure 4 show examples of definitions.
  • a V-CPU 1 that is a virtual CPU is composed of an R-CPU 1 and an R-CPU 2.
  • the V-CPU 2 is composed of an R-CPU 3 and an R-CPU 4.
  • the R-CPU 5 is further included as a real CPU, but it is in a standby state without being incorporated into the virtual CPU. In this case, the real CPU in the standby state may be reserved for future function enhancement. Moreover, you may hold
  • a virtual CPU and a real CPU may be mapped on a one-to-one basis.
  • the virtual CPU can be operated in the same manner as a normal computer or server.
  • the architecture of the virtual CPU may be selected simultaneously with the definition of the virtual CPU, and the instruction set conversion from the virtual CPU to the real CPU may be designated.
  • FIG. 5 illustrates the structure of a definition table that stores the result of defining a virtual CPU.
  • FIG. 6 shows a data example of a definition table that defines virtual CPUs.
  • the definition table includes a virtual CPU number (V-CPU number), an architecture, a real CPU number (R-CPU number), a real CPU physical number (R-CPU physical number), and a real CPU state (R-CPU state). including.
  • the definition table is stored in the nonvolatile memory on the bus by the service processor 15.
  • Architecture is a type of instruction set.
  • the architecture is specified as SPARC (registered trademark) VII, for example.
  • the real CPU physical number is a unique number for the virtual CPU to identify each real CPU.
  • FIG. 7 shows an example of the real CPU start register table in which the relationship between the real CPU number and the start register address is defined.
  • the actual CPU activation register table is defined in the nonvolatile memory on the bus.
  • the virtual CPU reads the real CPU start register table of FIG. 7 based on the real CPU number and starts the corresponding real CPU.
  • FIG. 8 shows an operation example of the server 1. According to the definition of the virtual CPU by the service processor 15, an area for holding a register group for the real CPU and a virtual register for the virtual CPU are newly secured on the firmware 14.
  • the operation procedure of the system shown in FIG. The correspondence relationship between the real CPU and the virtual CPU is already defined in the form of FIG. 3 or FIG. 4 by the service processor 4, and the real CPU and the virtual CPU are stored in the nonvolatile memory in the form of FIG. 5 or FIG. Is stored.
  • (2) One of the real CPUs starts executing the firmware from the specific memory where the firmware exists.
  • This real CPU is one of the CPUs mounted on hardware.
  • the R-CPU 1 will be described as the first activated CPU.
  • a CPU for which firmware is activated may be determined for each virtual CPU. In that case, in the case of a plurality of virtual CPUs, one real CPU is started up.
  • the R-CPU 1 executes the firmware, the status of all the real CPUs is scanned, and the status of the real CPU is written in the created table as shown in FIG.
  • the CPU state is, for example, activated (online), not activated (offline), or the like.
  • the R-CPU 1 defines a real CPU with a small physical CPU physical number defined in the table of each virtual CPU defined in the table (in the example of FIG. 3, in the V-CPU 2
  • the corresponding R-CPU 3 starts execution of the program from the specific memory where the firmware exists.
  • the real CPU cannot be started in (3-1), that is, if it is not online on the table, specify the specific memory where the firmware exists in the real CPU of the next physical number. Start program execution.
  • the real CPU transfers control to a specific exception address and executes exception processing.
  • the OS acquires information on the number of CPUs in order to perform process scheduling internally. At this time, an acquisition command is issued. If this command is issued, control is transferred to the firmware as shown in (4) above, and the CPU status is returned by returning the information in the table shown in FIG. 6 to the OS. (CPU installed number, CPU architecture, vendor, etc.) Thereafter, the OS starts operation based on these pieces of information, assuming that there are a plurality of processors (number of virtual CPUs).
  • the virtual CPU to which the process is dispatched further dispatches the process to each real CPU.
  • the processing of the virtual CPU is performed, for example, by copying a register group held in the virtual CPU to the real CPU and starting the processing of the real CPU.
  • the value is returned from the register group saved on the virtual CPU.
  • the process returns the value from the register group saved on the virtual CPU.
  • Such processing of the virtual CPU is the same as the process context switch by the OS of a normal computer.
  • the instruction is converted, and the emulation is performed by executing the processing with the real CPU. That is, when an architecture is defined for a virtual CPU and the architecture is different from the architecture of a real CPU, the virtual CPU may perform instruction conversion when processing is dispatched. There are two methods for this conversion.
  • Method 1 The first is a case where the conversion function of the real CPU is used. Some CPUs already have an architecture conversion function. In that case, when defining the relationship between the virtual CPU and the real CPU, the firmware issues an architecture conversion command to the CPU. The architecture of the conversion destination is notified to the real CPU as the CPU type. This notification procedure follows the specifications of each real CPU. For example, Itanium has an instruction to emulate IA-32 and can be switched.
  • Method 2 is a case where conversion is performed in a farm. That is, an architecture conversion table is prepared in the firmware, and the contents of instructions and registers are converted in the firmware based on the table.
  • an instruction or an instruction sequence of an instruction set constituting the conversion destination architecture may be defined for an instruction in the instruction set constituting the conversion source architecture.
  • the processed result is saved in a register group for each real CPU prepared on the virtual CPU.
  • the service processor 15 collects failure information related to various hardware, and also monitors errors that have occurred in the real CPU. If the real CPU error exceeds a certain threshold, the service processor disconnects the real CPU from the virtual CPU. Record the disconnection in the log.
  • the virtual CPU In detaching a real CPU, the virtual CPU first confirms that the real CPU is not in process, deletes the corresponding real CPU from the real CPU on the definition table defining the virtual CPU, and stops dispatching to that real CPU. To do.
  • the real CPU is separated from the virtual CPU, and the number of CPUs seen from the OS does not change.
  • the real CPU may be defined in the definition table and incorporated. That is, information on the corresponding real CPU is newly written on the definition table of the virtual CPU, and dispatching to the real CPU may be started.
  • DR Dynamic Reconfiguration
  • a real CPU for example, replacement of a failed CPU or addition of a real CPU due to improved performance can be considered.
  • the definition of the real CPU is added to the definition table of the virtual CPU to be added. This is due to an operator operation from the service processor. If there is a spare real CPU, it can be incorporated.
  • the virtual CPU dispatches each process to the real CPU and continues the process. The processing capacity of the virtual CPU is improved by adding the actual CPU, and the processing capacity of the OS or application is improved while the number of CPUs is fixed.
  • Fig. 9 illustrates the procedure for dispatching processes.
  • the virtual CPU receives a process dispatch from the OS (S1).
  • a virtual CPU that executes this processing corresponds to the activation unit.
  • the OS restores the process context including the application execution environment to the virtual CPU register.
  • the OS initializes the register of the virtual CPU when the application is initially started.
  • the OS activates the virtual register. For example, a value is set in a register for starting the CPU.
  • the virtual CPU selects one of the real CPUs constituting the virtual CPU (S2). This selection may be made, for example, by round robin. Moreover, you may select the real CPU with the least load among several real CPU. In that case, for example, a queue may be created for each real CPU, and processing may be assigned to the real CPU with the shortest queue. Then, when the real CPU becomes empty, the following processing may be actually executed on the real CPU.
  • the virtual CPU copies the virtual CPU register to the selected real CPU register (S3). Then, the virtual CPU activates the real CPU (S4).
  • a virtual CPU that executes this processing corresponds to a real processor activation unit. This activation is, for example, by setting a value in a real CPU activation register.
  • FIG. 10 exemplifies a process for monitoring an error occurring in the real CPU and managing the separation and addition of the real CPU.
  • This process is performed by the service processor 15 that monitors the system.
  • the service processor 15 monitors the error occurrence status of each real CPU through the bus of the real CPU.
  • the status that is, a flag indicating the occurrence of the error, and a bit pattern indicating the cause of the error are displayed at the address on the bus corresponding to the register indicating the status of the real CPU. Is output.
  • the service processor 15 detects that an error has occurred in the real CPU (S10).
  • the service processor 15 that executes this process corresponds to a monitoring unit.
  • the service processor 15 counts up the occurrence of the number of errors for each real CPU (S11). Then, the service processor 15 determines whether or not the number of errors exceeds a threshold value (S12). If the number of errors does not exceed the threshold, the service processor 15 continues the information system processing as it is (S13). Thereafter, the service processor 15 again monitors the state of the real CPU.
  • the service processor 15 determines whether there is a program running on the real CPU (S14). If there is a program running on the real CPU, the service processor 15 waits until a processing end report is received from the real CPU. In the process end report, a flag indicating a state is set at an address on the bus corresponding to a register indicating the end of the process.
  • the service processor 15 changes the setting of the virtual CPU and stops dispatching from the virtual CPU to the real CPU ( S16).
  • the service processor 15 that executes this processing corresponds to the configuration management unit.
  • the service processor 15 removes the real CPU from the configuration of the virtual CPU, and substantially disconnects the real CPU from the information system. Further, the service processor 15 records the disconnection of the real CPU in a log (S17).
  • the service processor 15 determines whether there is a waiting real CPU (S18). If there is a waiting real CPU, the waiting real CPU is incorporated into the virtual CPU instead of the real CPU separated in S17 (S19). The service processor 15 that executes this processing corresponds to the configuration management unit. Then, dispatch from the virtual CPU to the real CPU is started (S20).
  • the service processor 15 executes the processing for monitoring the number of errors of the real CPU, the separation processing for the real CPU, and the processing for incorporating the standby real CPU shown in FIG.
  • any one of the virtual CPUs may execute the processing of FIG.
  • a function for executing the processing of FIG. 10 may be incorporated in each virtual CPU.
  • the processing of the service processor 15 may be executed by one real processor. That is, a real processor may be provided that provides both the function of executing an application as the real processor and the function of the service processor 15.
  • Computer-readable recording medium A program (firmware) that causes a computer or other machine or device (hereinafter referred to as a computer or the like) including the plurality of real processors to realize any of the above functions can be recorded on a computer-readable recording medium.
  • the function can be provided by causing a computer or the like to read and execute the program of the recording medium.
  • a computer-readable recording medium is a recording medium that stores information such as data and programs by electrical, magnetic, optical, mechanical, or chemical action and can be read from a computer or the like.
  • Examples of such a recording medium that can be removed from a computer or the like include a flexible disk, a magneto-optical disk, a CD-ROM, a CD-R / W, a DVD, a DAT, an 8 mm tape, and a memory card.
  • a hard disk a ROM (read only memory), etc. as a recording medium fixed to a computer or the like.
  • ROM read only memory

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  • Hardware Redundancy (AREA)

Abstract

Les processeurs réels possèdent un registre réel qui gère un état d’exécution. Un processeur virtuel possède une partie stockage de configuration qui stocke la configuration d’un processeur réel intégré dans ce processeur virtuel, une partie démarrage qui reçoit le démarrage du traitement, un registre virtuel qui gère l’état d’exécution du processeur virtuel, et une partie démarrage de processeur réel qui, après la réception de ce démarrage, copie la valeur du registre virtuel dans le registre réel de l’un des processeurs réels intégrés dans le processeur virtuel qui a reçu le démarrage, et démarre le traitement par le biais du processeur réel.
PCT/JP2008/065561 2008-08-29 2008-08-29 Processeur d’informations comprenant un processeur virtuel, procédé de traitement d’informations, et programme Ceased WO2010023756A1 (fr)

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WO2011142042A1 (fr) * 2010-05-14 2011-11-17 株式会社日立製作所 Procédé de visualisation de la fiabilité des serveurs, système informatique, et serveur de gestion
WO2014111771A1 (fr) * 2013-01-15 2014-07-24 International Business Machines Corporation Accès dynamique à des éléments d'exécution par modification de règles d'émission
WO2016121973A1 (fr) * 2015-01-30 2016-08-04 日本電気株式会社 Système de nœud, dispositif de serveur, procédé de commande de mise à l'echelle et programme

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Cited By (10)

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Publication number Priority date Publication date Assignee Title
WO2011142042A1 (fr) * 2010-05-14 2011-11-17 株式会社日立製作所 Procédé de visualisation de la fiabilité des serveurs, système informatique, et serveur de gestion
JP5477602B2 (ja) * 2010-05-14 2014-04-23 株式会社日立製作所 サーバの信頼性可視化方法、計算機システム及び管理サーバ
WO2014111771A1 (fr) * 2013-01-15 2014-07-24 International Business Machines Corporation Accès dynamique à des éléments d'exécution par modification de règles d'émission
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US9928132B2 (en) 2013-01-15 2018-03-27 International Business Machines Corporation Dynamic accessing of execution elements through modification of issue rules
WO2016121973A1 (fr) * 2015-01-30 2016-08-04 日本電気株式会社 Système de nœud, dispositif de serveur, procédé de commande de mise à l'echelle et programme
KR20170109635A (ko) * 2015-01-30 2017-09-29 닛본 덴끼 가부시끼가이샤 노드 시스템, 서버 장치, 스케일링 제어 방법 및 프로그램
JPWO2016121973A1 (ja) * 2015-01-30 2017-11-09 日本電気株式会社 ノードシステム、サーバ装置、スケールリング制御方法及びプログラム
KR102059251B1 (ko) 2015-01-30 2019-12-24 닛본 덴끼 가부시끼가이샤 노드 시스템, 서버 장치, 스케일링 제어 방법 및 프로그램
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