WO2010016564A1 - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device of a low source resistance, which can perform an excellent enhancement action for a high-voltage action.  Over a substrate (101), there are formed a buffer layer (102) made of a first GaN-family semiconductor, a carrier transit layer (103) made of a second GaN-family semiconductor, a carrier feed layer (104) made of a third GaN-family semiconductor, a two-dimensional electron gas dissolving layer (105), which is made of a fourth GaN-family semiconductor and raises the conduction band of the carrier feed layer to the side of a vacuum-order side so that a two-dimensional electron gas may not accumulate in the carrier transit layer, and a low-resistance layer (106) made of a fifth GaN-family semiconductor.  The two-dimensional electron gas dissolving layer (105) and the low-resistance layer (106) are removed by recess-etching at the areas between a drain electrode and a gate electrode and at the areas below a lower portion of the gate electrode and a drain electrode (108).  Then, the remaining side faces of the two-dimensional electron gas dissolving layer (105) and the low-resistance layer (106) are so formed as not to be normal to the surfaces before the removal but to be tapered therefrom.  A source electrode (107) is formed in contact with the low-resistance layer (106), and the drain electrode (108) is formed in contact with the carrier feed layer (104).  Next, a gate-insulating film (109) is formed to form a gate electrode (110).  Finally, a protection film (111) is formed to manufacture a field effect transistor.

Description

Semiconductor device

[Description of related applications]
The present invention is based on the priority claim of Japanese Patent Application No. 2008-204602 (filed on Aug. 7, 2008), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a semiconductor device, and more particularly to a nitride semiconductor device.

Gate-recessed MISFET (Metal Insulated Field Transducer Structure) capable of reducing gate leakage current and operating in enhancement mode in AlGaN (aluminum gallium nitride) / GaN (gallium nitride) HFET (Hetero Junction Field Effect Transistor) structure. Has been reported.

For example, Patent Document 1 (Japanese Patent Laid-Open No. 2007-35905) discloses a structure using a Si ₃ N ₄ film as an insulating film on AlGaN / GaN.

FIG. 6 is a cross-sectional structure diagram of the field effect transistor disclosed in Patent Document 1 (FIG. 10 of Patent Document 1). As shown in FIG. 6, after the GaN channel layer 1, the AlGaN barrier layer 2, the GaN layers 3, 4, and the AlGaN layers 5, 6 are stacked, the gate electrodes of the GaN layers 3, 4 and the AlGaN layers 5, 6 are arranged. A recess is formed by removing the portion, a source electrode 8 and a drain electrode 9 are formed so as to be in ohmic contact with the AlGaN layers 5 and 6, a gate insulating film 15 is formed in the recess, and a gate electrode 10 is formed. It is produced by. With such a structure, the AlGaN barrier layer 2 is sufficiently thin, so that a normally-off operation is possible. In addition, due to the piezo effect (based on crystal distortion at the heterointerface) of both the AlGaN barrier layer 2 and the AlGaN layers 5 and 6, a piezo electric field is generated, and a two-dimensional electron gas in a region other than the gate electrode ( 2 (Dimensional (Electron Gas)) can be increased, and the on-resistance can be reduced.

JP 2007-35905 A (FIG. 10)

Note that the entire disclosure of Patent Document 1 is incorporated herein by reference.
The following is an analysis of the related art according to the present invention.

In the gate buried type MISFET structure as shown in FIG. 6, when the AlGaN barrier layer 2 is thinned, it is possible to set a pseudo enhancement mode in which the gate threshold voltage (Vth) is about 0 volts. However, it is extremely difficult to make +0.5 V or more.

Further, since the supply of carriers for reducing the source resistance is performed by the piezo effect of both the AlGaN barrier layer 2 and the AlGaN layers 5 and 6, there is a limitation due to the critical film thickness.

Furthermore, when an attempt is made to reduce the source resistance by increasing the AlGaN layer or doping the AlGaN layer, a two-dimensional electron gas is also formed at the interface between the GaN layer 4 and the AlGaN layer 6 on the drain electrode 9 side. Since the two-dimensional electron gas is opposed to the gate electrode 10 via the insulating film 15, high voltage operation becomes difficult. That is, it is difficult to achieve both low source resistance and high voltage operation.

Therefore, an object of the present invention is to provide a semiconductor device that performs a good enhancement operation, can operate at a high voltage, and has a low source resistance.

The invention disclosed in the present application is generally configured as follows in order to solve the above problems.

According to the present invention, in a field effect transistor comprising a group III-V nitride semiconductor and having an insulating film between the gate electrode and the semiconductor, two-dimensional electrons are present in the semiconductor layer between the drain electrode and the gate electrode. There is provided a semiconductor device in which a gas is formed and a region is formed by forming a two-dimensional electron gas in at least a part of a semiconductor layer between the source electrode and the gate electrode.

In the present invention, a recess structure in which a part of the III-V nitride semiconductor layer is removed is provided, a part of the drain electrode is disposed in a part of the recess region, and the source electrode is disposed in the recess region. Not.

In the present invention, a carrier supply layer (electron supply layer) and a carrier transit layer (electron transit layer) are provided between the drain electrode and the substrate, and two-dimensional electrons are provided between the source electrode and the carrier transit layer. A gas release layer is provided.

In the present invention, a low resistance layer using electrons as carriers is further provided between the source electrode and the two-dimensional electron gas elimination layer.

In the present invention, part or all of the semiconductor layers facing each other across the gate electrode and the insulating film are the n-type low resistance layer.

In the present invention, a part of the semiconductor layer facing the gate electrode and the insulating film is an n-type low resistance layer, and a part is a two-dimensional electron gas elimination layer or a carrier supply layer.

In the present invention, a part of the semiconductor layer facing the gate electrode and the insulating film is an n-type low resistance layer, a part is a two-dimensional electron gas elimination layer, and a part is a carrier supply layer.

In the present invention, the carrier traveling layer is made of In _x Ga _1-x N (0 ≦ x ≦ 1).

In the present invention, the carrier supply layer is made of unstrained or tensile strained In _a Al _b Ga _1-ab N (0 ≦ a, 0 <b, a + b ≦ 1).

In the present invention, the two-dimensional electron gas elimination layer is composed of unstrained or compressive strained GaN or compressive strained In _α Al _β Ga _1-α-β N (0 <α, 0 ≦ β, α + β ≦ 1). .

In the present invention, unstrained or compressive strained n-type In _y Ga _1-y N (0 ≦ y ≦ 1) or In _m Al ₁ Ga _1-ml N (0 ≦ m, 0 <l, m + l ≦ 1).

In the present invention, the gate insulating film is made of a substance (material) composed of one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and one or more of O and N.

According to the present invention, low resistance and high breakdown voltage can be independently achieved, and both low source resistance and high voltage operation can be achieved.

It is a figure which shows typically the cross-section of the 1st Example of this invention. It is a figure which shows typically the cross-section of the 2nd Example of this invention. It is a figure which shows typically the cross-section of the modification of the 2nd Example of this invention. It is a figure which shows typically the cross-section of the 3rd Example of this invention. It is a figure which shows typically the cross-sectional structure which shows the modification of the 3rd Example of this invention. It is a figure which shows typically the cross-section of related technology.

1 GaN channel layer 2 AlGaN barrier layer 3 GaN layer (source side)
4 GaN layer (drain side)
5 AlGaN layer (source side)
6 AlGaN layer (drain side)
7 Two-dimensional electron gas 8 Source electrode 9 Drain electrode 10 Gate electrode 15 Gate insulating film 101 Substrate 102 Buffer layer 103 made of the first GaN-based semiconductor Carrier carrier layer 104 made of the second GaN-based semiconductor Third GaN-based semiconductor Carrier supply layer 105 made of a four-dimensional electron gas elimination layer 106 made of a fourth GaN-based semiconductor Low resistance layer made of a fifth GaN-based semiconductor 107 Source electrode 108 Drain electrode 109 Gate insulating film 110 Gate electrode 111 Protective film 201 Substrate 202 Buffer layer 203 made of the first GaN-based semiconductor Carrier carrier layer 204 made of the second GaN-based semiconductor Carrier supply layer 205 made of the third GaN-based semiconductor Two-dimensional electron gas elimination layer made of the fourth GaN-based semiconductor 206 Low resistance layer 207 made of fifth GaN-based semiconductor Source electrode 208 Drain electrode 209 Gate insulating film 210 Gate electrode 211 Protective film 301 Substrate 302 First GaN-based semiconductor buffer layer 303 Second GaN-based semiconductor carrier transport layer 304 Third GaN-based semiconductor Carrier supply layer 305 Two-dimensional electron gas elimination layer 306 made of the fourth GaN-based semiconductor Low resistance layer 307 made of the fifth GaN-based semiconductor Source electrode 308 Drain electrode 309 Gate insulating film 310 Gate electrode 311 Protective film 312 Nucleation layer

The operation principle of one aspect of the present invention will be described. In one embodiment of the present invention, a two-dimensional electron gas is formed in the semiconductor layer between the drain electrode and the gate electrode, but in at least a part of the semiconductor layer between the source electrode and the gate electrode, By raising the conduction band of the carrier (electron) supply layer to the vacuum level side, a two-dimensional electron gas is formed by the two-dimensional electron gas elimination layer that prevents the two-dimensional electron gas from accumulating in the carrier (electron) traveling layer. The electrical conduction is performed through a low resistance layer on the two-dimensional electron gas elimination layer.

With such a structure, since the two-dimensional electron gas elimination layer between the two-dimensional electron gas and the low resistance layer becomes a barrier, when the gate voltage is 0 V, a current flows between the two-dimensional electron gas and the low resistance layer. Does not flow and is in enhancement mode.

On the other hand, by applying a positive voltage of, for example, +0.5 V or more as the gate voltage and lowering the barrier of the two-dimensional electron gas elimination layer, a current flows and can be turned on. At that time, the source resistance is determined by a low-resistance layer that does not use a two-dimensional electron gas, and the low-resistance layer exists only between the source electrode and the gate electrode. Does not exist. For this reason, a reduction in resistance and an increase in breakdown voltage can be performed independently, and both a reduction in source resistance and a high voltage operation can be achieved.

Embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram schematically showing a cross-sectional structure of the first embodiment of the present invention. Referring to FIG. 1, the field effect transistor of the present embodiment is
On the substrate 101,
A buffer layer 102 made of a first GaN-based semiconductor (group III-V nitride semiconductor);
A carrier traveling layer 103 made of a second GaN-based semiconductor,
A carrier supply layer 104 made of a third GaN-based semiconductor,
A two-dimensional electron gas elimination layer 105 made of a fourth GaN-based semiconductor, which works to prevent the two-dimensional electron gas from accumulating in the carrier traveling layer by raising the conduction band of the carrier supply layer to the vacuum level side;
Low resistance layer 106 made of a fifth GaN-based semiconductor
Are formed in this order.

Thereafter, the two-dimensional electron gas elimination layer 105 and the low resistance layer 106 are removed by recess etching between the drain electrode and the gate electrode, and a region below the gate electrode and a part below the gate electrode.

At that time, the remaining side surfaces of the two-dimensional electron gas elimination layer 105 and the low resistance layer 106 are formed so as to have a taper (taper angle) rather than perpendicular to the surface before the removal.

In contact with the low resistance layer 106, the source electrode 107,
A drain electrode 108 is formed in contact with the carrier supply layer 104,
Next, the gate insulating film 109 is formed, and the gate electrode 110 is formed.

Finally, a field effect transistor is manufactured by forming a protective film 111.

In this embodiment, as the substrate 101, for example, sapphire, silicon carbide, GaN, AlN or the like is used. In FIG. 1, the first to fifth GaN-based semiconductors are indicated by reference numerals 102 to 106, respectively.

As the first GaN-based semiconductor 102, for example, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, or the like is used. However, for forming the first semiconductor, a nucleation layer made of GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, or the like may be sandwiched between the substrate 101 and the buffer layer 102.

In the first GaN-based semiconductor 102,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added.

As the second GaN-based semiconductor 103, for example, GaN, InN, AlN, and a mixture of the above three kinds of GaN-based semiconductors are used.

In the second GaN-based semiconductor 103,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added. However, if the impurity concentration in the second GaN-based semiconductor increases, the mobility of electrons decreases due to the influence of Coulomb scattering, and therefore the impurity concentration is desirably 1 × 10 ¹⁷ cm ⁻³ or less.

As the third GaN-based semiconductor 104, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors are used. However, in this example, the material or composition has a smaller electron affinity than the second GaN-based semiconductor.

In the third GaN-based semiconductor 104,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added.

Examples of the fourth GaN-based semiconductor 105 include GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. However, in the present embodiment, since the fourth GaN-based semiconductor 105 needs to work to eliminate the two-dimensional electron gas, a substance or composition capable of inducing a negative charge at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer. It is.

In the fourth GaN-based semiconductor 105,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added.

The fifth GaN-based semiconductor 106 includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors.

In the fifth GaN-based semiconductor 106,
For example, Si, S, Se, or the like can be used as the n-type impurity. As the p-type impurity, for example, Be, C, Mg, or the like can be added, but the conductivity type is n-type.

In addition, as the gate insulating film 109, there is a substance composed of one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and one or more of O and N.

Further, as the protective film 111, there is a substance composed of one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and one or more of O and N, or an organic material.

Example 1
A first embodiment of the present invention will be described. The field effect transistor of this example is
A silicon (Si) substrate as the substrate 101;
As the first GaN-based semiconductor (buffer layer) 102, an AlGaN layer (Al composition ratio 0.2, film thickness 500 nm),
As the second GaN-based semiconductor (carrier running layer) 103, a GaN carrier running layer (film thickness 1000 nm),
As the third GaN-based semiconductor (carrier supply layer) 104, an AlGaN carrier supply layer (Al composition ratio 0.2, film thickness 15 nm),
As a fourth GaN-based semiconductor (two-dimensional electron gas elimination layer) 105, an InGaN two-dimensional electron gas elimination layer (In composition ratio 0.15, film thickness 10 nm, Mg-doped 1 × 10 ¹⁸ cm ⁻³ ),
As the fifth GaN-based semiconductor (low resistance layer) 106, an epitaxial substrate made of a GaN low resistance layer (film thickness: 50 nm, Si-doped 1 × 10 ¹⁹ cm ⁻³ ) is used.

On this epitaxial substrate, a SiN film of 200 nm is formed, and using a photoresist as a mask, for example, ICP (Inductivity Coupled Plasma) dry etching using SF6 (Sulfur Hexafluoride) as a process gas is performed. Open the recess.

After removing the photoresist, using the SiN film as a mask, recess etching is performed by ICP dry etching using, for example, a mixed gas of BCl3 (Boron Trichloride) and SF6 as a process gas to eliminate the two-dimensional electron gas The layer 105 and the low resistance layer 106 are removed.

In the recess etching using such a gas, the side surfaces of the SiN film are also etched at the same time, so that the side surfaces of the two-dimensional electron gas elimination layer 105 and the low resistance layer 106 are tapered.

Further, since the etching stops when F is bonded to the surface of the AlGaN carrier supply layer, the two-dimensional electron gas elimination layer 105 and the low resistance layer 106 can be selectively removed.

After the recess etching, the SiN film is removed using HF (Hydrogen Fluoride) aqueous solution,
Nb / Al / Nb / Au (film thickness 7 nm / 60 nm / 35 nm / 50 nm, heat treatment 850 ° C., 30 seconds) is formed as the source electrode 107 and the drain electrode 108.

Then, element isolation is performed by ion implantation,
As the gate insulating film 109, an Al ₂ O ₃ film (film thickness 20 nm),
As the gate electrode 110, Ni / Au (Ni layer thickness 10nm, Au layer thickness 400nm),
A SiON film (film thickness of 80 nm) is formed as the protective film 111, and a field effect transistor is manufactured.

In such a structure, since the two-dimensional electron gas and the two-dimensional electron gas elimination layer between the low resistance layer serve as a barrier, when the gate voltage is 0 V, the two-dimensional electron gas and the low resistance layer When a gate voltage of +3 V or higher was applied, no current flowed, and the device was turned on and a good enhancement mode was realized.

In the on state, the resistance of the GaN low-resistance layer doped with Si at a high density of 1 × 10 ¹⁹ cm ⁻³ is extremely low, so that a low source resistance can be realized.

Since the low resistance layer 106 exists only between the source electrode 107 and the gate electrode 110 and does not exist on the side of the drain electrode 108 to which a high voltage is applied during high voltage operation, the operation voltage is 50 V or more while having a low source resistance. High voltage operation was possible.

In addition, when the carrier supply layer is included in a part of the semiconductor layer facing the gate electrode and the insulating film as in this embodiment, the region works to alleviate electric field concentration, so that it is particularly suitable for high voltage operation. Is suitable.

In this embodiment, Si is used as the substrate 101, but any other substrate such as SiC or sapphire can be used.

In this embodiment, an AlGaN layer is used as the buffer layer 102. However, as the buffer layer 102, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used.

In this embodiment, a GaN layer is used as the carrier traveling layer 103. However, as the carrier traveling layer 103, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used. .

In this embodiment, an AlGaN layer is used as the carrier supply layer 104. However, as the carrier supply layer 104, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors, such as an InAlN layer, are used. it can. However, the electron affinity of the carrier supply layer 104 needs to be a material or composition smaller than the electron affinity of the carrier traveling layer 103.

In this embodiment, since the lattice constant of the carrier supply layer 104 is different from the lattice constant of the carrier traveling layer 103 which is the thickest layer, it is preferable that the carrier supply layer 104 be not more than the critical film thickness at which dislocation occurs.

In this embodiment, an InGaN layer is used as the two-dimensional electron gas elimination layer 105, but the two-dimensional electron gas elimination layer 105 is an InAlN layer, such as GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. Etc. can be used.

However, since the fourth GaN-based semiconductor needs to work to eliminate the two-dimensional electron gas, the fourth GaN-based semiconductor needs to be a substance or composition that can induce a negative charge at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer. Depending on the composition of the carrier running layer and the carrier supply layer, for example, unstrained or compressive strained GaN, or compressive strained In _α Al _β Ga _1-α-β N (0 <α, 0 ≦ β, α + β A layer composed of ≦ 1) or a layer to which a p-type impurity is added as in this embodiment is preferable.

In this embodiment, since the lattice constant of the two-dimensional electron gas elimination layer is different from the lattice constant of the carrier traveling layer, which is the thickest layer, it is preferable to set it to a critical film thickness or less where dislocation occurs.

In this embodiment, a GaN layer is used as the low resistance layer 106. However, the low resistance layer is an unstrained or compressive strained n-type In _y Ga _1-y N (0 ≦ y ≦ 1), or In _m Al _l Ga _1-ml N (0 ≦ m, 0 <l, m + l ≦ 1). However, when a composition different from the lattice constant of the carrier traveling layer, which is the thickest layer, is used, it is preferable that the thickness be equal to or less than the critical film thickness at which dislocation occurs.

Further, in this example, no impurities are added in the GaN carrier traveling layer 103,
As an n-type impurity, for example, Si, S, Se, etc.
For example, Be, C, Mg, or the like can be added as a p-type impurity. However, since the mobility decreases due to the influence of Coulomb scattering when the impurity concentration in the carrier traveling layer increases, the impurity concentration is desirably 1 × 10 ¹⁷ cm ⁻³ or less.

In this example, no impurities are added to the AlGaN carrier supply layer 104,
As an n-type impurity, for example, Si, S, Se, etc.
For example, Be, C, Mg, or the like can be added as a p-type impurity. However, if the n-type impurity concentration of the two-dimensional electron gas elimination layer is increased, it is difficult to eliminate the two-dimensional electron gas between the source electrode and the gate electrode. ^Therefore , the impurity concentration is desirably 1 × 10 ¹⁸ cm ⁻³ or less.

In this embodiment, Mg is added as a p-type impurity in the InGaN two-dimensional electron gas elimination layer 105. However, since the two-dimensional electron gas can be eliminated only by the piezo effect of InGaN itself, it is not necessary to add Mg.

In the two-dimensional electron gas elimination layer 105, for example, Be, C, Mg, or the like can be added as an n-type impurity, for example, a p-type impurity such as Si, S, or Se. However, since it becomes difficult to eliminate the two-dimensional electron gas between the source electrode and the gate electrode when the n-type impurity concentration in the carrier supply layer becomes high, the added impurity is preferably p-type.

In this embodiment, Si is added as an n-type impurity in the GaN low-resistance layer 106, but as an n-type impurity, for example, Be, C, Mg, or the like is added as a p-type impurity such as Si, S, or Se. It is possible. However, in this embodiment, since it is conduction by electrons, it is desirable to add an n-type impurity in order to reduce the resistance.

In this embodiment, Nb / Al / Nb / Au is used as the source electrode 107 and the drain electrode 108. However, the source electrode and the drain electrode are in ohmic contact with the AlGaN serving as the carrier supply layer 104 and the low resistance layer 106. For example, metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used. Or it can also be set as the structure which laminated | stacked the said some metal.

In this embodiment, Ni / Au is used as the gate electrode 110. However, since the gate electrode is not in direct contact with the semiconductor, a desired metal can be used. However, it is desirable not to react with the gate insulating film.

In this embodiment, an Al ₂ O ₃ film is used as the gate insulating film 109. However, as the gate insulating film 109, any one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr, and O and N are used. There exists a substance which consists of any one or more of these.

<Second Embodiment>
FIG. 2 is a diagram schematically showing a cross-sectional structure of the second embodiment of the present invention. Referring to FIG. 2, the field effect transistor of the present embodiment includes a buffer layer 202 made of a first GaN-based semiconductor, a carrier traveling layer 203 made of a second GaN-based semiconductor, and a third GaN-based material on a substrate 201. A carrier supply layer 204 made of a semiconductor, a two-dimensional electron gas elimination layer 205 made of a fourth GaN-based semiconductor, and a low resistance layer 206 made of a fifth GaN-based semiconductor are formed.

Thereafter, the two-dimensional electron gas elimination layer 205 and the low resistance layer 206 are removed by recess etching between the drain electrode and the gate electrode and in a region below the gate electrode and a part below the gate electrode. At this time, the side surfaces of the remaining two-dimensional electron gas elimination layer 205 and low resistance layer 206 are formed so as to be substantially perpendicular to the surface before removal. A source electrode 207 is in contact with the low resistance layer 206 and a drain electrode 208 is formed in contact with the carrier supply layer 204. Next, a gate insulating film 209 is formed, and a gate electrode 210 is formed. Finally, a field effect transistor is manufactured by forming a protective film 211.

In this embodiment, as the substrate 201, for example, sapphire, silicon carbide, GaN, AlN or the like is used. In the following, the first to fifth GaN-based semiconductors are also indicated by reference numerals 202 to 206, respectively.

Examples of the first GaN-based semiconductor 202 include GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. However, a nucleation layer made of GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, or the like may be sandwiched between the substrate 201 and the first semiconductor 202 in order to form the first semiconductor.

In the first GaN-based semiconductor 202,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added.

Also, as the second GaN-based semiconductor 203, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors are used.

In the second GaN-based semiconductor 203,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added. However, when the impurity concentration in the second GaN-based semiconductor increases, the mobility of electrons decreases due to the influence of Coulomb scattering, and therefore the impurity concentration is desirably 1 × 10 ¹⁷ cm ⁻³ or less.

The third GaN-based semiconductor 204 includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. However, in the embodiment of the present invention, the material or composition has a smaller electron affinity than that of the second GaN-based semiconductor.

In the third GaN-based semiconductor 204,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added.

The fourth GaN-based semiconductor 205 includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. However, in the present embodiment, the fourth GaN-based semiconductor 205 needs to have a function of eliminating the two-dimensional electron gas, so that a substance capable of inducing a negative charge at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer or Composition.

In the fourth GaN-based semiconductor 205,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added.

The fifth GaN-based semiconductor 206 includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors.

In the fifth GaN-based semiconductor 206, for example, Si, S, Se, etc. can be used as n-type impurities. As the p-type impurity, for example, Be, C, Mg or the like can be added, but the conductivity type is n-type.

In addition, as the gate insulating film 209, there is a substance including any one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and any one or more of O and N.

Further, as the protective film 211, there is a substance composed of one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and one or more of O and N, or an organic material.

(Example 2)
FIG. 2 is a diagram schematically showing a cross-sectional configuration of the second embodiment of the present invention. Referring to FIG. 2, the field effect transistor of this example is
As the substrate 201, a silicon carbide (SiC) substrate,
As the first GaN-based semiconductor 202, an AlGaN layer (Al composition ratio 0.1, film thickness 1000 nm),
As the second GaN-based semiconductor 203, a GaN carrier traveling layer (film thickness 40 nm),
As the third GaN-based semiconductor 204, an AlGaN carrier supply layer (Al composition ratio 0.25, film thickness 15 nm),
As the fourth GaN-based semiconductor 205, a GaN two-dimensional electron gas elimination layer (film thickness 10 nm, Mg-doped 1 × 10 ¹⁸ cm ⁻³ ),
As the fifth GaN-based semiconductor 206, an epitaxial substrate made of a GaN low resistance layer (film thickness: 30 nm, Si-doped 1 × 10 ¹⁹ cm ⁻³ ) is used.

A 200 nm SiO ₂ film is formed on the epitaxial substrate, and a recess portion of the SiN film is opened by ICP dry etching using, for example, SF 6 as a process gas using a photoresist as a mask.

After removing the photoresist, recess etching is performed by using, for example, ICP dry etching using a mixed gas of BCl ₃ and O ₂ as a process gas, using the SiO ₂ film as a mask, and the two-dimensional electron gas elimination layer 205, the low resistance layer 206 is removed.

At the time of recess etching using such a gas, the side surfaces of the SiO ₂ film are hardly etched, so that the side surfaces of the two-dimensional electron gas elimination layer 205 and the low resistance layer 206 are almost vertical.

Further, since the etching stops when O is bonded to the surface of the AlGaN carrier supply layer, the two-dimensional electron gas elimination layer 205 and the low resistance layer 206 can be selectively removed.

After the recess etching, the SiO ₂ film is removed using an HF aqueous solution, and Ti / Al / Nb / Au (film thickness 15 nm / 60 nm / 35 nm / 50 nm, heat treatment 850 ° C., 30 seconds) is used as the source electrode 207 and the drain electrode 208. Form.

Then, element isolation is performed by ion implantation,
As the gate insulating film 209, a SiN film (film thickness 20 nm),
As the gate electrode 210, Ni / Au (Ni layer thickness 10nm, Au layer thickness 400nm),
As the protective film 211, an SiON film (film thickness 80 nm) is formed,
A field effect transistor is fabricated.

In such a structure, since the two-dimensional electron gas elimination layer between the two-dimensional electron gas and the low resistance layer serves as a barrier, when the gate voltage is 0 V, a current flows between the two-dimensional electron gas and the low resistance layer. When a gate voltage of +3 V or higher was applied, the device was turned on and a good enhancement mode was realized.

In the on state, the resistance of the GaN low-resistance layer doped with Si at a high density of 1 × 10 ¹⁹ cm ⁻³ is very low, so that a low source resistance can be realized.

Since the low resistance layer 206 exists only between the source electrode 207 and the gate electrode 210 and does not exist on the side of the drain electrode to which a high voltage is applied during high voltage operation, a high voltage with an operating voltage of 50 V or more is achieved while having a low source resistance. I was able to work.

In the case where the carrier supply layer is included in a part of the semiconductor layer facing the gate electrode and the insulating film as in the embodiment shown in FIG. 2, the region works to alleviate electric field concentration. Suitable for voltage operation.

On the other hand, as in the embodiment shown in FIG. 3, when all the semiconductor layers facing each other with the gate electrode 210 and the insulating film 209 interposed therebetween are the low-resistance layers 206, the function of reducing the electric field concentration is lost, but all the gate electrodes 210 Since the distance from the two-dimensional electron gas elimination layer 205 is increased, the threshold voltage can be increased to the positive side.

In this embodiment, SiC is used as the substrate, but any other substrate such as Si or sapphire can be used.

In this embodiment, an AlGaN layer is used as the buffer layer 202, but a GaN layer such as GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used as the buffer layer.

In this embodiment, a GaN layer is used as the carrier traveling layer 203, but as the carrier traveling layer, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used. However, in this embodiment, since the lattice constant of the carrier traveling layer 203 is different from the lattice constant of the AlGaN buffer layer 202 which is the thickest layer, it is preferable to set the critical film thickness to be less than the critical film thickness at which dislocation occurs.

In this embodiment, an AlGaN layer is used as the carrier supply layer 204, but as the carrier supply layer, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, and the like can be used. However, the electron affinity of the carrier supply layer 204 needs to be a material or composition smaller than the electron affinity of the carrier traveling layer. In this embodiment, since the lattice constant of the carrier supply layer 204 is different from the lattice constant of the AlGaN buffer layer, which is the thickest layer, it is preferable that the carrier supply layer 204 be less than the critical film thickness at which dislocation occurs.

In this embodiment, a GaN layer is used as the two-dimensional electron gas elimination layer 205. However, the two-dimensional electron gas elimination layer is an InAlN layer, such as GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. Can be used.

However, since the fourth GaN-based semiconductor (two-dimensional electron gas elimination layer) 205 needs to work to eliminate the two-dimensional electron gas, a negative charge is induced at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer. It is necessary to be a material or a composition that can be used. Depending on the composition of the carrier running layer and the carrier supply layer, for example, unstrained or compressive strained GaN, or compressive strained In _α Al _β Ga _1-α-β N ( A layer composed of 0 <α, 0 ≦ β, α + β ≦ 1) or a layer to which a p-type impurity is added as in this embodiment is preferable.

In this embodiment, the lattice constant of the two-dimensional electron gas elimination layer is different from the lattice constant of the AlGaN buffer layer which is the thickest layer.

In this embodiment, a GaN layer is used as the low resistance layer 206, but the low resistance layer is an unstrained or compressive strain n-type In _y Ga _1-y N (0 ≦ y ≦ 1) or In _m AllGa. _1-ml N (0 ≦ m, 0 <l, m + l ≦ 1). However, when a composition different from the lattice constant of the AlGaN buffer layer, which is the thickest layer, is used as in the present embodiment, it is preferable to set it to a critical film thickness or less at which dislocation occurs.

Further, in this example, no impurities are added in the GaN carrier traveling layer 203,
As an n-type impurity, for example, Si, S, Se, etc.
For example, Be, C, Mg, or the like can be added as a p-type impurity. However, since the mobility decreases due to the influence of Coulomb scattering when the impurity concentration in the carrier traveling layer increases, the impurity concentration is desirably 1 × 10 ¹⁷ cm ⁻³ or less.

In this example, no impurities are added to the AlGaN carrier supply layer 204,
As an n-type impurity, for example, Si, S, Se, etc.
For example, Be, C, Mg, or the like can be added as a p-type impurity. However, if the n-type impurity concentration of the two-dimensional electron gas elimination layer 205 becomes high, it becomes difficult to eliminate the two-dimensional electron gas between the source electrode and the gate electrode. ^Therefore , the impurity concentration is desirably 1 × 10 ¹⁸ cm ⁻³ or less.

In this example, Mg was added as a p-type impurity in the GaN two-dimensional electron gas elimination layer 205. However, the GaN layer in this example is subjected to compressive strain, and the electron supply capability of the AlGaN carrier supply layer is low. Therefore, it is possible to eliminate the two-dimensional electron gas without converting Mg.

In the two-dimensional electron gas elimination layer 205,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg or the like can be added. However, if the n-type impurity concentration in the carrier supply layer is increased, it is difficult to eliminate the two-dimensional electron gas between the source electrode and the gate electrode, so that the added impurity is preferably p-type.

In this example, n-type impurities and Si were added to the GaN low resistance layer 206.
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg or the like can be added. However, in this embodiment, since it is conduction by electrons, it is desirable to add an n-type impurity in order to reduce the resistance.

In this embodiment, Ti / Al / Nb / Au is used as the source electrode 207 and the drain electrode 208. However, the source electrode and the drain electrode are in ohmic contact with the AlGaN and the low resistance layer 206 which are the carrier supply layer 204 in this embodiment. Any metal can be used as long as it is in contact with each other, and for example, metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the metals are stacked can be used.

In this embodiment, Ni / Au is used as the gate electrode 210. However, since the gate electrode is not in direct contact with the semiconductor, a desired metal can be used. However, it is desirable not to react with the gate insulating film.

In this embodiment, a SiN film is used as the gate insulating film 209. However, as the gate insulating film 209, any one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and any of O and N are used. One or more substances may be used.

<Example 3>
FIG. 4 is a diagram schematically showing a cross-sectional configuration of the third embodiment of the present invention. The field effect transistor of this example is
As the substrate 301, a silicon (Si) substrate,
AlN layer (film thickness 150 nm) as the nucleation layer 312,
As the first GaN-based semiconductor 302, a GaN layer (film thickness 1500 nm),
As the second GaN-based semiconductor 303, an InGaN carrier traveling layer (In composition ratio 0.04, film thickness 25 nm),
As the third GaN-based semiconductor 304, an InAlN carrier supply layer (Al composition ratio 0.83, film thickness 15 nm),
As the fourth GaN-based semiconductor 305, an InGaN two-dimensional electron gas elimination layer (In composition ratio 0.15, film thickness 10 nm),
As the fifth GaN-based semiconductor 306, an epitaxial substrate made of an AlGaN low resistance layer (Al composition ratio 0.05, film thickness 50 nm, Si-doped 1 × 10 ¹⁹ cm ⁻³ ) is used.

A 200 nm SiO ₂ film is formed on the epitaxial substrate, and a recess portion of the SiN film is opened by ICP dry etching using, for example, SF 6 as a process gas using a photoresist as a mask. After removing the photoresist, recess etching is performed by using, for example, ICP dry etching using BCl ₃ gas as a process gas with the SiO ₂ film as a mask, and the low resistance layer 306 is removed.

Again, a 200 nm SiO ₂ film is formed, and the recess portion of the SiN film is opened by ICP dry etching using, for example, SF ₆ as a process gas, using the photoresist as a mask.

After removing the photoresist, recess etching is performed using, for example, ICP dry etching using a mixed gas of BCl ₃ gas and O ₂ as a process gas, using the SiO ₂ film as a mask, and the two-dimensional electron gas elimination layer 305 is removed. To do.

At the time of recess etching, the side surfaces of the SiO ₂ film are hardly etched, so the side surfaces of the two-dimensional electron gas elimination layer 305 and the low resistance layer 306 are almost vertical.

Since the etching stops when O is bonded to the surface of the InAlN carrier supply layer, the two-dimensional electron gas elimination layer 305 can be selectively removed. After the recess etching, the SiO ₂ film is removed using an HF aqueous solution, and Ti / Al / Nb / Au (film thickness 15 nm / 60 nm / 35 nm / 50 nm, heat treatment 850 ° C., 30 seconds) is formed as the source electrode 307 and the drain electrode 308. .

Then, element isolation is performed by ion implantation,
As the gate insulating film 309, a SiN film (film thickness 20 nm),
As the gate electrode 310, Ni / Au (Ni layer thickness 10nm, Au layer thickness 400nm),
As the protective film 311, a SiON film (film thickness 80 nm) is formed,
A field effect transistor is fabricated.

In such a structure, since the two-dimensional electron gas elimination layer between the two-dimensional electron gas and the low resistance layer serves as a barrier, when the gate voltage is 0 V, a current flows between the two-dimensional electron gas and the low resistance layer. Thus, a good enhancement mode that turns on when a gate voltage of +3 V or higher was applied was realized.

In the on state, the resistance of the AlGaN low-resistance layer doped with Si at a high density of 1 × 10 ¹⁹ cm ⁻³ is very low, so that a low source resistance can be realized. In addition, since the low resistance layer exists only between the source electrode and the gate electrode and does not exist on the drain electrode side to which a high voltage is applied during high voltage operation, the high voltage operation with an operation voltage of 50 V or more is achieved while having a low source resistance. I was able to.

When the two-dimensional electron gas elimination layer 305 is included in a part of the semiconductor layer opposed to each other with the gate electrode 310 and the insulating film 309 interposed therebetween as in the embodiment shown in FIG. 4, the two-dimensional electron gas is not formed in that region. Good pinch-off characteristics can be realized. However, depending on the position of the gate electrode and the two-dimensional electron gas elimination layer, it is difficult to flow electrons even in the on state, so care must be taken.

On the other hand, as in the embodiment (modified example) shown in FIG. 5, the semiconductor layers facing each other with the gate electrode 310 and the insulating film 309 interposed therebetween are the low resistance layer 306, the two-dimensional electron gas elimination layer 305, and the carrier supply layer 304. In all cases, the region facing the carrier supply layer 304 serves to alleviate electric field concentration, and the region facing the two-dimensional electron gas supply layer 305 serves to achieve good pinch-off properties.

However, in this example, dry etching is required twice, and the number of processes is increased as compared with Example 1 and Example 2.

In this embodiment, Si is used as the substrate, but any other substrate such as SiC or sapphire can be used.

In this embodiment, a GaN layer is used as the buffer layer 302, but as the buffer layer, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, and the like can be used.

In this embodiment, an InGaN layer is used as the carrier traveling layer 303. However, as the carrier traveling layer, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used. . However, since the lattice constant of the carrier traveling layer is different from the lattice constant of the GaN buffer layer, which is the thickest layer, in this embodiment, it is preferable to set it to a critical film thickness or less where dislocation occurs.

In this embodiment, an InAlN layer is used as the carrier supply layer, but as the carrier supply layer, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, and the like can be used. However, the electron affinity of the carrier supply layer needs to be a material or composition smaller than the electron affinity of the carrier running layer.

In this embodiment, since the lattice constant of the carrier supply layer is slightly different from the lattice constant of the GaN buffer layer, which is the thickest layer, it is preferable that the carrier supply layer be less than the critical film thickness at which dislocation occurs.

In this example, an InGaN layer was used as the two-dimensional electron gas elimination layer, but as the carrier supply layer, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, and the like were used. Can do.

However, since the fourth GaN-based semiconductor 305 needs to work to eliminate the two-dimensional electron gas, the fourth GaN-based semiconductor 305 needs to be a substance or composition that can induce a negative charge at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer. Depending on the composition of the carrier running layer 303 and the carrier supply layer 304, for example, unstrained or compressive strained GaN, or compressive strained In _α Al _β Ga _1-α-β N (0 <α, 0 ≦ There is a layer composed of β, α + β ≦ 1) and a layer to which a p-type impurity is added as in this embodiment.

In this embodiment, the lattice constant of the two-dimensional electron gas elimination layer is different from the lattice constant of the GaN buffer layer, which is the thickest layer.

In this embodiment, an AlGaN layer is used as the low resistance layer. However, the low resistance layer may be an unstrained or compressive strained n-type In _y Ga _1-y N (0 ≦ y ≦ 1) or In _m Al _l Ga _1-ml N (0 ≦ m, 0 <l, m + l ≦ 1). However, when a composition different from the lattice constant of the GaN buffer layer, which is the thickest layer, is used as in the present embodiment, it is preferable to set it to a critical film thickness or less where dislocation occurs.

In this example, no impurities are added in the InGaN carrier traveling layer,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added. However, since the mobility decreases due to the influence of Coulomb scattering when the impurity concentration in the carrier traveling layer increases, the impurity concentration is desirably 1 × 10 ¹⁷ cm ⁻³ or less.

In this example, no impurities are added to the InAlN carrier supply layer,
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg, or the like can be added. However, if the n-type impurity concentration of the two-dimensional electron gas elimination layer is increased, it is difficult to eliminate the two-dimensional electron gas between the source electrode and the gate electrode. ^Therefore , the impurity concentration is desirably 1 × 10 ¹⁸ cm ⁻³ or less.

In this embodiment, no impurities are added to the InGaN two-dimensional electron gas elimination layer, but the two-dimensional electron gas elimination layer has n-type impurities, for example, p-type impurities such as Si, S, Se, for example Be, C, etc. Mg or the like can be added. However, since it becomes difficult to eliminate the two-dimensional electron gas between the source electrode and the gate electrode when the n-type impurity concentration in the carrier supply layer becomes high, the added impurity is preferably p-type.

In this example, Si was added as an n-type impurity in the AlGaN low resistance layer.
As an n-type impurity, for example, Si, S, Se, etc.
As the p-type impurity, for example, Be, C, Mg or the like can be added. However, in this embodiment, since it is conduction by electrons, it is desirable to add an n-type impurity in order to reduce the resistance.

In this embodiment, Ti / Al / Nb / Au is used as the source electrode 307 and the drain electrode 308. However, the source electrode and the drain electrode are in ohmic contact with InAlN and the low resistance layer 306 which are the carrier supply layers 304 in this embodiment. Any metal can be used as long as it is in contact with each other, and for example, metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the metals are stacked can be used.

In this embodiment, Ni / Au is used as the gate electrode 310. However, since the gate electrode is not in direct contact with the semiconductor in the present invention, a desired metal can be used. However, it is desirable not to react with the gate insulating film.

In this embodiment, a SiN film is used as the gate insulating film 309. However, as the gate insulating film 309, one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and any of O and N are used. There are substances consisting of one or more.

Note that the disclosure of Patent Document 1 above is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

Claims (22)

In a field effect transistor comprising a III-V nitride semiconductor and having an insulating film between the gate electrode and the semiconductor,
A two-dimensional electron gas is formed in the semiconductor layer between the drain electrode and the gate electrode,
A semiconductor device comprising a semiconductor layer in which a two-dimensional electron gas is not formed in at least a part of a semiconductor layer between a source electrode and the gate electrode. A recess region in which a part of the III-V nitride semiconductor layer is removed;
A part of the drain electrode is disposed in a part of the recess region;
The semiconductor device according to claim 1, wherein the source electrode is disposed in a predetermined region different from the recess region. A carrier supply layer and a carrier travel layer are provided between the drain electrode and the substrate,
The semiconductor device according to claim 1, further comprising a two-dimensional electron gas elimination layer between the source electrode and the carrier travel layer. 4. The semiconductor device according to claim 3, further comprising a low-resistance layer having electrons as carriers between the source electrode and the two-dimensional electron gas elimination layer. 5. The semiconductor device according to claim 1, wherein a part or all of the semiconductor layer facing the gate electrode and the insulating film is an n-type low resistance layer. 6. . The semiconductor layer facing the gate electrode and the insulating film includes an n-type low-resistance layer in part and a two-dimensional electron gas elimination layer or a carrier supply layer in another part. The semiconductor device according to claim 1. The semiconductor layer facing the gate electrode and the insulating film is
Including an n-type low resistance layer in part,
Another part includes a two-dimensional electron gas elimination layer,
The semiconductor device according to claim 1, further comprising a carrier supply layer in another part different from the part. The semiconductor device according to claim 3, wherein the carrier traveling layer is made of In _x Ga _1-x N (0 ≦ x ≦ 1). The carrier supply layer is composed of unstrained or tensile-strained In _a Al _b Ga _1-ab N (0 ≦ a, 0 <b, a + b ≦ 1), 8. The semiconductor device according to any one of 7 above. The two-dimensional electron gas elimination layer is made of unstrained or compressive strained GaN or compressive strained In _α Al _β Ga _1-α-β N (0 <α, 0 ≦ β, α + β ≦ 1). The semiconductor device according to claim 3, wherein the semiconductor device is characterized in that: The n-type low-resistance layer is an unstrained or compressive strained n-type In _y Ga _1-y N (0 ≦ y ≦ 1), or In _m AllGa _1- ml N (0 ≦ m, 0 <l, The semiconductor device according to claim 7, wherein m + l ≦ 1). The said insulating film consists of a substance which consists of any one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and any one or more of O and N, The said 5, 6, 7 characterized by the above-mentioned. The semiconductor device according to any one of the above. On the substrate, a buffer layer, a carrier traveling layer, a carrier supply layer are provided in this order,
On the partial region of the surface of the carrier supply layer, a two-dimensional electron gas elimination layer and a low resistance layer, which are sequentially laminated,
A drain electrode is provided in a predetermined region on the surface of the carrier supply layer and spaced apart from the partial region where the laminate of the two-dimensional electron gas elimination layer and the low resistance layer is provided,
A source electrode is provided in a predetermined region on the surface of the low resistance layer,
An insulating film covering a part of the low resistance layer and a part of the two-dimensional electron gas elimination layer, and a part of the carrier supply layer;
Through the insulating film,
A partial region of the low resistance layer;
A partial region of the low resistance layer and a partial region of the two-dimensional electron gas elimination layer;
A partial region of the low resistance layer, a partial region of the two-dimensional electron gas elimination layer, and a partial region of the carrier supply layer;
A gate electrode disposed opposite to any of the
A semiconductor device comprising: 14. The semiconductor device according to claim 13, wherein the buffer layer, the carrier traveling layer, the carrier supply layer, the two-dimensional electron gas elimination layer, and the low resistance layer are each made of a GaN-based semiconductor. A side surface of the laminate of the two-dimensional electron gas elimination layer and the low resistance layer facing the gate electrode through the insulating film is tapered.
The gate electrode passes through the insulating film,
A tapered surface of a laminate of the two-dimensional electron gas elimination layer and the low resistance layer;
A partial region of the resistance layer surface;
The semiconductor device according to claim 13, wherein the semiconductor device is opposed to a partial region of the carrier supply layer. The side of the laminate of the two-dimensional electron gas elimination layer and the low resistance layer facing the gate electrode with the insulating film interposed therebetween has a flush side wall,
The gate electrode passes through the insulating film,
A side wall of a laminate of the two-dimensional electron gas elimination layer and the low resistance layer;
A partial region of the resistance layer surface;
The semiconductor device according to claim 13 or 14, which is opposed to a partial region of the surface of the carrier supply layer. The side of the laminate of the two-dimensional electron gas elimination layer and the low resistance layer that faces the gate electrode through the insulating film is a step where the two-dimensional electron gas elimination layer protrudes from the low resistance layer. Have
The gate electrode passes through the insulating film,
15. The semiconductor device according to claim 13, wherein the semiconductor device is opposed to a part of the surface of the step portion of the two-dimensional electron gas elimination layer, a side wall of the low resistance layer, and a partial region of the surface of the low resistance layer. The side of the laminate of the two-dimensional electron gas elimination layer and the low resistance layer that faces the gate electrode through the insulating film is a step where the two-dimensional electron gas elimination layer protrudes from the low resistance layer. Have
The gate electrode passes through the insulating film,
A partial region of the surface of the carrier supply layer, a sidewall of the step portion of the two-dimensional electron gas elimination layer and a partial region of the surface, a sidewall of the low resistance layer and a partial region of the surface of the low resistance layer, 15. The semiconductor device according to claim 13 or 14, which is opposed to. A carrier supply layer and a carrier travel layer are provided between the drain electrode and the substrate, and a two-dimensional electron gas is formed in the semiconductor layer between the drain electrode and the gate electrode,
As a semiconductor layer in which a two-dimensional electron gas is not formed, a two-dimensional electron gas that works to prevent the two-dimensional electron gas from accumulating in the carrier traveling layer by raising the conduction band of the carrier supply layer to the vacuum level side. A resolution layer is provided on at least a part of the semiconductor layer between the source electrode and the gate electrode,
Electrical conduction is performed through a low resistance layer having electrons as carriers on the two-dimensional electron gas elimination layer,
When the gate voltage is 0 V, the two-dimensional electron gas elimination layer between the two-dimensional electron gas and the low-resistance layer serves as a barrier, and no current flows between the two-dimensional electron gas and the low-resistance layer. The semiconductor device according to claim 1, which is in a mode. When a predetermined positive voltage is applied as the gate voltage, a current flows by lowering the barrier of the two-dimensional electron gas elimination layer. At this time, the source resistance is determined by the low resistance layer, and the low resistance layer is The present invention exists between the source electrode and the gate electrode, and does not exist on the drain electrode side to which a high voltage is applied during a high voltage operation, thereby making it possible to achieve both a low source resistance and a high voltage operation. 19. The semiconductor device according to 19. A field supply transistor comprising a group III-V nitride semiconductor and having an insulating film between the gate electrode and the semiconductor, and a substrate including a carrier supply layer and a carrier traveling layer between the drain electrode and the substrate, A two-dimensional electron gas is formed in the semiconductor layer between the gate electrodes,
In at least part of the semiconductor layer between the source electrode and the gate electrode of the field effect transistor, the two-dimensional electron gas does not accumulate in the carrier transit layer by raising the conduction band of the carrier supply layer to the vacuum level side. A two-dimensional electron gas elimination layer that works like
Electrical conduction is performed through a low resistance layer having electrons as carriers on the two-dimensional electron gas elimination layer,
When the gate voltage is 0 V, the two-dimensional electron gas elimination layer between the two-dimensional electron gas and the low-resistance layer serves as a barrier, and no current flows between the two-dimensional electron gas and the low-resistance layer. A method for operating a semiconductor device, which performs a mode operation. When a predetermined positive voltage is applied as the gate voltage, a current flows by lowering the barrier of the two-dimensional electron gas elimination layer. At this time, the source resistance is determined by the low resistance layer, and the low resistance layer is 23. It exists between the source electrode and the gate electrode and does not exist on the drain electrode side to which a high voltage is applied during a high voltage operation, thereby making it possible to achieve both a low source resistance and a high voltage operation. An operation method of the semiconductor device described.

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