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WO2010079827A1 - Dispositif semi-conducteur et son procédé de fabrication - Google Patents

Dispositif semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2010079827A1
WO2010079827A1 PCT/JP2010/050151 JP2010050151W WO2010079827A1 WO 2010079827 A1 WO2010079827 A1 WO 2010079827A1 JP 2010050151 W JP2010050151 W JP 2010050151W WO 2010079827 A1 WO2010079827 A1 WO 2010079827A1
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WIPO (PCT)
Prior art keywords
film
upper electrode
hard mask
wiring
barrier
Prior art date
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Ceased
Application number
PCT/JP2010/050151
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English (en)
Japanese (ja)
Inventor
宗弘 多田
阪本　利司
幸重 斎藤
裕子 矢部
行広 迫坪
波田　博光
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NEC Corp
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NEC Corp
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Priority to JP2010545791A priority Critical patent/JP5799504B2/ja
Publication of WO2010079827A1 publication Critical patent/WO2010079827A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors

Definitions

  • the present invention is based on the priority claim of Japanese Patent Application No. 2009-004037 (filed on Jan. 9, 2009), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a field programmable gate array having a variable resistance nonvolatile element (hereinafter referred to as a “resistance variable element”) inside a multilayer wiring layer on a semiconductor substrate.
  • An FPGA and a method for manufacturing the same.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the FPGA enables the customer himself to perform an arbitrary circuit configuration after manufacturing the chip.
  • the FPGA has a variable resistance element inside a multilayer wiring layer so that customers themselves can arbitrarily connect the wiring.
  • the resistance change element include ReRAM (Resistance Random Access Memory) using a transition metal oxide and NanoBridge (registered trademark of NEC) using an ion conductor.
  • Non-patented switching elements using metal ion migration and electrochemical reactions in ion conductors solids in which ions can move freely by applying an electric field or the like
  • the switching element disclosed in Non-Patent Document 1 is composed of an ion conductive layer, and three layers of a first electrode and a second electrode disposed on the opposite surface in contact with the ion conductive layer. Among these, the 1st electrode has played the role for supplying a metal ion to an ion conductive layer. Metal ions are not supplied from the second electrode.
  • this switching element When the first electrode is grounded and a negative voltage is applied to the second electrode, the metal of the first electrode becomes metal ions and dissolves in the ion conductive layer. And the metal ion in an ion conductive layer turns into a metal and precipitates in an ion conductive layer, The metal bridge
  • the switch is turned on by electrically connecting the first electrode and the second electrode by metal bridge.
  • the first electrode is grounded and a positive voltage is applied to the second electrode in the ON state, a part of the metal bridge is cut.
  • the electrical connection between the first electrode and the second electrode is cut off, and the switch is turned off.
  • the electrical characteristics change from the stage before the electrical connection is completely cut off, such as the resistance between the first electrode and the second electrode is increased, or the capacitance between the electrodes is changed. Cut out.
  • the first electrode is grounded again and a negative voltage is applied to the second electrode.
  • Non-Patent Document 1 discloses the configuration and operation in the case of a two-terminal switching element in which two electrodes are arranged via an ion conductor and the conduction state between them is controlled. Furthermore, in addition to this, another control electrode (third electrode) is arranged, and voltage application to the control electrode causes conduction in the ion conductor between the first electrode and the second electrode. A three-terminal switching element for controlling the state has been proposed.
  • Such a switching element is characterized in that it is smaller in size and smaller in on-resistance than a conventionally used semiconductor switch (such as a MOSFET). Therefore, it is considered promising for application to programmable logic devices. Further, in this switching element, its conduction state (on or off) is maintained as it is even when the applied voltage is turned off, so that it can be applied as a nonvolatile memory element.
  • a memory cell including one selection element such as a transistor and one switching element as a basic unit a plurality of memory cells are arranged in the vertical direction and the horizontal direction, respectively. Arranging in this way makes it possible to select an arbitrary memory cell from among a plurality of memory cells with the word line and the bit line. Then, the nonvolatile state capable of sensing the conduction state of the switching element of the selected memory cell and reading which information “1” or “0” is stored from the ON or OFF state of the switching element. Memory can be realized
  • Non-Patent Document 1 is incorporated herein by reference. The following is an analysis of the related art according to the present invention.
  • the prior art has the following problems.
  • the main problem of the present invention is to provide a semiconductor device equipped with a variable resistance element that can achieve high reliability, high density, and low electrode resistance, and a method for manufacturing the same.
  • a semiconductor device having a resistance change element inside a multilayer wiring layer on a semiconductor substrate, wherein the resistance change element has a resistance change between an upper electrode and a lower electrode.
  • the multilayer wiring layer includes at least a wiring electrically connected to the lower electrode and a plug electrically connected to the upper electrode.
  • the side surface or bottom portion of the plug is covered with a barrier metal, and the uppermost portion of the upper electrode is in direct contact with the barrier metal, and the same material as the barrier metal or a component contained in the barrier metal. It is characterized by being comprised with the material containing the same component.
  • the uppermost portion of the upper electrode and the barrier metal are preferably made of Ti, Ta, W, or a nitride thereof.
  • the wiring also serves as the lower electrode.
  • the wiring and the lower electrode are made of copper.
  • a surface of the wiring is coated with CuSi.
  • variable resistance element film is preferably an oxide containing Ta.
  • the upper electrode has a configuration in which a first upper electrode and a second upper electrode are stacked in order from the resistance change element film side, and the first upper electrode is formed on the resistance change element film. It is preferable that the second upper electrode is the uppermost part of the upper electrode, including a metal material having an absolute value of free energy of oxidation smaller than that of the metal component.
  • the first upper electrode is made of Pt, Ru, or an oxide thereof.
  • an insulating barrier film is interposed between the lower electrode and the variable resistance element film, the insulating barrier film has an opening, and the variable resistance element film includes the opening
  • the hard mask film is disposed on the upper electrode in contact with the lower electrode, and the stacked body of the hard mask film, the upper electrode, and the resistance change element film is covered with a protective insulating film on the top surface or the side surface.
  • the protective insulating film is in contact with the insulating barrier film at the outer periphery of a stack of the hard mask film, the upper electrode, and the variable resistance element film, and the plug is connected to the protective insulating film and the hard mask film. It is preferable that the upper electrode is electrically connected through the barrier metal through a prepared hole.
  • an insulating barrier film is interposed between the lower electrode and the variable resistance element film, the insulating barrier film has an opening, and the variable resistance element film includes the opening
  • a hard mask film is disposed on the upper electrode, a second hard mask film made of a material different from the hard mask film is disposed on the hard mask film, the second hard mask film,
  • the laminate of the hard mask film, the upper electrode, and the variable resistance element film is covered with a protective insulating film on the side surface, and the protective insulating film includes the second hard mask film, the hard mask film, and the upper electrode.
  • the insulating barrier film is in contact with the outer periphery of the laminated body of the resistance change element film, and the plug is connected to the barrier through the second hard mask film and a pilot hole formed in the hard mask film. Which is preferably electrically connected to the upper electrode through the metal.
  • the stacked body of the second hard mask film, the hard mask film, the upper electrode, and the variable resistance element film is covered with a protective insulating film on an upper surface or a side surface, and the protective insulating film Is in contact with the insulating barrier film at the outer periphery of the stacked body of the second hard mask film, the hard mask film, the upper electrode, and the resistance change element film, and the plug includes the protective insulating film, the first 2 It is preferable that the upper electrode is electrically connected through the barrier metal through a hard mask film and a pilot hole formed in the hard mask film.
  • the protective insulating film is preferably made of the same material as the hard mask film and the insulating barrier film.
  • a first oxide comprising a metal oxide interposed between the variable resistance element film and the upper electrode and having a larger absolute value of oxidation free energy than a metal component in the variable resistance element film. It is preferable to include a second resistance change element film, and a second lower electrode interposed between the lower electrode and the resistance change element film and having a metal diffusion barrier property related to the lower electrode.
  • the second lower electrode is an electrode having a two-layer structure
  • the layer on the variable resistance element film side is preferably made of the same material as the first upper electrode.
  • the second lower electrode is an electrode in which TaN and Ru are sequentially stacked from the lower electrode side.
  • the method of manufacturing a semiconductor device includes a step of forming a wiring to be the lower electrode before the step of forming the variable resistance element film and the upper electrode, and the variable resistance element film and the upper electrode In the step of forming, the variable resistance element film and the upper electrode are preferably formed in this order on the wiring.
  • variable resistance element film is preferably formed at room temperature.
  • the upper electrode is preferably formed at 100 ° C. or lower.
  • the method of manufacturing a semiconductor device includes a step of forming an insulating barrier film having an opening on the lower electrode before the step of forming the variable resistance element film and the upper electrode, In the step of forming the variable element film and the upper electrode, the variable resistance element film, the upper electrode, and the hard mask film are formed in this order on the lower electrode in the opening, and the variable resistance element film and the upper electrode are formed in this order.
  • a protective insulating film is formed on the insulating barrier film including the hard mask film, the upper electrode, and the variable resistance element film stack.
  • the method of manufacturing a semiconductor device includes a step of forming an insulating barrier film having an opening on the lower electrode before the step of forming the variable resistance element film and the upper electrode, In the step of forming the change element film and the upper electrode, the resistance change element film, the upper electrode, the hard mask film, and the second hard mask film are formed in this order on the lower electrode in the opening, and the resistance change After the step of forming the element film and the upper electrode and before the step of forming the barrier metal, a laminate of the second hard mask film, the hard mask film, the upper electrode, and the resistance change element film A step of forming a protective insulating film on the insulating barrier film, and a lower portion of the protective insulating film, the second hard mask film, and the hard mask film that communicates with the upper electrode In the step of forming the barrier metal, the barrier metal is formed on the surface of the pilot hole and on the upper electrode, and the second hard mask film is formed with the hard mask film. Different materials are preferred.
  • the method of manufacturing a semiconductor device includes a step of forming an insulating barrier film having an opening on the lower electrode before the step of forming the variable resistance element film and the upper electrode, In the step of forming the change element film and the upper electrode, the resistance change element film, the upper electrode, the hard mask film, and the second hard mask film are formed in this order on the lower electrode in the opening, and the resistance change After the step of forming the element film and the upper electrode and before the step of forming the barrier metal, a laminate of the second hard mask film, the hard mask film, the upper electrode, and the resistance change element film Forming a protective insulating film on the insulating barrier film, and planarizing the protective insulating film and the second hard mask film until the second hard mask film has a predetermined thickness.
  • a step of scraping, and a step of forming a pilot hole that communicates with the upper electrode in the second hard mask film and the hard mask film, and the step of forming the barrier metal includes the surface of the pilot hole, and the upper part
  • the barrier metal is formed on the electrode, and the second hard mask film is made of a material different from that of the hard mask film.
  • the protective insulating film is made of the same material as the hard mask film and the insulating barrier film.
  • the step of forming the resistance change element film and the upper electrode in the step of forming the resistance change element film and the upper electrode, a second lower electrode, the resistance change element film, a second resistance change element film,
  • the upper electrode is formed in this order
  • the second lower electrode has a metal diffusion barrier property related to the lower electrode
  • the second resistance change element film is more oxidized than the metal component in the resistance change element film. It is preferably made of a metal oxide having a large absolute value of free energy.
  • step of forming the wiring in the step of forming the wiring, another wiring that does not become the lower electrode is formed at the same time, and in the step of forming the barrier metal, another barrier is formed on the other wiring.
  • step of forming a metal and forming the plug it is preferable to form another plug on the other barrier metal.
  • the uppermost part of the upper electrode and the barrier metal covering the plug are made of the same material, so that the barrier metal and the uppermost part of the upper electrode are integrated, the contact resistance is reduced, and the adhesion It is possible to improve the reliability by improving the reliability. Moreover, if the uppermost part of the upper electrode is made of a material containing the same component as that contained in the barrier metal, the contact resistance can be reduced and the adhesion can be improved.
  • the wiring as the lower electrode of the resistance change element that is, the wiring also serves as the lower electrode of the resistance change element, it is possible to achieve high density by miniaturization of the resistance change element and the number of processes. Can be simplified.
  • a resistance change element As an additional step to the normal Cu damascene wiring process, it is possible to mount a resistance change element simply by creating a 2PR mask set, and to simultaneously reduce the cost of the apparatus. Furthermore, a resistance change element can also be mounted inside a state-of-the-art device composed of copper wiring to improve the performance of the apparatus.
  • FIG. 14 is an enlarged cross-sectional view of a region R in FIG. 13 schematically showing a configuration of a semiconductor device according to Example 5 of the present invention.
  • the variable resistance element (22 in FIG. 1) includes an upper electrode (10 and 11 in FIG. 1) and a lower electrode (in FIG. 1). 5), a variable resistance element film (9 in FIG. 1) having a variable resistance is interposed therebetween, and the multilayer wiring layer is electrically connected to at least the lower electrode (5 in FIG. 1).
  • Said has straight contact barrier with metal (20 of FIG. 1) is formed of a material comprising said barrier same material as the metal or the barrier component and the same component contained in the metal.
  • the method for manufacturing a semiconductor device according to the second embodiment of the present invention is a method for manufacturing a semiconductor device having a variable resistance element inside a multilayer wiring layer on a semiconductor substrate, wherein the variable resistance element film and the upper electrode are formed on the lower electrode.
  • a step of forming a barrier metal on the upper electrode (FIG. 1), and a step of forming a plug on the barrier metal (FIG. 1), and the barrier metal (20 in FIG. 1) includes the same material as the uppermost portion (11 in FIG. 1) of the upper electrode, or the same component as the component included in the uppermost portion of the upper electrode. Material.
  • FIG. 1 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Example 1 of the present invention.
  • the semiconductor device according to the first embodiment is a device having a resistance change element 22 inside a multilayer wiring layer on the semiconductor substrate 1.
  • the multilayer wiring layer is formed on the semiconductor substrate 1 with an interlayer insulating film 2, a barrier insulating film 3, an interlayer insulating film 4, an insulating barrier film 7, a protective insulating film 14, an interlayer insulating film 15, an etching stopper film 16, and an interlayer insulating film.
  • the insulating laminate is formed by sequentially laminating the film 17 and the barrier insulating film 21.
  • the first wiring 5 is embedded through the barrier metal 6 in the wiring groove formed in the interlayer insulating film 4 and the barrier insulating film 3.
  • the second wiring 18 is embedded in the wiring groove formed in the interlayer insulating film 17 and the etching stopper film 16, and is formed in the interlayer insulating film 15, the protective insulating film 14, and the hard mask film 12.
  • a plug 19 is embedded in the prepared hole, the second wiring 18 and the plug 19 are integrated, and the side surfaces and the bottom surface of the second wiring and the plug 19 are covered with the barrier metal 20.
  • the multilayer wiring layer is formed by laminating the variable resistance element film 9, the first upper electrode 10, and the second upper electrode 11 in this order on the first wiring 5 serving as the lower electrode at the opening formed in the insulating barrier film 7.
  • the variable resistance element 22 is formed, the hard mask film 12 is formed on the second upper electrode 11, the variable resistance element film 9, the first upper electrode 10, the second upper electrode 11, and the hard mask film
  • the top surface or the side surface of the 12 laminated bodies is covered with a protective insulating film 14.
  • the variable resistance element 22 is a variable resistance nonvolatile element, and can be, for example, a switching element that utilizes metal ion migration and an electrochemical reaction in an ion conductor.
  • the resistance change element 22 has a configuration in which a resistance change element film 9 is interposed between the first wiring 5 serving as a lower electrode and the upper electrodes 10 and 11 electrically connected to the plug 19.
  • the resistance change element film 9 and the first wiring 5 are in direct contact with each other in the region of the opening formed in the insulating barrier film 7, and the plug 19 and the second wiring are formed on the second upper electrode 11.
  • the upper electrode 11 is connected via the barrier metal 20.
  • the resistance change element 22 performs ON / OFF control using the electric field diffusion of the metal related to the first wiring 5 into the resistance change element film 9.
  • the second upper electrode 11 and the barrier metal 20 are made of the same material. By doing so, the barrier metal 20 of the plug 19 and the second upper electrode 11 of the variable resistance element 22 are integrated, the contact resistance is reduced, and the reliability is improved by improving the adhesion. Can do.
  • the semiconductor substrate 1 is a substrate on which a semiconductor element is formed.
  • a substrate such as a silicon substrate, a single crystal substrate, an SOI (Silicon on ulatorInsulator) substrate, a TFT (Thin Film Transistor) substrate, or a liquid crystal manufacturing substrate can be used.
  • the interlayer insulating film 2 is an insulating film formed on the semiconductor substrate 1.
  • a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used.
  • the interlayer insulating film 2 may be a laminate of a plurality of insulating films.
  • the barrier insulating film 3 is an insulating film having a barrier property interposed between the interlayer insulating films 2 and 4.
  • the barrier insulating film 3 serves as an etching stop layer when the wiring groove for the first wiring 5 is processed.
  • a wiring groove for embedding the first wiring 5 is formed in the barrier insulating film 3, and the first wiring 5 is embedded in the wiring groove via the barrier metal 6.
  • the barrier insulating film 3 can be deleted depending on the selection of the etching conditions for the wiring trench.
  • the interlayer insulating film 4 is an insulating film formed on the barrier insulating film 3.
  • a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like can be used.
  • the interlayer insulating film 4 may be a laminate of a plurality of insulating films.
  • a wiring groove for embedding the first wiring 5 is formed in the interlayer insulating film 4, and the first wiring 5 is embedded in the wiring groove via the barrier metal 6.
  • the first wiring 5 is a wiring embedded in a wiring groove formed in the interlayer insulating film 4 and the barrier insulating film 3 via a barrier metal 6.
  • the first wiring 5 also serves as a lower electrode of the resistance change element 22 and is in direct contact with the resistance change element film 9.
  • a metal that can be diffused and ion-conducted in the resistance change element film 9 is used.
  • the first wiring 5 may have a surface coated with CuSi.
  • the barrier metal 6 is a conductive film having a barrier property that covers the side surface or the bottom surface of the wiring in order to prevent the metal related to the first wiring 5 from diffusing into the interlayer insulating film 4 or the lower layer.
  • the barrier metal 6 includes tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbonitride (WCN). Refractory metals such as these, nitrides thereof, and the like, or a laminated film thereof can be used.
  • the insulating barrier film 7 is formed on the interlayer insulating film 4 including the first wiring 5, prevents oxidation of a metal (for example, Cu) related to the first wiring 5, and the first wiring into the interlayer insulating film 15. 5 serves as an etching stop layer when the upper electrodes 11 and 10 and the resistance change element film 9 are processed.
  • a metal for example, Cu
  • the insulating barrier film 7 for example, a SiC film, a SiCN film, a SiN film, and a laminated structure thereof can be used.
  • the insulating barrier film 7 is preferably made of the same material as the protective insulating film 14 and the hard mask film 12.
  • the resistance change element film 9 is a film whose resistance changes.
  • the resistance change element film 9 can be made of a material whose resistance is changed by the action of metal (diffusion, ion transmission, etc.) on the first wiring 5 (lower electrode).
  • an ion conductive film is used.
  • an oxide insulating film containing Ta such as Ta 2 O 5 or TaSiO can be used.
  • the first upper electrode 10 is an electrode on the lower layer side of the upper electrode of the resistance change element 22 and is in direct contact with the resistance change element film 9.
  • a metal that is less ionized than the metal associated with the first wiring 5 and is less likely to diffuse and ion-conduct in the resistance change element film 9 is used.
  • the metal component (Ta) associated with the resistance change element film 9 It is preferable to use a metal material having a smaller absolute value of the free energy of oxidation.
  • Pt, Ru or the like can be used. It is indispensable for the resistance change characteristic that the first upper electrode 10 is in direct contact with the resistance change element film 9.
  • the first upper electrode 10 may be added with oxygen as a main component of a metal material such as Pt or Ru, or may have a laminated structure with a layer to which oxygen is added.
  • the second upper electrode 11 is an electrode on the upper layer side of the upper electrode of the variable resistance element 22, and is formed on the first upper electrode 10.
  • the second upper electrode 11 has a role of protecting the first upper electrode 10.
  • the second upper electrode 11 is preferably made of the same material as the barrier metal 20.
  • the hard mask film 12 is a film that becomes a hard mask when the second upper electrode 11, the first upper electrode 10, and the resistance change element film 9 are etched.
  • a SiN film or the like can be used for the hard mask film 12.
  • the hard mask film 12 is preferably made of the same material as the protective insulating film 14 and the insulating barrier film 7. That is, by surrounding all of the resistance change element 22 with the same material, the material interface is integrated, so that entry of moisture and the like from the outside can be prevented and detachment from the resistance change element 22 itself can be prevented. Become.
  • the protective insulating film 14 is an insulating film having a function of preventing the oxygen from the resistance change element film 9 without damaging the resistance change element 22.
  • a SiN film, a SiCN film, or the like can be used for the protective insulating film 14.
  • the protective insulating film 14 is preferably made of the same material as the hard mask film 12 and the insulating barrier film 7. In the case of the same material, the protective insulating film 14, the insulating barrier film 7 and the hard mask film 12 are integrated, and the adhesion at the interface is improved.
  • the interlayer insulating film 15 is an insulating film formed on the protective insulating film 14.
  • the interlayer insulating film 15 for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used.
  • the interlayer insulating film 15 may be a laminate of a plurality of insulating films.
  • the interlayer insulating film 15 may be made of the same material as the interlayer insulating film 17.
  • a pilot hole for embedding the plug 19 is formed in the interlayer insulating film 15, and the plug 19 is embedded through the barrier metal 20 in the pilot hole.
  • the etching stopper film 16 is an insulating film interposed between the interlayer insulating films 15 and 17.
  • the etching stopper film 16 has a role as an etching stop layer when the wiring groove for the second wiring 18 is processed.
  • a SiN film, a SiC film, a SiCN film, or the like can be used for the etching stopper film 16.
  • a wiring groove for embedding the second wiring 18 is formed, and the second wiring 18 is embedded in the wiring groove via a barrier metal 20.
  • the etching stopper film 16 can be deleted depending on the selection of the etching conditions for the wiring trench.
  • the interlayer insulating film 17 is an insulating film formed on the etching stopper film 16.
  • the interlayer insulating film 17 for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film can be used.
  • the interlayer insulating film 17 may be a laminate of a plurality of insulating films.
  • the interlayer insulating film 17 may be made of the same material as the interlayer insulating film 15.
  • a wiring groove for embedding the second wiring 18 is formed in the interlayer insulating film 17, and the second wiring 18 is embedded in the wiring groove via the barrier metal 20.
  • the second wiring 18 is a wiring buried in a wiring groove formed in the interlayer insulating film 17 and the etching stopper film 16 via a barrier metal 20.
  • the second wiring 18 is integrated with the plug 19.
  • the plug 19 is buried in a prepared hole formed in the interlayer insulating film 15, the protective insulating film 14, and the hard mask film 12 via a barrier metal 20.
  • the plug 19 is electrically connected to the second upper electrode 11 through the barrier metal 20.
  • Cu may be used for the second wiring 18 and the plug 19.
  • the barrier metal 20 covers the side surfaces or bottom surfaces of the second wiring 18 and the plug 19 in order to prevent the metal related to the second wiring 18 (including the plug 19) from diffusing into the interlayer insulating films 15 and 17 and the lower layer. It is a conductive film having a barrier property.
  • the barrier metal 20 includes tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbonitride.
  • a refractory metal such as (WCN), a nitride thereof, or a stacked film thereof can be used.
  • the barrier metal 20 is preferably made of the same material as the second upper electrode 11.
  • the barrier metal 20 has a stacked structure of TaN (lower layer) / Ta (upper layer), it is preferable to use TaN as the lower layer material for the second upper electrode 11.
  • the barrier metal 20 is Ti (lower layer) / Ru (upper layer), it is preferable to use Ti as the lower layer material for the second upper electrode 11.
  • the barrier insulating film 21 is formed on the interlayer insulating film 17 including the second wiring 10 to prevent oxidation of the metal (for example, Cu) related to the second wiring 10 and to prevent the metal related to the second wiring 10 to the upper layer from being oxidized. It is an insulating film having a role of preventing diffusion.
  • a SiC film, a SiCN film, a SiN film, and a laminated structure thereof can be used.
  • FIGS. 2 to 5 are process cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • an interlayer insulating film 2 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on a semiconductor substrate 1 (for example, a substrate on which a semiconductor element is formed), and then a barrier insulating film 3 (on the interlayer insulating film 2).
  • a semiconductor substrate 1 for example, a substrate on which a semiconductor element is formed
  • a barrier insulating film 3 on the interlayer insulating film 2.
  • an SiN film having a film thickness of 50 nm is deposited, and then an interlayer insulating film 4 (for example, a silicon oxide film having a film thickness of 300 nm) is deposited on the barrier insulating film 3.
  • Etching and photoresist removal are used to form wiring grooves in the interlayer insulating film 4 and the barrier insulating film 3, and then a barrier metal 6 (for example, TaN / Ta, film thickness 5 nm / 5 nm) is formed in the wiring grooves.
  • the first wiring 5 (for example, copper) is embedded through the wiring (step A1; see FIG. 2A).
  • the interlayer insulating films 2 and 4 can be formed by a plasma CVD method.
  • the plasma CVD (Chemical Vapor Deposition) method refers to, for example, vaporizing a gas source or a liquid source to continuously supply the reaction chamber under reduced pressure, bringing the molecules into an excited state by plasma energy, In this method, a continuous film is formed on a substrate by a phase reaction or a substrate surface reaction.
  • the first wiring 5 is formed by forming a barrier metal 6 (for example, a TaN / Ta laminated film) by, for example, PVD, and wiring copper by electrolytic plating after forming a Cu seed by PVD. It can be formed by embedding in the groove, after heat treatment at a temperature of 200 ° C. or higher, and then removing excess copper other than in the wiring groove by CMP. As a method for forming such a series of copper wirings, a general method in this technical field can be used.
  • a barrier metal 6 for example, a TaN / Ta laminated film
  • the CMP (Chemical-Mechanical-Polishing) method is used to flatten the unevenness of the wafer surface that occurs during the multilayer wiring formation process by bringing the polishing liquid into contact with a rotating polishing pad while flowing the polishing liquid over the wafer surface and polishing it. Is the method. By polishing excess copper embedded in the trench, a buried wiring (damascene wiring) is formed, or planarization is performed by polishing an interlayer insulating film.
  • an insulating barrier film 7 (for example, a SiN film, a film thickness of 50 nm) is formed on the interlayer insulating film 4 including the first wiring 5 (step A2; see FIG. 2B).
  • the insulating barrier film 7 can be formed by a plasma CVD method.
  • the thickness of the insulating barrier film 7 is preferably about 10 nm to 50 nm.
  • a hard mask film 8 (for example, a silicon oxide film) is formed on the insulating barrier film 7 (step A3; see FIG. 2C).
  • the hard mask film 8 is preferably made of a material different from the insulating barrier film 7 from the viewpoint of maintaining a high etching selectivity in the dry etching process, and may be an insulating film or a conductive film.
  • a silicon oxide film, TiN, Ti, Ta, TaN or the like can be used.
  • an opening is patterned on the hard mask film 8 using a photoresist (not shown), and an opening pattern is formed in the hard mask film 8 by dry etching using the photoresist as a mask.
  • the photoresist is removed by plasma ashing or the like (step A4; see FIG. 3A).
  • the dry etching is not necessarily stopped on the upper surface of the insulating barrier film 7 and may reach the inside of the insulating barrier film 7.
  • the insulating barrier film 7 exposed from the opening of the hard mask film 8 is etched back (dry etching) using the hard mask film (8 in FIG. 3A) as a mask.
  • An opening that communicates with the first wiring 5 is formed, and then an organic stripping process is performed with an amine-based stripping solution to remove copper oxide formed on the exposed surface of the first wiring 5 and at the time of etch back.
  • the generated etching double products are removed (step A5; see FIG. 3B).
  • the hard mask film (8 in FIG. 3A) is preferably completely removed during the etch-back, but may be left as it is in the case of an insulating material.
  • the shape of the opening of the insulating barrier film 7 can be circular, and the diameter of the circle can be 30 nm to 500 nm.
  • a resistance change element film 9 (for example, Ta 2 O 5 , film thickness 15 nm) is deposited on the insulating barrier film 7 including the first wiring 5 (step A6; see FIG. 3C).
  • the resistance change element film 9 can be formed using a PVD method or a CVD method.
  • step A6 moisture and the like are attached to the opening of the insulating barrier film 7 by the organic peeling process in step A5. Therefore, heat treatment is performed at a temperature of about 350 ° C. under reduced pressure before the resistance change element film 9 is deposited. It is preferable to degas by adding. At this time, care must be taken such as in a vacuum or a nitrogen atmosphere so that the copper surface is not oxidized again.
  • step A6 before the resistance change element film 9 is deposited, the first wiring 5 exposed from the opening of the insulating barrier film 7 is irradiated with SiH 4 gas under a reduced pressure of about 350 ° C. In this way, it is possible to suppress the diffusion of the metal (for example, copper) related to the first wiring 5 during the process by siliciding the surface of the first wiring 5.
  • the metal for example, copper
  • the first wiring 5 is formed, about 1 atm% Al is added to the Cu seed layer so that Al is diffused into the Cu during annealing of the Cu electroplating film, so that copper is alloyed. It becomes possible to become.
  • Such alloying or silicidation of copper has the effect of suppressing the mass transfer of copper itself in contact with the resistance change element film 9 (stabilizes copper), and improves the reliability when operating at a high temperature. Will be able to.
  • a second lower electrode (not shown; corresponding to 5a in FIG. 12) may be formed.
  • the second lower electrode for example, Ti, TiN, W, WN, Ta, TaN, Ru, RuO x or the like can be used, and their laminated structure (for example, TaN (lower layer) / Ru (upper layer)). There may be.
  • the first upper electrode 10 for example, Ru, film thickness 10 nm
  • the second upper electrode 11 for example, Ta, film thickness 50 nm
  • a hard mask film 12 for example, SiN film, film thickness of 30 nm
  • a hard mask film 13 for example, SiO 2 film, film thickness of 200 nm
  • the hard mask film 12 and the hard mask film 13 can be formed using a plasma CVD method.
  • the hard mask films 12 and 13 can be formed using a general plasma CVD method in this technical field.
  • the hard mask film 12 and the hard mask film 13 are preferably different types of films.
  • the hard mask film 12 can be an SiN film and the hard mask film 13 can be an SiO 2 film.
  • the hard mask film 12 is preferably made of the same material as a protective insulating film 14 and an insulating barrier film 7 described later. That is, all the surroundings of the variable resistance element are surrounded by the same material, so that the material interface can be integrated to prevent intrusion of moisture and the like from the outside and to prevent detachment from the variable resistance element itself.
  • a photoresist (not shown) for patterning the resistance change element portion is formed on the hard mask film 13, and then the hard mask film 13 is formed until the hard mask film 12 appears using the photoresist as a mask. After dry etching, the photoresist is removed using oxygen plasma ashing and organic peeling (step A9; see FIG. 4C).
  • the hard mask film (13 in FIG. 4C) As a mask, the hard mask film 12, the second upper electrode 11, the first upper electrode 10, and the resistance change element film 9 are continuously dry-etched (step) A10; see FIG. 5 (A)). At this time, the hard mask film (13 in FIG. 4C) is preferably completely removed during the etch-back, but may remain as it is.
  • step A10 for example, when the second upper electrode 11 is Ta, it can be processed by Cl 2 -based RIE, and when the first upper electrode 10 is Ru, RIE is performed with a mixed gas of Cl 2 / O 2. Can be processed. Further, in the etching of the resistance change element film 9, it is necessary to stop the dry etching on the insulating barrier film 7 on the lower surface.
  • the variable resistance element film 9 is an oxide containing Ta and the insulating barrier film 7 is a SiN film or a SiCN film, a CF 4 system, a CF 4 / Cl 2 system, or a CF 4 / Cl 2 / Ar system.
  • RIE processing can be performed by adjusting the etching conditions with a mixed gas such as.
  • variable resistance element portion can be processed without exposing the variable resistance element portion to oxygen plasma ashing for resist removal. Further, when the oxidation treatment is performed by oxygen plasma after the processing, the oxidation plasma treatment can be irradiated without depending on the resist peeling time.
  • a protective insulating film 14 (for example, a SiN film, 30 nm) is deposited on the insulating barrier film 7 including the hard mask film 12, the second upper electrode 11, the first upper electrode 10, and the resistance change element film 9. (Step A11; see FIG. 5B).
  • the protective insulating film 14 can be formed by a plasma CVD method, but it is necessary to maintain a reduced pressure in the reaction chamber before the film formation. At this time, oxygen is released from the side surface of the resistance change element film 9. There arises a problem that the leakage current of the ion conductive layer increases due to desorption. In order to suppress them, it is preferable to set the deposition temperature of the protective insulating film 14 to 250 ° C. or lower. Further, it is preferable not to use a reducing gas because the film is exposed to a film forming gas under reduced pressure before film formation. For example, it is preferable to use a SiN film or the like formed by using a mixed gas of SiH 4 / N 2 with high-density plasma at a substrate temperature of 200 ° C.
  • an interlayer insulating film 15 for example, silicon oxide film
  • an etching stopper film 16 for example, SiN film
  • an interlayer insulating film 17 for example, silicon oxide film
  • a wiring groove for the second wiring 18 and a pilot hole for the plug 19 are formed, and a barrier metal 20 (for example, TaN / Ta) is formed in the wiring groove and the pilot hole using a copper dual damascene wiring process.
  • the second wiring 18 for example, Cu
  • the plug 19 for example, Cu
  • the insulating barrier film 21 for example, SiN film
  • the second wiring 18 can be formed by using the same process as that for forming the lower wiring. At this time, by making the barrier metal 20 and the second upper electrode 11 the same material, the contact resistance between the plug 19 and the second upper electrode 11 is reduced, and the element performance is improved (the resistance of the resistance change element 22 when ON). Can be reduced).
  • the interlayer insulating film 15 and the interlayer insulating film 17 can be formed by a plasma CVD method.
  • step A12 in order to eliminate the step formed by the variable resistance element 22, the interlayer insulating film 15 is deposited thick, and the interlayer insulating film 15 is cut and planarized by CMP to form the interlayer insulating film 15 as a desired film. It is good also as thickness.
  • the uppermost portions of the upper electrodes 10 and 11 (second upper electrode 11) and the barrier metal 20 are made of the same material, so that the barrier metal 20 of the plug 19 and the second of the resistance change element 22 are formed.
  • the upper electrode 11 can be integrated, the contact resistance can be reduced, and the reliability can be improved by improving the adhesion.
  • the resistance change element 22 can be reduced in size and densified. As a result, the number of steps can be simplified.
  • the resistance change element 22 can be mounted only by creating a 2PR mask set, and the cost of the apparatus can be simultaneously reduced. Furthermore, the resistance change element 22 can be mounted inside a state-of-the-art device composed of copper wiring, and the performance of the apparatus can be improved.
  • FIG. 6 is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention.
  • Example 1 the variable resistance element film (9 in FIG. 1), the first upper electrode (10 in FIG. 1), the second upper electrode (11 in FIG. 1), and the hard mask film (FIG. 1). 12) is covered with a protective insulating film (14 in FIG. 1).
  • the variable resistance element film 9, the first upper electrode 10, the second A thick hard mask film 23 is formed on the stacked body of the upper electrode 11 and the hard mask film 12, and the resistance change element film 9, the first upper electrode 10, the second upper electrode 11, the hard mask film 12,
  • the side surface of the hard mask film 23 is covered with the protective insulating film 24.
  • the protective insulating film 24 is not formed on the hard mask film 23, but is formed on the insulating barrier film 7.
  • Other configurations are the same as those of the first embodiment.
  • the hard mask film 23 is a film that becomes a hard mask when the hard mask film 12 is etched.
  • the hard mask film 23 is preferably a different type of film from the hard mask film 12.
  • the hard mask film 23 can be a SiO 2 film.
  • the protective insulating film 24 is an insulating film having a function of preventing oxygen from detaching from the resistance change element film 9 without damaging the resistance change element 25.
  • the protective insulating film 24 is preferably made of the same material as the hard mask film 12 and the insulating barrier film 7. In the case of the same material, the protective insulating film 24, the insulating barrier film 7 and the hard mask film 12 are integrated to improve the adhesion at the interface.
  • FIG. 7 to 10 are process cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • an interlayer insulating film 2 (for example, a silicon oxide film, a film thickness of 300 nm) is deposited on a semiconductor substrate 1 (for example, a substrate on which a semiconductor element is formed), and then a barrier insulating film 3 (on the interlayer insulating film 2).
  • a semiconductor substrate 1 for example, a substrate on which a semiconductor element is formed
  • a barrier insulating film 3 on the interlayer insulating film 2.
  • an SiN film having a film thickness of 50 nm is deposited, and then an interlayer insulating film 4 (for example, a silicon oxide film having a film thickness of 300 nm) is deposited on the barrier insulating film 3.
  • Etching and photoresist removal are used to form wiring grooves in the interlayer insulating film 4 and the barrier insulating film 3, and then a barrier metal 6 (for example, TaN / Ta, film thickness 5 nm / 5 nm) is formed in the wiring grooves.
  • a barrier metal 6 for example, TaN / Ta, film thickness 5 nm / 5 nm
  • the first wiring 5 for example, copper
  • an insulating barrier film 7 for example, a SiN film, film thickness of 50 nm
  • a hard mask film (not shown, corresponding to 8 in FIG. 2C; for example, a silicon oxide film) is formed on the insulating barrier film 7, and then the hard mask film (FIG. 2C) is formed.
  • a photoresist (not shown) is used to pattern the opening, and dry etching is performed using the photoresist as a mask to form an opening pattern on the hard mask film (corresponding to 8 in FIG. 3A).
  • the photoresist is peeled off by oxygen plasma ashing or the like, and then the hard mask film (corresponding to 8 in FIG. 3A) is used as a mask and the hard mask film (corresponding to 8 in FIG. 3A).
  • the insulating barrier film 7 exposed from the opening is etched back (dry etching) to form an opening that leads to the first wiring 5 in the insulating barrier film 7.
  • Step B1 is the same as step A1 (see FIG. 2A) to step A5 (see FIG. 3B) of the first embodiment.
  • variable resistance element film 9 for example, Ta 0.8 Si 0.2 O x , film thickness 15 nm
  • RF Radio Frequency
  • a first upper electrode 10 for example, Ru, film thickness 10 nm
  • a second upper electrode 11 for example, Ta, film thickness 50 nm
  • Step B2 in RF sputtering of the resistance change element film 9, tantalum oxide containing 20% Si (Ta 0.8 Si 0.2 O x ) is used as a target, RF power is 2 KW, room temperature, Ar / O 2 mixed gas It can be deposited under conditions of 4 mTorr.
  • the first upper electrode 10 can be deposited by DC (Direct Current) sputtering using Ru as a target under conditions of DC power 0.2 kW, Ar gas, and 2 mTorr.
  • the second upper electrode 11 can also be deposited under the same conditions using Ta as a target by DC sputtering. Since both the upper electrodes 10 and 11 are deposited under reduced pressure, they are deposited at room temperature in order to suppress desorption of oxygen from the resistance change element film 9.
  • a hard mask film 12 for example, a SiN film, a film thickness of 30 nm
  • a hard mask film 23 for example, a SiO 2 film, a film thickness of 200 nm
  • the hard mask film 12 and the hard mask film 23 can be formed using a plasma CVD method.
  • the hard mask films 12 and 23 can be formed using a general plasma CVD method in this technical field.
  • a photoresist (not shown) for patterning the variable resistance element portion is formed on the hard mask film 23, and then the hard mask film 23 is formed until the hard mask film 12 appears using the photoresist as a mask.
  • the photoresist is removed using oxygen plasma ashing and organic peeling (step B4; see FIG. 8B).
  • a general parallel plate type dry etching apparatus can be used for the dry etching of the hard mask film 23.
  • step B5 using the hard mask film 23 as a mask, the hard mask film 12, the second upper electrode 11, the first upper electrode 10, and the resistance change element film 9 are continuously dry-etched (step B5; see FIG. 9A). ).
  • the planar shape of the hard mask film 23, the hard mask film 12, the second upper electrode 11, the first upper electrode 10, and the resistance change element film 9 is circular, the diameter is 50 to 550 nm, and the insulating barrier film 7 It is preferable that the dimension be larger than the diameter of the opening.
  • the hard mask film 23 is used as a mask, the hard mask film 12, the second upper electrode 11, the first upper electrode 10, and the insulating barrier film 7 including the resistance change element film 9, and the protective insulating film 24 (for example, SiN A film (30 nm) is deposited (step B6; see FIG. 9B).
  • the protective insulating film 24 for example, SiN A film (30 nm) is deposited (step B6; see FIG. 9B).
  • the protective insulating film 24 can be formed using SiH 4 and N 2 as source gases and using a high-density plasma at a substrate temperature of 200 ° C. Since a reducing gas such as NH 3 or H 2 is not used, the resistance change element film 9 (for example, Ta 0.8 Si 0.2 O x ) is reduced in the film forming gas stabilization process immediately before film formation. Can be suppressed. At this time, since the insulating barrier film 7, the protective insulating film 24, and the hard mask film 12 on the first wiring 5 are the same material as the SiN film, the periphery of the resistance change element is integrally protected to protect the interface. Adhesion is improved, hygroscopicity, water resistance, and oxygen desorption resistance are improved, and the yield and reliability of the device can be improved.
  • a reducing gas such as NH 3 or H 2
  • an interlayer insulating film 15 (for example, a silicon oxide film having a thickness of 500 nm) is deposited on the protective insulating film 24 by using a plasma CVD method (step B7; see FIG. 10A).
  • the interlayer insulating film 15 is planarized using CMP (step B8; see FIG. 10B).
  • CMP CMP
  • the CMP of the interlayer insulating film 15 can be polished using a general colloidal silica or ceria-based slurry.
  • the hard mask film 23 is exposed by planarizing the interlayer insulating film 15, and the hard mask film 23 and the protective insulating film 24 are also planarized.
  • an etching stopper film 16 for example, SiN film, film thickness 50 nm
  • an interlayer insulating film 17 for example, silicon oxide film; film thickness 300 nm
  • the barrier metal 20 in the wiring groove and the pilot hole is formed using a copper dual damascene wiring process.
  • the second wiring 18 for example, Cu
  • the plug 19 for example, Cu
  • the insulating barrier is formed on the interlayer insulating film 17 including the second wiring 18.
  • a film 21 for example, a SiN film is deposited (step B9; see FIG. 6).
  • step B9 the etching stopper film 16 and the interlayer insulating film 17 can be deposited using a plasma CVD method.
  • the second wiring 18 can be formed by using the same process as that for forming the lower layer wiring. At this time, by making the barrier metal 20 and the second upper electrode 11 the same material, the contact resistance between the plug 19 and the second upper electrode 11 is reduced, and the element performance is improved (the resistance of the resistance change element 25 when ON). Can be reduced).
  • Forming was performed by applying a voltage of ⁇ 5 V to the upper electrode 10 side of the resistance change element 25 formed in this way, and the resistance was changed to 100 ⁇ (low resistance). It was confirmed that 1 G ⁇ (high resistance) was obtained by applying a 0.5 V voltage in the reverse direction.
  • the same effects as those of the first embodiment are obtained, and in addition to the resistance change element 25, the outer peripheral portion of the plug 19 connected to the resistance change element 25 is also provided with the hard mask film 23 (for example, a silicon oxide film). Therefore, the connection part between the plug 19 and the resistance change element 25 is sufficiently protected, and the reliability can be improved.
  • the hard mask film 23 for example, a silicon oxide film
  • FIG. 11 is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to Example 3 of the present invention.
  • Example 2 the outer peripheral portion of the plug (19 in FIG. 6) connected to the variable resistance element (25 in FIG. 6) passes through a hard mask film (23 in FIG. 6; for example, a silicon oxide film).
  • the hard mask film 28 for example, a silicon oxide film
  • the protective insulating film 29 for example, SiN film
  • the interlayer insulating film 15 is disposed on the protective insulating film 29, and the resistance change element.
  • a plug 19 connected to 30 is buried in a prepared hole formed in the interlayer insulating film 15, the protective insulating film 29, the hard mask film 28, and the hard mask film 12 through the barrier metal 20.
  • Other configurations are the same as those of the second embodiment.
  • the hard mask film 28 is a film that becomes a hard mask when the hard mask film 12 is etched.
  • the hard mask film 28 is preferably a different type of film from the hard mask film 12.
  • the hard mask film 12 is a SiN film
  • the hard mask film 28 can be a SiO 2 film.
  • the protective insulating film 29 is an insulating film having a function of preventing the oxygen from the resistance change element film 9 without damaging the resistance change element 30.
  • the protective insulating film 29 is preferably made of the same material as the hard mask film 12 and the insulating barrier film 7. In the case of the same material, the protective insulating film 29, the insulating barrier film 7 and the hard mask film 12 are integrated to improve the adhesion at the interface.
  • the thickness of the hard mask film 28 (corresponding to 23 in FIG. 8A) is set in Step B3 of Example 2 (see FIG. 8A).
  • the protective insulating film 29 (24 in FIG. 10B) is not exposed when the interlayer insulating film 15 is planarized using CMP in step B8 (see FIG. 10B) in terms of thinning.
  • the second embodiment is the same as the second embodiment.
  • the same effect as that of the first embodiment is obtained, the thickness of the hard mask film 28 is reduced, and the area surrounded by the protective insulating film 29 is smaller than that of the second embodiment. It can also be applied to the most advanced devices with thin interlayer insulating films.
  • FIG. 12 is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to Example 4 of the present invention.
  • Example 1 the resistance change element film (9 in FIG. 1) is in direct contact with the first wiring (5 in FIG. 1) at the bottom, and the resistance change element film (9 in FIG. 1) is at the top.
  • the resistance change element film 9 is formed in the lower portion via the TaN / Ru laminated lower electrode 5a in the first wiring 5 in the configuration. And is electrically connected to the first upper electrode 10 via the upper resistance change element film 9a in the upper part.
  • Other configurations are the same as those of the first embodiment.
  • the TaN / Ru laminated lower electrode 5a is an electrode film interposed between the first wiring 5 and the variable resistance element film 9 in the variable resistance element 31, and is formed by stacking TaN (lower part) / Ru (upper part).
  • the resistance change element film 9 when copper is not required for the resistance change characteristic and ON / OFF is realized using a filament formed in the transition metal layer, the resistance change element film 9 and the first wiring 5 are used. In the meantime, it is necessary to divide with a material having a copper barrier property.
  • the TaN / Ru laminated lower electrode 5a is connected to the resistance change element film 9 and the first resistance change element film 9.
  • One wiring 5 is disposed.
  • TaN prevents diffusion of copper into the variable resistance element, and Ru has a small free energy for oxidation, which is advantageous for switching characteristics.
  • the upper resistance change element film 9 a is a resistance change element film disposed on the resistance change element film 9.
  • the upper resistance change element film 9a is made of a metal oxide having an absolute value of oxidation free energy larger than that of a metal component (eg, tantalum) in the resistance change element film 9 (for example, Ta 2 O 5 ).
  • a metal component eg, tantalum
  • a transition metal oxide such as Ti or Ni
  • a 3 nm-thick TiO film using a sputtering method can be used.
  • the first upper electrode 10 can be Ru
  • the second upper electrode 11 can be Ta.
  • the upper resistance change element film 9a can be controlled to be turned ON / OFF by forming a conductive path inside the oxide by applying a voltage or passing a current.
  • the TaN / Ru laminated lower electrode 5a is formed on the insulating barrier film 7 including the first wiring 5 in step A6 of the first embodiment (see FIG. 3C). Then, the resistance change element film 9 is formed in this order, and the upper resistance change element film 9a, the first upper electrode 10, and the second upper electrode 11 are formed on the resistance change element film 9 in step A7 (see FIG. 4A). In this order, in step A10 (see FIG. 5A), using the hard mask film (13 in FIG.
  • Example 2 is the same as Example 1 except that the variable resistance element film 9a, the variable resistance element film 9, and the TaN / Ru laminated lower electrode 5a are continuously dry-etched.
  • the same effect as that of the first embodiment is achieved, and the resistance change element film 9 does not require copper for the resistance change characteristic, and is turned on / off using the filament formed in the transition metal layer.
  • the present invention can also be applied when realizing the above.
  • FIG. 13 is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to Example 5 of the present invention.
  • FIG. 14 is an enlarged cross-sectional view of region R of FIG. 13 schematically showing the configuration of the semiconductor device according to Example 5 of the present invention.
  • a selection transistor 70 (MOSFET) is formed as a semiconductor element on the semiconductor substrate 1, and multilayer wiring layers (2 to 8, 15 to 21, 32 to 68) are formed on the semiconductor substrate 1 including the selection transistor 70.
  • the variable resistance element 22 similar to that of the first embodiment is incorporated.
  • the configuration around the resistance change element 22 is the same as that of the first embodiment.
  • the multilayer wiring layers (2 to 8, 15 to 21, and 32 to 68) are formed on the semiconductor substrate 1 with an interlayer insulating film 2, a barrier insulating film 3, an interlayer insulating film 4, an insulating barrier film 7, and a protective insulating film 14.
  • a plug 67 is embedded in a prepared hole formed in the barrier insulating film 3 via a barrier metal 68.
  • the first wiring 5 is embedded through the barrier metal 6 in the wiring groove formed in the interlayer insulating film 4 and the barrier insulating film 3.
  • the second wiring 18 is embedded in the wiring groove formed in the etching stopper film 16 and the interlayer insulating film 17, and is formed in the interlayer insulating film 15, the protective insulating film 14, and the hard mask film 12.
  • a plug 19 ′ is embedded in the prepared hole, the second wiring 18 and the plug 19 ′ are integrated, and the side surfaces and the bottom surface of the second wiring and the plug 19 ′ are covered with the barrier metal 20.
  • wiring 35 is embedded through barrier metal 36 in pilot holes formed in interlayer insulating film 32 and barrier insulating film 21 and wiring grooves formed in interlayer insulating film 34 and etching stopper film 33.
  • wiring 41 is embedded through barrier metal 42 in pilot holes formed in interlayer insulating film 38 and barrier insulating film 37 and wiring grooves formed in interlayer insulating film 40 and etching stopper film 39.
  • wiring 47 is embedded via barrier metal 48 in pilot holes formed in the interlayer insulating film 44 and the barrier insulating film 43 and wiring grooves formed in the interlayer insulating film 46 and the etching stopper film 45. ing.
  • wiring 53 is embedded via barrier metal 54 in pilot holes formed in interlayer insulating film 50 and barrier insulating film 49 and wiring grooves formed in interlayer insulating film 52 and etching stopper film 51.
  • the wiring 59 is embedded through the barrier metal 60 in the pilot holes formed in the interlayer insulating film 56 and the barrier insulating film 55 and the wiring grooves formed in the interlayer insulating film 58 and the etching stopper film 57. ing.
  • a wiring 64 is embedded in a prepared hole formed in the interlayer insulating film 62 and the barrier insulating film 61 via a barrier metal 65, and the wiring 64 is formed on the interlayer insulating film 62 via the barrier metal 65.
  • the barrier metal 66 is formed on the wiring 64
  • the protective insulating film 63 is formed on the interlayer insulating film 62 including the barrier metal 66, the wiring 64, and the barrier metal 65.
  • the source / drain electrodes of the selection transistor 70 are electrically connected to the uppermost wiring 64 via the corresponding plug 67, first wiring 5, plug 19 ′, second wiring 18, wiring 35, 41, 47, 53, 59. It is connected to the.
  • the multilayer wiring layer is formed by laminating the variable resistance element film 9, the first upper electrode 10, and the second upper electrode 11 in this order on the first wiring 5 serving as the lower electrode at the opening formed in the insulating barrier film 7.
  • the variable resistance element 22 is formed, the hard mask film 12 is formed on the second upper electrode 11, the variable resistance element film 9, the first upper electrode 10, the second upper electrode 11, and the hard mask film
  • the top surface or the side surface of the 12 laminated bodies is covered with a protective insulating film 14.
  • the resistance change element film 9 is interposed between the first wiring 5 serving as a lower electrode and the upper electrodes 10 and 11 electrically connected to the second wiring 18 through the plug 19. It has a configuration.
  • the resistance change element film 9 and the first wiring 5 are in direct contact with each other in the region of the opening formed in the insulating barrier film 7, and the plug 19 and the second wiring are formed on the second upper electrode 11.
  • the upper electrode 11 is connected via the barrier metal 20.
  • the plug 19 is buried in a prepared hole formed in the interlayer insulating film 15, the protective insulating film 14, and the hard mask film 12 via a barrier metal 20.
  • Copper can be used for wiring (including plugs; 5, 18, 19, 19 ', 35, 41, 47, 53, 59). Al can be used for the uppermost wiring 64. Tungsten can be used for the plug 67.
  • a Ta / TaN laminated body can be used for the barrier metal (6, 20, 36, 42, 48, 54, 60).
  • a Ti / TiN laminated body can be used for the barrier metals 65 and 66.
  • TiN can be used for the barrier metal 68.
  • As the interlayer insulating film (2, 4, 15, 17, 32, 34, 38, 40, 44, 46, 50, 52, 56, 58), a SiOCH film having a relative dielectric constant of 3 or less can be used.
  • a silicon oxide film can be used for the interlayer insulating film 62.
  • a silicon oxynitride film can be used for the protective insulating film 63.
  • SiN is used for the insulating barrier film 7 on the first wiring 5 and an insulating barrier film other than the insulating barrier film 7 (including a barrier insulating film and an etching stopper film; 3, 16, 21, 33, 37, 43) 49, 55, 61), a SiCN film having a low relative dielectric constant can be used.
  • the resistance change element 22 copper is used for the first wiring 5 serving as the lower electrode, TaSiO is used for the resistance change element film 9, Ru is used for the first upper electrode 10, and TaN is used for the second upper electrode 11.
  • the SiN film is used for the hard mask film 12 on the second upper electrode 11, and the SiN film formed by high-density plasma CVD is used for the protective insulating film 14 covering the resistance change element 22 including the hard mask film 12. be able to.
  • the periphery of the variable resistance element 22 can be formed by the same manufacturing method as that in the first embodiment, and the other methods use general techniques in the technical field. be able to.
  • variable resistance element 22 having the same configuration as that of the semiconductor device according to the first embodiment is applied has been described.
  • present invention is not limited thereto, and the semiconductor device according to the second to fourth embodiments. It is also possible to apply a resistance change element having the same configuration as in FIG.
  • variable resistance element 22 can be mounted inside the most advanced ULSI (Ultra-Large Scale Integration) logic.
  • Example 6 the materials used for the second upper electrode 11 and the barrier metal 20 in the semiconductor devices according to Examples 1 to 5 are replaced. Other configurations are the same as those in the first to fifth embodiments.
  • the second upper electrode 11 which is the uppermost part of the upper electrode is made of titanium nitride (TiN), and the barrier metal 20 is made of tantalum nitride (TaN).
  • TiN titanium nitride
  • TaN tantalum nitride
  • the adhesion is excellent and the connection resistance can be reduced.
  • the component contained in the second upper electrode 11 is TiN
  • the component contained in the barrier metal 20 is TaN containing nitrogen (N) which is the same component as the second upper electrode 11. This is because the connection resistance is reduced.
  • the second upper electrode 11 that is the uppermost part of the upper electrode is made of tantalum (Ta), and the barrier metal 20 is made of tantalum nitride (TaN).
  • Ta tantalum
  • TaN tantalum nitride
  • the adhesion is excellent and the connection resistance can be reduced.
  • the component contained in the second upper electrode 11 is Ta
  • the component contained in the barrier metal 20 is TaN containing Ta, which is the same component as the second upper electrode 11. This is because it has been reduced.
  • the uppermost part (second upper electrode 11) of the upper electrode in direct contact with the barrier metal 20 is made of a material containing the same component as that contained in the barrier metal 20.
  • the present invention can be applied to any device as long as it relates to the formation of a low-resistance and high-reliability element when a variable resistance element is formed in a copper multilayer wiring layer.
  • a variable resistance element is formed in a copper multilayer wiring layer.
  • the structure of the resistance change element is not limited to the present invention by using a laminated structure with another film.
  • the configuration of the present invention is that the copper wiring is integrated with the lower electrode or the lower electrode of the variable resistance element, and the upper surface of the variable resistance element is connected by a copper plug.
  • CMOS circuit which is a field of use as the background of the invention made by the present inventor, will be described in detail, and an example in which a variable resistance element is formed on a copper wiring on a semiconductor substrate will be described.
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random Access Memory
  • flash memory FRAM (Ferro Electric Random Access Memory)
  • MRAM Magnetic Random Access Memory
  • Semiconductor products having a memory circuit such as a resistance change type memory, bipolar transistor, etc., semiconductor products having a logic circuit such as a microprocessor, or the copper wiring of a board or a package on which the same is posted. it can.
  • the present invention can also be applied to bonding of electronic circuit devices, optical circuit devices, quantum circuit devices, micromachines, MEMS, and the like to semiconductor devices.
  • the example of the switch function has been mainly described.
  • the present invention can be used for a memory element using both non-volatility and resistance change characteristics.
  • the substrate joining method according to the present invention can be confirmed from the completion. Specifically, when a cross section of the device is observed with a TEM (Transmission Electron Microscope), it is confirmed that copper wiring is used in the multilayer wiring layer, and a resistance change element is mounted. It can be confirmed by observing whether the lower surface of the resistance change element is a copper wiring and the upper part is a copper plug. In addition to TEM, elemental analysis by EDX (Energy Dispersive X-ray Spectroscopy), EELS (Electron Energy-Loss Spectroscopy), etc. is performed, so that the second upper electrode and It can be confirmed whether the barrier metal of the plug is the same material. Furthermore, by performing the same composition analysis, it is possible to specify whether the insulating barrier film on the copper wiring and the protective film of the resistance change element are the same material.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur avec un élément de changement de résistance intégré qui permet d'augmenter la fiabilité, d'augmenter la densité et de réduire la résistance des électrodes. Elle concerne un dispositif semi-conducteur qui comporte un élément de changement de résistance à l'intérieur d'une couche de circuit multicouche sur un substrat semi-conducteur, dans lequel l'élément de changement de résistance est configuré avec une pellicule d'élément de changement de résistance dont la résistance change, intercalée entre une électrode supérieure et une électrode inférieure, et dans lequel la couche de circuit multicouche est équipée d'au moins un circuit qui est électriquement connecté à l'électrode inférieure et une borne qui est électriquement connectée à l'électrode supérieure, et dans lequel un métal de barrière recouvre les surfaces latérales et le fond de la borne et la partie supérieure de l'électrode supérieure est en contact direct avec le métal de barrière et est configurée à partir du même matériau que le métal de barrière ou un matériau qui contient les mêmes constituants que les constituants contenus dans le métal de barrière.
PCT/JP2010/050151 2009-01-09 2010-01-08 Dispositif semi-conducteur et son procédé de fabrication Ceased WO2010079827A1 (fr)

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JP2012099659A (ja) * 2010-11-02 2012-05-24 Toshiba Corp 記憶装置及びその製造方法
WO2012074131A1 (fr) * 2010-12-03 2012-06-07 日本電気株式会社 Dispositif à semi-conducteurs, et procédé de fabrication de celui-ci
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WO2013054515A1 (fr) * 2011-10-12 2013-04-18 パナソニック株式会社 Dispositif de mémoire non volatile à semi-conducteur et son procédé de fabrication
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CN110854266A (zh) * 2019-11-27 2020-02-28 上海华力微电子有限公司 阻变存储器及其形成方法
CN112467029A (zh) * 2020-11-25 2021-03-09 厦门半导体工业技术研发有限公司 一种半导体器件及其制造方法
CN113659074A (zh) * 2021-07-13 2021-11-16 桂林电子科技大学 一种平面型十字交叉阵列结构的阻变存储器及制备方法
CN119163524A (zh) * 2024-08-30 2024-12-20 南京理工大学 微推进器阵列装药药室与点火芯片层间键合涂胶的工艺

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US10490743B2 (en) 2015-09-24 2019-11-26 Nec Corporation Crossbar switch and method of manufacturing the same and semiconductor device
CN110854266A (zh) * 2019-11-27 2020-02-28 上海华力微电子有限公司 阻变存储器及其形成方法
CN112467029A (zh) * 2020-11-25 2021-03-09 厦门半导体工业技术研发有限公司 一种半导体器件及其制造方法
CN113659074A (zh) * 2021-07-13 2021-11-16 桂林电子科技大学 一种平面型十字交叉阵列结构的阻变存储器及制备方法
CN119163524A (zh) * 2024-08-30 2024-12-20 南京理工大学 微推进器阵列装药药室与点火芯片层间键合涂胶的工艺

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