WO2010075815A1

WO2010075815A1 - Method, apparatus and system for testing integrated circuits

Info

Publication number: WO2010075815A1
Application number: PCT/CN2010/000071
Authority: WO
Inventors: 林正浩
Original assignee: 上海芯豪微电子有限公司
Priority date: 2009-01-03
Filing date: 2010-01-15
Publication date: 2010-07-08
Also published as: CN101770967A

Abstract

A method, apparatus and system for testing integrated circuits are disclosed. A plurality of devices under test and a plurality of operation result comparison devices are in a common substrate. Identical input stimulations are applied to each of the plurality of devices under test and operation results are generated. The operation results are compared by using the corresponding comparison devices and compared features are obtained. Failure devices under test are sorted out according to the compared features.

Description

Integrated circuit parallel test method, device and system

Technical field

The invention belongs to the field of integrated circuits, and in particular relates to a parallel testing method, device and system for an integrated circuit. Background technique

A typical semiconductor fabrication process is to fabricate a plurality of identical rectangular dies on a thin, uniform wafer of semiconductor material. The grains are separated by a scribe line having a width of 60 to 80 μm. Mask aligners are often placed on the scribe lines and tested for wafer quality test (WAT) during production.

During fabrication, the lithography machine exposes one region at a time, referred to as a stepper field, each lithographic region containing one or more dies. When all the fabrication processes are completed, each die on the wafer passes a functional test. The wafer prober uses a probe card to contact the pad of the die to be tested, and transmits the test stimulus generated by the test program to the die to be measured, and the measured die response input is generated. The corresponding output is transmitted to the tester via the test card and compared with the expected result. If the two are equal/matched, the measured die is considered to be functioning correctly. Test one die at a time.

When a measured die passes all test procedures, its position is recorded for preparation for subsequent packaging. The measured die that has not passed the test will be marked with ink or stored in a file called a wafer map (waferraap). When all the tests are completed, the wafer will be cut along the scribe line, the separated functionally correct dies will be packaged, and the failed dies will be discarded. The packaged chip will be tested after packaging and the functionally correct chip will be delivered to the customer.

1 is a schematic diagram of a general wafer test in which a wafer to be tested (101) is placed on a wafer testing device (102), and a tester (103) energizes a test generated by a test vector generator (104) through an input cable ( 105) Passed to the needle test card (107) on the test head (106), the needle test card (107) inputs data into the die to be tested (108), and reads out from the die to be tested (108) As a result, the test head (106) and the output cable (111) are passed to the tester (103), and the tester (103) sends the result to the comparator (109) and compares it with the expected result (110) to determine the Whether the die (107) to be tested is invalid.

As integrated circuit manufacturing processes have evolved, wafer sizes have increased from 1 inch to 12 inches, resulting in ever-increasing parallelism in die production, accommodating nearly 10,000 wafers per wafer. But because of the test equipment test channel (channel) The limitation of the number makes the wafer test still serial, and each die is tested one by one. The wafer test time is proportional to the number of die on the wafer, the test time becomes extremely long, and the test cost becomes high. On the test equipment, only the probe moves to another die after testing one die for 100ms~250ms. This time cannot be used for testing and is wasted. This further increases test time and increases test costs. At present, in the production of integrated circuits, the cost of testing and packaging has accounted for about 25% to 30% of the total production cost, and even has reached 50%.

In addition, since the test equipment to die connection delay limits the test frequency, the test can only be performed at a lower frequency. To solve this problem, one approach is to implement parallel testing using multi-site. However, the method is limited by the number of channels of the test equipment; the number of channels per test equipment is between 128 024, and the number of pads of a die is hundreds of thousands, so that the parallelism of the test does not increase much, generally Two to four channels, and the channel is expensive, increasing the channel will greatly increase the price of test equipment and increase the cost of testing.

Another method is to implement on-wafer chip self-testing. The following three patents relate to this method, but are different from this patent. Patent No. 200510008164. X Chinese Patent "Wafer that can perform aging and electrical testing and its implementation method" proposes a method for simultaneous aging and electrical testing on a wafer. The method provides an aging pattern generation circuit on the wafer, which can generate non-functional, continuously inverted excitations into the die while performing aging and electrical testing, which does not require testing. The device outputs test results.

The Chinese patent "Semiconductor Wafer with Test Circuits and Manufacturing Method" of Patent No. 200410046002. 0 proposes a method for accurately measuring the voltage of a chip on a wafer. The method sets a test circuit on the scribe line, so that the output impedance is much smaller than the impedance of the probe, and the input impedance is much larger than the output impedance of the die, so that the probe can accurately measure the reference voltage of each electrode pad of the die.

The Chinese patent "Circuit Structure for Testing Integrated Circuit Components" of the patent No. 86105604 proposes a test circuit structure based on circuit components on a substrate. The circuit components under test are formed as an integrated circuit on a common substrate and are operable via common supply and input lines on the substrate. The test circuit and the switch unit of the circuit structure are formed as an integrated circuit on the same substrate, and the switch unit can be controlled by the test circuit and inserted in the connection between the test circuit and the circuit component, and the expected value is transmitted to the substrate for use. The circuit is compared for comparison. The i-type circuit is equipped with an output circuit that transmits the test result. When testing the circuit component, the self-test uses the central unit of the test circuit to compare the actual and expected values to determine whether the component is qualified or not, and serially tests.

In summary, the existing integrated circuit test methods, devices, and systems, due to the limitation of the number of test channels, can only test one or several units to be tested at a time, and cannot achieve large-scale simultaneous/parallel comparison of the units under test. . The number of test channels is limited Restrict the bottleneck of improving test efficiency. Summary of the invention

The present invention provides an integrated circuit test method, apparatus, and system for testing a plurality of functionally identical microelectronic circuits on a common substrate, including a plurality of executions of the same on a common substrate The test excitation unit is tested, and the signal of the output of the device under test (DUT) is compared with the expected result in parallel by the comparing device, or the signals of the corresponding output ends of the plurality of tested units are compared with each other by the comparing device, To detect the failed unit under test. The invention realizes parallel testing of thousands of units to be tested without substantially increasing the test channel.

The present invention provides an integrated circuit test method for testing a plurality of functionally identical microelectronic circuits in parallel on a common substrate; the substrate may be a wafer or a single integrated circuit chip. It can also be a circuit board; wherein the method includes:

(a) input the same test stimulus to the plurality of functionally identical units under test on the substrate;

(b) comparing the corresponding outputs of the plurality of measured units in parallel by the comparing means;

(c) outputting comparison results and position information of a plurality of comparison devices through an output path;

(d) Detecting the comparison result of the output and the position information on the substrate, classifying the corresponding unit to be tested, classifying the unit under test with the same/matched comparison result as a normal unit, and measuring the unequal/unmatched comparison results The unit is classified as a suspected failure unit.

The present invention also provides an integrated circuit testing method for testing a plurality of functionally identical microelectronic circuits in parallel on a common substrate; the substrate may be a wafer, a single integrated circuit chip, or a circuit board; The method includes:

(a) input the same test stimulus to a plurality of functionally identical units under test on the substrate through an input path;

(b) comparing, by the comparing means, the output of the plurality of measured units in parallel with the expected result of the corresponding position input from the input path;

• (d) Detecting the comparison result of the output and the position information on the substrate, classifying the corresponding unit to be tested, and comparing the results The equal/matched unit under test is classified as a normal unit, and the unit under test whose unequal/unmatched comparison result is classified as a failed unit.

The present invention provides a wafer comprising a plurality of functionally identical dies to be tested, wherein the functional modules of the plurality of dies or the plurality of dies having the same function are the units to be tested; wherein the wafer is on the wafer Also included is an auxiliary test device fabricated by a semiconductor process; the auxiliary test device may be partially located inside the unit to be tested, or may be entirely located outside the unit to be tested, including:

(a) a power supply circuit that is connected to the power input of the auxiliary test device;

(b) an input path connecting the signal inputs of the plurality of measured units; the input path is also used to transmit the expected result to one end of the comparing device when the expected result exists;

(c) a comparison device, one input connected to the output to be tested of a unit under test, the other input being connected to the output of the other unit under test, or for inputting the expected result The corresponding input channels are connected;

(d) a register circuit that connects the output of the comparator and the output circuit for registering the output of the comparator;

(e) The output circuit is connected to a plurality of register circuits, and outputs the comparison result of the corresponding comparison device and the position information of the corresponding measured unit.

When the auxiliary test device on the wafer of the present invention is located inside the die to be tested, the auxiliary test device can be set to disable when the measured die is working normally; when the auxiliary test device is located When the outside of the die is measured, the electrical connection between the auxiliary test device and the die to be tested can be completely cut off when the wafer is cut.

The additional test pads required for testing on the wafer of the present invention can be placed in the die, placed in the scribe line, or placed in the unused corner pad of the die. It can also be placed in the unused no connection pad position of the die; when testing, the probe contacts the port pad or test pad corresponding to a single or multiple die on the wafer, and can pass the input. The channel transmits power and signals to the grains in all or selected areas of the wafer.

The unit under test on the wafer of the present invention can wirelessly obtain power by means of electromagnetic waves.

The power supply circuit on the wafer of the present invention can also be connected to the power input terminals of a plurality of units to be tested.

The power supply circuit on the wafer of the present invention may be formed by hard wiring, or by a configurable switching line, or by a combination of hard wiring and configurable switching lines.

The input path on the wafer of the present invention can be electrically connected through a wired interconnect circuit connected to the signal input end of the unit under test A hybrid connection, or a direct transmission mode of electromagnetic waves, or a hybrid connection of electrical interconnections of wired interconnection circuits and direct transmission of electromagnetic waves, inputs data signals and control signals to a plurality of units to be tested on the wafer. The wired connection between the input path of the wafer and the unit under test and the comparison device of the present invention may be composed of hardwired wires, or formed of configurable switch lines, or a combination of hardwired and configurable switch lines. The input path on the wafer of the present invention may further comprise a conversion device connected to the device under test for converting the input signal and then inputting to the input terminal. The conversion includes, but is not limited to, conversion of a digital signal to an analog signal or conversion of an analog signal to a digital signal.

When the wired interconnection circuit of the unit under test on the wafer of the present invention is configurable, the on/off of the circuit connection in the wired interconnection circuit can be configured by an external device in a parallel or serial configuration. When the data signal and the control signal or the expected result are transmitted, the circuit connection corresponding to the input terminal is configured to be turned on, and the circuit connection corresponding to the output terminal is configured to be disconnected. By configuring the connection between the corresponding input terminals of different units to be tested, according to the position where the test excitation source is located, the connection in the direction away from the position where the test excitation source is located is turned on and the connection in the opposite direction is disconnected. The propagation network of the same test excitation input between the units is measured, so that the plurality of units under test obtain the same test excitation.

In one embodiment, the wired interconnect circuit of the present invention includes a tape-driven connection that is disconnectable between respective input pads of the measured die. Configuring the connection between the different tested dies corresponding to the input end, according to the position of the test excitation source, turning on the belt-driven connection away from the position where the test excitation source is located and disconnecting the opposite direction The driving connection can form a propagation network of the same test excitation input between the measured crystal grains, so that each measured crystal obtains the same test excitation.

+ comparing means on the wafer of the present invention for sampling signals at the output of each of the plurality of cells under test and in parallel with corresponding expected results input from the input path, or for a plurality of The signals of the output of each unit under test and the corresponding output of another unit under test are sampled and compared with each other. The comparing means on the wafer of the present invention may comprise switching means coupled to the unit under test for converting the signal at the output before comparing.

The comparison device on the wafer of the present invention may further comprise a result merging compression device for temporally and spatially merging compression of the comparison result. The merging compression in time, that is, the comparing means may further include an accumulating circuit connected to the unit under test for accumulating and registering the output of the comparing means. The spatial merge compression combines the comparison results of the adjacent plurality of outputs of the same measured unit into one result. The comparing device for testing the unit under test on the wafer in parallel, for applying the same excitation to the input end of each unit under test, sampling, converting and comparing the output and expectation of the output end of the output end Whether the result is equal/matched, or the sampling, conversion, and comparison of the corresponding output outputs of the plurality of measured units. The output of the output terminal may be a signal value on an external output port of the unit under test, or may be a signal value inside the unit under test. The output sampling point of the output terminal may be an external output port of the unit under test, or may be a sampling point inside the unit under test. The sampled sample can be any form of signal including, but not limited to, a digital signal, an analog signal. The conversion includes, but is not limited to, simulating a conversion of a signal such as current, voltage, impedance, etc. to a digital signal or a conversion of a digital signal to an analog signal. The comparison may be a parallel comparison between the running results of the tested units and the expected results of the incoming, or may be a parallel comparison between the operating results of the tested units.

When using the present invention for grain parallel testing, a single or multiple output signals of a single or a plurality of measured units can be sampled to ensure that the change of the signal at the output or the output is correct to avoid Some errors, such as a power failure, cause the unit under test to be inoperable, but the results of the operation show a valid misjudgment. The singular or plural output signals may be singular bits or a plurality of bits of the digital output, or may be one or more ports of the simulated output. The plurality of bits or ports may be taken from different units to be tested. The sampling judgment may be performed by sampling the corresponding single or plural operation result signals and sending them to an external device for judgment, or may use the functional modules on the wafer to sample the corresponding single or plural operation result signals. Judgment. The functional modules include, but are not limited to, a counter. The determination method includes, but is not limited to, checking whether the number of signal changes recorded by the counter is consistent with expectations.

The sampling and judging method can be described by taking a microprocessor die as an example. This embodiment is implemented on the premise of the technical solution of the present invention, but the present invention is not limited by the embodiment. Take a bit signal in the microprocessor data output bus for sampling judgment. The corresponding counter has a storage function that can store the recorded value. The counter is initially zero. After the test vector is started, the logic value of the signal is detected every internal clock cycle of the microprocessor. Each time a logic 1 is detected, the corresponding counter is incremented by 1. After all test vectors have been run, if the value stored in the corresponding counter is consistent with the expected value, it means that the test is valid, and it can be determined whether the unit under test is valid according to the corresponding test characteristics. If the value stored in the corresponding counter does not match the expected value, it means that the test is invalid or the unit under test is invalid.

Taking the DC characteristic test of the measured unit as an example, the DC characteristic value obtained by the test can be compared to determine whether the DC characteristic value satisfies the requirement. The comparison includes, but is not limited to, a comparison with a reference DC characteristic, and a comparison between a plurality of measured cell DC characteristic values.

The comparison device may be a device including only sampling and comparison functions, or may include sampling, conversion, and comparison work. Able device. In the comparison device of the present invention, the operation result may be sampled first, and then the samples obtained by sampling may be compared; the running result may be continuously compared first, and the continuous comparison result may be sampled as an actual comparison result. • The comparison device may also include a failure determination function. When the expected result exists, the specific determination method is: if the output signal of the output of the unit under test is equal/matched with the expected result, the unit to be tested can be determined to be an effective unit; if the output of the unit under test outputs a signal and an expectation If the result is not equal/mismatched, it can be determined that the unit under test is a suspected failure unit. When the expected result does not exist, the specific determination method is: comparing the output signal of the output of each unit under test with the output signal of the corresponding output of the adjacent single or multiple units under test, if all the comparisons are completely equal/matched, Then, the unit under test can be determined to be an effective unit, otherwise the unit under test can be determined to be a suspected failure unit. For the suspected failed unit, further judgment can be made according to a simple rule, which can be implemented on the wafer including the unit under test, or can be implemented outside the wafer including the unit under test. Since the number of effective units in the unit under test is far more than the number of failed units, for the suspected failed unit, the conventional test excitation can be separately performed as needed to determine whether it is a true failed unit.

If the port of the unit under test on the wafer of the present invention is used as input and test/output bi-directional multiplexing, then the port will be connected to the port when the port is used as an output. The corresponding input path is set to high impedance. For the input of the unit under test and the test/output bidirectional multiplexer that is directly in contact with the probe, there may be an additional output corresponding to the port for testing the bidirectional multiplexed port. The input and test/output bi-directional multiplexers and the additional outputs are both coupled to a comparison device.

The output circuit on the wafer of the present invention may be constructed of hardwired or constructed of configurable switch lines or by a combination of hardwired and configurable switch lines.

The output circuit for testing the unit under test on the wafer in parallel can output position information of a plurality of measured units in the wafer and the result of the corresponding comparison device to the probe, probe card or test Machine. The output circuit can be configurable or fixed. When the output circuit is configurable, it includes an output path and a connection switch, and each output path is connected to a single number or a plurality of comparison means. According to the configuration of the conduction connection switch, different output paths at both ends of the connection switch can be connected to a single number of output paths. According to the configuration, the connection switches are disconnected, and the different output paths at both ends of the connection switch are independent output paths. When the output circuit of the present invention constitutes a single number or a plurality of output paths by a fixed connection, the connection switch can be omitted.

The output mode of the output circuit includes, but is not limited to, a serial output, such as serial output of a single number of output paths to output corresponding output information, or parallel output, such as multi-probe parallel acquisition of corresponding output information from a plurality of output paths, or The serial parallel hybrid outputs the corresponding output information. If the output circuit only contains a single number of output paths, you can use serial shifting Get all the output information. If the output circuit includes a plurality of output paths, the comparison result may be sequentially obtained from the plurality of output paths in parallel by using multiple probes, or the comparison result may be sequentially obtained from the plurality of output paths by using a single number or a plurality of sets of probes in turn. .

The output information outputted by the output circuit may be a determination result of whether each of the tested units is invalid, or may be a comparison result output by the comparison device corresponding to the output end of the measured unit.

The input channel and the output circuit for testing the unit under test on the wafer in parallel can be established at the same time by inputting configuration information in a serial manner, or can be established step by step by inputting configuration information multiple times. The input channel can transfer input excitation and expected results from the unit under test where the probe is located to all units under test. The output circuit can output test information of all the tested units or the output of the measured unit to the unit under test where the probe is located. The design of the input channel and the output circuit of the invention is higher than the design reliability of the unit under test, and has a self-detection function, which can be pre-tested once after the establishment is completed to ensure the input channel and the output circuit. The correctness of itself. If the prediction is not passed, the probe can be moved to re-establish the input channel and output circuit from the other unit under test, and the self-test is repeated. For example, the test excitation for self-test can be transmitted to each unit under test through the input channel, and then the test excitation of the self-test is serially derived through the output circuit, thereby realizing the input channel and the output circuit. test.

The input channel for testing the unit under test on the wafer in parallel may be located on the wafer including the unit under test, and the specific location on the wafer includes but is not limited to the unit under test The inner portion and the portion are outside the unit to be tested on the wafer and all outside the unit to be tested on the wafer. The wires used to form the input channel or output circuit can be placed in the scribe line or placed within or through the die. The means and wires placed in the scribe line are automatically cut off during die cutting without affecting the function of the die itself. The test pads placed in the corner pads and vacant pads also do not affect the function of the die itself. On the wafer, the alignment marks can be moved to the corner pad locations of the die. The auxiliary test device can be placed within the die, or placed in a scribe line or placed on another wafer and coexisted with a test structure for wafer acceptance testing. The method of coexistence may be to bypass the wafer acceptance test (WAT) test structure or share the WAT test structure at certain locations, such as borrowing a test pad from the WAT test structure for input of the stimulus.

In addition, capacitors can be fabricated in the scribe line to mimic the load to be driven by the measured die output, making the test more realistic. .

Some or all of the layout of the auxiliary test device on the wafer of the present invention can be automatically generated based on a few basic cells using a computer place and route tool. Because the current provided by the existing test machine is not large enough, it is difficult to complete large-scale shared base integrated circuit test with high clock frequency by using the common base integrated circuit test system built by the existing test machine. One solution is to perform multiple tests on a shared base integrated circuit. The multiple test can first test the complete long test program of a large number of tested units at a low speed, complete the functional test, and then partition the high-speed test of the critical path short test program of a small number of tested units to test the speed of the tested unit. Another solution is to use the integrated circuit test system described below.

The present invention provides an integrated circuit parallel test system, including a test wafer, a probe card, and a test machine; wherein the test wafer may include all or part of an auxiliary test device fabricated by a semiconductor process; The probe card may be composed of another substrate including some or all of the auxiliary test devices; the test machine has a plurality of power supplies and corresponding current limiters, which can be all on the wafer The measuring unit shunts simultaneously supplies sufficient current to ensure that the unit under test can work at a given operating frequency and can cut off the corresponding power supply when any of the units under test are short-circuited.

The system of the present invention is capable of performing self-tests to eliminate errors in the auxiliary test device itself, including the ability to establish input paths and output circuits on the wafer, and to maintain or reconstruct inputs based on test results of the input and output circuits. Path and output circuit.

The auxiliary testing device of the system of the present invention comprises:

(a) a power supply circuit connected to the power input of the auxiliary test device;

(c) Comparing device, one input connected to the output to be tested of one measured unit, the other input connected to the corresponding output of the other measured unit, or the corresponding input path for inputting the expected result Connected

In the system of the present invention, the electrical connection between the auxiliary test device located outside the die on the wafer to be tested and the die to be tested can be completely cut off when the wafer is cut.

In the system of the present invention, the unit under test can obtain power wirelessly by means of electromagnetic waves.

The power supply circuit in the system of the present invention can also be connected to the power input terminals of a plurality of units to be tested. The wafer in the system of the present invention, wherein the wired power supply circuit may be composed of hardwired wires, or may be composed of configurable switch lines, or a combination of hardwired and configurable switch lines.

The input path in the auxiliary test device in the system of the present invention can be electrically connected by a wired interconnection circuit connected to a signal input end of the unit under test, or directly transmitted by electromagnetic waves, or electrically connected by a wired interconnection circuit and directly transmitted by electromagnetic waves. The data signal and the control signal are input to a plurality of units to be tested on the wafer.

The wired connection between the input path of the auxiliary test device and the unit under test and the comparison device in the system of the present invention may be composed of hardwired or configurable switch lines, or hardwired and configurable switch lines. Combined composition.

The input path in the auxiliary test device in the system of the present invention may further comprise a conversion device connected to the device under test for converting the input signal and then inputting to the input terminal.

The comparing device in the auxiliary testing device in the system of the present invention is configured to sample the signal of the output end of each of the plurality of tested units and compare them with the corresponding expected result input from the input path, or to a plurality of The signals of the output of each of the units under test and the corresponding outputs of the other unit under test are sampled and compared with each other. The comparison means in the auxiliary test apparatus of the system of the present invention may include a conversion means coupled to the unit under test for converting the signal on the output prior to comparison.

The comparison means in the auxiliary test apparatus of the system of the present invention may further comprise a result merging compression means for comparing the results with temporal and spatial merge compression.

In the system of the present invention, if the port of the unit under test is bidirectionally multiplexed as input and test/output, the corresponding input path connected to the port is set to high impedance by the configuration when the port is used as an output.

The output circuit in the auxiliary test device of the system of the present invention may be constructed of hardwired or constructed of configurable switchwires or by a combination of hardwired and configurable switchwires.

Another substrate constituting the probe card in the system of the present invention includes, but is not limited to, a wafer or a printed circuit board; the other substrate can simultaneously supply all or part of the power of all or part of the unit under test on the tested wafer and The signal input port provides power and test excitation.

In the system of the present invention, the probe card and the tested wafer are connected by a bump; the protrusion may be located on the probe card, or may be located on the wafer to be tested, or in the probe card and measured There are bumps on the wafer. The other end of the other substrate is connected to the test machine.

For example, a solder ball on a wafer can be used as a probe and other wafers or other boards can be overlaid onto the wafer under test. On the top, test some or all of the tested units on the tested wafer in parallel. In the test system including other wafers or other boards, the comparators for testing may be located on the wafer under test or on other wafers or other boards. The other wafers include, but are not limited to, the same process as the wafer to be tested and a process that is later than the wafer to be tested. The other wafers or other boards include, but are not limited to, wafers or boards of the same size as the wafer being tested, or wafers or boards larger than the wafer being tested. The other wafer or other circuit board includes, but is not limited to, through silicon vias

(TSV, through silicon via) wafer or circuit board with through holes and metal wires, and wafers with integrated circuit blocks on both sides. It is also possible to use a printed circuit board with a metal wire as a probe card, and use a solder ball as a probe to transmit power and test excitation through the metal wire through the solder ball to all or part of the unit under test. Or part of the input port.

In the system of the present invention, the probe card is electrically connected to the tested wafer, and the test excitation and/or power supply can be transmitted to the plurality of units under test by electromagnetic wave.

The test machine features in the system of the present invention include:

(a) capable of generating or storing configuration information corresponding to the connection relationship between the device under test and the auxiliary test device on the wafer, and capable of adjusting the corresponding configuration information according to the coordinates of the current die of the probe and transmitting the same to the wafer Configuration information;

(b) The positional information of the unit under test in the substrate and the result of the corresponding comparison device can be read from the wafer. The test machine features in the system of the present invention may include the ability to generate or store data signals and control signals for testing the unit under test on the corresponding wafer, i.e., test excitation, and to transmit the test stimulus to the wafer.

The test machine features in the system of the present invention can include the ability to generate or store an expected result of a corresponding test stimulus and to transmit the expected result to the wafer. The test machine feature in the system of the present invention may include the ability to classify the unit under test according to whether the comparison result satisfies the test requirement, and record and output the position information of the unit under test on the wafer or on the wafer and within the die. .

The present invention provides an integrated circuit chip including a plurality of functional modules to be tested, wherein the plurality of functional modules having the same function are the tested units to be tested; wherein the integrated circuit chip further includes an auxiliary testing device. The auxiliary test device operates only when the integrated circuit chip is in a test mode; the test mode includes but is not limited to a plurality of measured units operating in parallel to perform the same input excitation; the auxiliary test device may be partially Located inside the unit under test, it can also be located in whole or in part outside the unit under test, including:

(a) a power supply circuit that connects the power input terminals of the plurality of units to be tested; (b) an input circuit that connects the signal inputs of the plurality of cells to be tested; and when there is an expected result, the input circuit is further configured to transmit the expected result to one end of the comparing device;

(c) Comparing device, one input connected to the output of the device under test to be tested, the other input connected to the corresponding output to be tested of the other unit under test, or a corresponding input circuit for inputting the expected result Connected

(e) The output circuit is connected to the output terminals of the plurality of comparison devices, and outputs the comparison result of the corresponding comparison device and the position information of the corresponding unit to be tested. In the integrated circuit chip of the present invention, the input circuit can electrically input the data signal and the control signal to the unit under test in the integrated circuit chip through a wired interconnection circuit connected to the signal input end of the unit under test.

The input circuit in the integrated circuit chip of the present invention may further comprise a conversion device connected to the device under test for converting the input signal and then inputting to the input terminal.

The connection of the input circuit to the unit under test and the comparing means in the integrated circuit chip of the present invention may be constituted by hard wiring, or by a configurable switching line, or by a combination of hard wiring and configurable switching lines.

The test excitation source for generating the data signal and the control signal in the integrated circuit chip of the present invention may be external to the integrated circuit chip, or may be inside the integrated circuit chip, and may also be generated by externally generating test excitation and stored in the Within the integrated circuit chip.

The comparing means in the integrated circuit chip of the present invention may further comprise switching means connected to the unit under test for converting the signal on the output before comparing.

The comparison means in the integrated circuit chip of the present invention may further comprise a result merging compression means for temporally and spatially merging compression of the comparison result. The output circuit of the integrated circuit chip of the present invention may be composed of hard-wired or configurable switch lines, or a combination of hard-wired and configurable switch lines.

The integrated circuit chip of the present invention can output the position of the unit under test in the substrate and the result of the corresponding comparison device through the output circuit, and can also save the test result in the memory inside the integrated circuit chip.

The integrated circuit chip of the present invention can mark the failed function module to be tested according to the test result stored in the memory, and include the integrated circuit if the effective function module having the same function as the failed function module is redundant. The chip's hardware/software system can replace the failed function module with redundant effective function modules for self-repair. W

13

The invention provides a circuit board comprising a plurality of tested units with the same function, wherein the unit to be tested is a packaged chip to be tested; wherein the circuit board has a plurality of slots (chip socket) The circuit board has an interface for connecting to the test machine; the circuit board also has an auxiliary test device, including:

(a) at least one comparison chip;

(b) an electrical connection to the comparison chip, the plurality of units to be tested, and the test machine interface. The circuit board of the present invention may further include at least one buffer chip connected to the test unit and the test machine interface through an electrical connection.

The circuit board of the present invention, wherein the test excitation of the unit under test can be transmitted from the test machine directly to the plurality of units under test via an electrical connection on the circuit board, or buffered from the test machine via the buffer chip. Then, it is transmitted to a plurality of units to be tested through an electrical connection, or transmitted from the test machine to the plurality of units under test via electromagnetic wave generators in the form of electromagnetic waves.

Each of the comparison chips in the circuit board of the present invention has a complex array dedicated input port, and all of the dedicated input ports of all the comparison chips are respectively connected to the output of the plurality of slots through electrical connection one by one. a port and an input/output multiplexing port; the comparison chip is capable of receiving an output signal of the test unit after the test unit is excited by an electrical connection, and receiving each output signal of each measured unit and the other measured unit The corresponding output signals are compared in parallel to generate a comparison result.

Each of the comparison chips in the circuit board of the present invention has a complex array dedicated input port, and all of the dedicated input ports of all the comparison chips are respectively connected to the output of the plurality of slots through electrical connection one by one. a port and an input/output multiplexing port; the comparison chip further has an electrical connection with the test machine interface for receiving an expected result; and the comparison chip is capable of receiving an output signal of the test unit after the test unit is excited by the electrical connection And comparing each received output signal of each measured unit with the corresponding expected result in parallel to generate a comparison result.

The comparison chip in the circuit board of the present invention may further comprise a result merging compression device for performing temporal and spatial merging compression on the comparison result to generate a test result.

In the circuit board of the present invention, the test result of the comparison chip to the unit under test is transmitted back to the test machine through an electrical connection.

The circuit board of the present invention may further include only one type of chip; the chip includes functions of a comparison chip and a buffer chip. The complete function of the circuit board in the circuit board of the present invention may be implemented by a plurality of electrically connected circuit boards; a circuit board of the plurality of circuit boards may implement a part of the complete function or the complete function.

The essence of the integrated circuit parallel test method, apparatus and system proposed by the present invention and the existing methods, devices and systems are as follows:

1. The technical solution of the present invention can transmit the same test excitation and/or expected result to all the tested units in the selected area on the substrate through the input channel, while the existing methods, devices and systems only The test stimulus and/or expected result can be transmitted to one unit under test at a time. Even if the multi-probe test machine is used, it is essentially tested in turn, and it is impossible to test all the units tested in parallel;

2. The technical solution of the present invention can perform parallel testing on all the tested units in the selected area on the substrate, and the existing methods, devices and systems can only test all the tested units in turn;

3. The comparison in the technical solution of the present invention may be a parallel comparison between the output signals of all the tested units and the expected results, and the existing methods, devices, and systems respectively separate the output signals of the measured unit from the expected results. Comparison of each;

4. The comparison in the technical solution of the present invention may also be a parallel comparison between the signals of the output units of the tested units that are not known to be effective, and the existing methods, devices, and systems all use the output signals of the units to be tested. Known reference values are known, and known reference values include values stored in the test instrument or results of known valid units.

Beneficial effects:

At present, the efforts in the field of integrated circuit testing are mainly in the following three aspects:

1. Reduce the test cost (Test Cost);

2. Shorten the time to mass production (Time to Market);

3. Defective Parts Per Million; The invention adopts a method of parallel testing of multiple integrated circuits under test, and can test a single or a plurality of integrated circuits under test with one input excitation, which is compared with the traditional one test. Testing an integrated circuit and testing each of the N-die requires a N* (M+L) test time. The test method of the present invention requires only M+L+N*R test time (where M is a mobile pin card or mobile) The time of the integrated circuit to be tested, L is the time to perform the test excitation, R is the time to output the test feature, R is much smaller than M+L), so the invention can reduce the test time of the integrated circuit by an order of magnitude, and reduce the test cost. It also shortens the mass production time of product formation; the invention can increase the test incentive appropriately by greatly reducing the number of input excitation operations. The length, the test coverage is improved, and the leakage rate is effectively reduced. The invention has no additional requirements on the number of test bench channels, which helps to reduce the test cost. For the wafer test, when the comparison device is integrated on the wafer, the delay of the high-frequency signal transmission through the cable can be avoided, so that a higher frequency can be performed. For testing, you can also use the low-end test bench for high-end testing. DRAWINGS

While the invention may be modified in various forms of modifications and alterations, some specific embodiments are illustrated and described in detail. It should be understood that the inventor's point of departure is not to limit the invention to the particular embodiments set forth, but rather, the inventor's point of departure is to protect all modifications, equivalent transformations and modifications based on the spirit or scope defined by the claims. .

Figure 1 is a schematic diagram of a general wafer test (prior art).

2 is a flow chart of testing the shared base integrated circuit test apparatus of the present invention with expected results. 3 is a flow chart of testing of the shared base integrated circuit test apparatus of the present invention without expected results. Figure 4 is a schematic diagram of the structure of the grain output compared to the expected results.

Fig. 5 is a schematic view showing the structure in which the crystal outputs are compared with each other.

Figure 6 is a schematic illustration of the comparator within and outside the die.

Figure 7 is a schematic diagram of the determination of die failure during the test.

Fig. 8 is an embodiment of the positional relationship of adjacent units to be tested in the present invention.

Figure 9 is a schematic diagram showing the comparison of the operation results to analog signals.

Figure 10 is an embodiment of the present invention for a power supply mode.

Figure 11 is a diagram showing possible positional distributions of the embodiment of the present invention for alignment mark locations on a wafer. Figure 12 is a diagram showing an internal input channel structure diagram and an output circuit structure of a lithography area on a wafer.

Figure 13 is an embodiment of the present invention for a circuit wiring arrangement when the dies are compared with each other.

Figure 14 is an embodiment of the present invention for a configuration method.

Figure 15 is a schematic diagram of a wafer test input path and test feature derivation path.

Figure 16 is a schematic diagram of a wafer with a large power interface.

Figure 17 is a schematic diagram of wafer testing of a radio frequency die. Figure 18 is a schematic diagram of a self test wafer.

Figure 19 is a diagram of a new wafer test system.

Figure 20 is a diagram showing the internal test structure of a multi-operation unit/multi-core integrated circuit chip.

Figure 21 is a schematic diagram showing the wiring pattern of the crystal output to the comparator.

Figure 22 is a four embodiment of wafer testing on a wafer under test using other wafers.

Figure 23 is an embodiment of DC testing of the measured die. .

Figure 24 is an embodiment of a test for a complementary metal-oxide-semiconductor (CMOS) image sensor.

Figure 25 is an embodiment of a wafer test station capable of providing a sufficient amount of power for a specified number of units under test at rated voltage.

Figure 26 is a diagram showing a test result table for storing test results when a functional module in an integrated circuit chip is tested by the present invention.

Figure 27 is a test circuit diagram compared to the expected results.

Figure 28 is a cross-sectional view showing a wafer test using a circuit board.

Figure 29 is an embodiment of a packaged integrated circuit test device. detailed description

The technical idea of the present invention is that multiple tested integrated circuits/die/function chips having the same structure and function perform the same input excitation, each generating an operation result, and the operation results are compared with each other in parallel or in parallel with the expected result to detect the failure. Integrated circuit / die / function chip.

Please refer to FIG. 2. FIG. 2 is a flow chart of testing the shared base integrated circuit testing device of the present invention with expected results. The comparison device in this embodiment does not include a failure determination function. First, go to step one (202), input the excitation, and then go to step two (203) to run each unit under test in parallel. Then, proceed to step 3 (205) to sample the running results of each unit under test, and compare them with the expected results in parallel, and record the comparison result. The number of times of sampling comparison depends on the requirements of the test accuracy. After the sampling comparison of the running results of all the test excitations is completed, the process proceeds to step 4 (206), and the result is determined, and the position information of the tested unit and the corresponding determination result are generated. Finally, proceed to step 5 (207) to output the position information of the unit under test and the corresponding determination result. Please refer to FIG. 3. FIG. 3 is a flow chart of testing the shared base integrated circuit test apparatus of the present invention without any expected result. The comparison device in this embodiment includes a failure determination function. First, go to step one (302), input the excitation, and then go to step two (303) to run each unit under test in parallel. Then, proceed to step 3 (304) to sample the operation results of the units to be tested, compare and compare the operation results between the units to be tested, and record the comparison features. The number of times this sample is compared depends on the accuracy of the test. After the sampling comparison of the running results of all the test energies is completed, the process proceeds to step 4 (306) to generate a determination result of the unit under test. Finally, proceed to step 5 (307) to output the position information of the unit under test and the corresponding determination result. The test feature is a suspected failure unit or a failure unit determination result. The result of the determination may be failure unit coordinate information or other information that can locate the failed unit. After the completion of the shared base integrated circuit test, the suspected failed unit can be retested as needed, or the suspected failed unit can be simply considered to be truly invalid according to the requirements. A failed unit can be physically marked.

Figure 4 is a schematic diagram of the structure of the grain output compared to the expected results. The bidirectional switch (403), the bidirectional switch (404), the bidirectional switch (443), the bidirectional switch (444) are configured to transmit to the right, and the wired interconnect circuit (402) passes the left incoming excitation (401) through the input pad (406). The input pad (407) and the input pad (408) are respectively introduced into the die (409), the die (410), and the die (411). The expected result (412) is passed from the left side and passed to the comparator (414), the comparator (415), the comparator (416), the die (409), the die (410), the die through the connection circuit (413). (411) The lower operation results are respectively transmitted to the comparator (414), the comparator (415), and the comparator (416) through the respective output pads (425), output pads (426), and output pads (427). The comparison/decision results of the comparator (414), the comparator (415), and the comparator (416) are stored in the feature register (417), the feature register (418), and the feature register (419), respectively. The initial value of all feature registers is set by the external control signal or by self-excitation. When the two sets of comparator inputs are not equal/mismatched, the internal value of the feature register changes and only changes once, that is, if the output of the adjacent die is not equal/mismatched once, the associated die is marked as a suspected failure crystal. grain. The feature register (417), the feature register (418), the feature register (419) and other feature registers can be connected to a shift register chain (420) for outputting position information of the measured die and corresponding comparison/judgment results. The excitation (401) can be directly connected to the internal module through the input pad (406), the input pad (407), and the input pad (408), and the comparison/decision result can also pass through the output pad (425) and output. The pad (426) and output pad (427) are directly output by metal wires. The comparator can have a single or multiple inputs.

Fig. 5 is a schematic view showing the structure in which the crystal outputs are compared with each other. The bidirectional switch (503) and the bidirectional switch (504) are configured to transmit to the right, and the wired interconnect circuit (502) passes the left incoming excitation (501) through the input pad (505), the input pad (506), The input pads (507) are respectively introduced into the die (508), the die (509), and the die (510). The operation result under the die (509) is transmitted to the comparator (514) and the comparator (515) through the output pad (512), and the operation result under the die (508) is transmitted to the comparator through the output pad (511). (514) is compared to the output of the die (509). The results of the operation of the die (510) are compared by the output pad (513) to the comparator (515) for comparison with the output of the die (509). The comparison/decision results of the comparator (514) and the comparator (515) are stored in the feature register (516) and the feature register (517), respectively. The initial value of all feature registers is set uniformly by the external control signal or by self-excitation. When the input of the comparator is not equal/mismatched, the internal value of the characteristic register changes and only changes once, that is, if the output of the adjacent crystal grains is not equal/mismatched once, the relevant crystal grains are suspected to be invalid crystals. grain. The feature register (516), the feature register (517) and other feature registers may be coupled into a shift register chain (518) for outputting position information of the measured die and corresponding comparison/decision result test feature values. The excitation (501) can be directly connected to the internal module by the input pad (505), the input pad (506), and the input pad (507), and the comparison/determination result can also pass through the output pad (511) and output. The pad (512) and the output pad (513) are directly outputted by metal wires. The comparator can have a single or multiple inputs.

Figure 6 (a) is a schematic diagram of the comparator in the die. The transmission network (601) inputs the expected result or the operation result of the adjacent die into the current die through the pad (603) of the input/output port (I/O pin) (602), and the corresponding operation result of the current die (604) Use the comparator (605) for comparison. At this time, the output driver (606) in the input and output port (602) is set to high impedance, and the input driver (608) is turned on.

Figure 6 (b) is a schematic diagram of the comparator outside the die. The current die operation result (611) is output to the comparator (614) through the output driver (612) and its pad (613) to the expected result of the pad (616) or the operation result of the adjacent die (615) ) compared to.

Figure 7 is a schematic diagram of the determination of die failure during the test. In the schematic diagram, the operation results on the four sides of each measured die are compared with the running results on the corresponding sides of the adjacent measured die by a comparison device, wherein the comparison result is an equal/matched comparison device. The icon is white, and the comparison device icon whose comparison result is unequal/unmatched is black. In this embodiment, all means for determining whether the die has failed may be on the wafer or on an off-wafer test machine. As shown in the figure, Figure 7 (a) is a schematic diagram of the test case when there is no failure of the die, in which the operation results of the measured die (701) on the four sides pass through the connection (707) and the measured die ( 702), the measured die (703), the measured die (704), the measured edge (705) corresponding side of the operation results are compared, the comparator (706) is shown in white to indicate the measured die (701 ) The comparison with the corresponding sides of the measured grain (704) is equal/matched, and the comparisons on the four sides in the figure are completely equal/matched, so It is determined that the measured crystal (701) is a normal crystal grain.

Figure 7 (b) is a schematic diagram of the test situation when a portion of the measured die fails. The measured die (711) is on the four sides with the measured die (712), the measured die (713), and Comparing the operation results of the measured die (714) and the corresponding edge of the measured die (715), wherein the comparator (716) and the comparator (717) are shown in black, respectively indicating the measured die (711) and the measured The comparison of the die (712) and the measured die (714) is not equal/mismatched, and the wires (718) and wires (719) are their corresponding wires. The comparison between the measured die (711) and the measured die (713) and the corresponding edge of the measured die (715) is equal/matched, so that the measured die (711) can be determined to be partially failed.

Figure 7 (c) is a schematic diagram of the test situation when the measured die is completely failed. The measured die (721) and the measured die (722), the measured die (723), and the measured die (724) The measured die (725) is not equal/mismatched on the four sides. The comparator (726), comparator (727), comparator (728), comparator are shown. (729), comparator (730), comparator (731), comparator (732), and comparator (733) are all black, and the connection (734) is the unit under test (721) and the comparator (726). The connection between. Therefore, it can be determined that the measured crystal grain (721) is a failed crystal grain. When comparing, the comparison result of each port can be compared by logic circuit, only one comparison result is output, and the comparison result is spatially compressed; the comparison result can be accumulated by the accumulation circuit to achieve compression of the comparison result in time. . After compression, the bandwidth requirements of the output circuit can be reduced and the test process can be accelerated.

Fig. 8 is an embodiment of the positional relationship of adjacent units to be tested in the present invention. A, B, C, and D are the four corners of the unit under test. As shown in the figure, Figure 8 (a) is a schematic diagram of the normal placement position, the unit under test (801), the unit under test (802), and the unit under test. (803), the unit under test (804) is placed in a uniform orientation, and each output port of the unit under test is compared with an output port on a corresponding side of the adjacent unit under test by a connection, such as an output port of the unit under test (801). Compare with the corresponding output port of the unit under test (802). The connection (813) in the figure is the connection between the corresponding output port of the unit under test (802) and the unit under test (804).

Figure 8 (b) is a schematic diagram of the rotational placement position, where the position of each unit to be tested is in a rotational relationship with the position of the adjacent unit to be tested, such as the position of the unit under test (806) and the unit to be tested (805) The position of the unit to be tested (808) is rotated by 180 degrees, and the position of the unit to be tested (808) is rotated by 180 degrees with the position of the unit under test (806) and the unit to be tested (807). In this way, when testing, the output port of each unit under test is adjacent to the output port of the adjacent unit under test, shortening the trace distance and making it easy to connect. As shown in the figure, the connection (814) is a connection between the unit under test (806) and the corresponding output port of the unit under test (808).

Figure 8 (c) is a schematic diagram of the placement position of the mirror, the placement position of each unit under test and the placement position of the adjacent unit under test In a mirror image relationship, if the position of the unit under test (809) is mirrored with the position of the unit under test (810) and the unit to be tested (811), the position of the unit under test (811) is measured and measured. The placement position of the unit (809) and the unit under test (812) is in a mirror image relationship. The output port of the unit under test is closer to the corresponding output port position of the adjacent unit under test, and it is more convenient to connect the lines. As shown in the figure, the connection (815) is a connection between the measured unit (810) and the corresponding output port of the unit under test (812). This embodiment is more suitable for testing non-directional chips such as RFID.

Figure 9 is a schematic diagram showing the comparison of the operation results to analog signals. When the operation result of the die (901) is an analog signal, the sampling of the signal is converted by the analog-to-digital converter (902), and the converted result is sent to the digital comparator (903) to generate whether the two crystal grains are equal. / Matching comparison/judgment result, and storing the comparison/judgment result in the feature register (904). The input of the die (901) can be a direct analog signal input, or a digital signal can be input after digital analog conversion.

Figure 10 is an embodiment of the present invention for a power supply mode. All of the die (1001) power pads (1002) in the wafer can be connected to the global power network (1003), or the zone power supplies can be connected together to form multiple local power networks. The ground pad (1004) can also be fully connected to the ground grid (1005) or partitioned to form multiple local ground networks. The ground pads in the global or partition can all be connected together. Each power pad is connected to a global or partitioned power network via a large sized PM0S device. The gates of these PMOS devices are connected to a configurable network, controlling each. The on and off of the die power supply. The pads are constructed of metal, placed on the outside of the die or on the die, and may be joined to the structure of the present invention by metal wires.

Figure 11 (a) is an embodiment of the present invention for alignment mark positions. There is a 60 μm to 80 μm scribe line (1101) between each die on the wafer. The alignment mark (1102) is used for the alignment of each reticle, usually in the scribe line (1101), and occupies all Layout layer. Since the present invention requires the design of long wires in the scribe line (1101), the alignment marks can be moved to the corner pads (1104) of the die in order not to collide with the alignment marks. The input channel, comparator, and output circuitry can coexist with the WAT test structure used for wafer acceptance testing. The coexistence method can be to bypass the WAT test structure or share the WAT test structure at certain locations, such as borrowing a needle pad from the WAT test structure for the input of the stimulus.

Figure 11 (b) is a possible location map of the needle pad on the wafer. In the present invention, it is necessary to provide a test pad for the test network for incoming clocks, configuration information, and the like. If there are unused vacant pads in the die (1111), it can be used as a needle pad, such as A position (1112), B position (1113); can also be placed on the crystal The corner pad of the pellet (1111), such as the C position (1114). It is also possible to place the needle test pad in the cutting path (1101), such as the D position (1117) and the E position (1118).

Figure 11 (c) is a possible location diagram of the probe pad when using flip chip or wafer level chip package. When using a flip chip package, the probe card can be used as a needle pad using the vacant pads (1122) on the die (1121). Please refer to FIG. 12. FIG. 12 is a structural diagram of an input channel and an output circuit structure of a lithography area on a wafer. Figure 12 (a) is the internal input channel structure diagram of the lithography area on the wafer, and Figure 12 (b) is the structure diagram of the measured crystal output circuit in the lithography area on the wafer.

As shown in Figure 12 (a), the test stimulus is transmitted to each of the lithographic areas (1206) via a pin test card (1201) and through wires (such as wires (1202)) on the scribe lines on the wafer. Measure the die (such as the measured die (1203)), wherein the wire on the scribe line has been determined at the layout stage, and can not be changed throughout the test phase, each test die is run to test excitation, and the operation result is generated. Compare/determine results by comparing with each other or comparing with expected results.

As shown in FIG. 12(b), in the lithography region (1206), the comparison/judgment result of each of the measured crystal grains is connected by an output circuit (1204) composed of a shift register and a hard wiring, and passed through The output circuit is output to an external device via a pin test card (1201), where the output circuit is determined during the layout phase and cannot be changed throughout the test phase.

Fig. 13 is a view showing an embodiment of the circuit wiring arrangement in the present invention for the comparison of the crystal grains, Fig. 13 (a) is a top view of the embodiment, and Fig. 13 (b) shows the connection details between the three crystal grains. The probe of the pin test card (1316) falls on a die (1311), and the incoming input excitation can be transmitted to the corresponding input pads of the die (1310) and the die (1312) through the wired interconnect circuit (1302). . The wired interconnect circuit (1302) is composed of a plurality of basic transmission units (1303). The basic transmission unit (1303) ensures that the signal can be transmitted from the left (right) to the right (left) or from the upper (lower) to the lower (upper) via the bidirectional switch (1304). The bidirectional switch is configured by the configuration network so that the bidirectional switch is configured The pin test card (1316) can be transmitted to all dies at any die input stimulus. When the input excitation is transmitted, the bidirectional switch (1304) is unidirectional, and when the output is compared, the bidirectional switch (1304) is turned off. When the bidirectional switch (1304) is unidirectional, its conduction direction can be determined by the configuration memory (1308), or by the input/output control pad (1309) and the configuration memory (1308) of the device under test. The driver (1305) of the Basic Transmission Unit (1303) does not attenuate signal transmission. If the attenuation is not large, the wired interconnect circuit can also have no driver (1305). If necessary, a latch can be added to the wired interconnect circuit to transmit the signal in a pipelined manner. In the comparison phase, the bidirectional switch (1304) is configured to be disconnected, and the pad (1301) acts as an output pad to pass the die run result, at which point the comparator (1306) operates. The pad (1301) in the above embodiment is an input/output pad, and a separate input pad or output pad connection method is a subset of this embodiment.

Figure 14 is an embodiment of the present invention for a configuration method. The wired interconnect circuit and the output circuit have different topologies. The input excitation is required to be transmitted from the probe drop point to the four sides in the shortest path, and the output circuit is serially passed through each unit to be tested. At each node, the wired interconnect circuit and the output circuit do not necessarily have the same direction of transmission. The purpose of this embodiment is to simultaneously establish a serial output configuration to serially output the comparison/judgment result of all the units to be tested to the test list where the probe is located. The element and the wired interconnect circuit that configures the input excitation from the unit under test to which the probe is located. The method adopted is to establish a chain passing through each unit to be tested from the position of the probe in a point-by-point configuration by point-by-point transmission. The reverse direction of this chain is the true comparison/decision result transmission direction, while establishing the chain. The transmission direction of the wired interconnect circuit is also configured. The configuration information of each node transmitted through the chain includes: wired interconnect circuit structure configuration information and output circuit structure configuration information. Specifically, the configuration information and clock (1427) from the probe position (1401) are serially transmitted to all nodes through the network (1402), as shown in Figure 14 (a). For the node (1408), the clock signal and the node configuration information (1427) are transmitted from above, the configuration memory (1308) of the transmission direction of the excitation signal on the node (1408), and the derivation direction configuration for controlling the output direction of the output circuit are configured. Register (1407). The Export Direction Configuration Register (1407) indicates to the right to create a comparison/decision result output circuit (including forward clock transfer, forward configuration information transfer, and reverse comparison/decision result transfer channel). The configuration memory (1308) indicates that the input stimulus is passed down (1414). For the node (1403), the clock signal and the node configuration information arrive at the local node (1403) from the left node (1408), configure the configuration memory (1308) of the transmission direction of the excitation signal on the node (1403), and control comparison/determination. The result is exported to the direction configuration register (1407). The export direction configuration register (1407) instructs to continue to build a comparison/decision result output circuit to the right (including forward clock transfer, forward configuration information transfer, and reverse comparison/judgment result transfer channel). The configuration memory (1308) indicates that the input stimulus is passed down (1404). For node (1406)', the clock signal and node configuration information arrives at the node (1406) from the left node (1403), configures the configuration memory (1308) of the transmission direction of the excitation signal on the node (1406), and controls comparison/ The determination result is derived from the direction configuration register (1407). The Export Direction Configuration Register (1407) instructs to continue to build a comparison/decision result output circuit to the right (including forward clock transfer, forward configuration information transfer, and reverse comparison/judgment result transfer channel). The configuration memory (1308) indicates that the input stimulus (1488) is passed down. After each node is configured once, the configuration memory (1308) and the export direction configuration register (1407) are not changed by subsequent configuration information of the node. However, when the power is turned off and the reset signal is externally supplied, all are set to the initial values. Thus, all node configurations are sequentially transmitted through the node configuration information and the clock transmission path (1427), the node configuration information and the clock transmission path (1415), the node configuration information and the clock transmission path (1405), the node configuration information, and the clock transmission path (1420). Information and clock, transmitted to the required link nodes as needed. An inverse comparison/decision result output circuit is established by comparing/determining the result transmission path (1429), the comparison/decision result transmission path (1430), the comparison/decision result transmission path (1431), etc., and outputting all the comparison features, inputting the excitation The transmission direction configuration is also completed while the output circuit is being built. Figure 14 (b) is a connection diagram of a node (1408), a node (1403), and a node (1406).

Figure 15 (a) is a schematic diagram of a wafer test input channel, which is a top view; the pin test card (1501) passes An input channel (1503) on the wafer (1502) transmits the excitation to each die (1504), wherein the input channel (1503) can be configured to select an excitation transmission path. With this structure, the needle test card (1501) can complete the transmission of test excitation without moving, saving test time; it can also be configured to select partial area transmission excitation for sub-area test.

Figure 15 (b) is a schematic diagram of a wafer comparison/judgment result output circuit, which is also a top view; the wafer under test (1502) has a comparison/decision result output circuit (1505), which is connected All the characteristic registers of the die to be tested (1504); all the characteristic registers form a shift register, and the comparison/judgment result can be read by the shift register serial shift, without moving the pin test card (1501) All comparison/judgment results can be read. It is also possible to configure only the comparison/judgment results of partial areas by configuration. The comparison/decision result output circuit (1505) can be pre-tested once after the establishment is completed to ensure the correctness of the input channel and the comparison/decision result output circuit itself, and the input can be passed from the pin test card (1501). The node (1506) is passed in, after the comparison/decision result output circuit, and then read from the node (1507) through the pin test card (1501), the two are compared with each other, and the equal/matching means that the pre-test is passed, otherwise, Pass pre-test. If the pre-test is not passed, the card test card (1501) can be moved to re-establish the input channel and the comparison/decision result output circuit from another unit under test, and the self-test is repeated. In the self-test mode, the self-test excitation is transmitted to each unit under test through the input channel, and the self-test excitation is serially derived through the comparison/decision result output circuit.

Figure 15 (a) and Figure 15 (b) use the input channel and comparison/judgment result output circuit established in Figure 14. Figure 16 is a schematic diagram of a wafer with a large power interface; in addition to a general die (1602) on a wafer (1601), there may be several large power interfaces (1603), which are (1603) ) A hard-wired connection to the power supply of the surrounding die. Since it can pass a large power supply, it can simultaneously supply multiple dies in one area, and the dies can be tested at higher frequencies. This requires a dedicated probe that can be used with a large power supply.

Figure 17 is a schematic diagram of wafer testing of a radio frequency die. As shown in the figure, during the wafer test of the RF die, the pin test card (1703) has an antenna input pad for each die (such as the die (1702)) on the wafer (1701). A corresponding receiving antenna or coupler (such as a receiving antenna and a coupler (1704)) is input to the test RF and the corresponding measured RF die (such as the measured RF die (1702)) by electromagnetic wave transmission. Power supply, each tested RF die (such as the measured RF die (1702)) runs the test excitation, and the operation result is transmitted to the corresponding comparison device through the connection line on the wafer (1701), through each measured die. (If the measured results of the measured RF die (1702) are compared with each other or compared with the expected result, the comparison/judgment result is obtained, and the comparison/judgment result is transmitted to the feature marking device through the output probe on the pin test card (1703). To achieve wafer testing of RF dies. Test excitation and power supply can be transferred to the measured Grain. For the die that already contains the antenna, the test excitation and power supply can be directly input in the form of electromagnetic wave transmission. Figure 18 is a schematic diagram of a self-test wafer. As shown in the figure, a test excitation generating device (1801) is integrated on the wafer (1803), and the generated test excitation is transmitted through the connection to each measured die (e.g. The die (1802) is measured, and the output port of each die (such as the die (1802) to be tested is also connected to the corresponding comparison device on the wafer (1803) through the wire, the entire wafer (1803) A complete test environment has been formed. In the case of power-on, the entire wafer (1803) can complete all die tests independently without the participation of an external test machine, and the comparison/judgment result is passed through the pin test card. The output probe on the output is output to the signature device. In this embodiment, the test excitation generating device (1801) can also be integrated into the scribe line (1804) on the wafer (1803) without occupying the die position.

19 is a diagram of a novel wafer test system; the structure includes a tester (1901), a special test device (1902), which are connected by a cable (1903), and can be used for a wafer test machine (1904). The test wafer (1905) on the test is tested. The dedicated test device (1902) can provide a large power supply, and the probe (1906) on the dedicated test device (1902) can also contact the power supply/± of all the crystals on the tested wafer (1905) to achieve the measured Wafer (1905) Power is supplied to the full wafer or part of the wafer area. The excitation generated by the tester (1901) can be transmitted to the plurality of units to be tested in parallel through a dedicated test device (1902) to drive all or part of the measured crystal grains on the tested wafer (1905), and each of the crystal grains is simultaneously operated at a high speed. Input excitation; comparison/decision results will be exported to the tester (1901) through the dedicated test device (1902) and cable (1903). If the test result is a comparison result, the tester (1901) will determine the suspect based on the comparison result of the output. Failed unit. The system can also test the suspected failure unit separately based on the results of the operation and has the function of marking the failed unit.

20 is an internal test structure diagram of a multi-operation unit/multi-core integrated circuit chip. As shown in the figure, inside the multi-operation unit/multi-core integrated circuit chip (2011), a test excitation generator (2001) generates a test stimulus and transmits it to Each unit to be tested (such as the unit under test (2002), the unit under test (2004), the unit under test (2007), the unit under test (2009)), where the unit under test is inside the multi-operation unit/multi-core integrated circuit chip Arithmetic unit or processor core. Each unit under test (such as the unit under test (2002), the unit under test (2004), the unit under test (2007), the unit under test (2009)) runs test excitation, and the operation result is transmitted to the corresponding comparator (such as a comparator). (2003), Comparator (2005), Comparator (2006), Comparator (2008)) are compared with each other to obtain a comparison/judgment result, and the test result is written into the feature register (2010), thereby implementing a multi-operation unit inside the chip/ Multi-core testing. In this embodiment, the test results of each unit under test (such as the unit under test (2002), the unit under test (2004), the unit under test (2007), and the unit under test (2009) are tested by mutual comparison. In the specific implementation, the test result can also be tested by comparing the running result of the tested unit with the expected result.

Figure 21 is a schematic diagram showing the manner in which the die is output to the comparator. Comparator (2103), comparator (2104) are located The cut path may be cut in the area (2107), the cut area (2109), the die (2101), the output pad (2110) of the die (2102), the output pad (2108) and the comparator (2103), compared The wires between the devices (2104) must be cut through the dicing channel to determine the cut-off region (2105) to ensure that the comparator can only work during the chip test. After the chip is cut, the output pad between the crystal and the grain is compared with the comparator. The wires are all cut off and the comparator does not load the output pads.

Figure 22 is a four embodiment of wafer testing on a wafer under test using other wafers. In the first embodiment, the test wafer (2201) in Figure 22(a) is overlaid on the wafer (2202) as part of the test system for testing. In this embodiment, the test wafer (2201) is divided into the same structure as the wafer under test (2202), and in FIG. 22(b), the test wafer (2201) and the wafer to be tested (2202) The position corresponding to the die (2204) is used to place the solder ball (2205) to transfer the test power/test excitation to the die to be tested. The free position on the corner of the test wafer (2201) (2203) is used for the connection test. Cable (2206). Figure 22 (c) is a cross-sectional view of the embodiment, in which the solder balls (2205) on the test wafer (2201) correspond one-to-one with the pads on the wafer to be tested (2202), and the flattening device (2210) is pressed against On the test wafer (2201), the pads of the two wafers are in tight contact with the solder balls. Using the gap between the two wafers formed by the pad and the solder balls, the test cable (2206) can be directly connected to the vacant position (2203) on the corners of the test wafer (2201) via the fixture (2208). During the test, the test power/test excitation is transmitted to the test wafer (2201) through the test cable (2206) through the fixture (2208), and transmitted to the wafer under test through the solder ball (2205) on the test wafer (2201) ( Corresponding pads for each die on 2202) are used as input for testing. The results of the test stimulus can be compared on the wafer under test or transmitted back to the test wafer for comparison with the comparator on the test wafer.

Figure 22 (d) is the second embodiment. The test wafer (2211) is larger than the wafer to be tested (2202), and the test cable (2206) can be directly connected to the test wafer (2211) through the fixture (2208) to extend the wafer to be tested (2202) The part that can solve the problem that the test cable (2206) in Figure 22 (c) cannot be too thick. In this embodiment, the test power/test excitation is transmitted to the test wafer (2211) through the test cable during testing, and is transmitted to the wafer under test (2202) through the solder ball (2212) on the test wafer (2211). The corresponding pads for each die are used as input for testing. The results of the test excitation can be compared on the wafer under test or transmitted back to the test wafer using a comparator on the test wafer.

Figure 22 (e) is a third embodiment. In this embodiment, the wafer to be tested (2215) and the test wafer (2211) are originally the same size, but the wafer to be tested (2215) is cut off and tested. The wafer (2211) is a complete wafer. During the test, the test power/test excitation is transmitted to the test wafer (2211) via the test cable, and the solder ball (2212) on the test wafer (2211) is transferred to the measured crystal. The corresponding pads of each die on the circle (2215) were used as input for the test. Test motivated The results of the execution can be compared on the wafer being tested, or can be transmitted back to the test wafer and compared using a comparator on the test wafer. In this embodiment, the wafer to be tested (2215) is only cut off, but in practical applications, the polygons can be cut according to different needs.

Figure 22 (f) is a fourth embodiment. The test wafer (2214) is a wafer with through silicon vias (TSV). In this embodiment, the test cable (2216) does not need to be directly connected to the front side of the test wafer (2214), but is connected to the back side of the test wafer (2214), and the test power supply/test excitation transmission is transmitted through the TSV through hole. Go to the wafer under test (2202). In order to clarify the technical idea of the embodiment more clearly, the flattening device and the fixing member are omitted.

In Examples 22 (a), 22 (b), 22 (c), 22 (d), 22 (e), 22 (f), except that the solder balls on the test wafer are in contact with the wafer under test. In addition to the solder pads, the solder pads on the test wafer can be used to contact the solder balls on the wafer to be tested, and the solder balls on the wafer are contacted with solder balls on the wafer to be tested.

Figure 23 is an embodiment of DC testing of the measured die. In this embodiment, a current source (2303) is connected to a pad/tin ball (2302) of the die (2301) to be tested. When tested, the current source (2303) passes through the pad/tin ball (2302). Give the measured die (2301) - a quantitative power supply. At this time, the pad/tin ball (2302) generates a potential difference corresponding to the ground (GND). The pad/sol ball can be known by an analog-to-digital conversion device (2304). 2302) Upper voltage value. By comparing this voltage value with the reference DC characteristic voltage value, it can be determined whether the DC characteristic value satisfies the requirement.

Figure 24 is an embodiment of a test for a complementary metal oxide semiconductor (CMOS) image sensor. In this embodiment, the die on the wafer (2401) is a CMOS image sensor. A light emitting device (2404) can emit light of different brightness and chromaticity to the upper portion of the wafer (2401) or even to all of the CMOS image sensors. The probe (2405) of the dedicated pin test card (2403) does not block the light emitted by the illumination device (2404) and contacts the corresponding pads of a CMOS image sensor on the wafer (2401). By comparing the luminance and chrominance values received by different CMOS image sensors in parallel, or comparing the luminance and chrominance values received by the CMOS image sensor with the reference value in parallel, and passing the determination result back from the probe (2405) via the output circuit. A dedicated pin test card (2403) enables parallel comparison of a large number of CMOS image sensors on a common substrate.

Figure 25 is an embodiment of a wafer tester that provides sufficient power for a specified number of units under test at rated voltage. The power supply device (2501) can provide a power supply for testing all of the tested dies at the same time. During the test, the test excitation and power supply device (2501) in the test host (2502) transmits the power from the test interface (2503) through the probe (2505) to all the measured crystals in the tested wafer (2504). Granules, simultaneous testing of all measured grains. In this embodiment, the test interface (2503) can be implemented by a wafer or by a circuit board.

Figure 26 is a diagram showing a test result table for storing a determination result when a functional module in an integrated circuit chip is tested by the present invention. The judgment result is saved in the test result table (2601), and each label (2602) corresponds to one measured in the system. Unit, the information at the position indicates the state of the unit under test, where "?" indicates that the corresponding unit under test is not measured, "X" indicates that the corresponding unit under test has failed, and "0" indicates that the corresponding unit under test is normal. The test result table can be in the integrated circuit chip or outside the integrated circuit chip. The storage medium may be volatile or non-volatile; it may be one-time writes that are not changed, or may be erasable and write-once. When the effective function module with the same function as the failed function module is redundant, the failed function module is bypassed, and the failed function module is replaced by the redundant effective function module, so that the system can operate normally, improve the yield, and realize the system. Self-healing feature. ·

Figure 27 is a test circuit diagram compared to the expected results. The test probe falls on the pad (2703) or pad (2704) in the scribe line, and the input signal is the expected operation result of the die (2701) and the die (2702). The expected operation result is transmitted to the comparator (2708) and the comparator (2709) through the transmission path (2705), and is compared with the output of the die (2701) (2713) and the output of the die (2702) (2714). The comparison/decision result is stored in the register (2711) and the register (2712).

Figure 28 is a cross-sectional view showing a wafer test using a circuit board. The board (2801) is attached to the wafer under test (2805) by a fixture (2803). There are multiple trace channels (2807) on the board (2801). In addition, the circuit board ( 2801 ) can also have a solder ball ( 2804 ) connected to the trace channel ( 2807 ), the position of which corresponds to the position of all pads of the tested wafer ( 2805 ), and the flattening The device (2811) is pressed against the circuit board (2801) such that the solder balls (2804) are in tight contact with the pads. Through the test cable (2813), the power supply and test excitation can be transmitted to the wafer under test (2805) through the trace channel (2807) of the board (2801) and the solder ball (2804), so that the wafer to be tested (2805) All power and test excitations for all of the die are passed through the solder balls (2804) on the board (2801). At the same time, the test equipment receives the test results from the tested wafer ' (2805) through the test cable (2813) and the trace channel (2807) on the board (2801) and the solder ball (2804). In this embodiment, the position of the solder ball (2804) on the circuit board (2801) may also correspond to the pad portion on the wafer to be tested (2805). At this time, part of the die is input to the circuit board (2801). The solder balls (2804) are incoming, and some of the inputs are passed through the pads of the other die through the input channels on the tested wafer (2805). The soldering pad (2804) may not be included on the circuit board (2801), and has a pad connected to the routing channel (2807). At this time, the test pads on the tested wafer (2805) need to be connected to the corresponding solder balls. The position of the pads on the circuit board (2801) corresponds to the position of the solder balls on the tested wafer (2805). The test device in this embodiment is not shown.

Figure 29 (a) shows an embodiment of a packaged integrated circuit test device. On the test board (2901) there are a plurality of units to be tested (2902), a block buffer comparison chip (2903), and an input/output interface (2904) for communicating with the test station. The unit under test (2902) is located in the slot of the board, and its input is compared with the buffer comparison chip (2903). W

28

The output terminal of the test unit (2902) is connected to a set of input terminals for comparison of the buffer comparison chip (2903); the remaining input terminals of the buffer comparison chip (2903) are connected to the interface (2904), Receive test incentives and expected results.

The test excitation generated by the test machine can be tested by inputting the buffer comparison chip (2903) to a plurality of test units (2902), and the operation result of the test unit (2902) is input to the buffer comparison chip (2903) and the test machine. The expected result of the input of the interface (2904) is compared, and the comparison result is transmitted back to the test machine through the interface (2904) to determine whether the unit under test (2902) is valid.

The two sets of buffer comparison chips (2903) for comparison can be connected to the corresponding outputs of different units under test (2902), and the outputs of different units under test (2902) are compared with each other, and no test machine is needed at this time. The station can provide the expected result to determine the valid and suspected failure of the unit under test (2902).

The input excitation of the unit under test (2902) can also come from electromagnetic waves.

Figure 29 (b) shows another example of a packaged integrated circuit test device. There are only a plurality of units under test (2915) and electrical connection interfaces (2912) on the test board (2911). On another board (2918) there are a plurality of buffer comparison chips (2916), electrical connection interfaces (2914), and an input and output interface (2919) for communicating with the test station. A plurality of test circuit boards (2911) are connected to a power connection interface (2914) of the circuit board (2918) through an electrical connection interface (2912) to form a set of test devices, and the three-dimensional effect diagram thereof is as shown in Fig. 29 (c). . The input and output ports of the unit under test (2915) on the test board (2911) are connected to the electrical connection interface (2912). The test machine inputs test excitation to the unit under test (2915) through the input/output interface (2919), the electrical connection interface (2914) and the electrical connection interface (2912), and compares the chip to the buffer through the input/output interface (2919) (2916). ) Enter the expected result. The buffer comparison chip (2916) determines whether the unit under test (2915) is valid by comparing the operation result of the unit under test (2915) with the electrical connection interface (2914) and the electrical connection interface (2912).

The buffer comparison chip (2916) can also compare the corresponding outputs of different units to be tested (2915). At this time, the test unit (2915) can be determined to be valid and suspected to be invalid without providing the expected result.

The input excitation of the unit under test (2915) can also come from electromagnetic waves.

For the sake of clarity, the test machine in the above two embodiments, the interconnection between the components is not shown.

Claims

1. An integrated circuit test method for testing a plurality of functionally identical microelectronic circuits on a common substrate; the substrate may be a wafer

(wafer), which may be a single integrated circuit chip or a circuit board; wherein the method includes:

(a) input the same test stimulus to a plurality of functionally identical device under test (DUT) on the substrate through an input path;

(d) Detecting the comparison result of the output and the position information on the base, classifying the corresponding unit to be tested, classifying the unit under test with the same/matched comparison result as a normal unit, and measuring the results that are not equal/mismatched The unit is classified as a suspected failure unit.

2. An integrated circuit test method for testing a plurality of functionally identical microelectronic circuits in parallel on a common substrate; the substrate may be a wafer, a single integrated circuit chip, or a circuit board; Methods include:

(d) Detecting the comparison result of the output and the position information on the substrate, classifying the corresponding unit to be tested, classifying the unit under test with the same/matched comparison result as a normal unit, and measuring the results that are not equal/mismatched The unit is classified as a failed unit.

3. A wafer comprising a plurality of functionally identical dies to be tested, wherein the functional modules of the plurality of dies or the plurality of dies having the same function are the unit under test; wherein the wafer is further The auxiliary test device may be partially located in the unit to be tested, or may be located outside the unit to be tested, including:

(b) an input path connecting the signal inputs of the plurality of measured units; the input path is also used to transmit the expected result to one end of the comparing device when the expected result exists; (c) a comparison device, one input connected to the output to be tested of a unit under test, the other input being connected to the corresponding output of the other unit under test, or for inputting the expected result The corresponding input channels are connected;

(d) a register circuit that connects the output of the comparator and the output circuit for registering the output of the comparator; and

(e) The output circuit is connected to a plurality of register circuits, and outputs a comparison result of the corresponding comparison device and position information of the corresponding measured unit.

4. The wafer of claim 3, wherein the electrical connection between the auxiliary test device located outside the die to be tested and the die to be tested is completely cut off during wafer dicing.

5. The wafer according to claim 3, wherein the unit to be tested can be wirelessly powered by electromagnetic waves.

6. The wafer of claim 3 wherein the power supply circuit is further connectable to a power input of the plurality of cells to be tested.

7. A wafer according to claims 3 and 6, wherein the power supply circuit can be constructed of hardwired or configurable switch lines, or a combination of hardwired and configurable switch lines.

8. The wafer according to claim 3, wherein the input path is electrically connected by a wired interconnection circuit connected to the signal input end of the unit under test, or directly transmitted by electromagnetic waves, or electrically connected by a wired interconnection circuit and directly transmitted by electromagnetic waves. The hybrid mode of transmission inputs data signals and control signals to a plurality of units under test on the wafer.

9. The wafer of claim 8 wherein the wired connection of the input path to the unit under test and the comparison device can be either hardwired or configurable, or hardwired. It can be configured with a combination of switch lines.

10. The wafer of claim 3 wherein the input path further comprises switching means coupled to said unit under test for converting the input signal and then inputting to the input.

11. The wafer of claim 3 wherein the comparing means is operative to sample the signal at the output of each of the plurality of cells under test and in parallel with the corresponding expected result input from the input path. Or sampling the signals of the output of each of the plurality of measured units and the corresponding output of the other measured unit and comparing them with each other.

12. A wafer according to claim 3 wherein the comparing means comprises switching means coupled to said unit under test for converting the signal at the output prior to comparison.

13. The wafer of claim 3 wherein the comparing means further comprises a result merging compression means for temporally and spatially merging the comparison.

The wafer according to claim 3, wherein if the port of the unit under test is used as an input and test/output bi-directional multiplexing, when the port is used as an output The corresponding input path connected to the port is set to high impedance by configuration.

15. A wafer according to claim 3 wherein the output circuit can be constructed of hardwired or constructed of configurable switch lines or by a combination of hardwired and configurable switch lines.

16. The wafer of claim 3, wherein part or all of the layout of the auxiliary test device can be based on a few basics using a computer's place and route tool. The cells are automatically generated.

17. An integrated circuit parallel test system, comprising:

a wafer to be tested, including all or part of an auxiliary test device fabricated by a semiconductor process;

a probe card consisting of another substrate containing some or all of the auxiliary test devices; and a test machine having a plurality of power supplies and corresponding current limiters capable of crystallizing All the units under test on the circle are shunted to provide sufficient current to ensure that the unit under test can work at a given operating frequency and can cut off the corresponding power supply when any of the units under test are short-circuited.

18. The system of claim 17 wherein said system is capable of performing a self test to eliminate errors in the auxiliary test device itself, including the ability to establish an input path and an output circuit on said wafer, and based on said input Test results of the path and output circuit to maintain or reconstruct the input path and output circuit.

The system of claim 17, wherein the auxiliary testing device comprises:

(c) Comparing device, one input connected to the output to be tested of one measured unit, the other input connected to the corresponding output to be tested of another unit under test, or the corresponding input path for inputting the expected result Connected

(e) an output circuit, connected to a plurality of register circuits, outputting a comparison result of the corresponding comparison device and a corresponding test order Meta location information.

20. The system of claim 19 wherein the auxiliary test device located outside the die on the wafer under test is electrically disconnected from the die to be tested and can be completely severed during wafer dicing.

A system according to claim 19, wherein the unit under test can wirelessly obtain power by means of electromagnetic waves.

22. The system of claim 19 wherein the power supply circuit is further connectable to a power input of the plurality of measured units.

23. System according to claim 19, 22, characterized in that the power supply circuit can be constituted by hard wiring, or by a configurable switching line, or by a combination of hard wiring and configurable switching lines.

24. The system according to claim 19, wherein the input path in the auxiliary test device is electrically connected by a wired interconnect circuit connected to the signal input end of the measured unit, or directly transmitted by electromagnetic waves, or electrically connected to the wired interconnect circuit. The connection of the connection and the direct transmission of the electromagnetic waves inputs the data signal and the control signal to a plurality of units to be tested on the wafer.

25. The system according to claim 24, wherein the wired connection between the input path of the auxiliary test device and the unit under test and the comparison device may be composed of hardwired or configurable switch lines, or Hardwired and configurable switch lines are combined.

26. The system of claim 19, wherein the input path in the auxiliary test device further comprises a conversion device coupled to the device under test for converting the input signal and then inputting to the input.

27. The system of claim 19 wherein the comparing means in the auxiliary testing device is operative to sample the signal at the output of each of the plurality of cells under test and the corresponding expected result input from the input path. Parallel comparison, or sampling the signals of the output of each of the plurality of measured units and the corresponding output of the other measured unit and comparing with each other. ·

28. A system according to claim 19 wherein the comparing means in the auxiliary testing means comprises switching means coupled to said unit under test for converting the signal on the output prior to comparison.

29. The system of claim 19 wherein the comparing means in the auxiliary testing device further comprises a result merging compression means for temporally and spatially merging compression of the comparison.

30. The system of claim 19, wherein the port of the unit under test is used as an input and test/ The output is bidirectionally multiplexed, and the corresponding input path connected to the port is configured to be high impedance when the port is used as an output.

31. System according to claim 19, characterized in that the output circuit in the auxiliary test device can consist of hardwired or configurable switch lines or a combination of hardwired and configurable switch lines.

32. The system of claim 17 wherein the other substrate constituting the probe card comprises, but is not limited to, a wafer or a printed circuit board; the other substrate can simultaneously be on the wafer under test or All or part of the power supply and signal input ports of some of the tested units provide power and test excitation.

33. The system according to claim 32, wherein the probe card is connected to the substrate to be tested by a bump; the protrusion may be located on the probe card or on the wafer to be tested. Or there are bumps on the probe card and the wafer to be tested.

34. The system according to claim 32, wherein the probe card is electrically connected to the tested wafer, and the test excitation and/or power supply can be transmitted in parallel to the plurality of measured units by electromagnetic waves.

35. The system of claim 17 wherein said test machine features comprise:

(a) capable of generating or storing configuration information corresponding to the connection relationship between the device under test and the auxiliary test device on the wafer, and capable of adjusting the corresponding configuration information according to the coordinates of the current die of the probe and transmitting the same to the wafer Configuration information; (b) The position information of the unit under test in the substrate and the result of the corresponding comparison device can be read from the wafer.

36. The system of claim 17 wherein the test results are stored in a memory internal to the integrated circuit chip.

37. The system of claim 17 wherein the test machine feature can include an expected result capable of generating or storing a corresponding test stimulus and capable of transmitting the expected result to a wafer.

38. The system of claim 17, wherein the test machine feature can include classifying the unit under test based on whether the comparison result meets the test requirement, recording and outputting the unit under test on a wafer or in Location information on the wafer and within the die.

39. An integrated circuit chip comprising a plurality of functional modules to be tested, wherein the plurality of functional modules having the same function are the tested units to be tested; wherein the integrated circuit chip further includes an auxiliary testing device; The auxiliary test device operates only when the integrated circuit chip is in a test mode; the test mode includes, but is not limited to, a plurality of measured units operating in parallel to perform the same input excitation; the auxiliary test device may be partially located Tested Inside the element, it can also be located in whole or in part outside the unit under test, including -

(a) a power supply circuit that connects the power input terminals of the plurality of units to be tested;

(b) an input circuit that connects the signal inputs of the plurality of cells to be tested; and when there is an expected result, the input circuit is also used to transmit the expected result to one end of the comparison device;

(e) The output circuit is connected to the output terminals of the plurality of comparison devices, and outputs the comparison result of the corresponding comparison device and the position information of the corresponding unit to be tested.

40. The integrated circuit chip according to claim 39, wherein the input circuit can electrically input the data signal and the control signal into the integrated circuit chip through a wired interconnection circuit connected to the signal input end of the measured unit signal. Measurement unit.

41. The integrated circuit chip of claim 39, wherein the input circuit further comprises conversion means coupled to the unit under test for converting the input signal and then inputting to the input.

42. The integrated circuit chip of claim 39, wherein the connection of the input circuit to the unit under test and the comparison device is either hardwired or configurable, or hardwired It can be configured with a combination of switch lines.

43. The integrated circuit chip according to claim 39, wherein the test excitation source for generating the data signal and the control signal may be external to the integrated circuit chip, or may be inside the integrated circuit chip, The test stimulus is generated externally and stored in the integrated circuit chip.

44. The integrated circuit chip of claim 39, wherein the comparing means further comprises switching means coupled to said unit under test for converting the signal on the output prior to comparing.

45. The integrated circuit chip of claim 39, wherein the comparing means further comprises result merging compression means for temporally and spatially merging compression of the comparison result.

46. The integrated circuit chip of claim 39, wherein the output circuit is comprised of hardwired or configurable switch lines, or a combination of hardwired and configurable switch lines.

47. The integrated circuit chip of claim 39, wherein the unit under test can be passed through an output circuit The position of the substrate and the resulting output of the corresponding comparison device can also be saved in the memory inside the integrated circuit chip.

48. The integrated circuit chip according to claim 47, wherein the failed function module to be tested is marked according to the test result saved in the memory, and the effective function module having the same function as the failed function module is redundant. In this case, the software/hardware system including the integrated circuit chip can replace the failed function module with a redundant effective function module to realize self-repair.

49. A circuit board comprising a plurality of tested units of the same function, wherein the unit to be tested is a packaged chip to be tested; wherein the circuit board has a plurality of sockets (chip sockets) For connecting the unit under test; the circuit board also has an interface for connecting to the test machine; the circuit board also has an auxiliary test device, including -

(a) at least one comparison chip; and

(b) an electrical connection to the comparison chip, the plurality of units to be tested, and the test machine interface.

50. The circuit board of claim 49, further comprising at least one buffer chip connected to the test unit and the test machine interface by electrical connection. '

51. The circuit board according to claim 49, wherein the test excitation of the unit under test can be transmitted from the test machine directly via an electrical connection on the circuit board to a plurality of units to be tested, or from the test machine. After being buffered by the buffer chip, it is transmitted to a plurality of units to be tested through an electrical connection, or transmitted from the test machine to the plurality of units to be tested in the form of electromagnetic waves via an electromagnetic wave generator.

52. The circuit board according to claim 49, wherein each of said comparison chips has a complex array dedicated input port, and all of said dedicated input ports of all said comparison chips are respectively electrically connected by a one-to-one correspondence An output port of the plurality of slots and an input/output multiplexing port; the comparison chip is capable of receiving an output signal of the test unit after the test unit is excited by an electrical connection, and each of the received units to be tested is received The output signal is compared in parallel with the corresponding output signals of other units under test to generate a comparison result.

53. The circuit board according to claim 49, wherein each of said comparison chips has a complex array dedicated input port, and all of said dedicated input ports of all said comparison chips are electrically connected by a one-to-one correspondence An output port of the plurality of slots and an input/output multiplexing port; the comparison chip further has an electrical connection with the test machine interface for receiving an expected result; and the comparison chip is capable of receiving the measured connection through the electrical connection Output letter after unit operation test excitation No., and compare each received output signal of each measured unit with the corresponding expected result to generate a comparison result.

54. The circuit board of claim 49, wherein the comparison chip further comprises a result merging compression device for temporally and spatially merging compression of the comparison result to generate a test result.

55. The circuit board according to claim 49, wherein the test result of the comparison chip to the unit under test is transmitted back to the test machine through an electrical connection.

56. The circuit board of claim 49, further comprising only one type of chip; said chip comprising a function of a comparison chip and a buffer chip.

57. The circuit board of claim 49, wherein the complete function of the circuit board can be implemented by a plurality of electrically connected circuit boards; one of the plurality of circuit boards can implement the Part of a full feature or full feature.