WO2010072993A1

WO2010072993A1 - Ccd sensor

Info

Publication number: WO2010072993A1
Application number: PCT/GB2009/002899
Authority: WO
Inventors: David James Burt; Paul Andrew Jerram
Original assignee: e2v Technologies UK Ltd
Current assignee: Teledyne UK Ltd
Priority date: 2008-12-23
Filing date: 2009-12-16
Publication date: 2010-07-01
Anticipated expiration: 2011-06-23
Also published as: GB2466502B; GB2466502A; GB0823470D0

Abstract

A back- illuminated CCD sensor comprises a substrate of one polarity type, buried charge transfer channels (102) of the opposite polarity type, control electrodes (100) fabricated on the front face of the sensor for transporting charge along the channels, the bias on a first bias connection on a channel stop region (113) of the first polarity type surrounding the sensor area and the bias of the control electrodes being such that the channels are surface pinned. While this would normally result in only a shallow depletion layer under the buried channels and hence poor spatial resolution, the invention provides a guard diode ring (115) surrounding the channel stop region, the guard diode region being of the same polarity type as the channels, and the depletion region under the guard diode ring spreading to meet the depletion region beneath the buried channels (102), thereby enabling the front surface bias (114) and rear surface bias (111) to be maintained at different potentials, thus permitting the depletion region associated with the channels to be adjusted to a desired depth.

Description

CCD SENSOR

This invention relates to CCD sensors.

The invention especially relates to CCD sensors fabricated for illumination on the back-face, which thereby avoids losses with imaging through the control electrodes that are used for transporting charge on the front face. The thickness of undepleted silicon beneath the channels must be minimised to avoid loss of spatial resolution through the lateral diffusion that is possible with any charge photo-generated in this region. Once charge has reached the edge of the depletion region, or is actually generated in the depletion region, there is a field to move it directly to the nearest pixel for collection.

Maximising resolution thus requires the silicon to be thinned to about the depth of depletion. However, this can mean that the silicon thickness is now too small to adsorb much of the light at the long wavelength end of the spectrum and low quantum efficiency results. Since the depth of depletion is approximately proportional to the square root of the product of the operating voltages and the silicon resistivity, thicker devices can be possible using higher resistivity silicon for fabrication. The voltages, however, are generally limited to those required for normal CCD operation, i.e. for both charge transfer and the output circuit (or circuits if more than one is employed). Also, high-resistivity silicon is, it must be said, is more difficult to prepare.

In order to increase the signal-to-noise ratio, it is desirable to minimise so-called "dark current", which can be generated at the interface of the Si substrate with its SiO₂ coating. One technique for doing this is by "pinning" the potential of this interface to the potential of the substrate, so that holes can flood the interface and swamp the trapping states causing the dark current. Unfortunately, this generally means setting the potential of the substrate at a value which reduces, rather than increases, the depletion depth.

For this reason, it has not been hitherto been possible to offer a back-illuminated charge-coupled device with a combination of front surface "pinning" to achieve low dark current and full depletion of the underlying substrate to achieve highest spatial resolution.

US patent nos. 6 608 337 and 7 271 468 disclose CCD sensors which use a guard ring to enable a higher bias voltage to be applied to the back surface of the silicon to increase the depth of depletion, whilst leaving the voltages on the front surface of the silicon at the usual levels required for normal CCD operation.

The Applicants have now appreciated that it is possible to "pin" the front surface of a CCD sensor to minimise dark current even though guard rings are employed which enable a higher back surface bias voltage and deeper depletion.

"Pinning" has not been appreciated as a possibility in the two US patents referred to. One embodiment of the former employs a virtual phase charge transport electrode, wherein one of the set of charge transport electrodes for each pixel which transfer the charge accumulated during an exposure from one pixel to the next is replaced by a doped region (the virtual phase electrode), creating a photodiode. The photodiode is described as being "pinned", although in this context it just means that holes are supplied to maintain its potential at the necessary value to enable charge transport to take place by varying the voltages only on the other two conventional charge transport electrodes, and there is no suggestion that the "pinning" should be applied to the nonvirtual phase conventional charge transport electrodes.

The invention provides a CCD sensor comprising: a semiconductor substrate of one polarity type; charge transfer channels of the opposite polarity type; control electrodes, fabricated on the front face of the sensor, for transporting charge along the channels, the sensor being adapted for illumination at the back face; the channels being arranged to be surface pinned along their entire length beneath the electrodes by means of a first bias connection made to a first region of the same polarity type as the substrate; a region of the same polarity type as the channels forming a guard ring diode around the region used for the first bias connection, the depletion region of which extends in use to the depletion region associated with the channels to permit the front and back faces of the substrate to be maintained at different potentials; and a second bias connection made to a second region of the same polarity type as the substrate and used for applying a voltage to the back face in order to adjust the depletion region associated with the channels to a desired depth.

Such a sensor can thus have both high resolution due to the deep depletion controlled by the back-surface bias and low dark current due to the pinned operation (pinning the front surface of the channels to the voltage of the front surface of the substrate) controlled by the front surface bias, and does not require fabrication using high resistivity silicon nor the application of cryogenic cooling to obtain these advantages. The technique could also be applicable to semiconductor materials other than silicon operated under similar pinned conditions.

One way of carrying out the invention will now be described in detail, by way of example, with reference to the accompanying drawings, in which:

Figure 1 is a cross-section of a part of a typical prior-art CCD sensor fabricated for back-face illumination, the cross-section being taken through the lines Y-Y in Figure 2, and illustrates the voltage distribution;

Figure 2 is a section through the CCD sensor of Figure 1;

Figure 3 is a section through the sensor of Figure 2 with the voltages appropriate to achieve "pinned" conditions;

Figure 4 is a view of the sensor corresponding to Figure 1 but with the voltages appropriate for pinned operation.

Figure 5 is a section through a part of back-face illuminated CCD sensor fabricated with two substrate connections, taken through the lines Z-Z in Figure 7, in accordance with the invention;

Figure 6 is a cross-section of the sensor of Figure 5 taken through the lines Y-Y in Figure 5, and showing the voltage distribution; and Figure 7 is a plan view of apart of the front face the sensor shown in Figures 5 and 6.

Like parts have been given like reference numerals through all the drawings.

The CCD sensor of the invention, as shown in Figures 5 to 7, as well as the prior art CCD sensor of Figures 1 to 4, consists of an array of pixels best seen in fragmentary form in Figure 7. The fragment shown in plan view (looking at the front surface) in Figure 7 shows four columns of the array, two of which are indicated by the reference numeral 102. Each pixel has three charge transport electrodes, three of which are indicated by the reference numeral 100. Figure 7 shows seven charge transport electrodes, and thus two complete rows of pixels and a part of a third. In reality the sensor would consist of, say, an array of 256 rows by 1024 columns. The array architecture could be of the full-frame, frame-transfer or interline-transfer types, and would be read out via the usual output register(s) and output circuit(s). These variants are well known and are not therefore described. The array could also be of linear architecture with just a single row of pixels.

Referring now to Figures 1 to 4 in connection with the prior art CCD sensor, Figure 1 shows a cross-section through a conventional buried channel CCD comprising a charge transport electrode 100 over a layer of insulator 101 formed on the surface of the underlying silicon semiconductor material. The doping of the semiconductor is such that there is a shallow layer of n-type to form the buried channel 102, and the remaining underlying semiconductor has doping of the opposite p-type, and in operation will have a certain depth of depletion 104. The remaining undepleted silicon is shown as 103. Also shown is the potential distribution from the electrode with applied bias voltage VQ, through the channel and down into the underlying semiconductor substrate with applied bias voltage Vs. For the case of zero stored charge, the depth of depletion increases with the square root of the product of the resistivity of the substrate and the amount by which the maximum voltage in the buried channel V_M exceeds the substrate voltage Vs-

Referring to Figure 2, the CCD sensor is fabricated for back-face illumination. The active region of the device comprising the charge transport electrodes 100, insulator 101 and the associated n-type buried channel 102 are fabricated on the front face of the device. Around the device periphery is a layer with increased p-type doping 105, designated p+, the channel stop, which is provided for isolation purposes and is also used to make contact with the underlying p-type semiconductor substrate. The bias connection made to the p+ layer 106 is therefore described as the substrate connection with bias voltage Vs- The potential distribution between the two arrows Y-Y in Figure 2 is as shown in Figure 1. Note that a voltage Vs is shown applied to the back surface in Figure I₅ whereas it is in fact applied to the p+ connection 106 at the front surface with a low resistance path being present through the periphery of the semiconductor to maintain the back surface at this same voltage. The illumination is incident on the back-face of the device 107 and, to minimise the spread of photo-generated charge and thereby maximise the spatial resolution, the thickness of the semiconductor is such that preferably all, or at least a substantial proportion thereof, is depleted 104. Since devices are generally manufactured with the semiconductor material in relatively thick wafer form, in the case of a back-illuminated device additional stages of manufacture are required to reduce the semiconductor thickness, for example by chemical etching. For any particular device implementation, the actual thickness is generally chosen such that a reasonable depth of depletion is achieved within the constraints of the available values for the substrate resistivity, VQ and Vs. It is also generally necessary to incorporate some means for increasing the p-type doping in a thin layer at the back surface 108. This is to both minimise the recombination of photo-generated charge and provide a sufficiently low resistance path to maintain the voltage at the applied value of Vs across the back surface of the device under normal operation.

Whereas for a device fabricated on semiconductor material of given resistivity the depth of depletion can be controlled by adjustment of VQ and/or Vs, there is an operating mode where this is no longer possible. This is when pinned operation is employed to reduce dark current.

Thus, if V_G is taken to voltages sufficiently more negative than Vs and causes holes from the substrate to accumulate as minority carriers at the semiconductor surface, the surface component of dark current is suppressed leaving the very much smaller bulk component. However, as shown in the device cross-section of Figure 3 and the associated voltage distribution between the two arrows Y-Y shown in Figure 4, the fact that there are holes at the surface 109 leads to the surface being at the same voltage as the substrate, which is why the term "pinned" is used, and the value for the depleting voltage becomes fixed at a value Vp that is independent of both V_G and Vs. The actual value for Vp depends only on the buried channel parameters and is typically a few volts, with the result that the depth of depletion in this mode is relatively small, as can be seen by comparing the depletion depth 104 in Figures 1 and 2 with that in Figures 3 and 4. One method of increasing the depth of depletion is to use material of higher resistivity, but this is not so readily available for device fabrication. According to the invention, a structure is used that permits the use of different voltages on the front and back substrate connections, while still permitting the front surface to be pinned.

Referring to Figures 5 to 7, the CCD sensor of the invention is a back-illuminated n- channel device which achieves both full depletion and pinned operation.

The CCD sensor of Figures 5 to 7 differs from the prior art CCD sensor of Figures 1 to 4, in that the channel stop p+ region 113 having a first bias connection 114 is now of smaller lateral extent than the corresponding p+ channel stop 105 and is surrounded by n+ doped guard ring 115 having a connection 116. The lateral extent of the channel stop region 113 should be less than the lateral extent of the guard ring region 115. In turn, surrounding the guard ring 115 is p+ doped region 110 having a second bias connection 111, which connects via low resistance path 112 to p+ doped back surface 108. The rings 113, 115 and 110 are visible in Figure 7 which shows the top of a fragment of the CCD sensor of the invention. The terms p+, n+ refer to enhanced p, n doping respectively.

In the voltage diagrams of Figure 6, a voltage V_BS is shown applied to the back surface of the sensor, whereas it is in fact applied to the p+ connection 110 on the front surface, the low resistance path 112 being present through the periphery of the semiconductor to maintain the back surface at this same voltage. The p+ region 110 around the outer edge of the chip is sufficiently wide to ensure that the peripheral regions 112 remain undepleted and thereby of relatively low resistance. The front- surface p+ regions 113 provide a channel-stop for isolation around the active pixel area and the transistors used for the final output circuit(s). The n+ guard ring regions 115 are held at a fixed positive voltage VQD with connection 116.

In operation, the charge transport electrodes 100 and front substrate 113 are held at the same voltages as would be used to obtain pinning in a conventional device. Figure 6 shows the voltage distribution between the two arrows Y-Y in Figure 5. The bias voltage VQ on the charge transport electrodes is set such as to cause holes from the front substrate p+ region 115 at bias V_FS to accumulate as minority carriers at the semiconductor surface. This is now the source of holes for the layer across the surface 109 at this voltage and the resulting peak voltage in the buried channel is Vp more positive than Vps- However, the back surface p+ layer 108 is biased with VB_S at a voltage less positive than VF_S, SO the difference in voltage between the channel maximum V_M and the underlying semiconductor increases to Vp + V_FS - VB_S, with a consequent increase in the depth of depletion 104.

Normally, with connections at different voltages across a region of semiconductor having one doping type (i.e. p-type in this case), currents would flow. These currents are avoided by having the front p+ regions 113 of small area and being surrounded by n-type regions 115 (of the same polarity as that of the buried channel of the CCD). The depletion region 104 beneath the buried channel 102 spreads out to meet the depletion region beneath the guard ring 115 and they join at 117 to cut off the possible front-to-back current path, much in the same way as current in a JFET is cut off with an appropriate gate voltage. The concentric rings extend around the whole periphery of the device. For any given practical device the necessary dimensions to avoid current flow will depend on the substrate resistivity and the required depth of depletion under the buried channel, but values can be easily derived using commercial simulation software.

Devices designed to exploit this effect require a connection around the periphery 110 of the chip for the back-surface substrate bias, a front-surface substrate with the p+ regions 113 of limited size and the remaining areas taken up with guard rings. The active regions of the device remain unchanged.

As has been mentioned above, the control electrodes are biased at such a voltage with respect to the underlying silicon that minority charge carriers of the opposite type to the channel majority carrier accumulate at the surface. These minority carriers effectively suppress the component of dark current that is generated at the silicon surface leaving the generally much smaller bulk contribution. However, with all electrodes thus biased, the potentials in the underlying buried channel are the same and there is no potential well to store signal charge. A practical device requires some means of modifying the channel potentials under at least part of one or more electrodes in the sequence comprising one pixel of the device to form a well for charge storage purposes. Additional dopants are typically introduced for this purpose in a variety of different configurations. These schemes are not relevant to the present invention as all result in signal charge being collected under conditions of minority carriers being accumulated at the silicon surface for dark current suppression. For simplicity, therefore, the description has simply shown electrodes with accumulated surface minority charge without the additional structures required to form the potential wells for charge storage.

In general, it is likely that V_FS would be held at a fixed voltage necessary to achieve correct operation of the CCD and V_BS varied to give full depletion for any given thickness of silicon.

The invention is suitable for use with devices having a silicon thickness in the range from 5 microns to 1 mm and with a resistivity lying within the range from 1 ohm.cm to 20k ohm.cm. The sensor is responsive to illumination from the near infra-red, down through the range of visible light to ultra-violet and X-ray wavelengths.

Of course, variations can be made without departing from the scope of the invention. Thus, it is also possible to make an opposite polarity device with a p-type buried channel, n-type substrate, n+ peripheral and back surface regions, p+ guard rings and opposite polarity bias voltages. It is not essential for the back bias V_BS to be applied via the peripheral ring at the front surface. The peripheral ring 110 could be omitted altogether, and the bias connection for the back surface could be made by a contact directly made to the back surface. Equally, the connection could be made to the peripheral edge of the chip that extends between the upper and lower faces. Each pixel has been described as having three charge transport electrodes. However, in addition to such a three phase clocking scheme, the invention is also applicable to two-phase or four-phase clocking schemes. The CCD sensor may be of the area type with full-frame, frame-transfer or interline-transfer architecture, or of the linear type with a single row of pixels.

Claims

1. A CCD sensor comprising: a semiconductor substrate of one polarity type; charge transfer channels of the opposite polarity type; control electrodes, fabricated on the front face of the sensor, for transporting charge along the channels, the sensor being adapted for illumination at the back face; the channels being arranged to be surface pinned along their entire length beneath the electrodes by means of a first bias connection made to a first region of the same polarity type as the substrate; a region of the same polarity type as the channels forming a guard ring diode around the region used for the first bias connection, the depletion region of which extends in use to the depletion region associated with the channels to permit the front and back faces of the substrate to be maintained at different potentials; and a second bias connection made to a second region of the same polarity type as the substrate and used for applying a voltage to the back face in order to adjust the depletion region associated with the channels to a desired depth.

2. A CCD sensor as claimed in claim 1, in which the second region surrounds the guard ring region.

3. A CCD sensor as claimed in claim 1 or claim 2, in which the resistivity of the substrate lies within the range of from 1 ohm. cm to 20k ohm. cm

4. A CCD sensor as claimed in claimed 3, in which the resistivity of the substrate lies within the range of from 1 ohm.cm to 200 ohm.cm..

5. A CCD sensor as claimed in any one of claims 1 to 4, in which the thickness of the substrate is within the range of from 5 microns to lmm.

6. A CCD sensor as claimed in claim 5, in which the thickness of the substrate is within the range of from 5 microns to 100 microns .

7. A CCD sensor as claimed in any one of claims 1 to 6, in which the first region includes a channel stop region abutting an array of pixels.

8. A CCD sensor as claimed in claim 7, in which the first region surrounds the array of pixels.

9. A CCD sensor as claimed in claim 7 or claim 8, in which the lateral extent of the first region is less than the lateral extent of the guard ring region.

10. A CCD sensor substantially as herein described with reference to Figures 5 to 7 of the accompanying drawings.