WO2010069193A1 - Data communication method and ethernet device - Google Patents

Abstract

A data communication method and an Ethernet device are provided by the present invention. The method comprises: a physical layer PHY chip multiplexes n paths of first speed physical layer data received from n ports into one path of second speed data and transmits it to an MAC chip; n is a natural number greater than 1; and when receiving the second speed data from the PHY chip, the MAC chip demultiplexes it into n paths of first speed data. Application of the present invention enables a single MAC chip in the Ethernet device to support larger port density, and reduces the cost of applying the broadband accessing to home.

Description

 Data communication method and an Ethernet device

 The present invention relates to the field of Ethernet technologies, and more particularly to a data communication method and an Ethernet device. Background of the invention

 The current broadband access-to-home technology mainly includes XDSL technology, Ethernet technology and FTTH technology, which use telephone lines, network cables and fiber-optic transmission media to the home. After the emergence of the new Long Range Ethernet (LRE) technology, Ethernet technology can also be accessed by telephone lines, which greatly reduces the barriers to Ethernet in practical applications. However, compared with XDSL devices, there is a significant disadvantage in that the number of supported ports is small. Currently, an Ethernet device (or a single board of a rack device) generally supports 24 ports, or It is 48 ports, and XDSL devices can be ^^ to 72 ports.

 In practical applications, there are many high-rise buildings, such as an 18-story building with about 128 households. In this case, it is obvious that the number of ports supported by an access device is as high as possible. Therefore, Ethernet devices (such as Ethernet switches) need to provide a larger number of physical ports to further enhance the core competitiveness in broadband access applications.

Currently, a medium independent interface (ΜΠ, Medium Independent Interface) is used between the physical layer (PHY) chip and the medium access control layer (MAC) chip in the Ethernet device. The Ethernet media interface includes: a media independent interface, and a cylinder. The media independent interface RMII and the serial media independent interface SMII, all of which come from the 。. ΜΠ refers to the media is copper shaft, fiber, cable, etc., because these media The related work is done by the PHY or MAC chip. ΜΠ Supports 10 megabits and 100 megabits of operation. One ΜΠ interface consists of 14 signal lines. Its support is flexible, but one drawback is that there is too much signal line for a ΜΠ interface.

 The RMII is a cylindrical ΜΠ interface that doubles the signal line in data transmission and reception, so it typically requires a 50 megabit bus clock. RMII is generally used in multi-port switches. It does not arrange for each port to receive and send two clocks. Instead, all data ports share one clock for all ports. This saves a lot of port data lines. . One port of the RMII requires seven signal lines, which is twice as small as ΜΠ, so the switch can access ports with twice the data. Like ΜΠ, RMII supports 10 Mbps and 100 Mbps bus interface speeds.

 SMII has fewer signal lines than RMII, and S means serial. Because it uses only one signal line to transmit data, and one signal line transmits and receives data, so in order to meet the 100 M demand on the clock, its clock frequency is 4艮 high, reaching 125M, why use 125M, because the data Some control information is transmitted inside the line. SMII — The port uses only 4 signal lines to transmit 100M signals, which is about twice as large as the RMII. SMII's support in the industry is very high. For the same reason, the data transmission and reception of all ports share the same external 125M clock.

 It can be seen that the interface between the Ethernet PHY chip and the MAC layer chip is one-to-one, that is, each physical layer interface uses a separate port interface to perform one-to-one communication with the corresponding MAC layer port, between the ports. Independent of each other, do not share data lines.

FIG. 1 is a schematic diagram of a connection between a PHY chip and a MAC chip in an Ethernet device in the prior art. As shown in FIG. 1 , in the prior art, the number of ports supported by the MAC chip is relatively large, generally 24, and the number of ports supported by the PHY chip is relatively small, generally 8, so that one MAC chip can be connected. The interface between the PHY chip, the PHY chip and the MAC chip is one-to-one. The method shown in Figure 1 greatly simplifies the design and cost of the Ethernet PHY chip. Since the ports between the MAC and the PHY are one-to-one and the input and output rates are the same, only the PHY chip needs to be very With less buffer storage, and the number of ports supported by the PHY chip is small, the number of pins required is small, so the design and cost of the PHY chip can be greatly reduced. However, the drawback of this method is that the MAC layer chip cannot support a large number of ports.

 The new LRE technology supports variable rates below 100Mbps, such as 33Mbps and 50Mbps, and in broadband access-to-home applications, this speed is sufficient for many years. Cost and interface density are a key factor in broadband applications.

 In the prior art, the number of ports supported by the MAC layer chip is relatively large (for example, 24), while the number of ports supported by the PHY chip is relatively small (for example, 8), and each port requires a separate data interface, so the MAC layer The number of pins that the chip needs to support is relatively large, and it is difficult to support a relatively large number, such as 64 or 72. In this case, even if the SMII interface is used, 4*64=256 pins are required. The number of pins required is too large. This is the main reason why the MAC chip of an Ethernet switch cannot support the large number of ports on a single chip at an optimal price/performance ratio. Therefore, how to support larger port density and further reduce costs on existing ΜΠ interfaces has become an important issue in broadband access-to-home applications. Summary of the invention

 The present invention provides two data communication methods that enable a single MAC chip in an Ethernet device to support a larger port density and reduce the cost of broadband access to the home application.

The present invention also provides an Ethernet device in which a single MAC chip can support a larger port density, thereby reducing the cost of broadband access to the home application. The present invention also provides a PHY chip and a MAC chip that enable a single MAC chip in an Ethernet device to support a larger port density and reduce the cost of broadband access to the home application.

 To achieve the above objective, the technical solution of the present invention is specifically implemented as follows: The present invention discloses a data communication method, and the method includes:

 The physical layer PHY chip combines the n-channel first-rate physical layer data received from the n ports into a second-rate data, and sends the data to the MAC chip through an interface between the PHY chip and the media access control layer MAC chip; a natural number greater than one;

When the MAC chip receives the data of the second rate from the PHY chip, it demultiplexes the data of the first rate of the n channels.

 The invention also discloses a data communication method, the method comprising:

 The MAC chip combines the n-channel first-rate MAC layer data into one second-rate data, and then sends the signal to the PHY chip through an interface between the PHY chip and the MAC chip; n is a natural number greater than one;

 When the PHY chip receives the data of the second rate from the MAC chip, it demultiplexes and synthesizes the first rate data.

 The invention also discloses an Ethernet device, comprising: a MAC chip and one or more PHY chips connected to the MAC chip; each PHY chip comprises: a first composite processing module; the MAC chip comprises: a second composite processing Module

 Each first composite processing module is configured to combine n-channel first rate data from n ports of the PHY chip to which it belongs to form a second rate data, and then send the signal to the MAC through an interface between the PHY chip and the MAC chip. Chip; n is a natural number greater than one;

The second composite processing module is configured to receive the second rate data from the PHY chip and decompose the data into the first rate of the n channels. The present invention discloses a PHY chip. The PHY chip includes: a first composite processing module, configured to combine n-channel first rate data from n ports of the PHY chip to which the PHY chip belongs to form a second rate data, and then pass The interface between the PHY chip and the MAC chip is sent to the MAC chip; n is a natural number greater than one.

 The present invention discloses a MAC chip. The MAC chip includes: a second composite processing module, configured to combine the n-channel first-rate MAC layer data into a second-rate data, and pass between the PHY chip and the MAC chip. The interface is sent to the PHY chip; n is a natural number greater than one.

 It can be seen from the foregoing technical solution that the PHY chip of the present invention combines n first-rate physical layer data received from multiple ports into one second-rate data and sends the data to the MAC through an interface between the PHY chip and the MAC chip. a chip; when the MAC chip receives the data of the second rate from the PHY chip, the technical solution of combining the data into multiple channels of the first rate, because the multi-path physical layer data is combined into one channel of data, and then passes through the PHY chip and the MAC. The ΜΠ transmission between the chips, thus enabling one ΜΠ interface to support multiple physical interfaces, thereby enabling a single MAC chip to support a larger port density and reducing the cost of broadband access to the home application.

 1 is a schematic diagram of connection between a PHY chip and a MAC chip in an Ethernet device in the prior art;

 2 is a flowchart of a data communication method according to an embodiment of the present invention;

 3 is a schematic diagram of a data communication method in an embodiment of the present invention;

4 is a block diagram showing the structure of an Ethernet device according to an embodiment of the present invention. Mode for carrying out the invention

 The core idea of the present invention is: to change the one-to-one design between the physical layer port and the MAC layer port (the port) of the current Ethernet PHY chip to a many-to-one design, thereby the number of port pins in the same port. Under the condition, support a larger number of physical layer ports, improve transmission efficiency, and reduce equipment costs.

 In order to make the objects, technical solutions and advantages of the present invention more comprehensible, the present invention will be further described in detail below.

 2 is a flow chart of a data communication method according to an embodiment of the present invention. As shown in Figure 2, the method includes the following steps:

 Step 201: The physical layer PHY chip combines the n-channel first-rate physical layer data received from the n ports into a second-rate data, and sends the data to the MAC through an interface between the PHY chip and the media access control layer MAC chip. Chip; n is a natural number greater than one.

 Step 202: When the MAC chip receives the data of the second rate from the PHY chip, the data is combined into n-channel first rate data.

 Figure 2 shows the process by which the PHY chip sends data to the MAC chip. Similarly, the process of the MAC chip transmitting data to the PHY chip is: the MAC chip combines the n-channel first-rate MAC layer data into one second-rate data and sends the signal to the PHY chip through the interface between the PHY chip and the MAC chip; the PHY chip Upon receiving the data of the second rate from the MAC chip, the solution is combined into n second rate data.

 In an embodiment of the present invention, the first rate data of the n channels is combined into the second rate data of one channel in a time division multiplexing manner; wherein the second rate is at least n times the first rate. And the interface between the PHY chip and the MAC chip is RMII, SMII or ΜΠ.

3 is a schematic diagram of a data communication method in an embodiment of the present invention. Referring to Figure 3, here is the port between the ΡΗΥ chip and the MAC chip. Take the SMII as an example. The port of the SMII. The rate is 125 Mbps, and the rate at which valid data is transmitted is 100 Mbps. If the LRE supports an external physical port of 50 Mbps, the same SMII port can transmit data of two 50 Mbps LRE physical ports. The valid data of the two 50 Mbps LRE ports can be time division multiplexed, for example, in bytes. Multiplexing, first transfer one byte of data of the first LRE port, then transfer one byte of data of another LRE port, and so on, the effective data of the two LRE ports is exactly 100Mbps. Similarly, if the LRE supports 25 Mbps external physical port, the same SMII port can transmit data of four 25 Mbps LRE physical ports. The effective data of the four 25 Mbps LRE ports are multiplexed in bytes, four The valid data of the LRE port is recombined to exactly 100 Mbps.

 In Figure 3, in order to complete the above processing, the following improvements are required to the existing PHY chip and MAC chip:

 (1) Adding a variable rate reference clock and a composite processing module based on the original PHY chip function module

 The composite processing module in the PHY chip multiplexes and demultiplexes the data according to the data transmission direction and the data reception direction of the PHY chip with respect to the MAC chip. Since the data received by the composite processing module is variable rate data, and the composite data is the standard rate data that caters to the SMII port, the PHY chip requires two working clocks, namely: a variable rate reference clock and a standard rate reference. clock. Referring to FIG. 3, the working clock of the LRE physical port of the PHY chip and the original PHY module therein is a variable rate reference clock; the working clock of the interface of the composite processing module of the PHY chip connected to the original PHY module is a variable rate reference clock, The working clock of the interface of the composite processing module connected to the SMII port is a standard rate reference clock; the working clock of the SMII port of the PHY chip is a standard rate reference clock.

(2) When adding variable rate reference based on the original MAC chip function module Clock and composite processing module

 The composite processing module in the MAC chip multiplexes and demultiplexes the data according to the data transmission direction and the data reception direction of the MAC chip with respect to the PHY chip. The same MAC chip requires two operating clocks: the variable rate reference clock and the standard rate reference clock. Referring to FIG. 3, the working clock of the SMII port of the MAC chip is a standard rate reference clock; the working clock of the interface of the composite processing module of the MAC chip connected to the SMII interface is a standard rate reference clock, and the composite processing module is connected to the original MAC module. The working clock of the interface is a standard rate reference clock; the working clock of the original MAC module in the MAC chip is a standard rate reference clock; wherein the composite processing module in the MAC chip demultiplexes the data from the SMII interface in units of bytes ( Assuming that the PHY chip is multiplexed in units of bytes to obtain multiplexed variable rate data, the multiplexed variable rate data is multiplexed into a standard rate data in units of data frames, and then sent to the original The MAC module performs MAC layer processing, so a variable rate reference clock is required in the composite processing module.

 In the above solution, after multiplexing the multiplexed data into one channel of data in a time division multiplexing manner, when demultiplexing, the demultiplexing may be performed according to a predetermined time division multiplexing manner. For example, multiplexing is performed in units of bytes when multiplexing, that is, one byte of data of the first LRE port is transmitted first, and then one byte of data of the second LRE port is transmitted, and thus, when it is demultiplexed, Demultiplexing the first byte received into the data of the first LRE port, demultiplexing the second byte into the data of the second LRE port, and demultiplexing the third byte into the first LRE The data of the port, the fourth byte is demultiplexed into the data of the second LRE port, and so on. Similarly, multiplexing can also be performed in units of bits, that is, one bit of data of the first LRE port is transmitted first, and then one bit of data of the second LRE port is transmitted, and so on.

In addition, when multiplexing multiple channels of data into one channel of data, it is also possible to The LRE port data carries the corresponding LRE port identifier, and the demultiplexing can be performed according to the LRE port identifier.

 A specific example is given below: Referring to FIG. 3, an PHY chip that connects an 8 (corresponding to n in FIG. 3 equal to 8) LRE physical port (hereinafter referred to as LRE port) of the MAC chip is taken as an example. Each LRE port has a variable rate data input of 50 Mbps. The LRE port and the original PHY module of the PHY chip both operate at a 50 Mbps reference clock, and the processing flow for transmitting data includes:

 (11) The data input from the eight LRE ports reaches the composite processing module of the PHY chip at a rate of 50 Mbps after being processed by the original PHY module.

 (12) The composite processing module of the PHY chip combines 8 channels of 50 Mbps data in units of bytes to obtain 4 channels of 100 Mbps data and sends them to the MAC chip through 4 SMII ports.

 In this step, the data of the LRE ports 1 and 2 are combined into one channel in units of bytes, and the data of the LRE physical ports 3 and 4 are combined into one channel in units of bytes, and the data of the LRE ports 5 and 6 are in bytes. The unit is combined into one way, and the data of the LRE ports 7 and 8 are combined into one way in units of bytes; taking the data combination of the LRE ports 1 and 2 as an example, the data of the LRE port 1 of one byte is transmitted first. Then transfer one byte of LRE port 2 data, then transfer one byte of LRE port 1 data, transfer one byte of LRE port 2 data, ..., and so on.

 (13) The four SMII ports of the MAC chip receive the four channels of 100 Mbps data and send the data to the composite processing module of the MAC chip;

 (14) The composite processing module of the MAC chip first decompresses four channels of 100 Mbps data and restores them to eight channels of 50 Mbps data.

Here, the decomposed processing in this step is described by taking the first 100 Mbps data as an example: The composite processing module of the MAC chip will be the first of the first 100 Mbps data. The byte is used as the data of LRE port 1, the second byte is used as the data of LRE port 2, the third byte is used as the data of port 1, and the fourth byte is used as the data of port 2, ... ..., and so on, to decompose the first 100 Mbps data into two

50 Mbps data, and corresponding to LRE ports 1 and 2, respectively. The solution process of the other road data is the same, and will not be repeated here.

 (15) The composite processing module of the MAC chip combines the demultiplexed eight channels of 50 Mbps data into two units of data frames, and obtains four channels of 100 Mbps data, and then sends the data to the original MAC module for MAC layer processing.

 Since the original MAC module works under the standard 100 Mbps reference clock and is processed in units of data frames when performing MAC layer processing, the frame header of the data frame includes some MAC layer information required for MAC layer processing, including The source MAC address and the destination MAC address are the same. Therefore, in this step, the data needs to be combined into data of 100 Mbps in units of data frames, and then sent to the original MAC module for processing. The process of time division multiplexing in units of data frames in this step is similar to the above process of time division multiplexing in units of bytes, and will not be repeated here.

 The reverse process of the above process, that is, the processing flow of receiving data, is as follows:

 (21) The original MAC module of the MAC chip will correspond to the data of LRE ports 1 and 2, the data corresponding to LRE ports 3 and 4, the data corresponding to ports 5 and 6, and the data corresponding to ports 7 and 8, respectively. The frame is combined into 4 channels of data at a rate of 100 Mbps and sent to the composite processing module of the MAC chip.

 (22) The composite processing module of the MAC chip decomposes each 100 Mbps data sent by the original MAC module in units of data frames to obtain 8 channels of 50 Mbps data.

In this step, the composite processing module of the MAC chip will have the first 100 Mbps number. According to the data frame unit, the two channels of 50 Mbps corresponding to LRE ports 1 and 2 are decomposed, and so on, and the second/three/four way 100 Mbps solution is combined to correspond to ports 3/4/7 and 4. /6/8 two-way 50Mbps data.

 (23) The composite processing module of the MAC chip combines the eight channels of 50 Mbps data in units of bytes to obtain four channels of 100 Mbps data and transmits them to the PHY chip through four SMII ports.

 (24) The four SMIIs of the PHY chip receive the four 100 Mbps data and send them to the composite processing module of the PHY chip.

 (25) The composite processing module of the PHY chip decomposes the four channels of 100 Mbps data in units of bytes, and obtains eight channels of 50 Mbps data and transmits the data to the original PHY module;

 (26) The original PHY module performs physical layer processing on the eight channels of 50 Mbps data, and then transmits them through the LRE ports 1 to 8, respectively.

 It can be seen that with the above scheme, a 24-port MAC chip can only connect three 8-port PHY chips in the existing manner. With the solution of the present invention, if the effective data rate of the SMII port is 100 Mbps, if the rate of the LRE port data is 50 Mbps, a 24-port MAC chip can connect six 8-port PHY chips; if the LRE port data At a rate of 25 Mbps, a 24-port MAC chip can connect to 12 8-port PHY chips. Similarly, the effective data rate of the RMII port is 50 Mbps. If the LRE port data rate is 25 Mbps, a 24-port MAC chip can connect six 8-port PHY chips.

4 is a block diagram showing the structure of an Ethernet device according to an embodiment of the present invention. As shown in FIG. 4, the device includes: a MAC chip and one or more PHY chips connected to the MAC chip; each PHY chip includes: a PHY module and a first composite processing module; and the MAC chip includes: a MAC module and a second composite Processing module; wherein Each PHY module is configured to process, after processing the physical layer data of the first rate of the n-channel received from the n ports of the chip to which it belongs, to the first composite module;

 Each first composite processing module is configured to combine the data of the first rate of the n-way from the n ports of the chip to which the UI module is sent into a second rate data, and then pass between the chip and the MAC chip. The interface is sent to the MAC chip; the second composite processing module is configured to receive the second rate data from the PHY chip, and decompose the data into the first rate of the n channels and send the data to the MAC module;

 The MAC module is configured to receive data from the second composite processing module and process the same. In FIG. 4, the MAC module is configured to send the MAC layer data to the second composite processing module, and the second composite processing module is configured to combine the n-channel first-rate MAC layer data into a second rate. After the data is sent to the PHY chip through the interface between the PHY chip and the MAC chip; the first composite processing module is configured to receive the second rate data from the MAC chip, and decompose the data into the n-channel first rate and send the data to a PHY module, configured to receive n-channel first rate data from the first composite processing module and perform processing separately.

 In FIG. 4, the first composite processing module is configured to combine the n-channel first rate data of the n ports from the PHY chip to which the PHY module is transmitted in a time division multiplexing manner, in units of bytes or bits. a second rate data; configured to decompose the second rate data from the MAC chip into bytes or bits into n-channel first rate data, and send the data to the PHY module; wherein, the second rate is at least the first N times the rate.

 a second composite processing module, configured to combine n first-rate MAC layer data in a time division multiplexing manner into a second rate data in units of bytes or bits; and to use the second rate data from the PHY chip, The data is decomposed into n-channel first rate in units of bytes or bits and sent to the MAC module.

In FIG. 4, the second composite processing module is further used to be from a MAC mode After the MAC layer data of the second rate of the block is decomposed into the first layer of the MAC layer data in the data frame unit, the MAC layer data of the n first rate is combined into bytes or bits. The second rate data is sent to the PHY chip through the interface between the PHY chip and the MAC chip; further used to receive the second rate data from the PHY chip, and is decomposed into n channels in units of bytes or bits. After the data of the rate, the decomposed n-channel first rate data is combined into a second rate data in units of data frames in a time division multiplexing manner, and then sent to the MAC module.

 In FIG. 4, the working clock of the PHY chip includes: a reference clock of a first rate and a reference clock of a second rate; and an operating clock of the MAC chip includes: a reference clock of the first rate and a reference clock of the second rate.

 In FIG. 4, the interface between the PHY chip and the MAC chip is RMII, SMII or ΜΠ.

 It should be noted that, for the sake of simplicity, only the internal structure of one core piece is shown in Fig. 4, and the internal structure of the other chip is not shown.

 In summary, the chip of the present invention combines the n-level first-rate physical layer data received from a plurality of ports into a second-rate data and transmits the data to the MAC chip through an interface between the chip and the MAC chip. When the MAC chip receives the data of the second rate from the PHY chip, the technical solution of recombining into the data of the multiple first rate is formed by combining the multiple physical layer data into one data and then passing through the PHY chip and the MAC chip. The transmission between the two, so that a single interface can support multiple physical interfaces, which enables a single MAC chip to support a larger port density, reducing the cost of broadband access to the home application.

 The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modifications, equivalents, improvements, etc., which are made within the spirit and principles of the present invention, should be included. It is within the scope of the invention.

Claims

Claim  A data communication method, characterized in that the method comprises:  The physical layer PHY chip combines the n-channel first-rate physical layer data received from the n ports into a second-rate data, and sends the data to the MAC chip through an interface between the PHY chip and the media access control layer MAC chip; a natural number greater than one;  When the MAC chip receives the data of the second rate from the PHY chip, it demultiplexes the data of the first rate of the n channels.  2. The method according to claim 1, wherein the method further comprises: the MAC chip merging n first-rate MAC layer data into one second-rate data and passing an interface between the PHY chip and the MAC chip Sent to the PHY chip; When the PHY chip receives the data of the second rate from the MAC chip, it demultiplexes and synthesizes the first rate data.  3. The method of claim 1 wherein:  The combining the first rate data of the n channels into the second rate data includes: combining the first rate data of the n channels into a second rate data of one channel in units of bytes or bits in a time division multiplexing manner; The second rate is at least n times the first rate;  When the MAC chip receives the data of the second rate from the PHY chip, decompressing the data into the first rate of the n channel includes: when the MAC chip receives the data of the second rate from the PHY chip, in bytes or The bit is unit-resolved into data of the first rate of the n-channel;  The method further includes: after receiving the data of the second rate from the PHY chip, the MAC chip decomposes the data into the first rate of the n channels, and further decomposes the first rate of the n channels in a time division multiplexing manner. The data is combined into a second rate of data in units of data frames. 4. The method of claim 1 wherein: The working clock of the PHY chip includes: a reference clock of a first rate and a reference clock of a second rate;  The working clock of the MAC chip includes: a reference clock of a first rate and a reference clock of a second rate.  5. A data communication method, characterized in that the method comprises:  The MAC chip combines the n-channel first-rate MAC layer data into one second-rate data, and then sends the signal to the PHY chip through an interface between the PHY chip and the MAC chip; n is a natural number greater than one;  When the PHY chip receives the data of the second rate from the MAC chip, it demultiplexes and synthesizes the first rate data.  6. The method of claim 5, wherein  The combining the first rate data of the n channels into the second rate data includes: combining the first rate data of the n channels into a second rate data of one channel in units of bytes or bits in a time division multiplexing manner; The second rate is at least n times the first rate;  When the PHY chip receives the data of the second rate from the MAC chip, decompressing the data into the first rate of the n channel includes: when the PHY chip receives the data of the second rate from the MAC chip, in bytes or The bit is unit-resolved into data of the first rate of the n-channel;  Before the MAC chip combines the n-channel first-rate MAC layer data into one-way second-rate data, the method further includes: the MAC chip decomposing the second-rate MAC layer data into the n-channel first rate in units of data frames. MAC layer data of the data.  7. The method of claim 5, wherein  The working clock of the PHY chip includes: a reference clock of a first rate and a reference clock of a second rate; The working clock of the MAC chip includes: a first rate reference clock and a second speed Rate reference clock.  An Ethernet device, comprising: a MAC chip and one or more PHY chips connected to the MAC chip; each PHY chip comprises: a first composite processing module; and the MAC chip comprises: a second composite Processing module  Each first composite processing module is configured to combine n-channel first rate data from n ports of the PHY chip to which it belongs to form a second rate data, and then send the signal to the MAC through an interface between the PHY chip and the MAC chip. Chip; n is a natural number greater than one;  The second composite processing module is configured to receive the second rate data from the PHY chip and decompose the data into the first rate of the n channels.  9. The Ethernet device of claim 8 wherein:  The second composite processing module is further configured to combine the n-channel first-rate MAC layer data into one second-rate data and send the signal to the PHY chip through an interface between the PHY chip and the MAC chip;  The first composite processing module is further configured to receive the second rate data from the MAC chip and decompose the data into the first rate of the n channels.  10. The Ethernet device of claim 9, wherein:  a first composite processing module, configured to combine n-channel first rate data from n ports of the PHY chip to which the PHY chip belongs to be combined into a second rate data in a time division multiplexing manner; and a second composite processing module, configured to The first rate of MAC layer data is combined into a second rate data in a time division multiplexing manner;  The second rate is at least n times the first rate. A PHY chip, wherein the PHY chip comprises: a first composite processing module, configured to combine n-channel first rate data from n ports of its own PHY chip into a second rate data Through the PHY chip and MAC chip The interface between them is sent to the MAC chip; n is a natural number greater than 1.  12. The PHY chip of claim 11 wherein:  The first composite processing module is further configured to receive second rate data from the MAC chip and decompose into n-channel first rate data.  The PHY chip according to claim 11, wherein the first composite processing module is configured to time-multiplex a n-channel first rate data from n ports of the PHY chip to which it belongs, The second rate data is combined into one channel in units of bytes or bits.  A MAC chip, wherein the MAC chip comprises: a second composite processing module, configured to combine the n-channel first-rate MAC layer data into a second-rate data, and pass the PHY chip and the MAC chip. The interface is sent to the PHY chip; n is a natural number greater than 1.  The MAC chip according to claim 14, wherein the second composite processing module is further configured to receive the second rate data from the PHY chip and combine the data into the first rate of the n channels.  The MAC chip according to claim 15, wherein the second composite processing module is configured to combine the n-way first-rate MAC layer data into bytes or bits in a time division multiplexing manner. A second rate data; for receiving second rate data from the PHY chip, and decomposing into n-channel first rate data in units of bytes or bits. The MAC chip according to claim 16, wherein the second composite processing module is further configured to decompose the MAC layer data of the second rate into a MAC of the first rate of the first channel in units of data frames. After layer data, the n-channel first-rate MAC layer data is combined into a second rate data in units of bytes or bits; further used to receive second rate data from the PHY chip, and in bytes Or bit is single After the bit solutions are combined into n-channel first rate data, the de-compressed n-channel first rate data is combined into a second-rate data in units of data frames in a time division multiplexing manner.