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WO2010059830A1 - Solution phy provisoire pour une compatibilité lpi avec des dispositifs existants - Google Patents

Solution phy provisoire pour une compatibilité lpi avec des dispositifs existants Download PDF

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Publication number
WO2010059830A1
WO2010059830A1 PCT/US2009/065154 US2009065154W WO2010059830A1 WO 2010059830 A1 WO2010059830 A1 WO 2010059830A1 US 2009065154 W US2009065154 W US 2009065154W WO 2010059830 A1 WO2010059830 A1 WO 2010059830A1
Authority
WO
WIPO (PCT)
Prior art keywords
phy
pause
period
data
mac
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2009/065154
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English (en)
Inventor
Hugh Barrass
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cisco Technology Inc
Original Assignee
Cisco Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cisco Technology Inc filed Critical Cisco Technology Inc
Priority to CN200980142892.6A priority Critical patent/CN102204390B/zh
Priority to EP09828224.7A priority patent/EP2351454B1/fr
Publication of WO2010059830A1 publication Critical patent/WO2010059830A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40039—Details regarding the setting of the power status of a node according to activity on the bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/10—Current supply arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/12—Arrangements for remote connection or disconnection of substations or of equipment thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/26—Flow control; Congestion control using explicit feedback to the source, e.g. choke packets
    • H04L47/266—Stopping or restarting the source, e.g. X-on or X-off
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Definitions

  • the disclosure relates generally to providing backward compatibility to legacy devices when implementing IEEE 802.3 az (Energy Efficient Ethernet).
  • Ethernet transceivers include a Media Access Control device (MAC) and a Physical Layer Device (PHY) coupled by a Media Independent Interface (Mil).
  • the MAC layer is responsible for, among other things, controlling access to the media
  • the PHY layer is responsible for transmitting bits of information across a link.
  • the interface between the MAC and the PHY is specified by IEEE 802.3 and has evolved from the 10 pin Mil (Media Independent Interface) for 10/100 Ethernet, to the 20 pin GMII (Gigabit Media Independent Interface) for GE, to the 36 pin XGMII (10 Gigabit Media Independent Interface) for IOGE along with other variants such as SMII, SGMII, XAUI and others.
  • IEEE P802.3az is currently defining a new Energy Efficient Ethernet mode of operation for multiple Ethernet PHYs.
  • 100BASE-TX, 1000-BASE-T, 1 OGBASE-T and some backplane PHYs will be modified to support a Low Power Idle (LPI) mode that allows the PHY and other system components to save energy during periods of low network traffic load.
  • LPI Low Power Idle
  • This energy saving is achieved when using the LPI state because the 802.3az- compliant PHY's activity level may drop after it is instructed to enter the LPI state and it will receive ample warning to exit the LPI from 802.3az- compliant host side hardware (e.g. 802.3az-compliant MAC and host ASICs) before live network traffic is expected.
  • 802.3az- compliant host side hardware e.g. 802.3az-compliant MAC and host ASICs
  • FIG. 1 illustrates an example of a system implementing Energy
  • FIG. 2 illustrates an example embodiment of the invention
  • FIG. 3 illustrates an example embodiment of the local PHY
  • Fig. 4A illustrates the operation of an example embodiment
  • Fig. 4B illustrates the operation of an example embodiment.
  • a buffer is included in a first physical layer device (PHY) and the buffer is adapted to receive data from a host media access control device (MAC), not designed to be compliant with Energy Efficient Ethernet, when the first PHY is in a Energy Efficient Ethernet low-power idle (LPI) state.
  • PHY physical layer device
  • MAC media access control device
  • a control circuit, included in the first PHY is adapted to control the first PHY to respond to data sent from the host MAC when the first PHY is in the LPI state by signaling the host MAC to pause data transmission for a first pause period, writing data transmitted from the local MAC, before the local MAC pauses data transmission, into the buffer and trans itioning the local PHY from the LPI state to an active state during a wake up period.
  • the control circuit is further adapted to control the first PHY to transmit data from the buffer to a link partner subsequent to completion of the wake period and before the completion of the first pause period and to transmit data received at the first PHY from the host MAC to the link partner after completion of the pause period.
  • Fig. 1 is a block diagram of a system utilizing a typical implementation compliant with Energy Efficient Ethernet.
  • a first Ethernet PHY 10 has a line-side interface (Ethernet port) 12 and a host-side interface (GMII port) 14 coupled to a first MAC 12.
  • a second Ethernet PHY 20 has a line-side interface (Ethernet port) 22 and an host-side interface (GMII port) 24 coupled to a second MAC 22.
  • the first and second PHYs and MACs have been re-architectured to be compliant with IEEE 802.3az.
  • the line-side interfaces 12 and 22 of both PHYs are coupled to an Ethernet link 30 and the host-side interfaces 14 and 24 are coupled to receive messages from the MACs over respective GMII buses.
  • the second PHY 20 receives a sleep code on its GMII 24 interface it transitions to the LPI mode and sends a notification to the first PHY 10 over the link 30.
  • the first PHY 10 will then transition to the LPI mode and send a sleep code on its GMII interface 14 to the first MAC 12.
  • Fig. 2 is a block diagram of an Ethernet link pair utilizing an example embodiment of a modified local PHY to implement Energy Efficient Ethernet (IEEE 802.3az).
  • a modified local PHY 40 has a line-side interface 42 coupled to a compliant link partner over the link 30, where the link partner includes the compliant second PHY 20 and supporting hardware, e.g., the compliant MAC 22.
  • the host-side interface of the modified local PHY 40 is connected by the GMII bus to a legacy MAC 42 and to other legacy hardware, such as switch fabric ASICs, that is not designed to be IEEE 802.3az compliant.
  • the receive circuit of the line-side interface of the modified local PHY 40 appears to the link partner to be fully IEEE 802.3az compliant.
  • the receive circuit of the line-side interface 42 of the local PHY 40 receives notification that the transmit circuit of the link partner is going into LPI mode. There may follow periodic "refresh" activity before the local PHY 40 receives an indication that the transmit circuit of the link partner wishes to leave the idle mode in order to transmit data. There are specified delays for the transitions involved. An additional delay may be imposed on the link partner transmit side to prevent data being sent until some extra time has elapsed after the PHY-layer wake period. The local PHY 40 may support such idle operations without any interaction with its host system.
  • the local PHY 40 must control the decision to enter LPI mode, must interact with the link partner 20 and must shield the MAC and switch fabric ASICs from the detailed requirements of the Energy Efficient Ethernet operation.
  • the decision to enter the low power idle state is made by a management entity that is outside the definition of the standard. It has been assumed that complex analysis of system state and traffic patterns will be needed to implement an optimal energy saving algorithm.
  • the local PHY 40 may only receive background support from system software to assist the decision-making algorithm.
  • the local PHY 40 waits for a fixed interval following the end of a packet that has been transmitted. If no following packet is to be sent before the end of the fixed interval then the local PHY 40 enters low power idle mode and signals the change of state to the link partner 20.
  • the inherent burstiness of network traffic especially at the edge of the network, causes the probability that another packet will need to be sent to decrease with time after the end of a packet that has been sent.
  • the local PHY 40 will wait for an interval that is determined by the management software of the local system. This interval may vary depending on factors such as the time of day and the historical traffic patterns observed.
  • the local PHY 40 may implement an algorithm that allows it to vary the time it waits following a packet depending on its own observation of historical traffic. The precise nature of this algorithm could vary.
  • the legacy host MAC 42 might start to transmit data without regard for the specified delays required to transition from the LPI state to the active state. Data would arrive at the local PHY 40 before the system had transitioned to the active state and data would be lost.
  • Fig. 3 depicts an example embodiment of the modified PHY 40.
  • the modified PHY includes a buffer 60 and a control circuit 62 for generating flow-control indications when data is received from the host and the local PHY is in the LPI state and for performing other functions described below.
  • Fig. 4A if the local PHY is in the LPI state, then when the host starts to transmit data to the local PHY the data will be held in the buffer 60 and the control circuit 62 of the local PHY will control the local PHY to assert a first flow-control signal that causes the host to stop transmitting data.
  • the depth of the buffer is determined by the response latency of the host MAC to the flow-control signal asserted by the modified PHY.
  • the system has a known pause response latency from the Mil (or equivalent) input to the Mil output. At a minimum the buffer must absorb all data transmitted by the host until the first flow-control signal is acted upon and the host MAC has paused the transmission of data for a specified pause period.
  • the flow-control signal includes a field specifying the duration of the pause period.
  • the duration of the pause period is specified to include the wake up period required to transition the local PHY 40 and the link partner PHY 20 from the LPI state and the buffer read period required to read data from the buffer.
  • the buffer read period must be sufficient to read data from a full buffer because the amount of data stored in the buffer 60 is not determinable in advance.
  • the modified PHY 40 then signals wake up to the link partner PHY 20 and transitions all systems out of the LPI mode during the wake up period.
  • the modified PHY 40 transmits data from the buffer 60 to the link partner PHY 20 and prepares for the resumption of transmission of data from the local host. Once the wake up period expires the host resumes the transmission of data to the modified PHY 40 for transmission over the link.
  • the local PHY 40 supports a flow control mechanism to halt transmission on its 802.3az ports.
  • flow control is implemented using IEEE 802.3x (PAUSE) but other mechanisms would be equally valid.
  • PAUSE IEEE 802.3x
  • a PAUSE signal is sent by a receiving endpoint to a transmitting endpoint to assert backpressure when the receiving endpoint can not accept more data.
  • the transmitting endpoint Upon receipt of the PAUSE signal the transmitting endpoint sends a pause frame to the transmitting endpoint' s MAC that specifies the duration of a pause period. No data is transmitted until the pause period expires.
  • first and second flow-control signals are asserted by the modified PHY 40.
  • the first flow control signal specifies a first pause period having a long duration. The pause period could be equal to the pause period of the embodiment of Fig. 4A.
  • the control circuit 62 causes the local PHY 40 to read data from the buffer and transmit the data to the link partner PHY 20.
  • the second flow-control signal is sent immediately when all the data has been read from the buffer and transmitted.
  • the local MAC immediately resumes transmission of data.
  • the example embodiment of Fig. 4B reduces the latency caused by transitioning from the LPI state in the case where the buffer has not been filled during the pause response latency. Transmission from the MAC is resumed immediately when the buffer is empty instead of waiting for the expiration of the buffer read period specifying the time to empty a full buffer.
  • modified PHY Various example embodiments of a modified PHY have been described that can be utilized in high density switching systems so that re-architecting the core silicon of the switching devices is not required.
  • the modified PHYs can be utilized as interfaces between the legacy silicon, including MAC and switch fabric ASICs, of the high density switching devices and edge devices such PCs and servers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

Selon un mode de réalisation de l’invention, un PHY local modifié est conçu pour coupler un dispositif hôte existant à un partenaire de liaison mettant en œuvre un Ethernet économe en énergie. Le PHY local modifié comprend un tampon et si l'hôte existant transmet des données lorsque le PHY local modifié est dans un état inactif à faible consommation (LPI), alors les données sont stockées dans le tampon et une transmission est interrompue jusqu'à ce que le PHY local modifié effectue une transition de l'état LPI à un état actif.
PCT/US2009/065154 2008-11-24 2009-11-19 Solution phy provisoire pour une compatibilité lpi avec des dispositifs existants Ceased WO2010059830A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN200980142892.6A CN102204390B (zh) 2008-11-24 2009-11-19 用于与旧式设备的lpi兼容性的过渡phy解决方案
EP09828224.7A EP2351454B1 (fr) 2008-11-24 2009-11-19 Solution phy provisoire pour une compatibilité lpi avec des dispositifs existants

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/277,010 2008-11-24
US12/277,010 US8107365B2 (en) 2008-11-24 2008-11-24 Interim PHY solution for LPI compatibility with legacy devices

Publications (1)

Publication Number Publication Date
WO2010059830A1 true WO2010059830A1 (fr) 2010-05-27

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PCT/US2009/065154 Ceased WO2010059830A1 (fr) 2008-11-24 2009-11-19 Solution phy provisoire pour une compatibilité lpi avec des dispositifs existants

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Country Link
US (1) US8107365B2 (fr)
EP (1) EP2351454B1 (fr)
CN (1) CN102204390B (fr)
WO (1) WO2010059830A1 (fr)

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Also Published As

Publication number Publication date
EP2351454A4 (fr) 2013-01-09
US8107365B2 (en) 2012-01-31
EP2351454B1 (fr) 2014-01-15
CN102204390B (zh) 2014-03-12
EP2351454A1 (fr) 2011-08-03
US20100128738A1 (en) 2010-05-27
CN102204390A (zh) 2011-09-28

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