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WO2010058492A1 - Modulateur delta sigma et appareil de communication sans fil - Google Patents

Modulateur delta sigma et appareil de communication sans fil Download PDF

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Publication number
WO2010058492A1
WO2010058492A1 PCT/JP2009/001714 JP2009001714W WO2010058492A1 WO 2010058492 A1 WO2010058492 A1 WO 2010058492A1 JP 2009001714 W JP2009001714 W JP 2009001714W WO 2010058492 A1 WO2010058492 A1 WO 2010058492A1
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WIPO (PCT)
Prior art keywords
signal
digital
analog
filter
quantizer
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Ceased
Application number
PCT/JP2009/001714
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English (en)
Japanese (ja)
Inventor
三谷陽介
松川和生
高山雅夫
道正志郎
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Panasonic Corp
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Panasonic Corp
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Priority to JP2010539104A priority Critical patent/JPWO2010058492A1/ja
Publication of WO2010058492A1 publication Critical patent/WO2010058492A1/fr
Priority to US13/094,519 priority patent/US20110200077A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/38—Calibration
    • H03M3/386—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H03M3/388—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/456—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a first order loop filter in the feedforward path

Definitions

  • the present invention relates to a delta-sigma modulator and a wireless communication apparatus using the same.
  • a delta-sigma modulator used in an analog-to-digital converter is a Nyquist analog by noise shaping technology and oversampling technology as described in Non-Patent Document 1, for example. It is known as a method capable of realizing high accuracy and low power compared to a digital converter.
  • Non-Patent Documents 1 and 2 As a technique suitable for a high-speed / wideband delta-sigma modulator, a continuous-time delta-sigma modulator described in Non-Patent Documents 1 and 2 is known.
  • FIG. 11 is a block diagram showing a schematic configuration of a continuous-time delta-sigma modulator.
  • a continuous-time delta-sigma modulator shown in FIG. 11 includes a loop filter 502 having an arbitrary frequency characteristic, a quantizer 503 that quantizes an output signal of the loop filter 502 and outputs the quantized signal as a digital output signal, and a quantizer 503.
  • a digital-to-analog converter (DAC) 504 that converts the output signal of the analog signal into an analog value and feeds back, and a subtractor 501 that calculates the difference between the analog value output from the DAC 504 and the analog input signal
  • the output of the subtracter 501 is input to the loop filter 502.
  • FIG. 12 is a block diagram showing a linear model of the continuous-time delta-sigma modulator.
  • the transfer function of the loop filter 602 is H (s)
  • the quantizer 503 of FIG. 11 is placed with the adder 603 of the quantization noise E
  • the step response of the DAC 605 is expressed by the transfer function to represent DAC (s).
  • the transfer function representing the relationship between the analog input signal X and the digital output signal Y can be expressed as the following Equation 1.
  • a term related to the quantization noise E is called a noise transfer function (Noise Transfer Function; NTF)
  • a term related to the analog input signal X is called a signal transfer function (Signal Transfer Function; STF).
  • the change in the transfer function of the feedback path in this way means that an error occurs in the amount of charge integrated by the analog integrator constituting the loop filter 502.
  • the stability is significantly affected, and problems such as a decrease in accuracy of the output signal and oscillation occur.
  • This delay is generally called an excess loop delay.
  • Patent Documents 2 and 3 and Non-Patent Documents 3 and 4 describe an example of a mitigation method.
  • a signal obtained by digital-analog conversion of the output signal of the quantizer is fed back to the input unit of the quantizer, and the difference from the output signal of the loop filter (analog filter unit) is calculated.
  • the transfer function whose stability is reduced due to the delay is converted into a stable transfer function.
  • Patent Documents 2 and 3 and Non-Patent Documents 3 and 4 require an additional digital-analog converter for feeding back to the input unit of the quantizer.
  • an operational amplifier with a high gain bandwidth is required, which causes a problem that power consumption and cost increase.
  • the input amplitude to the quantizer becomes small. For this reason, the input range of the quantizer becomes narrow, and it is easily affected by the quantizer offset and manufacturing variations, resulting in a problem of reduced accuracy.
  • Patent Document 1 conventionally describes an example of a method for dealing with an excess loop delay and not requiring an additional DAC. More specifically, this method is a technique in which an output signal of a quantizer is passed through a digital modulation loop circuit and then fed back to a part of an analog filter unit through a digital / analog converter.
  • Patent Document 1 has the following problems. That is, 1. Due to the delay of the digital modulation loop itself, there is a problem that stability is lowered and abnormal oscillation is likely to occur.
  • the output of the quantizer is arithmetically processed by a digital modulation loop, and the output subjected to the arithmetic processing is directly input to the DAC.
  • a method for reducing the influence of manufacturing variation such as dynamic element matching (DEM) is added to a plurality of DAC portions, the excess loop delay increases, resulting in accuracy and stability. It will reduce the sex.
  • DEM dynamic element matching
  • the present invention has an object of reducing the influence of delay on a high-speed / wideband signal and improving the accuracy of an output signal, and a radio communication apparatus using the delta-sigma modulator Is to provide.
  • the recursive type that compensates for this delay and matches the original transfer function.
  • a configuration is adopted in which a digital filter such as a filter is added, and an appropriate output digital signal without delay corresponding to the output of the digital filter and the digital output of the quantizer is stored in a table in advance. As a result, the delay amount in the digital modulation loop is reduced to improve the stability of the delta-sigma modulator caused by the excess loop delay.
  • the delta-sigma modulator of the present invention includes an analog filter, a quantizer that converts the output of the analog filter into a digital signal and outputs the digital signal, and a first digital signal from the quantizer.
  • a digital filter that performs predetermined digital processing on the signal and outputs the processing result as a table control signal, a first digital signal from the quantizer, and a second digital signal corresponding to the table control signal from the digital filter Are stored in advance, a digital-analog converter that converts the second digital signal from the table as an analog feedback signal, and a difference between the input analog signal and the output signal of the digital-analog converter is subtracted.
  • a subtractor for outputting a signal of the subtraction result to the analog filter, That.
  • the delta-sigma modulator of the present invention includes an analog filter, a quantizer that converts the output of the analog filter into a digital signal and outputs the digital signal, and a first digital signal from the quantizer.
  • a digital filter that performs predetermined digital processing and outputs the processing result as a first table control signal;
  • a DEM address generation unit that generates a DAC selection signal based on the first table control signal from the digital filter;
  • Digital-to-analog conversion that converts the second digital signal from the table as an analog feedback signal If, by subtracting the difference between the input analog signal and the output signal of the digital-to-analog converter, characterized in that it comprises a subtractor for outputting a signal of the subtraction result to the analog filter.
  • the present invention is characterized in that, in the delta-sigma modulator, the table includes an adjusting means for adjusting an output gain of the table.
  • the present invention is characterized in that, in the delta-sigma modulator, the digital filter is a recursive filter circuit of an arbitrary order.
  • the wireless communication device of the present invention includes a receiving unit having the delta-sigma modulator, a transmitting unit that modulates a transmission signal, an antenna, supply of a transmission signal from the transmitting unit to the antenna, and from the antenna to the receiving unit. And a transmission / reception switching unit that switches between supply of a reception signal to the terminal and the reception signal.
  • the digital signal from the quantizer and the table control signal as a result of digital processing of the digital signal from the quantizer by a digital filter such as a recursive filter circuit of any order Accordingly, a compensation value (second digital signal) that does not change the transfer function of the analog filter even when an excess loop delay occurs is stored in the table in advance. Therefore, the delay amount of the signal in the feedback path can be reduced, and as a result, the stability of the delta sigma modulator due to the excess loop delay is improved, and it is possible to avoid a decrease in accuracy of the output signal. Become. Furthermore, since the compensation value is stored in the table in advance, an appropriate compensation value can be output without being calculated each time, and a small circuit can be realized.
  • the delay amount of the signal in the feedback path can be reduced, and the stability of the delta-sigma modulator caused by the excess loop delay can be improved. Become.
  • the delay amount of the signal in the feedback path can be reduced, and as a result, the stability of the delta-sigma modulator due to the excess loop delay can be improved, and the output signal can be improved. There is an effect that accuracy degradation can be avoided.
  • FIG. 1 is a block diagram showing a configuration of a delta-sigma modulator according to Embodiment 1 of the present invention.
  • FIG. 2 is a diagram showing a specific example of the LUT provided in the delta-sigma modulator.
  • FIG. 3 is a diagram illustrating a connection relationship among the quantizer, the correction signal generation unit, and the DAC.
  • FIG. 4 is a diagram illustrating specific examples of the quantizer, the correction signal generation unit, and the DAC.
  • FIG. 5 is a block diagram showing a configuration of a delta-sigma modulator according to Embodiment 2 of the present invention.
  • FIG. 6 is a block diagram showing a configuration of a delta-sigma modulator according to Embodiment 3 of the present invention.
  • FIG. 7 is a diagram showing a specific example of the LUT provided in the delta-sigma modulator.
  • FIG. 8 is an explanatory diagram of an operation model of the DEM.
  • FIG. 9 is a block diagram showing a configuration of a wireless reception apparatus according to Embodiment 4 of the present invention.
  • FIG. 10 is a block diagram showing a configuration of a wireless communication apparatus according to Embodiment 5 of the present invention.
  • FIG. 11 is a block diagram showing a configuration of a conventional delta-sigma modulator.
  • FIG. 12 is a diagram showing a linear model showing a transfer function of a conventional delta-sigma modulator.
  • FIG. 1 is a block diagram showing a configuration of a delta-sigma modulator according to Embodiment 1 of the present invention.
  • the delta-sigma modulator includes an analog filter unit 100 that passes a specific frequency, a quantizer 110 that quantizes an analog signal into a digital signal, and a digital signal S1101 from the quantizer 110.
  • a correction signal generation unit 120 that generates a corrected digital output signal, a digital output signal output from the correction signal generation unit 120 is received as an analog feedback signal, and is converted from digital to analog, and an analog signal S1300 is output to the analog filter unit 100. It is composed of an arbitrary bit DAC (digital-to-analog converter) 130.
  • the analog filter unit 100 includes a subtractor 101 that subtracts the feedback signal S1300 from the DAC 130 and outputs the analog input signal, and a loop filter (analog filter) 102.
  • the correction signal generation unit 120 includes an LUT (table) 121, a subtractor 122, a variable gain 123, and a delay element 124.
  • the subtractor 122, the variable gain 123, and the delay element 124 constitute a first-order recursive filter circuit (digital filter) 125.
  • the subtractor 122 is variable from the digital signal S1101 output from the quantizer 110.
  • the output signal of the gain 123 is subtracted, and the subtraction result is output as an LUT control signal (table control signal) S1200 to the LUT 21.
  • the delay element 124 delays and outputs the LUT control signal S1200 from the subtractor 122, and the variable gain 123 gives a predetermined gain to the signal output from the delay element 124 and outputs it.
  • the predetermined gain of the variable gain 123 is controlled by an external microcomputer (CPU) 6000.
  • the loop filter H (z) ′ created here can realize substantially the same transfer function as the original transfer function H (z) by adding the correction coefficient ⁇ even when the delay z ⁇ 1 occurs.
  • Specific examples of these transfer functions are shown by a third-order loop filter.
  • a path having a gain of ⁇ may be added to the feedback path.
  • the transfer function of this part is represented by the following formula 5 when a first-order filter is exemplified. This is the transfer function of a first order recursive filter.
  • the LUT 121 receives the digital signal (first digital signal) S1101 output from the quantizer 110 and the LUT control signal S1200 output from the subtractor 122. As shown in FIG. 2, the LUT 121 holds in advance an output digital signal corresponding to the digital input signal from the quantizer 110 and the LUT control signal S1200 from the subtractor 122.
  • This output digital signal realizes a transfer function of the following equation 6 where X is an input digital signal to the LUT 121, Y is an output signal from the LUT 121, a is the gain of the variable gain 123, and k is the gain of the LUT 121. It is a signal of a corresponding relationship.
  • the transfer function expressed by Equation 6 is added as the transfer function of the feedback path of the delta sigma modulator.
  • the output digital signal Y from the LUT 121 is a correction digital signal (second digital signal), which is a digital output signal of the delta-sigma modulator 1000.
  • the digital output signal generated by the correction signal generation unit 120 based on the digital signal S1101 output from the quantizer 110 is input to the DAC 130 of the feedback unit.
  • the LUT control signal 1200 is output as a digital signal obtained by performing so-called first-order recursive filter processing on the signal output from the quantizer 110.
  • the LUT 121 stores data (adjustment means) that selects and outputs an arbitrary bit width in order to adjust the gain of the output signal S1101 of the quantizer 110.
  • This data is the coefficient k in Equation 6 above.
  • the correction signal generator 120 determines a transfer function corresponding to the correction of the excess loop delay. Therefore, the correction signal generation unit 120 that connects the quantizer 110 and the DAC 130 maintains a numerical correspondence that optimizes the transfer function, thereby minimizing the error.
  • the compensation value calculated in advance is stored in the LUT 121, it is possible to obtain an output signal without calculation every time, and it can be realized with a small circuit.
  • the LUT 121 can be configured by SRAM, information can be rewritten. Therefore, the accuracy of the output signal can be maintained by changing the contents of the LUT 121 as necessary in accordance with the fluctuation of the delay amount.
  • FIG. 5 is a block diagram showing a configuration of the delta-sigma modulator 2000 according to Embodiment 2 of the present invention.
  • the delta sigma modulator 2000 according to the second embodiment is the same as the delta sigma modulator 1000 according to the first embodiment of the present invention, in which the LUT control signal S1500 in the correction signal generation unit 120 is second-order recursion.
  • the configuration generated by the type filter circuit 158 is different.
  • the correction signal generation unit 150 includes an LUT 151, two subtracters 152 and 153, two delay elements 156 and 157, and two variable gains 154 and 155.
  • the first delay element 157 delays and outputs the LUT control signal S1500 from the second subtractor 153.
  • the first variable gain 155 gives a predetermined gain to the signal output from the first delay element 157 and outputs it.
  • the second delay element 156 delays the signal output from the first delay element 157 and outputs the delayed signal.
  • the second variable gain 154 gives a predetermined gain to the signal output from the second delay element 156 and outputs the signal.
  • the first subtracter 152 subtracts the difference between the digital signal S1101 output from the quantizer 110 and the output signal of the second variable gain 154 and outputs the result.
  • the second subtracter 153 subtracts the output of the first variable gain 155 from the output signal of the first subtracter 152 and outputs the result to the LUT 151 and the first delay element 157 as the LUT control signal S1500.
  • the LUT 151 is an output corresponding to the digital signal S1101 output from the quantizer 110 and the LUT control signal S1500 output from the second subtractor 153, as in the first embodiment.
  • Digital signals are stored in advance, and output digital signals corresponding to both signals are output.
  • the input digital signal to the LUT 151 is X
  • the output digital signal from the LUT 151 is Y
  • the gain of the second variable gain 154 is a
  • the gain of the first variable gain 155 is b
  • the gain of the LUT 121 is a signal having a correspondence relationship that realizes the transfer function of the following equation (7).
  • This transfer function is added as a transfer function of the feedback path of the delta-sigma modulator.
  • the quantization error is more improved than that of the primary recursive filter circuit. It can be even less.
  • FIG. 6 is a block diagram showing the configuration of the delta-sigma modulator 3000 according to Embodiment 3 of the present invention.
  • the delta-sigma modulator 3000 according to the third embodiment of the present invention has a configuration in which the DEM address generation unit 165 in the correction signal generation unit is added to the delta-sigma modulator 1000 according to the first embodiment. Is different.
  • the DEM operation when the DAC 130 includes a DEM mechanism will be described.
  • a DEM mechanism is generally used as a method for compensating for the variation in the DAC.
  • the DWA method which is a typical DEM algorithm will be described. This DWA method is a method of averaging the number of times each element is used by sequentially selecting a plurality of DAC elements constituting the DAC 130. .
  • the DEM control signal is 3 bits will be described as an example.
  • the correction signal generation unit 160 includes an LUT 161, a subtractor 162, a variable gain 163, a delay element 164, and a DEM address generation unit 165.
  • the subtractor 162, the variable gain 163, and the delay element 164 constitute a first-order recursive filter circuit (digital filter) 166 as in the first embodiment.
  • the DEM address generation unit 165 receives the LUT control signal (first table control signal) S1600 from the subtractor 162, and outputs a DEM address control signal S1601 according to the LUT control signal.
  • the LUT 161 includes a digital signal (first digital signal) S1101 output from the quantizer 110, an LUT control signal (first table control signal) S1600 output from the subtractor 162, and the DEM address generation.
  • the DEM address control signal (DAC selection signal) S1601 from the unit 165 is input.
  • the LUT 161 includes a digital input signal from the quantizer 110, an LUT control signal S1600 from the subtractor 122, and a DEM address control signal (DAC selection signal) from the DEM address generation unit 165.
  • An output digital signal (second digital signal) corresponding to S1601 is held in advance.
  • the input digital signal to the LUT 161 is X
  • the output digital signal from the LUT 161 is Y
  • the gain of the variable gain 163 is a
  • the gain of the LUT 161 is k. It is a signal of a corresponding relationship.
  • the number of DACs 130 driven by the digital output signal output from the LUT 161 itself does not change, and the total current value fed back is the same.
  • the position of the driven DAC 130 is different.
  • the correction signal generation unit 160 realizes the same transfer function as that shown in Equation 2 above.
  • the DEM mechanism is added to the DAC 130, the amount of additional delay due to the processing signal generation processing of the excess loop delay is minimized, and the output signal of the high-speed / wideband signal can be reduced. Accuracy can be maintained.
  • FIG. 9 shows a configuration of a wireless reception apparatus according to Embodiment 4 of the present invention.
  • the wireless reception device 4000 includes a delta-sigma modulator 205, a low noise amplifier (LNA) 202, a mixer 203, and an automatic device according to any of the first to third embodiments described above.
  • a receiving unit 201 having a gain control circuit (AGC) 204, a digital baseband processing unit 206, and an antenna 200 are provided.
  • AGC gain control circuit
  • FIG. 10 shows a configuration of a wireless communication apparatus 5000 according to Embodiment 5 of the present invention.
  • the wireless communication apparatus includes a delta-sigma modulator 205 according to any of the first to third embodiments, a low noise amplifier (LNA) 202, a mixer 203, an automatic gain, and the like.
  • a transmission / reception switching unit 208 and an antenna 200 are provided.
  • variable gain 123 of the correction signal generation unit 120 may be a fixed gain.
  • the LUT control signal S1500 of the correction signal generation unit 150 may be generated by recursive filter processing of any order.
  • the DEM address generation unit 165 may be provided with a secondary recursive filter circuit instead of the primary recursive filter circuit 166.
  • the present invention can reduce the delay amount of the signal in the feedback path and, as a result, improve the stability of the delta-sigma modulator caused by the excess loop delay.
  • the accuracy of the output signal can be maintained, which is useful for electronic devices such as data conversion circuits, wireless communication devices, audio equipment, and video equipment.
  • Analog filter unit 102 502, 602 Loop filter (analog filter) 101, 122, 152, 153, 501, 601 Subtractor 110, 503 Quantizer 120, 150, 160 Correction signal generator 121, 151, 161 LUT (table) 123, 154, 155, 163 Variable gain 124, 156, 157, 164 delay element 125, 166 primary recursive filter (digital filter) 158 Second-order recursive filter (digital filter) 130, 504, 605 Digital-to-analog converter (DAC) 165 DEM address generator k coefficient (adjustment means) 200 Antenna 201 Receiving Unit 207 Transmitting Unit 208 Transmission / Reception Switching Unit 5000 Wireless Communication Device

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Abstract

L'invention porte sur un modulateur delta sigma qui comprend une boucle le long de laquelle un signal de sortie provenant d'un quantificateur est traité numériquement puis renvoyé à un filtre analogique par l'intermédiaire d'un convertisseur numérique-analogique (CNA). Dans le modulateur delta sigma, le quantificateur (110) quantifie un signal analogique provenant de la partie filtre analogique (100) en un signal numérique. Le signal numérique provenant du quantificateur (110) est traité numériquement par un circuit de filtre récursif du premier ordre (125) comprenant un gain variable (123) et un élément à retard (124). Une table de référence (LUT)(121) reçoit en tant qu'entrées le signal numérique provenant du quantificateur (110) et un signal de commande de table (S1200), qui est un signal de sortie du circuit de filtre récursif (125), afin de stocker une valeur de compensation en fonction de ces deux signaux à l'avance. La valeur de compensation provenant de la table de référence (121) est un signal de sortie numérique dans lequel le retard a été corrigé, tandis que ce signal de sortie numérique est converti par le CNA (130) en un signal analogique, qui est ensuite utilisé pour effectuer une soustraction à un signal d'entrée analogique dans la partie filtre analogique (100). Ainsi, l'influence d'un retard est réduite pour les signaux à large bande haut débit, ce par quoi la précision des signaux de sortie peut être améliorée.
PCT/JP2009/001714 2008-11-20 2009-04-14 Modulateur delta sigma et appareil de communication sans fil Ceased WO2010058492A1 (fr)

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US13/094,519 US20110200077A1 (en) 2008-11-20 2011-04-26 Delta-sigma modulator and wireless communication device

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