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WO2010058440A1 - Procédé d’initialisation de la mémoire et programme d’initialisation de la mémoire - Google Patents

Procédé d’initialisation de la mémoire et programme d’initialisation de la mémoire Download PDF

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Publication number
WO2010058440A1
WO2010058440A1 PCT/JP2008/003390 JP2008003390W WO2010058440A1 WO 2010058440 A1 WO2010058440 A1 WO 2010058440A1 JP 2008003390 W JP2008003390 W JP 2008003390W WO 2010058440 A1 WO2010058440 A1 WO 2010058440A1
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WO
WIPO (PCT)
Prior art keywords
area
kernel
initialization
storage device
main storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/003390
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English (en)
Japanese (ja)
Inventor
▲高▼井徹男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2008/003390 priority Critical patent/WO2010058440A1/fr
Priority to JP2010539051A priority patent/JP5158206B2/ja
Publication of WO2010058440A1 publication Critical patent/WO2010058440A1/fr
Priority to US13/095,396 priority patent/US8423757B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

Definitions

  • FIG. 2 is a diagram showing a conventional memory initialization process by hardware provided in a computer.
  • the computer 1 shown in FIG. 2 includes three CPUs 10 (10-1, 10-2, 10-3), a memory 20, a ROM 30 in which firmware 31 is stored, and an external storage device 40 in which an OS 41 is stored.
  • the computer 1 is a multiprocessor computer including three CPUs 10.
  • FIG. 2 conventionally, even in a computer 1 having a multiprocessor configuration, one CPU 10 executes firmware and performs memory initialization processing.
  • FIG. 4 is a diagram showing a problem when the page size is 4 MB. As shown in FIG. 4, when 1 MB of data is written on a 4 MB page 23, a 3 MB unused area is generated on the page 23. Such a decrease in page use efficiency becomes more prominent as the page size is increased.
  • Japanese Laid-Open Patent Publication No. 10-260819 Japanese Unexamined Patent Publication No. 2007-264978 Japanese Laid-Open Patent Publication No. 10-260819 Japanese Unexamined Patent Publication No. 2007-264978
  • An object of the present invention is to speed up the time required for memory initialization processing in a computer boot sequence.
  • the memory initialization method of the present invention is premised on a memory initialization method in a boot sequence of a computer having a plurality of CPUs.
  • the CPU includes a CPU core mounted on a one-chip CPU. That is, in the present invention, when expressed as a plurality of CPUs, this has the same meaning as a plurality of CPU cores.
  • the memory initialization is performed by executing the firmware stored in the first storage means by the first CPU, and the first area necessary for the operation of the firmware on the main storage device And a step of initializing a second area necessary for starting the kernel, and execution of the firmware by the first CPU, loading the kernel stored in the second storage means into the second area,
  • the step of starting and executing the kernel by the second CPU, the kernel executed by the second CPU, and the firmware executed by the first CPU are executed in parallel on the remaining memory on the main storage device. And executing a process including initialization of the area.
  • FIG. 5A is a flowchart showing the procedure of the boot sequence of this embodiment.
  • the same step numbers as in FIG. 1A are assigned to steps that perform the same processing as in FIG.
  • the boot sequence shown in FIG. 5A is based on the boot sequence of a computer having a plurality of CPUs or CPU cores.
  • CPU when it is described as CPU, it includes CPU core.
  • the memory initialization processing in the kernel initial setting in step S3 is shared by the firmware 131 and the kernel, and each is executed by separate CPUs, whereby the memory initialization is performed by parallel processing.
  • the boot sequence method of the present embodiment makes it possible to shorten the time required for kernel initial setting (boot processing).
  • FIG. 6 is a flowchart showing the flowchart of FIG. 5A in more detail.
  • the same step numbers are assigned to the same steps as those in FIG.
  • FIG. 7 is a diagram showing an initialization part of the main memory 20 at each step in step S13 of the flowchart of FIG.
  • the kernel initial setting (boot process) in step S13 first, memory initialization by the firmware 131 is executed (step S131a).
  • memory initialization an area on the main memory 20 necessary for the firmware 131 to operate (area 20a-1 in FIG. 7) and a minimum area necessary for kernel activation (area 20a-2 in FIG. 7) Is initialized. Then, the kernel is loaded in the area 20a-2.
  • step S131C kernel activation
  • step S131b memory initialization by the firmware 131
  • the activated kernel initializes the area after the area 20a of the main memory 20 (area 20b in FIG. 7) (step S132).
  • the firmware 131 initializes the remaining part of the area 20a (area 20a-3 in FIG. 7) (step S131b).
  • step S131c and step S132 and execution of step S131b are performed in parallel by separate CPUs mounted on the computer. Accordingly, a part of the region 20a-3 and the region 20b are initialized simultaneously by the parallel processing.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

Selon l’invention, dans un ordinateur comprenant une pluralité d’unités centrales ou une pluralité de cœurs de processeur, un traitement d’initialisation de la mémoire lors de sa séquence d’amorçage est réalisé par l’exécution parallèle d’un microprogramme et d’un noyau. À présent, le microprogramme et le noyau sont exécutés par des unités centrales ou par des cœurs de processeur séparés. Ceci permet de raccourcir le temps requis pour l’initialisation de la mémoire lors de la séquence d’amorçage de l’ordinateur.
PCT/JP2008/003390 2008-11-19 2008-11-19 Procédé d’initialisation de la mémoire et programme d’initialisation de la mémoire Ceased WO2010058440A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2008/003390 WO2010058440A1 (fr) 2008-11-19 2008-11-19 Procédé d’initialisation de la mémoire et programme d’initialisation de la mémoire
JP2010539051A JP5158206B2 (ja) 2008-11-19 2008-11-19 メモリ初期化方法、メモリ初期化プログラム
US13/095,396 US8423757B2 (en) 2008-11-19 2011-04-27 Memory initialization by performing parallel execution of firmware and kernel by different CPUs

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2008/003390 WO2010058440A1 (fr) 2008-11-19 2008-11-19 Procédé d’initialisation de la mémoire et programme d’initialisation de la mémoire

Related Child Applications (1)

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US13/095,396 Continuation US8423757B2 (en) 2008-11-19 2011-04-27 Memory initialization by performing parallel execution of firmware and kernel by different CPUs

Publications (1)

Publication Number Publication Date
WO2010058440A1 true WO2010058440A1 (fr) 2010-05-27

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PCT/JP2008/003390 Ceased WO2010058440A1 (fr) 2008-11-19 2008-11-19 Procédé d’initialisation de la mémoire et programme d’initialisation de la mémoire

Country Status (3)

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US (1) US8423757B2 (fr)
JP (1) JP5158206B2 (fr)
WO (1) WO2010058440A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012256117A (ja) * 2011-06-07 2012-12-27 Mitsubishi Electric Corp マルチプロセッサシステム
TWI464681B (zh) * 2010-08-17 2014-12-11 Wistron Corp 加速開機方法及系統
WO2017104168A1 (fr) * 2015-12-16 2017-06-22 三菱電機株式会社 Dispositif d'enregistrement-de lecture video et procédé d'activation
US10459645B2 (en) 2016-03-28 2019-10-29 Fujitsu Limited Information processing apparatus and method of controlling information processing apparatus
CN119759433A (zh) * 2024-12-10 2025-04-04 零束科技有限公司 一种引导加载程序的方法、装置、电子设备和存储介质

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5783809B2 (ja) * 2011-06-03 2015-09-24 キヤノン株式会社 情報処理装置、起動方法およびプログラム
US10346177B2 (en) * 2016-12-14 2019-07-09 Intel Corporation Boot process with parallel memory initialization
US11593487B2 (en) * 2021-06-14 2023-02-28 Dell Products, L.P. Custom baseboard management controller (BMC) firmware stack monitoring system and method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH086914A (ja) * 1994-06-17 1996-01-12 Toshiba Corp マルチプロセッサシステムにおける主記憶装置初期化方法
JPH09212431A (ja) * 1996-01-31 1997-08-15 Toshiba Corp 計算機装置
JPH11265289A (ja) * 1998-03-16 1999-09-28 Mitsubishi Electric Corp 情報処理装置および情報処理装置の高速初期起動方法
US6158000A (en) * 1998-09-18 2000-12-05 Compaq Computer Corporation Shared memory initialization method for system having multiple processor capability

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5826090A (en) 1997-03-17 1998-10-20 International Business Machines Corporation Loadable hardware support
US7065688B1 (en) * 2003-02-19 2006-06-20 Advanced Micro Devices, Inc. Simultaneous multiprocessor memory testing and initialization
US7194660B2 (en) * 2003-06-23 2007-03-20 Newisys, Inc. Multi-processing in a BIOS environment
JP5011780B2 (ja) 2006-03-28 2012-08-29 ブラザー工業株式会社 情報処理装置、及びその起動方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH086914A (ja) * 1994-06-17 1996-01-12 Toshiba Corp マルチプロセッサシステムにおける主記憶装置初期化方法
JPH09212431A (ja) * 1996-01-31 1997-08-15 Toshiba Corp 計算機装置
JPH11265289A (ja) * 1998-03-16 1999-09-28 Mitsubishi Electric Corp 情報処理装置および情報処理装置の高速初期起動方法
US6158000A (en) * 1998-09-18 2000-12-05 Compaq Computer Corporation Shared memory initialization method for system having multiple processor capability

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI464681B (zh) * 2010-08-17 2014-12-11 Wistron Corp 加速開機方法及系統
JP2012256117A (ja) * 2011-06-07 2012-12-27 Mitsubishi Electric Corp マルチプロセッサシステム
WO2017104168A1 (fr) * 2015-12-16 2017-06-22 三菱電機株式会社 Dispositif d'enregistrement-de lecture video et procédé d'activation
JPWO2017104168A1 (ja) * 2015-12-16 2018-04-12 三菱電機株式会社 映像記録再生装置及び起動方法
US10459645B2 (en) 2016-03-28 2019-10-29 Fujitsu Limited Information processing apparatus and method of controlling information processing apparatus
CN119759433A (zh) * 2024-12-10 2025-04-04 零束科技有限公司 一种引导加载程序的方法、装置、电子设备和存储介质

Also Published As

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JPWO2010058440A1 (ja) 2012-04-12
US20110213955A1 (en) 2011-09-01
JP5158206B2 (ja) 2013-03-06
US8423757B2 (en) 2013-04-16

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