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WO2010057065A3 - Method and apparatus to provide secure application execution - Google Patents

Method and apparatus to provide secure application execution Download PDF

Info

Publication number
WO2010057065A3
WO2010057065A3 PCT/US2009/064493 US2009064493W WO2010057065A3 WO 2010057065 A3 WO2010057065 A3 WO 2010057065A3 US 2009064493 W US2009064493 W US 2009064493W WO 2010057065 A3 WO2010057065 A3 WO 2010057065A3
Authority
WO
WIPO (PCT)
Prior art keywords
application execution
secure application
provide secure
application
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2009/064493
Other languages
French (fr)
Other versions
WO2010057065A2 (en
Inventor
Frank Mckeen
Uday Savagaonkar
Carlos V. Rozas
Michael A. Goldsmith
Howard C. Herbert
Asher Altman
Gary Graunke
David Durham
Simon P. Johnson
Michael E. Kounavis
Vincent R. Scarlata
Joseph Cihula
Stalinselvaraj Jeyasingh
Bernard Lint
Gil Neiger
Dion Rodgers
Ernie Brickell
Jianguo Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to JP2011536548A priority Critical patent/JP2012508938A/en
Publication of WO2010057065A2 publication Critical patent/WO2010057065A2/en
Publication of WO2010057065A3 publication Critical patent/WO2010057065A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/56—Computer malware detection or handling, e.g. anti-virus arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Health & Medical Sciences (AREA)
  • Virology (AREA)
  • Health & Medical Sciences (AREA)
  • Storage Device Security (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Retry When Errors Occur (AREA)

Abstract

A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
PCT/US2009/064493 2008-11-14 2009-11-14 Method and apparatus to provide secure application execution Ceased WO2010057065A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011536548A JP2012508938A (en) 2008-11-14 2009-11-14 Secure application execution method and apparatus

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US19931808P 2008-11-14 2008-11-14
US61/199,318 2008-11-14
US59076709A 2009-11-13 2009-11-13
US12/590,767 2009-11-13

Publications (2)

Publication Number Publication Date
WO2010057065A2 WO2010057065A2 (en) 2010-05-20
WO2010057065A3 true WO2010057065A3 (en) 2010-08-19

Family

ID=42170755

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/064493 Ceased WO2010057065A2 (en) 2008-11-14 2009-11-14 Method and apparatus to provide secure application execution

Country Status (2)

Country Link
JP (1) JP2012508938A (en)
WO (1) WO2010057065A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9448950B2 (en) 2013-12-24 2016-09-20 Intel Corporation Using authenticated manifests to enable external certification of multi-processor platforms
US9501668B2 (en) 2013-09-25 2016-11-22 Intel Corporation Secure video ouput path
US9705892B2 (en) 2014-06-27 2017-07-11 Intel Corporation Trusted time service for offline mode

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9087200B2 (en) 2009-12-22 2015-07-21 Intel Corporation Method and apparatus to provide secure application execution
US8181176B2 (en) * 2010-06-21 2012-05-15 Intel Corporation Uniform storage device access using partial virtual machine executing within a secure enclave session
EP2769502A4 (en) 2011-10-18 2015-07-08 Intel Corp Methods, systems and apparatus to facilitate client-based authentication
US9189411B2 (en) * 2012-12-28 2015-11-17 Intel Corporation Logging in secure enclaves
US9747102B2 (en) 2012-12-28 2017-08-29 Intel Corporation Memory management in secure enclaves
US9323686B2 (en) 2012-12-28 2016-04-26 Intel Corporation Paging in secure enclaves
US9177353B2 (en) 2013-03-15 2015-11-03 Intel Corporation Secure rendering of display surfaces
US9430384B2 (en) * 2013-03-31 2016-08-30 Intel Corporation Instructions and logic to provide advanced paging capabilities for secure enclave page caches
US9355262B2 (en) 2013-12-27 2016-05-31 Intel Corporation Modifying memory permissions in a secure processing environment
US9606940B2 (en) 2015-03-27 2017-03-28 Intel Corporation Methods and apparatus to utilize a trusted loader in a trusted computing environment
US10552344B2 (en) 2017-12-26 2020-02-04 Intel Corporation Unblock instruction to reverse page block during paging

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5224166A (en) * 1992-08-11 1993-06-29 International Business Machines Corporation System for seamless processing of encrypted and non-encrypted data and instructions
US20040143748A1 (en) * 2003-01-21 2004-07-22 Kabushiki Kaisha Toshiba Data access control method for tamper resistant microprocessor using cache memory
US20050100163A1 (en) * 2003-11-10 2005-05-12 Broadcom Corporation System and method for securing executable code
US20080072004A1 (en) * 2006-09-20 2008-03-20 Arm Limited Maintaining cache coherency for secure and non-secure data access requests

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4263976B2 (en) * 2003-09-24 2009-05-13 株式会社東芝 On-chip multi-core tamper resistant processor
JP4945200B2 (en) * 2006-08-29 2012-06-06 株式会社日立製作所 Computer system and processor control method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5224166A (en) * 1992-08-11 1993-06-29 International Business Machines Corporation System for seamless processing of encrypted and non-encrypted data and instructions
US20040143748A1 (en) * 2003-01-21 2004-07-22 Kabushiki Kaisha Toshiba Data access control method for tamper resistant microprocessor using cache memory
US20050100163A1 (en) * 2003-11-10 2005-05-12 Broadcom Corporation System and method for securing executable code
US20080072004A1 (en) * 2006-09-20 2008-03-20 Arm Limited Maintaining cache coherency for secure and non-secure data access requests

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9501668B2 (en) 2013-09-25 2016-11-22 Intel Corporation Secure video ouput path
US9448950B2 (en) 2013-12-24 2016-09-20 Intel Corporation Using authenticated manifests to enable external certification of multi-processor platforms
US9705892B2 (en) 2014-06-27 2017-07-11 Intel Corporation Trusted time service for offline mode

Also Published As

Publication number Publication date
WO2010057065A2 (en) 2010-05-20
JP2012508938A (en) 2012-04-12

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