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WO2010049087A3 - A semiconductor device including a reduced stress configuration for metal pillars - Google Patents

A semiconductor device including a reduced stress configuration for metal pillars Download PDF

Info

Publication number
WO2010049087A3
WO2010049087A3 PCT/EP2009/007549 EP2009007549W WO2010049087A3 WO 2010049087 A3 WO2010049087 A3 WO 2010049087A3 EP 2009007549 W EP2009007549 W EP 2009007549W WO 2010049087 A3 WO2010049087 A3 WO 2010049087A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
metal pillars
device including
reduced stress
stress configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2009/007549
Other languages
French (fr)
Other versions
WO2010049087A2 (en
WO2010049087A8 (en
Inventor
Alexander Platz
Frank Küchenmeister
Matthias Lehr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102008054054A external-priority patent/DE102008054054A1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to JP2011533584A priority Critical patent/JP2012507163A/en
Priority to CN2009801437874A priority patent/CN102239555A/en
Publication of WO2010049087A2 publication Critical patent/WO2010049087A2/en
Publication of WO2010049087A3 publication Critical patent/WO2010049087A3/en
Anticipated expiration legal-status Critical
Publication of WO2010049087A8 publication Critical patent/WO2010049087A8/en
Ceased legal-status Critical Current

Links

Classifications

    • H10W72/20—
    • H10W42/121—
    • H10W72/019—
    • H10W74/137—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H10W72/012—
    • H10W72/01255—
    • H10W72/221—
    • H10W72/242—
    • H10W72/283—
    • H10W72/29—
    • H10W72/90—
    • H10W72/923—
    • H10W72/9232—
    • H10W72/934—
    • H10W72/9415—
    • H10W74/147—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In a metallization system of a sophisticated semiconductor device, metal pillars 271 may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer 260 that is in tight mechanical contact with the metal pillar, for example by providing an additional stress distribution element 272 in contact with the pillar 271 and the final passivation layer 260.
PCT/EP2009/007549 2008-10-31 2009-10-21 A semiconductor device including a reduced stress configuration for metal pillars Ceased WO2010049087A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011533584A JP2012507163A (en) 2008-10-31 2009-10-21 Semiconductor device including reduced stress structure for metal pillars
CN2009801437874A CN102239555A (en) 2008-10-31 2009-10-21 A semiconductor device including a reduced stress configuration for metal pillars

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008054054.4 2008-10-31
DE102008054054A DE102008054054A1 (en) 2008-10-31 2008-10-31 Semiconductor device having a structure for reduced strain of metal columns
US12/575,618 2009-10-08
US12/575,618 US8039958B2 (en) 2008-10-31 2009-10-08 Semiconductor device including a reduced stress configuration for metal pillars
DE12/575,618 2009-10-08

Publications (3)

Publication Number Publication Date
WO2010049087A2 WO2010049087A2 (en) 2010-05-06
WO2010049087A3 true WO2010049087A3 (en) 2010-06-24
WO2010049087A8 WO2010049087A8 (en) 2011-07-07

Family

ID=41559023

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2009/007549 Ceased WO2010049087A2 (en) 2008-10-31 2009-10-21 A semiconductor device including a reduced stress configuration for metal pillars

Country Status (1)

Country Link
WO (1) WO2010049087A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8729699B2 (en) 2011-10-18 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connector structures of integrated circuits
US20130341785A1 (en) * 2012-06-22 2013-12-26 Lei Fu Semiconductor chip with expansive underbump metallization structures
US10756040B2 (en) * 2017-02-13 2020-08-25 Mediatek Inc. Semiconductor package with rigid under bump metallurgy (UBM) stack
US12261141B2 (en) * 2020-06-02 2025-03-25 Texas Instruments Incorporated IC device with chip to package interconnects from a copper metal interconnect level

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030025202A1 (en) * 2001-07-17 2003-02-06 Nec Corporation Semiconductor device having an external electrode
US20040175914A1 (en) * 2003-03-06 2004-09-09 Yoshinori Shizuno Semiconductor device fabrication method
US20050230782A1 (en) * 2004-03-17 2005-10-20 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US20080169562A1 (en) * 2006-12-28 2008-07-17 Siliconware Precision Industries Co., Ltd. Semiconductor device having conductive bumps and fabrication method thereof
US20080197490A1 (en) * 2007-02-16 2008-08-21 Chipmos Technologies Inc. Conductive structure for a semiconductor integrated circuit and method for forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030025202A1 (en) * 2001-07-17 2003-02-06 Nec Corporation Semiconductor device having an external electrode
US20040175914A1 (en) * 2003-03-06 2004-09-09 Yoshinori Shizuno Semiconductor device fabrication method
US20050230782A1 (en) * 2004-03-17 2005-10-20 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US20080169562A1 (en) * 2006-12-28 2008-07-17 Siliconware Precision Industries Co., Ltd. Semiconductor device having conductive bumps and fabrication method thereof
US20080197490A1 (en) * 2007-02-16 2008-08-21 Chipmos Technologies Inc. Conductive structure for a semiconductor integrated circuit and method for forming the same

Also Published As

Publication number Publication date
WO2010049087A2 (en) 2010-05-06
WO2010049087A8 (en) 2011-07-07

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