WO2010047228A1 - Wiring board and method for manufacturing same - Google Patents

Abstract

Provided is a wiring board which has: a substrate; a first structural layer which includes first insulating layers, first wiring and first external terminals and is arranged on one side of the substrate; and a second structural layer which includes second insulating layers, second wiring and second external terminals, and is arranged on the other side of the substrate.  At least the number or arrangement of the first external terminals on the said side of the substrate is different from the number or arrangement of the second external terminals on the other side.

Description

Wiring board and manufacturing method thereof

The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board having a wiring structure on both sides of the board.

In recent years, with the rapid demand for miniaturization and thinning of electronic devices, there has been a demand for thinning and high density especially in semiconductor devices. In addition, with the demand for higher performance of electronic devices, it has become necessary to increase the number of terminals in semiconductor elements as the speed and functionality of semiconductor elements increase.

Conventionally, WLP (Wafer Level Package) technology has been used to reduce the thickness and increase the density of semiconductor devices. However, since the WLP technique provides a wiring layer only on one side of a semiconductor device, it has become difficult to reduce the thickness, increase the density, and increase the number of terminals because of cost and warpage.

In response to this situation, technologies using both sides of the semiconductor device are being studied. Furthermore, a technique related to a three-dimensional LSI in which semiconductor devices are stacked has been studied.

Japanese Patent Laid-Open No. 2004-274035 (Patent Document 1) has a structure in which an electronic component such as a transistor or a capacitor is embedded in an insulating layer between a pair of wiring boards, and vias for connecting wirings between the boards are provided. An electronic component built-in module is disclosed.

Japanese Unexamined Patent Application Publication No. 2007-096030 (Patent Document 2) and Japanese Unexamined Patent Application Publication No. 2008-103387 (Patent Document 3) disclose semiconductor devices based on CSP (Chip Size Package) technology.

A semiconductor device described in Patent Document 2 includes an electronic circuit formed on a substrate surface, a pad electrode connected to the electronic circuit and formed on the substrate surface, a via hole penetrating the semiconductor substrate, and the pad electrode through the via hole. And a wiring layer on the back surface of the substrate connected to the substrate, and ball-like conductive terminals are provided on the back surface of the substrate so as to be electrically connected to the wiring layer. These via holes, pad electrodes, and wiring layers are arranged outside the formation area of the electronic circuit on the substrate plane.

The semiconductor device described in Patent Document 3 includes a circuit unit formed on a substrate surface, a surface wiring connected to the circuit unit and formed on the substrate surface, a via hole penetrating the semiconductor substrate, and the surface wiring through the via hole. And external connection bumps are provided on the back surface of the substrate so as to be electrically connected to the back surface wiring. These via holes and backside wiring are arranged outside the circuit portion formation region on the substrate plane.

Japanese Patent Application Laid-Open No. 2007-059826 (Patent Document 4) discloses a semiconductor integrated circuit device in which a plurality of semiconductor layers on which an integrated circuit is formed are stacked on a substrate for the purpose of reducing resistance and increasing integration of through wiring. It is disclosed. In this semiconductor integrated circuit device, a bump connected to the through wiring is provided on the surface of the upper semiconductor layer opposite to the surface on which the integrated circuit is formed. In addition, the upper semiconductor layer and the lower semiconductor layer are stacked such that the bumps on the lower surface side of the upper semiconductor layer and the bumps on the upper surface side of the lower semiconductor layer overlap.

However, the techniques described in the above patent documents have the following problems.

In the technique described in Patent Document 1, the connection points between the embedded electronic component and the wiring board are made finer and higher in density than the technique of directly forming the wiring layer on the wafer on which the semiconductor element is formed. It is difficult and the function of the semiconductor element included in the electronic component is limited. Moreover, since the difference in thermal expansion coefficient between the electronic component and the material used for the wiring board is large, the direction and amount of warpage differ between the portion where the electronic component is embedded and the portion where it is not embedded due to the thinning. Warping occurs.

In the techniques described in Patent Documents 2 and 3, since there is a difference in thickness or formation of an insulating layer or a protective layer between the front side and the back side of the semiconductor device, there is a gap between the front side and the back side of the semiconductor device. Therefore, stress is biased and warping occurs. In particular, when a semiconductor substrate is thinned in order to achieve a reduction in thickness, warping due to stress bias increases. Further, if the support is provided on one side for the purpose of warpage correction and surface protection, the effective wiring accommodation rate is lowered.

In Patent Document 4, since the bump positions for connecting to other semiconductor layers are the same between the semiconductor layers, the degree of freedom in design when stacking a plurality of semiconductor layers is low. In particular, when trying to stack semiconductor layers having different sizes, the stacking order is fixed, or the circuit layout inside each semiconductor layer is restricted. Furthermore, in each semiconductor layer, since the wiring layer that forms the circuit is formed only on one side of the substrate, stress is biased between the front side and the back side of the semiconductor layer, and warping occurs. In particular, when a semiconductor substrate is thinned in order to achieve a reduction in thickness, warping due to stress bias is further increased.

An object of the present invention is to solve the above-described problems, and is to provide a high-density wiring board with a high degree of freedom in connection with other electronic components.

According to the present invention, a core substrate;
A first structural layer including a first insulating layer, a first wiring, and a first external terminal, provided on one surface side of the core substrate;
Including a second insulating layer, a second wiring, and a second external terminal, and a second structural layer provided on the other surface side of the core substrate,
A wiring board is provided in which at least one of the number and arrangement of the first external terminals and the second external terminals is different between one surface side and the other surface side of the core substrate.

According to the invention, there is provided an element circuit structure including an element on the core substrate and including a wiring and an interlayer insulating film electrically connected to the element between the core substrate and the first structure layer. A wiring board as described above is provided having a layer.

According to the invention, the first structural layer has a multilayer wiring structure in which the first insulating layer and the first wiring are alternately provided, and the second structural layer includes the second insulating layer and the second insulating layer. Any one of the above wiring boards having a multilayer wiring structure in which the second wirings are alternately provided is provided.

Further, according to the present invention, there is provided any of the above wiring boards having a through via that penetrates the core substrate and electrically connects the first wiring and the second wiring.

Further, according to the present invention, there is provided any of the above wiring boards comprising at least one of an electronic component connected to the first external terminal and an electronic component connected to the second external terminal.

Also, according to the present invention, any one of the above, comprising: an electronic component connected to the first external terminal; and another electronic component connected to the second external terminal and having a different external size from the electronic component. A wiring board is provided.

According to the invention, a plurality of electronic components connected to the first external terminal or the second external terminal are provided on one surface side of the core substrate, and two or more of the electronic components include the wiring substrate. Any of the above wiring boards that are electrically connected to each other are provided.

According to the invention, the electronic component includes an electronic component core substrate, a first electronic component insulating layer, a first electronic component wiring, and a first electronic component external terminal, and one surface side of the electronic component core substrate. Including a first electronic component structure layer, a second electronic component insulating layer, a second electronic component wiring, and a second electronic component external terminal, and a second electronic component core board provided on the other surface side of the electronic component core substrate. Any one of the above wiring boards, which is another wiring board having an electronic component structure layer, is provided.

In addition, according to the present invention, there is provided any one of the above wiring boards, wherein the connection between the electronic component and the first external terminal or the second external terminal is via a solder material or a low melting point metal material. .

Further, according to the present invention, there is provided any one of the above wiring board arrangements in which the connection between the electronic component and the first external terminal or the second external terminal is made through a bonding wire.

Furthermore, according to the present invention, in the method for manufacturing a wiring board, the first structure layer is formed on one surface side of the core substrate, and the second structure layer is formed on the other surface side of the core substrate. A method for manufacturing a wiring board is provided.

According to the invention, in the formation of the first structure layer and the second structure layer, the formation of the first wiring is performed by simultaneously forming the first insulation layer and the second insulation layer in the same process. And a method of manufacturing the wiring board, wherein the formation of the second wiring is simultaneously performed in the same process.

According to the invention, in the formation of the first structural layer and the second structural layer, the formation of the first insulating layer and the first wiring, the formation of the second insulating layer, and the second wiring There is provided a method for manufacturing a wiring board as described above, which is alternately performed.

Further, according to the present invention, there is provided the above-described method for manufacturing a wiring substrate, wherein a through via penetrating the core substrate is formed in the course of forming the first structural layer.

According to the invention, the wiring board is manufactured as described above, wherein a through via penetrating the core substrate is formed between the step of forming the first structure layer and the step of forming the second structure layer. A method is provided.

In addition, according to the present invention, there is provided the above-described method for manufacturing a wiring board, wherein a through via penetrating the core substrate is formed in the course of forming the second structural layer after forming the first structural layer. Is done.

According to the present invention, a step of forming a wiring board according to any of the above methods,
Provided is a method for manufacturing a wiring board, including a step of connecting an electronic component to at least one of the first structural layer side and the second structural layer side of the wiring board via the first external terminal or the second external terminal. Is done.

According to the present invention, a step of forming a plurality of wiring boards according to any of the above methods,
There is provided a method of manufacturing a wiring board, including a step of connecting these wiring boards to each other through the first or second external terminals or the first and second external terminals.

Further, according to the present invention, there is provided the above-described method for manufacturing a wiring board, wherein the wiring board and the electronic component are connected using a solder material or a low melting point metal material.

Further, according to the present invention, there is provided the method for manufacturing a wiring board as described above, wherein the wiring boards are connected using a solder material or a low melting point metal material.

Further, according to the present invention, there is provided the above-described method for manufacturing a wiring board, wherein the wiring board and the electronic component are connected by wire bonding.

Further, according to the present invention, there is provided the above-described method for manufacturing a wiring board, wherein the wiring boards are connected by wire bonding.

According to the present invention, it is possible to provide a high-density wiring board with a high degree of freedom in connection with other electronic components.

It is a perspective view which shows an example of the wiring board by 1st Embodiment of this invention. It is a fragmentary sectional view of the wiring board shown in FIG. It is a fragmentary sectional view which shows the element circuit structure layer of the wiring board shown in FIG. It is a fragmentary sectional view which shows the other example of the wiring board by 1st Embodiment of this invention. It is a fragmentary sectional view which shows the structural example of the electrode part (terminal) of the wiring board by 1st Embodiment of this invention. It is a fragmentary sectional view showing an example of a wiring board by a 2nd embodiment of the present invention. It is a fragmentary sectional view which shows the other example of the wiring board by 2nd Embodiment of this invention. It is a fragmentary sectional view showing an example of a wiring board by a 3rd embodiment of the present invention. It is a fragmentary sectional view which shows the other example of the wiring board by 3rd Embodiment of this invention. It is a fragmentary sectional view which shows the other example of the half wiring board by 3rd Embodiment of this invention. It is sectional drawing which shows the laminated structure example of the wiring board by 4th Embodiment of this invention. It is a fragmentary sectional view for explaining a manufacturing method of a wiring board by one embodiment of the present invention. FIG. 13 is a diagram for further explaining the manufacturing method described with reference to FIG. 12. It is a fragmentary sectional view for explaining a manufacturing method of a wiring board by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a wiring board by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a wiring board by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a wiring board by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a wiring board by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a wiring board by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a wiring board by other embodiments of the present invention.

A wiring substrate according to an embodiment of the present invention includes a core substrate, a first insulating layer, a first wiring, and a first external terminal, a first structure layer provided on one surface side of the core substrate, A second structure layer provided on the other surface side of the core substrate including two insulating layers, a second wiring, and a second external terminal. In this wiring board, the number of first external terminals is different from the number of second external terminals, or the arrangement of first external terminals (layout in the board plane) is different from the arrangement of second external terminals. Both the number and arrangement of the first external terminals and the second external terminals may be different between the one surface side and the other surface side of the wiring board.

The above wiring board may be provided with an element such as an active element or a passive element. In that case, an element circuit structure layer including a wiring electrically connected to this element and an interlayer insulating layer is provided. The first structure layer is provided on the element circuit structure layer. The element circuit structure layer has a structure in which a plurality of wirings are stacked via an interlayer insulating film, and is provided with vias that connect the wirings on the upper layer side and the lower layer side. A semiconductor substrate provided with elements is used as the core substrate, and a wiring board provided with an element circuit structure layer on the semiconductor substrate is appropriately referred to as a “semiconductor device”.

The first structure layer has a via for connecting the upper layer side wiring and the lower layer side wiring when a plurality of the first wirings are stacked via the interlayer insulating film. When a plurality of second wirings are stacked via an interlayer insulating film, the second structure layer has a via for connecting the upper layer side wiring and the lower layer side wiring. Wirings and vias in the first structural layer are collectively referred to as “first wiring” and “first via”, respectively, and wirings and vias in the second structural layer are collectively referred to as “second wiring” and “second via”, respectively. To do.

Since such a wiring board has the first structure layer and the second structure layer, the degree of freedom in connection with the electronic component can be increased.

In addition, it is possible to increase the wiring accommodation rate and to mount electronic components such as other wiring boards and chip parts on both sides of the board with high density.

Moreover, since a plurality of electronic components can be connected with a short wiring length via this wiring board, the electrical characteristics can be improved.

In addition, the action of the insulating layer included in the first structure layer and the second structure layer can disperse the force at the time of impact, can prevent chipping and cracking of the core substrate, and improve impact resistance. Can do. Furthermore, the stress generated when the wiring board is connected to the mounting board or another component can be more sufficiently relaxed, and the connection reliability can be improved.

Further, by providing the first structure layer and the second structure layer, the stress on one side of the core substrate and the stress on the opposite side can be made uniform, and even when the core substrate is thin The amount of warpage can be suppressed. That is, the stress generated on both sides of the core substrate can be offset, a wiring substrate with less warpage can be realized, and a thinner wiring substrate can be provided. From such a viewpoint, when the element circuit structure layer is provided, the first structure layer and the second structure layer are preferably sufficiently thicker than the element circuit structure layer, and the thickness of the first structure layer and the second structure layer is The thicker the film, the smaller the influence of the stress caused by the element circuit structure layer, and the more uniform the stress between the first structure layer and the second structure layer without being greatly affected by the structure of the element circuit structure layer. Can be achieved.

By making both or one of the wiring layer and the insulating layer between the first structure layer and the second structure layer the same number, the effect of reducing the warpage can be further enhanced.

From the viewpoint of obtaining the above-mentioned effect more sufficiently, the thickness of the first structure layer and the second structure layer is preferably at least twice the thickness of the element circuit structure layer, more preferably at least three times. The ratio (T1 / T2) between the thickness T1 of the first wiring layer and the thickness T2 of the second structure layer is preferably in the range of 0.7 to 1.3, and in the range of 0.8 to 1.2. It is more preferable. At that time, the thickness of the wiring of the element circuit structure layer is preferably 0.1 to 1.6 μm, more preferably 0.2 to 1.2 μm, and the thickness of the first wiring and the second wiring is preferably 3 to 12 μm. 5 to 10 μm is more preferable. The thickness of the insulating layer of the element circuit structure layer is preferably 0.1 to 1.6 μm, more preferably 0.2 to 1.2 μm, and the thickness of the first insulating layer and the second insulating layer is preferably 5 to 50 μm. 10 to 30 μm is more preferable.

In the above-described embodiment, the element circuit structure layer corresponds to the layer from the insulating layer in contact with the substrate to the layer including the uppermost layer wiring, and the first structure layer is in contact with the uppermost layer wiring of the element circuit structure layer. It corresponds to a layer (insulating layer or wiring) to an insulating layer in contact with the uppermost wiring of the first structural layer, and the second structural layer is from a layer (insulating layer or wiring) in contact with the opposite surface of the substrate. This corresponds to the insulating layer in contact with the uppermost wiring of the second structural layer.

Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

First Embodiment First, a first embodiment of the present invention will be described.

FIG. 1 is a perspective view showing a wiring board according to a first embodiment of the present invention. FIG. 1A shows the first structure layer 14 side on which a first external terminal 18 is provided, and FIG. ) Shows the second structure layer 19 side on which the second external terminals 23 are provided. FIG. 2 is a partial sectional view showing a part of the wiring board, and FIG. 3 is an enlarged sectional view of the element circuit structure layer 13 of the wiring board shown in FIG.

As shown in FIG. 1, the wiring substrate (semiconductor device) 11 of the present embodiment is provided with a first structure layer 14 on one surface side of a semiconductor substrate (core substrate) 12 and a second structure on the other surface side. A layer 19 is provided. As shown in FIG. 2, the element circuit structure layer 13 is provided on one surface of the semiconductor substrate 12, and the first structure layer is directly provided thereon. As shown in FIG. 3, an element 30 is provided on the semiconductor substrate 12. The element circuit structure layer 13 can be provided when an element such as an active element or a passive element, which will be described later, is installed, or according to the connection of the entire wiring board. The semiconductor substrate 12 is formed of, for example, Si, germanium, gallium arsenide (GaAs), gallium arsenide phosphorus, gallium nitride (GaN), silicon carbide (SiC), II-VI group compound, III-V group compound, diamond, or the like. Yes. You may use the board | substrate with which the semiconductor layer which consists of these semiconductor materials was provided on the support substrate which consists of sapphire, glass, etc. When the element and the element circuit structure layer are not provided, the core substrate is not limited to the semiconductor substrate, and a support substrate according to desired characteristics can be used.

As shown in FIG. 2, the first structure layer 14 includes first wirings 15, first insulating layers 16, and first vias 17, and the first wirings 15 and the first insulating layers 16 are alternately stacked. In this laminated structure, the first wiring on the upper layer side and the first wiring on the lower layer side are connected by a first via penetrating the first insulating layer between these wiring layers, and the first wiring on the lowermost layer side is connected to the lowermost layer side. The first insulating layer (the first insulating layer on the element circuit structure layer) is connected to the wiring layer 31 on the surface side of the first structure layer by a first via. The first structure layer is not limited to the structure shown in FIG. 2, and the first insulating layer 16 provided on the element circuit structure layer, and the first wiring 15 provided on the first insulating layer, The first via 17 that connects the first wiring and the wiring 31 on the surface side of the element circuit structure layer and the first external terminal 18 may be provided, and more than the number of layers shown in FIG. It may be laminated. The first external terminals 18 are provided on the surface of the first structural layer, and these are electrically connected to the first wiring 15.

As shown in FIG. 2, the second structure layer 19 is provided on the surface opposite to the surface on which the element circuit structure layer 13 of the semiconductor substrate 12 is provided, and the second wiring 20, the second insulating layer 21, and the second via 22. The second wiring 20 and the second insulating layer 21 are alternately stacked. In this laminated structure, the second wiring on the upper layer side and the second wiring on the lower layer side are connected by a second via penetrating the second insulating layer between these wiring layers. The second structural layer is not limited to the structure shown in FIG. 2, and the second insulating layer 21 provided on the semiconductor substrate, the second wiring 20 provided on the second insulating layer, It is only necessary to have at least two external terminals 23, and the number of layers may be greater than or equal to that shown in FIG. The second external terminals 23 are provided on the surface of the second structural layer, and these are electrically connected to the second wiring 20.

In the structure shown in FIG. 2, the first wiring 15 and the second wiring 20 have the same number of layers, and the first insulating layer 16 and the second insulating layer 21 have the same number of layers. The number of layers may be different. However, from the viewpoint of reducing the amount of warpage, either the number of stacked layers of the first wiring 15 and the second wiring 20 and the number of stacked layers of the first insulating layer 16 and the second insulating layer 21, or both are the same number of layers. It is desirable to be.

The first external terminal 18 and the second external terminal 23 are respectively configured by wiring on the surface layer side, and the position thereof may be changed according to the connection method, or provided directly on the first via 17 and the second via 22, respectively. May be.

The element circuit structure layer 13 is provided on the semiconductor substrate 12 on which a plurality of semiconductor elements 30 are formed, as shown in FIG. In the present embodiment, a MOS transistor (Metal Oxide Semiconductor: metal oxide semiconductor) is provided as the semiconductor element 30. This MOS transistor includes a source region 25 and a drain region 26 provided on the surface of the semiconductor substrate 12, and a gate electrode 24 provided on a region sandwiched between these regions via a gate insulating film (not shown). It is configured. Instead of such a planar MOS transistor, a vertical transistor having a three-dimensional structure, a Fin-type FET, or a transistor using an organic material may be used.

An interlayer insulating film 29 is provided on the semiconductor substrate 12 so as to cover these semiconductor elements 30, and wirings 31 are provided on the interlayer insulating film 29. A space between the wirings 31 is filled with an insulating film 32, and a wiring layer 28 composed of the inter-wiring insulating film 32 and the wirings 31 is formed. Such a wiring layer 28 (wiring 31 and inter-wiring insulating film 32) and interlayer insulating film 29 are alternately laminated to form a multilayer wiring structure. The lowermost wiring 31 is electrically connected to the source region 25 or the drain region 26 through a plug 27 formed in the lowermost interlayer insulating film 29. The upper layer side wiring 31 and the lower layer side wiring 31 in this multilayer wiring structure are electrically connected through a via 33 formed in the interlayer insulating film 29 between these wirings.

Examples of the wiring material for the element circuit structure layer 13 include copper and aluminum. The wiring of the element circuit structure layer can be formed by, for example, a damascene method. The formation of wiring by the damascene method can be performed as follows, for example. First, an insulating film is formed, and a groove (trench) corresponding to a desired wiring pattern or a hole corresponding to a via pattern is formed in the insulating film using a lithography technique and a dry etching technique. Next, a barrier metal layer is formed on the entire surface including the inside of the groove or hole by a sputtering method, a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, etc., and a power supply layer for electrolytic plating is formed by a sputtering method, Then, a copper film is formed so as to fill the groove or hole by electrolytic copper plating. Next, the copper film is polished by CMP (Chemical Mechanical Polishing) so that copper remains only in the groove or hole.

The thickness of the interlayer insulating film 29 in the element circuit structure layer 13 can be set in the range of 0.2 to 2 μm, for example, 0.2 to 1.6 μm. Of the plurality of interlayer insulating films 29, at least one interlayer insulating film 29 provided near the semiconductor substrate 12 is preferably formed of a low-k material. An example of the low-k material is a porous silicon oxide film, and it is desirable that the elastic modulus at 25 ° C. is in the range of 4 to 10 GPa.

Passive elements such as capacitors, inductors and resistors can be formed by thin film technology. The passive element is connected to another conductive part via the wiring 31 and the first via 33. The passive element may be provided inside the first structure layer 14 or the second structure layer 19. By forming an active element, a function as a semiconductor device can be given, and by forming a passive element, functions such as decoupling, noise reduction, an antenna, and a shield can be given. One of the active element and the passive element may be provided, or both may be provided.

The first wiring 15 of the first structure layer 14 and the second wiring 20 of the second structure layer 19 can be formed using, for example, copper, and the thickness thereof is, for example, 5 μm. The first wiring 15 and the second wiring 20 can be formed by a wiring forming method different from the wiring of the element circuit structure layer 13 such as a subtractive method, a semi-additive method, and a full additive method. In the subtractive method, for example, as described in JP-A-10-51105, a copper foil provided on a substrate or a resin is etched using a resist having a desired pattern as a mask, and then the resist is removed. In this method, a desired wiring pattern is obtained by removal. For example, as described in Japanese Patent Laid-Open No. 9-64493, the semi-additive method is a resist in which a power supply layer is formed by electroless plating, sputtering, CVD, aerosol, or the like, and then opened in a desired pattern. Is formed, electrolytic plating is deposited in the resist opening, and after removing the resist, the power feeding layer is etched to obtain a desired wiring pattern. In the full additive method, as described in, for example, JP-A-6-334334, a resist having a desired pattern is formed after an electroless plating catalyst is adsorbed on the surface of a substrate or resin, and this resist is formed on an insulating layer. In this method, the catalyst is activated as it is, and a desired wiring pattern is obtained by depositing metal in the opening of the insulating layer by electroless plating.

The first wiring 15 and the first external terminal 18 of the first structural layer 14 and the second wiring 20 and the second external terminal 23 of the second structural layer 19 are respectively connected to the semiconductor substrate 12 side via an adhesive layer. It may be provided on the insulating layer 16 and the second insulating layer 21. The adhesion layer may be any material that has adhesion to the material of the first insulating layer 16 or the second insulating layer 21, such as titanium, tungsten, nickel, tantalum, vanadium, chromium, molybdenum, copper, aluminum, and the like. Among them, titanium, tungsten, tantalum, chromium, molybdenum, and alloys thereof are preferable, and titanium, tungsten, and alloys thereof are more preferable. The surface of the first insulating layer 16 or the second insulating layer 21 may be a roughened surface having fine irregularities, and in this case, good adhesion can be easily obtained even with copper or aluminum. Further, as a means for improving the adhesion, it is desirable to form a wiring material by sputtering.

The first wiring 15 of the first structure layer 14 is thicker than the wiring layer 28 of the element circuit structure layer 13, that is, thicker than the wiring 31. The thickness of the first wiring 15 is, for example, 3 to 12 μm, and preferably 5 to 10 μm. If the first wiring is too thin, the wiring resistance increases and the electrical characteristics of the power supply circuit of the semiconductor device deteriorate. If the first wiring is too thick, the surface of the insulating layer that covers the wiring layer is likely to generate large undulations reflecting the irregularities of the wiring layer, limiting the number of layers, and increasing the thickness of the first structure layer 14 itself. However, warpage of the entire wiring board becomes large, and manufacturing becomes difficult due to process restrictions.

The second wiring 20 of the second structure layer 19 is thicker than the wiring layer 28 of the element circuit structure layer 13, that is, thicker than the wiring 31. The thickness of the second wiring 20 is 3 to 12 μm, for example, and preferably 5 to 10 μm. If the second wiring is too thin, the wiring resistance increases and the electrical characteristics of the power supply circuit of the semiconductor device are degraded. If the second wiring is too thick, the surface of the insulating layer that covers the wiring layer is likely to generate large undulations reflecting the irregularities of the wiring layer, limiting the number of layers, and increasing the thickness of the second structure layer 19 itself. However, warpage of the entire wiring board becomes large, and manufacturing becomes difficult due to process restrictions.

The first insulating layer 16 of the first structural layer 14 and the second insulating layer 21 of the second structural layer 19 are made of, for example, an organic material. Examples of the organic material include epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), and polynorbornene resin. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. As the organic material, either a photosensitive material or a non-photosensitive material may be used. When a photosensitive organic material is used, the opening to be the first via 17 or the second via 22 can be formed by a photolithography method. When a non-photosensitive organic material or an organic material that is photosensitive but has low pattern resolution, the opening can be formed by a laser method, a dry etching method, a blast method, or the like.

By using an organic material for the first insulating layer 16 and the second insulating layer 21, when the wiring board is mounted on the mounting board, the stress applied to the wiring board from the first external terminal 18 and the second external terminal 23 is mainly reduced. Further, the stress propagation to the element circuit structure layer 13 can be effectively reduced by relaxing the first insulating layer 16 and the second insulating layer 21 by deformation. The elastic modulus at 25 ° C. of the material of the first insulating layer 16 and the second insulating layer 21 is preferably in the range of 0.15 to 8 GPa, for example. If the elastic modulus of the insulating material is too low, the amount of deformation of the first insulating layer 16 and the second insulating layer 21 during stress relaxation is large, and most of the stress is applied to the first wiring 15 and the second wiring 20. The disconnection of the first wiring 15 and the second wiring 20 and the breakdown at the first wiring 15 / first via 17 interface and the second wiring layer 20 / second via 22 interface are likely to occur. If the elastic modulus of the insulating material is too high, the amount of deformation of the first insulating layer 16 and the second insulating layer 21 becomes insufficient, and the stress relaxation in the first structure layer 14 and the second structure layer 19 becomes insufficient, and the element circuit structure layer In FIG. 13, delamination, insulation film breakdown, etc. are likely to occur. By using a combination of insulating materials in which the elastic modulus of the first insulating layer 16 and the second insulating layer 21 is lower than the elastic modulus of the interlayer insulating film 29 of the element circuit structure layer 13, the first insulating layer 16 and the second insulating layer are combined. The layer 21 can relieve stress more effectively, and can enhance the protection effect of the element circuit structure layer 13.

In FIG. 2, the first structure layer 14 is electrically connected to the element circuit structure layer 13 through the first via 17, and the second structure layer 19 has the second insulating layer 21 in contact with the semiconductor substrate 12. However, as shown in FIG. 4, the first structure layer 14 may be electrically connected to the element circuit structure layer 13 through the first wiring 15, and the second structure layer 19 Two wirings 20 may be provided on the semiconductor substrate 12. When the second wiring 20 of the second structure layer 19 is provided on the semiconductor substrate 12, it is desirable that the surface of the semiconductor substrate 12 be insulative.

The first external terminal 18 of the first structure layer may have the structure shown in FIGS. In FIG. 5A, when connecting using a solder material, the first external terminal 18 is exposed by the first insulating layer 16 on the surface side so that the solder is supplied only to the first external terminal 18. The opening is restricted. Due to the restriction by the first insulating layer 16, the amount of solder flow is restricted, so that the mounting height when the wiring board is connected to the mounting board or another component can be stabilized. 5A shows a structure in which the first insulating layer 16 covers the periphery of the first external terminal 18, but a structure that is not covered by the first insulating layer 16 may be used. In the structure shown in FIG. 5B, when connecting using wire bonding, the connection to the terminal portion can be made favorable. In the structure shown in FIG. 5C, the lower portion of the external terminal is provided in the opening of the first insulating layer 16 on the surface side. According to this structure, when the connection with the solder material is performed at a narrow pitch, Connection reliability can be improved.

The first external terminal 18 is made of, for example, a laminated body, and on the surface of the first external terminal 18 in consideration of wettability of solder balls formed on the surface of the first external terminal 18 and connectivity with the bonding wire, For example, a layer made of at least one metal or alloy selected from the group consisting of copper, aluminum, gold, silver and solder materials is provided. The first external terminal 18 has a nickel layer and a gold layer laminated on a copper layer, for example, and the gold layer is a surface. The nickel layer has a thickness of 3 μm, for example, and the gold layer has a thickness of 1 μm, for example. .

The second external terminal 23 of the second structure layer 19 can have the same structure as the first external terminal 18 of the first structure layer 14. The first external terminal 18 and the second external terminal 23 may be appropriately selected from structures having a desired effect for connection, and need not have the same structure.

The first external terminals 18 and the second external terminals 23 are different from each other in the number and arrangement of external terminals so that these external terminals can be used effectively. In other words, when connecting to electronic components (including other wiring boards) of different external sizes or when sandwiched between a mounting board and another wiring board, the degree of freedom of connection can be increased and stable. Connection reliability can be ensured. Here, the external size refers to the size of the shape of the electronic component outline on the board plane (projection shape of the electronic part on the board plane). When the shape is rectangular, the length of each side, In the case of diameter and other shapes, it can be indicated by the length of the contour line.

In FIG. 2, three layers of the first wiring 15 and four layers of the first insulating layer 16 are shown, but the present invention is not limited to this, and the number of layers can be set as necessary. In FIG. 3, the eight wiring layers 28 and the eight interlayer insulating films 29 are shown, but the present invention is not limited to this, and the number of layers can be set as necessary.

The wiring 31, the first wiring 15, and the second wiring 20 are made of at least one metal or alloy selected from the group consisting of copper, aluminum, nickel, gold, and silver, for example. In particular, copper is preferable from the viewpoint of electrical resistance value and cost. Nickel can prevent an interfacial reaction with other materials such as an insulating material, can be used as a barrier film, has characteristics as a magnetic material, and can be used as an inductor or a resistance wiring.

The thickness of the first wiring 15 of the first structure layer 14 is larger than that of the wiring 31 of the element circuit structure layer 13, and therefore has a larger allowable current amount than the wiring 31. Further, the second wiring 20 of the second structure layer 19 has a larger allowable current amount than the wiring 31 because the thickness thereof is thicker than the wiring 31 of the element circuit structure layer 13. For this reason, in one or both of the first structure layer 14 and the second structure layer 19, a plurality of power supply wirings and ground wirings using the same voltage can be bundled to reduce the number of wirings. By combining these plural wirings, the number of the first external terminals 18 and the second external terminals 23 can be reduced as compared with the case where they are not combined. By reducing the number of the first external terminals 18 and the second external terminals 23, the size and interval (pitch) of the first external terminals 18 and the second external terminals 23 can be increased. The area is increased, and stable mounting and high connection reliability can be realized.

As described above, in the wiring board (semiconductor device) of the present embodiment, the first structural layer 14 and the second structural layer 19 are provided on both surfaces of the semiconductor substrate 12, so that the wiring accommodation rate can be increased. Furthermore, electronic components such as other wiring boards and chip parts can be mounted at high density on both sides of the board.

Also, the stress generated by the difference in thermal expansion between the semiconductor substrate 12 and the layer laminated thereon can be offset, and the amount of warpage can be suppressed even if the semiconductor substrate 12 is thinned. In particular, between the first structure layer 14 and the second structure layer 19, both or one or both of the wiring layers and the insulating layers have the same number, so that the effect of reducing the warpage can be further enhanced.

In addition, the action of each organic insulating layer included in the first structure layer 14 and the second structure layer 19 can soften the impact received by the wiring board, prevent chipping and cracks, and improve impact resistance. it can.

By making the thickness of the first wiring 15 of the first structural layer 14 and the second wiring 20 of the second structural layer 19 larger than the thickness of the wiring 31 of the element circuit structural layer 13, the first wiring 15 and the second wiring 20. Can be prevented, and the wiring resistance of the first wiring 15 and the second wiring 20 can be made smaller than that of the wiring 31. Further, as the thickness of the first wiring 15 and the second wiring 20 is increased, the thickness of each layer of the first insulating layer 16 and the second insulating layer 21 is increased, so that the effect of relaxing the stress is enhanced.

Further, when the first wiring 15 and the second wiring 20 are thick, a plurality of power supply systems and ground wirings using the same voltage are combined into one wiring in the first structure layer 14 and the second structure layer 19, respectively. be able to. In the wafer level CSP in which rewiring is performed on the surface of the semiconductor element, the wiring when provided in the semiconductor component is simply changed in the one-to-one relationship without reducing the number of connection terminals. is doing. In a semiconductor component having about 500 or more external terminals, particularly about 1500 or more, about 60 to 80% of the number of terminals is a power supply system and ground system terminal in order to maintain the performance of the device. By consolidating the power supply wiring and ground wiring, the number of first external terminals 18 of the first structure layer 14 is greatly reduced as compared with the number of electrical connection points formed on the surface of the element circuit structure layer 13. be able to. Furthermore, the number of second external terminals 23 can be reduced also in the second structure layer 19. For this reason, since the size and interval (pitch) of the first external terminals 18 and the second external terminals 23 can be increased, stable mounting properties and high connection reliability of the wiring board can be realized.

As described above, the first structure layer 14 and the second structure layer 19 are thin and less warped, and the propagation of stress and impact to the element circuit structure layer 13 is reduced, so that the connection reliability at the time of mounting is high. A high-density wiring board can be realized.

Second Embodiment Next, a second embodiment of the present invention will be described.

FIG. 6 is a partial cross-sectional view showing an example of a wiring board according to the second embodiment of the present invention. The wiring board according to the first embodiment is different in that a through via 34 is provided so as to penetrate the semiconductor substrate 12. Hereinafter, parts different from the wiring board according to the first embodiment will be described. Portions not specifically described are the same as those of the wiring board according to the first embodiment. The first external terminal 18 and the second external terminal 23 in FIG. 6 may have the structure shown in FIGS.

The through via 34 allows the element circuit structure layer 13 and the first structure layer 14 provided on one surface of the semiconductor substrate 12 and the second structure layer 19 provided on the other surface according to a required function. Connect them electrically. That is, either or both of the element circuit structure layer 13 and the first structure layer 15 are electrically connected to the second structure layer 19 through the through via 34.

The through via 34 can be formed as follows. First, a through hole is formed in the semiconductor substrate 12 by dry etching or wet etching. Next, an inorganic or organic insulating film is formed on the inner wall of the through hole by thermal oxidation, CVD, ALD, spin coating, lamination, printing, or the like. If necessary, the insulating film may be processed by a photolithography method, a laser method, dry etching, or wet etching. Next, a through via 34 is formed in the through hole by forming a conductor by CVD, sputtering, electrolytic plating, electroless plating, printing, vapor deposition, ink jet, or the like. As the material of the through via 34, at least one conductive material selected from the group consisting of copper, aluminum, tungsten, gold, silver, nickel, and impurity-containing polysilicon, or an alloy containing any one of metals can be used. . From the viewpoint of cost and electrical characteristics, copper or a copper alloy is preferable.

FIG. 7 is a partial cross-sectional view showing another example of the wiring board according to the second embodiment. In FIG. 7, the pitch of the through vias 34 is smaller than the pitch of the first external terminals 18 and the second external terminals 23. A plurality of through vias 34 are bundled by the first wiring 15 and the second wiring 20. This is because such a wiring structure is possible because the first wiring and the second wiring are sufficiently thick and the wiring resistance is small.

In the wiring board according to the second embodiment, in addition to the effects of the wiring board according to the first embodiment, the wiring structure layers provided on both sides of the board are electrically connected through the through vias. Furthermore, the degree of freedom in wiring design is further improved, and a higher density than that of the wiring board according to the first embodiment can be realized. In addition, since electronic components provided on one surface side and the other surface side of the substrate can be connected with a short distance, performance as a semiconductor device can be improved.

Third Embodiment Next, a third embodiment of the present invention will be described.

8 to 10 are partial sectional views showing specific examples of the wiring board according to the third embodiment of the present invention. In the third embodiment, the wiring board according to the first embodiment and the wiring board according to the second embodiment are laminated. 8 and 9, the wiring board according to the first embodiment is laminated on the wiring board according to the second embodiment, and in FIG. 10, two wiring boards according to the second embodiment are laminated. The laminated form of the wiring board is not limited to these. Further, the first external terminal 18 and the second external terminal 23 in FIGS. 8 to 10 may have a structure shown in FIGS. 5B and 5C. The wiring board according to the third embodiment will be described below. Portions not specifically described are the same as those of the wiring substrate according to the first embodiment or the second embodiment.

In the structure shown in FIG. 8, the wiring board shown in FIG. 2 is laminated on the wiring board shown in FIG. The first external terminal 18 of the wiring board shown in FIG. 6 and the second external terminal 23 of the wiring board shown in FIG. 2 are connected by the connecting portion 35 provided between the two wiring boards. Solder balls 36 are provided on the second external terminals 23 on the lower surface side. The connecting portion 35 can be formed of at least one material selected from the group consisting of low melting point metal materials such as solder material, tin, gold, silver, palladium, copper, and aluminum. In order to further improve the reliability of the connection portion 35, an underfill resin may be injected between the wiring boards to increase the strength.

The structure shown in FIG. 9 is connected to the first external terminal 18 of the wiring board shown in FIG. 6 and the first external terminal 18 of the wiring board shown in FIG. 2 in comparison with the structure shown in FIG. The point is different. In other words, the first structural layers of the two wiring boards are stacked so as to face each other. High-speed and high-speed data communication is possible between the facing wiring boards, and high performance can be realized.

In the structure shown in FIG. 10, two wiring boards shown in FIG. 6 are laminated, an electronic component 37 is provided on the upper surface side, and a solder ball 36 is provided on the lower surface side. The electronic component is electrically connected to the first external terminal 18 on the upper surface side via the connection portion 38. The solder ball 36 is directly connected to the second external terminal 23 on the lower surface side. Examples of the electronic component 37 include other wiring boards, chip capacitors, chip resistors, discretes, diodes, LEDs, sensors, MEMS, and optical components. The connecting portion 38 can be formed of at least one material selected from the group consisting of low melting point metal materials such as solder material, tin, gold, silver, palladium, copper, and aluminum. By providing other electronic components, the circuit operation can be stabilized and the function of the system can be improved.

8 to 10 show a structure in which two wiring boards are stacked, but the present invention is not limited to this, and three or more wiring boards may be stacked. Further, the structure having the solder ball 36 is shown in the lowermost layer of the stack, but the present invention is not limited to this, and pins, Au bumps, copper bumps, spare solder, metal pearls, ACF, NCF, etc. are used. A structure based on a connection method may be used.

In the wiring board according to the third embodiment, in addition to the effects of the wiring board according to the first embodiment and the wiring board according to the second embodiment, the footprint is expanded by stacking a plurality of wiring boards and electronic components. It is possible to realize a high-density system with a minimum of.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described.

FIG. 11 is a partial cross-sectional view showing a laminated structure example of a wiring board according to the fourth embodiment of the present invention. In the fourth embodiment, the wiring board 11 according to the first embodiment or the second embodiment and another wiring board 11c are laminated. In FIG. 11, these wiring boards 11 and 11c are illustrated in a simplified manner. The wiring board 11 does not need to provide an element and an element circuit structure layer on the core substrate, and can provide an element and an element circuit structure layer 13 on the core substrate as necessary. The direction of connection between the wiring board 11 and the wiring board 11c can be determined according to the function and performance. The wiring boards 11 and 11c may be equipped with electronic components. The wiring board according to the fourth embodiment will be described below. Portions not particularly described are the same as those of the wiring board according to the above-described embodiment.

FIG. 11A shows a structure in which a plurality of other wiring boards 11 c are connected to the lower surface side of the wiring board 11. In this structure, the wiring board 11 is provided so as to straddle the two wiring boards 11c, and the two wiring boards 11c are connected at a short distance. According to such a structure, high performance and high density as a semiconductor device can be realized. In FIG. 11A, a combination of two wiring boards 11c and one wiring board plate 11 is shown. However, the present invention is not limited to this combination. Good. The wiring board 11c may be the wiring board according to the above-described embodiment.

FIG. 11B shows a structure in which two wiring boards 11c having different outer sizes are laminated on the upper surface side and the lower surface side of the wiring board 11. FIG. According to the present invention, since the arrangement and number of the first external terminals 18 and the second external terminals 23 of the wiring board 11 can be set separately, the degree of freedom of the combination of the wiring boards can be increased in this way. it can. FIG. 11B shows a combination of two wiring boards 11c and one wiring board 11. However, the combination is not limited to this combination, and a combination of wiring boards as many as necessary may be used. . The wiring board 11c may be the wiring board according to the above-described embodiment.

FIG. 11 (c) shows a structure in which two wiring boards 11c having different outer sizes are laminated on the upper surface side and the lower surface side of the wiring board 11, and further solder balls 36 are provided on the lower surface side. According to the present invention, since the arrangement and number of the first external terminals 18 and the second external terminals 23 of the wiring board 11 can be set separately, not only the combination of the wiring boards but also the degree of freedom of the mounting method is increased. be able to. In FIG. 11C, a combination of two wiring boards 11c and one wiring board 11 is shown, but the present invention is not limited to this combination, and may be a combination of as many wiring boards as necessary. . The wiring board 11c may be the wiring board according to the above-described embodiment.

11A, 11B, and 11C show the case where the wiring boards are connected to each other and the wiring board is connected to the board using the solder balls 35 and 36. However, the present invention is not limited to this structure. The connection structure may be a connection method using pins, Au bumps, copper bumps, spare solder, metal pearls, ACF, NCF, or the like.

In the wiring board according to the fourth embodiment, in addition to the effects of the wiring board according to the above-described embodiment, a plurality of wiring boards and electronic components can be integrated at a high density, and the system can be multifunctional and have high performance. Can be realized.

In the first to fourth embodiments described above, a circuit noise filter or the like is provided at a desired position of the laminated circuit composed of the semiconductor substrate 12, the element circuit structure layer 13, the first structure layer 14, and the second structure layer 19. A capacitor that plays the role of decoupling may be provided. Examples of the dielectric material constituting the capacitor include metal oxides such as titanium oxide, tantalum oxide, Al ₂ O ₃ , SiO ₂ , ZrO ₂ , HfO ₂ , and Nb ₂ O ₅ ; BST (Ba _x Sr _1-x TiO _{3 ), PZT (PbZr x Ti 1} -x O 3), PLZT (Pb 1-y La y Zr x Ti 1-x O 3) perovskite such material (0 ≦ x ≦ 1,0 <y <1); And Bi-based layered compounds such as SrBi ₂ Ta ₂ O ₉ . Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.

In addition, the counter electrode is disposed at a desired position of one or more of the insulating layers in the first structure layer 14 and the second structure layer 19 on the upper and lower wiring layers via a dielectric having a dielectric constant of 9 or more. A capacitor that plays the role of a circuit noise filter or decoupling may be provided by forming. The dielectric material constituting the _{capacitor, Al 2 O 3, ZrO 2} , HfO 2, Nb metal oxides such as _{2 O 5; BST (Ba x} Sr 1-x TiO 3), PZT (PbZr x Ti 1- _x O ₃ ), perovskite materials such as PLZT (Pb _1-y La _y Zr _x Ti _1-x O ₃ ) (0 ≦ x ≦ 1, 0 <y <1); Bi such as SrBi ₂ Ta ₂ O ₉ System layered compounds are mentioned. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.

Hereinafter, an example of manufacturing a wiring board according to an embodiment of the present invention will be specifically described with reference to the drawings.

First Manufacturing Example First, a first manufacturing example will be described with reference to FIG. FIG. 12 is a partial cross-sectional view for explaining the present manufacturing example.

In each step described below, cleaning or heat treatment may be performed as appropriate. Further, the semiconductor substrate 12 may be ground to a thickness of less than 300 μm as necessary. When the thin semiconductor substrate 12 is used, a support member made of the same material or metal as that of the semiconductor substrate 12 may be used in order to improve handling properties.

First, as shown in FIG. 12A, as described in the first embodiment, elements and an element circuit structure layer 13 are formed on the semiconductor substrate 12. The wiring 31 in the element circuit structure layer 13 can be formed by the damascene method as described above, and the insulating layers 28 and 29 can be formed by, for example, the CVD method or the spin coating method.

Next, as shown in FIG. 12B, as described in the first embodiment, the first structure layer 14 is formed so as to be in direct contact with the element circuit structure layer 13. When the element circuit structure layer 13 is not provided, the first structure layer 14 is formed on the semiconductor substrate 12.

The first wiring 15 of the first structure layer 14 can be formed as described above, and is made of, for example, copper and has a thickness of, for example, 5 μm. When forming fine wiring, the semi-additive method is preferable.

The first insulating layer 16 of the first structure layer 14 can be formed by a CVD method or a spin coating method when an inorganic material is used as an insulating material. The opening serving as the first via 17 can be formed by dry etching. When an organic material is used as the insulating material, either photosensitive or non-photosensitive may be used, and the first insulating layer can be formed by a spin coating method, a laminating method, a pressing method, or a printing method. As described above, the opening serving as the first via 17 can be formed by a photolithography method when a photosensitive resin is used, and a non-photosensitive organic material or an organic material having a low pattern resolution even when photosensitive is used. When used, it can be formed by a laser method, a dry etching method, a blast method, or the like. The first via 17 can be formed by filling the opening formed in this way with a conductive material. In addition, a metal post is formed on the portion to be the first via 17 by a plating method or a printing method, and after the first insulating layer 16 is formed, the first via a dry etching method, a CMP method, a grinding method, a lapping method or the like. The first via 17 can also be formed by removing a portion of the insulating layer 16 on the metal post and exposing the metal post.

In the structure shown in FIG. 12, the opening of the first via 17 is shown by a vertical wall, but a taper angle may be provided. By providing a taper angle in the first via 17 connected to the wiring of the element circuit structure layer, the connection area between the first via 17 and the wiring of the element circuit structure layer 13 can be reduced. The surface wiring density can be increased. In addition, since the junction area between the first via 17 and the first wiring 15 can be increased, connection reliability can be improved. Furthermore, since the first via 17 has a taper angle, wiring formation is facilitated.

Next, as shown in FIG. 12C, as described in the first embodiment, the second structure layer 19 is placed on the opposite surface of the surface of the semiconductor substrate 12 on which the element circuit structure layer 13 is formed. Form directly.

The second wiring 20, the second insulating layer 21, and the second via 22 of the second structural layer 19 are formed in the same manner as the first wiring 15, the first insulating layer 16, and the first via 17 of the first structural layer described above. can do. If necessary, the aforementioned adhesion layer or roughened surface is formed.

Although the manufacturing method described with reference to FIG. 12 has been described as an example of the manufacturing method of the structure illustrated in FIG. 2, the structure illustrated in FIG. 4 can be manufactured using a similar method. The first external terminal 18 and the second external terminal 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.

According to the first manufacturing example, the wiring board according to the first embodiment can be efficiently formed. Further, as shown in FIG. 13A, a plurality of wiring boards 11 are formed on the wafer 39, and along the solid line in FIG. 13A and the broken line in FIG. 13B, blade dicing, laser dicing, You may cut | disconnect by water cutter, dry etching, wet etching, etc., and divide into each wiring board 11 separately.

Second Manufacturing Example A second manufacturing example will be described with reference to FIG. FIG. 14 is a partial cross-sectional view for explaining the present manufacturing example.

The second production example is different from the first production example in that the first structural layer 14 and the second structural layer 19 are formed by progressively laminating at the same time. Hereinafter, differences from the first manufacturing example will be described. Parts not particularly described are the same as those in the first production example.

After forming the element and element circuit structure layer 13 on the semiconductor substrate 12 as shown in FIG. 14A, as shown in FIG. 14B, the substrate side portion of the first structure layer 14 (wiring 15 and insulation) The layer 16 and the via 17) are formed so as to be in direct contact with the element circuit structure layer 13, and the substrate side portion (the wiring 20 and the insulating layer 21) of the second structure layer 19 is formed on the substrate surface on which the element circuit structure layer 13 is formed. Directly formed on the opposite surface. When the element circuit structure layer 13 is not formed, a substrate side portion of the first structure layer 14 is formed on the semiconductor substrate 12. Subsequently, an upper layer side portion of the first structure layer and an upper layer side portion of the second structure layer are formed to form a desired structure shown in FIG. At that time, the formation of the first insulating layer and the formation of the second insulating layer are simultaneously performed in the same process, and the formation of the first wiring and the formation of the second wiring are simultaneously performed in the same process. The insulating layer can be formed on both sides by attaching an insulating sheet on both sides and performing heat treatment. Wiring can be formed by forming electroless plating on both sides, forming a resist pattern on both sides, performing electrolytic plating on both sides simultaneously, and etching on both sides simultaneously.

The manufacturing method described with reference to FIG. 14 has been described as an example of the manufacturing method of the structure illustrated in FIG. 2, but the structure illustrated in FIG. 4 can be manufactured using a similar method. The first external terminal 18 and the second external terminal 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.

According to the second manufacturing example, the wiring board according to the first embodiment can be efficiently formed. In particular, as compared with the first manufacturing example, the semiconductor substrate 12 can be manufactured stably even if it is thin.

Third Manufacturing Example A third manufacturing example will be described with reference to FIG. FIG. 15 is a partial cross-sectional view for explaining the present manufacturing example.

The third manufacturing example is different from the first manufacturing example in that the first structural layer 14 and the second structural layer 19 are alternately stacked in units of combinations of insulating layers and wirings. ing. Hereinafter, differences from the first manufacturing example will be described. Parts not particularly described are the same as those in the first production example.

After forming the element and element circuit structure layer 13 on the semiconductor substrate 12 as shown in FIG. 15A, as shown in FIG. 15B, the substrate side portion of the first structure layer 14 (wiring 15, insulation) The layer 16 and the via 17) are formed so as to be in direct contact with the element circuit structure layer 13. When the element circuit structure layer 13 is not formed, a substrate side portion of the first structure layer 14 is formed on the semiconductor substrate 12.

Next, as shown in FIG. 15C, the substrate side portion (the wiring 20 and the insulating layer 21) of the second structure layer 19 is directly formed on the opposite surface of the substrate surface on which the element circuit structure layer 13 is formed.

Next, an upper layer side portion of the first structure layer and an upper layer side portion of the second structure layer are formed to form a desired structure shown in FIG. At that time, the formation of the first insulating layer and the first wiring, and the formation of the second insulating layer and the formation of the second wiring are alternately performed.

The manufacturing method described with reference to FIG. 15 has been described as an example of the manufacturing method of the structure shown in FIG. 2, but the structure shown in FIG. 4 can be manufactured using a similar method. The first external terminal 18 and the second external terminal 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.

According to the third manufacturing example, the wiring board according to the first embodiment can be efficiently formed. In particular, as compared with the first manufacturing example, the semiconductor substrate 12 can be stably manufactured even if it is thin, and the positional accuracy between the first structure layer 14 and the second structure layer 19 can be further increased.

Fourth Manufacturing Example A fourth manufacturing example will be described with reference to FIG. FIG. 16 is a partial cross-sectional view for explaining the present manufacturing example.

The fourth manufacturing example is different from the first, second, and third manufacturing examples in that the through via 34 is formed in the semiconductor substrate 12. Hereinafter, differences from the first, second, and third production examples will be described. Parts not particularly described are the same as those in the first, second, and third production examples.

As shown in FIG. 16, the element and element circuit structure layer 13 are formed on the semiconductor substrate 12, and the through via 34 is formed. When the element circuit structure layer 13 is not formed, the through via 34 is formed in the semiconductor substrate 12. The through via 34 can be formed by the method described in the second embodiment, and may be formed after the element circuit structure layer 13 is formed, or may be formed before the element circuit structure layer 13. In addition, the semiconductor substrate 12 is provided with a recess serving as a through via 34 and filled with a conductor, and then the element circuit structure layer 13 is formed. A method of exposing the through via 34 by etching may be performed. The through via 34 has a function necessary for the element circuit structure layer 13 and the first structure layer 14 provided on one surface side of the semiconductor substrate 12 and the second structure layer 19 provided on the other surface side. It forms so that it may electrically connect according to. That is, one or both of the element circuit structure layer 13 and the first structure layer 15 are electrically connected to the second structure layer 19.

In the process after the structure shown in FIG. 16 is formed, the first structure layer 14 and the second structure layer 19 can be formed by the processes described with reference to FIGS.

According to the fourth manufacturing example, in addition to the effects of the first, second and third manufacturing examples, the wiring according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. A board | substrate can be manufactured efficiently.

Fifth Manufacturing Example A fifth manufacturing example method will be described with reference to FIG. FIG. 17 is a partial cross-sectional view for explaining the present manufacturing example.

The fifth manufacturing example is different from the fourth manufacturing example in that the through via 34 is formed in the semiconductor substrate 12 during the manufacturing process of the first structural layer 14. Below, a different point from the 4th manufacture example is explained. Parts not particularly described are the same as in the fourth production example.

As shown in FIG. 17A, the substrate side portion (the wiring 15, the insulating layer 16, and the via 17) of the first structural layer 14 is formed on the element circuit structural layer 13 in accordance with the above-described manufacturing method. When the element circuit structure layer 13 is not formed, a substrate side portion of the first structure layer 14 is formed on the semiconductor substrate 12.

Next, as shown in FIG. 17B, a through via 34 is formed in the semiconductor substrate 12. The through via 34 can be formed using the method described in the second embodiment.

In addition, a recess is provided in a portion where the through via 34 of the semiconductor substrate 12 is formed and filled with a conductor, and then a part of the element circuit structure layer 13 and the first structure layer 14 is formed. You may perform the method of exposing the through-via 34 by grinding or etching the surface of the side in which 13 is not formed.

The through via 34 has a function necessary for the element circuit structure layer 13 and the first structure layer 14 provided on one surface side of the semiconductor substrate 12 and the second structure layer 19 provided on the other surface side. It forms so that it may electrically connect according to. That is, one or both of the element circuit structure layer 13 and the first structure layer 14 are electrically connected to the second structure layer 19.

After the through via 34 is formed, the remaining portion of the first structure layer 14 and the second structure layer 19 are formed according to the above-described manufacturing method.

According to the fifth manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the wiring according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. A board | substrate can be manufactured efficiently. Furthermore, it is easy to form the through via 34 that is directly connected to both the element circuit structure layer 13 and the first structure layer 14, and a higher-density wiring board can be manufactured.

Sixth Manufacturing Example A sixth manufacturing example will be described with reference to FIG. FIG. 18 is a partial cross-sectional view for explaining the present manufacturing example.

The sixth manufacturing example is different from the fifth manufacturing example in that the through via 34 is formed in the semiconductor substrate 12 after the formation process of the first structural layer 14 is completed. Hereinafter, differences from the fifth manufacturing method will be described. Parts not particularly described are the same as those in the fifth production example.

As shown in FIG. 18A, the first structure layer 14 is formed on the element circuit structure layer 13 in accordance with the manufacturing method described above. When the element circuit structure layer 13 is not formed, the first structure layer 14 is formed on the semiconductor substrate 12.

Next, as shown in FIG. 18B, a through via 34 is formed in the semiconductor substrate 12. The through via 34 can be formed using the method described in the second embodiment. In addition, a recess is formed in a portion of the semiconductor substrate 12 where the through via 34 is formed, and after filling the conductor, the element circuit structure layer 13 and the first structure layer 14 are formed, and the element circuit structure layer 13 of the semiconductor substrate 12 is formed. You may perform the method of exposing the penetration via 34 by grinding or etching the surface of the side which is not carried out.

After the through via 34 is formed, the second structure layer 19 is formed as shown in FIG.

The first structure layer 14 and the second structure layer 19 shown in FIG. 18 are the same as the structure shown in FIG. 2, but even a structure similar to the structure shown in FIG. 4 can be manufactured by the same method. Moreover, you may produce the 1st external terminal 18 and the 2nd external terminal 23 so that it may become a structure shown in FIG.5 (b) or (c) according to the connection method.

According to the sixth manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the wiring according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. A board | substrate can be manufactured efficiently. Further, it is easy to form the through via 34 that is directly connected to the first wiring 15 of the first structure layer 14, and a higher-density wiring board can be manufactured.

Seventh Manufacturing Example A seventh manufacturing example will be described with reference to FIG. FIG. 19 is a partial cross-sectional view for explaining the present manufacturing example.

In the seventh manufacturing example, the through via 34 is formed in the semiconductor substrate 12 after the formation of the second insulating layer 21 on the substrate side in the step of forming the second structural layer 19 as compared with the sixth manufacturing example. Is different. Hereinafter, differences from the sixth production example will be described. Parts not particularly described are the same as in the sixth production example.

As shown in FIG. 19A, after the element circuit structure layer 13 and the first structure layer 14 are formed on one surface of the semiconductor substrate 12, the second insulation of the second structure layer 19 is formed on the other surface of the semiconductor substrate 12. The layer 21 is formed, and an opening corresponding to the through via 34 to be formed is provided. Next, as shown in FIG. 19B, a through via 34 is formed in the semiconductor substrate 12 in accordance with the opening.

After the through via 34 is formed, the remaining part of the second structural layer 19 is formed as shown in FIG.

According to the seventh manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the wiring according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. A board | substrate can be manufactured efficiently. Furthermore, the precision of the formation position of the through via 34 connected to the second structure layer 19 can be increased, and a higher-density wiring board can be manufactured.

Eighth Manufacturing Example An eighth manufacturing example will be described with reference to FIG. FIG. 20 is a partial cross-sectional view for explaining the present manufacturing example.

The eighth manufacturing example differs from the other manufacturing examples described above in that a plurality of wiring boards according to any of the above-described embodiments are stacked. Further, one or more other wiring boards 11c and electronic components 37 may be connected. The eighth production example will be described below. Portions that are not particularly described are the same as in the manufacturing method described above.

First, as shown in FIG. 20 (a), a plurality of wiring boards are connected by a connecting portion 35. Multiple wiring boards can be connected by connecting the wiring board parts in the wafer state, connecting individual wiring boards, or connecting the wiring board parts in the wafer state and the individual wiring boards. It doesn't matter. The wiring substrate portion in the wafer state can be divided after connection. From the viewpoint of yield, it is preferable to connect the wiring board as the lowermost layer in a wafer state and connect the laminated wiring boards as individual wiring boards.

Next, as shown in FIG. 20B, solder balls 36 as external terminals are formed on the lower surface side of the lowermost wiring board. Instead of such a solder ball 36, a connection structure using pins, Au bumps, copper bumps, spare solder, metal pearls, ACF, NCF, or the like may be formed.

The multilayer wiring board shown in FIG. 20B corresponds to the multilayer wiring board shown in FIG. 8, but the wiring board shown in FIGS. 9, 10, and 11 is manufactured by using a similar method. Can do. Moreover, it is not limited to the laminated structure of two wiring boards, You may laminate | stack three or more wiring boards.

According to the eighth manufacturing example, the wiring board according to the third embodiment and the wiring board according to the fourth embodiment can be efficiently manufactured.

The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

This application claims priority based on Japanese Patent Application No. 2008-271186 filed on Oct. 21, 2008, the entire disclosure of which is incorporated herein.

Claims (22)

A core substrate;
A first structural layer including a first insulating layer, a first wiring, and a first external terminal, provided on one surface side of the core substrate;
Including a second insulating layer, a second wiring, and a second external terminal, and a second structural layer provided on the other surface side of the core substrate,
A wiring board in which at least one of the number and arrangement of the first external terminals and the second external terminals is different between one surface side and the other surface side of the core substrate. 2. An element circuit structure layer including an element on the core substrate and including a wiring and an interlayer insulating film electrically connected to the element between the core substrate and the first structure layer. Wiring board as described in. The first structural layer has a multilayer wiring structure in which the first insulating layer and the first wiring are alternately provided, and the second structural layer has the second insulating layer and the second wiring alternately. The wiring board according to claim 1, wherein the wiring board has a provided multilayer wiring structure. The wiring board according to any one of claims 1 to 3, further comprising a through via that penetrates the core substrate and electrically connects the first wiring and the second wiring. The wiring board according to any one of claims 1 to 4, comprising at least one of an electronic component connected to the first external terminal and an electronic component connected to the second external terminal. The electronic component connected to the first external terminal, and another electronic component connected to the second external terminal and having a different external size from the electronic component, according to any one of claims 1 to 5. The wiring board described. A plurality of electronic components connected to the first external terminal or the second external terminal are provided on one surface side of the core substrate, and two or more of the electronic components are electrically connected via the wiring substrate. The wiring board according to any one of claims 1 to 6. The electronic component includes an electronic component core substrate, a first electronic component insulating layer, a first electronic component wiring, and a first electronic component external terminal. The first electronic component is provided on one surface side of the electronic component core substrate. A component structure layer; a second electronic component structure layer including a second electronic component insulating layer, a second electronic component wiring, and a second electronic component external terminal, and provided on the other surface side of the electronic component core substrate; The wiring board according to claim 5, which is another wiring board. The wiring board according to any one of claims 5 to 8, wherein the connection between the electronic component and the first external terminal or the second external terminal is via a solder material or a low melting point metal material. The wiring board according to any one of claims 5 to 8, wherein the connection between the electronic component and the first external terminal or the second external terminal is via a bonding wire. 2. The method for manufacturing a wiring board according to claim 1, wherein the first structural layer is formed on one surface side of the core substrate, and the second structural layer is formed on the other surface side of the core substrate. A method of manufacturing a wiring board. In the formation of the first structure layer and the second structure layer, the formation of the first insulating layer and the formation of the second insulating layer are simultaneously performed in the same process, and the formation of the first wiring and the formation of the second wiring are performed. The method for manufacturing a wiring board according to claim 11, wherein the steps are performed simultaneously in the same process. In the formation of the first structure layer and the second structure layer, the formation of the first insulating layer and the formation of the first wiring, and the formation of the second insulating layer and the formation of the second wiring are alternately performed. The manufacturing method of the wiring board of Claim 11. 12. The method of manufacturing a wiring board according to claim 11, wherein a through via penetrating the core substrate is formed in the course of forming the first structural layer. 12. The method of manufacturing a wiring board according to claim 11, wherein a through via penetrating the core substrate is formed between the step of forming the first structural layer and the step of forming the second structural layer. 12. The method for manufacturing a wiring board according to claim 11, wherein after forming the first structural layer, a through via penetrating the core substrate is formed in the course of forming the second structural layer. Forming a wiring board according to the method of any one of claims 11 to 16;
A method for manufacturing a wiring board, comprising: connecting an electronic component to at least one of the first structural layer side and the second structural layer side of the wiring board via the first external terminal or the second external terminal. Forming a plurality of wiring boards according to the method of any one of claims 11 to 16,
A method of manufacturing a wiring board, comprising a step of connecting these wiring boards to each other through respective first or second external terminals or via first and second external terminals. The method for manufacturing a wiring board according to claim 17, wherein the connection between the wiring board and the electronic component is performed using a solder material or a low melting point metal material. The method for manufacturing a wiring board according to claim 18, wherein the wiring boards are connected using a solder material or a low melting point metal material. The method for manufacturing a wiring board according to claim 17, wherein the wiring board and the electronic component are connected by wire bonding. The method for manufacturing a wiring board according to claim 18, wherein the wiring boards are connected to each other by wire bonding.

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