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WO2009128112A1 - Electronic processing system for aid to unmanned navigation in particular unmanned air navigation - Google Patents

Electronic processing system for aid to unmanned navigation in particular unmanned air navigation Download PDF

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Publication number
WO2009128112A1
WO2009128112A1 PCT/IT2009/000160 IT2009000160W WO2009128112A1 WO 2009128112 A1 WO2009128112 A1 WO 2009128112A1 IT 2009000160 W IT2009000160 W IT 2009000160W WO 2009128112 A1 WO2009128112 A1 WO 2009128112A1
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WIPO (PCT)
Prior art keywords
communication
nodes
fpga device
unit
bus
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PCT/IT2009/000160
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French (fr)
Inventor
Massimo Verola
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Alenia Aermacchi SpA
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Alenia Aeronautica SpA
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Publication of WO2009128112A1 publication Critical patent/WO2009128112A1/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory

Definitions

  • the present invention relates to an electronic processing system for aid to unmanned navigation, in particular unmanned air navigation, that allows, in an efficient, flexible, and reliable way, to automatically provide aid to navigation of a vehicle, in particular an aircraft.
  • OBS On Board System
  • an processing system for aid to unmanned navigation comprising one or more processing nodes, each connected to a respective system controller, in turn connected to memory means through a first communication channel or bus, characterised in that the system controller of each one of said one or more nodes is connected, through a respective PCI bus, to a FPGA device incorporating first I/O interface means, the FPGA device further comprising, for each one of said one or more nodes, a PCI communication unit connected to the corresponding system controller, and first means of control between the respective PCI bus and said first I/O interface means.
  • said processing nodes may be at least two independent from each other, and in that the FPGA device implements communication between said at least two nodes through a shared memory architecture, comprising a shared memory unit, preferably integrated in said memory means, accessible by the PCI buses of said at least two nodes through an arbiter to which respective memory managers, operating as interfaces of control between the respective PCI buses of said at least two nodes and the shared memory unit, connect.
  • a shared memory architecture comprising a shared memory unit, preferably integrated in said memory means, accessible by the PCI buses of said at least two nodes through an arbiter to which respective memory managers, operating as interfaces of control between the respective PCI buses of said at least two nodes and the shared memory unit, connect.
  • the arbiter may manage accesses of said memory managers to the shared memory unit according to a round robin scheduling algorithm.
  • the arbiter and said memory managers may be implemented on programmable logic device (FPGA) by means of the VHDL language.
  • FPGA programmable logic device
  • the FPGA device may further comprise a system logic reset unit and/or a power management unit and/or at least one unit for checking operation of said one or more nodes.
  • the FPGA device may further comprises a board-to-board wide band communication unit, for carrying out the connection with at least one external, preferably identical, system, more preferably connected so as to execute processing in parallel.
  • said first I/O interface means comprises or consists in one or more units selected from the group comprising RS 232 interface unit, RS 422/485 interface unit, and general purpose digital interface unit, preferably in LVTTL technology, more preferably with 12 input ports and 6 output ports, said first control means of the FPGA device comprising state machines and registers necessary to operations of interface between the respective PCI bus and said one or more units
  • each one of said one or more nodes may be provided with at least one CPU, preferably operating up to 1 GHz, more preferably an ATMEL PowerPC 7447A CPU with AltiVec Technology.
  • each first bus may be a 32 bit one, preferably operating up to 66MHz.
  • said memory means may comprise or consist of one or more, preferably two, banks of 256 MB
  • SDRAM memory with EDAC - Error Detection And Correction more preferably operating up to 100 MHz, and/or of one or more, preferably two,
  • Flash non-volatile memories more preferably of 4 MB
  • each PCI bus may be a 32 bit one, preferably operating up to 66MHz.
  • the FPGA device may be a Xilinx XQ2V6000-4CF1144M.
  • the system may comprise cPCI connectors means, to which said first I/O interface means is connected.
  • At least one PCI bus may be connected to said cPCI connectors means.
  • said board-to-board communication unit may be connected to said cPCI connectors means, preferably through 64 pins of the FPGA device
  • the FPGA device may be connected to second communication means and may further comprise, for at least one processing node, second means of control between the respective PCI bus and said second communication means.
  • said second communication means may comprise or consist of at least one ARINC 429 communication unit, preferably provided with a transmission channel and with a reception channel, said first second of control of the FPGA device comprising state machines and registers necessary to operations of interface between the respective PCI bus and said at least one ARINC 429 communication unit.
  • said second communication means may be connected to said cPCI connectors means.
  • the system may comprise at least one PMC (PCI Mezzanine Card) board connected to a system controller through the respective PCI bus
  • PMC PCI Mezzanine Card
  • said at least one PMC board may be connected to said cPCI connectors means.
  • the system may comprise at least one fast Ethernet 10/100 communication controller connected to a system controller through the respective PCI bus.
  • said at least one fast Ethernet 10/100 communication controller may be connected to said cPCI connectors means.
  • the system may comprise at least one MIL-STD communication controller with double redundancy 1553/1760, connected to a respective PCI bus, the FPGA device comprising at least one management unit managing the communication of the E MIL-1553 xceivers (transceivers - trasmitters-receivers).
  • said at least one MIL-STD communication controller with double redundancy 1553/1760 may be connected to said cPCI connectors means.
  • each system controller may be further connected, through a respective second bus, preferably a
  • each system controller may be further connected, through the respective second bus, to at least one ' clock signal generator.
  • the system may be mounted onto a heatsink plate, preferably of aluminium, shaped and sized in such a way to operate as passive cooling structure capable to create "thermal paths" for heat generated by "hot spots” of the board onto which the system electronics is mounted.
  • Figure 1 shows a circuit logic scheme of the preferred embodiment of the system according to the invention
  • Figure 2 shows the architecture of the FPGA device of the system of Figure 1 ;
  • Figure 3 shows the architecture of communication among the nodes of the system of Figure 1.
  • the inventors have developed a specific circuit architecture of the electronic system according to the invention that allows fast execution of the necessary processing for aid to navigation.
  • the preferred embodiment of the electronic system according to the invention comprises a first processing unit, or node, 1 and a second processing node 2, identical to each other and both provided with CPU (preferably
  • the two processing nodes 1 and 2 are independent from each other and they are symmetrically located with respect to a FPGA device 3 operating as unit for interconnecting the nodes 1 and 2 with some I/O
  • the two nodes 1 and 2 are connected to a respective system controller, respectively 4 and 5, that is in turn connected, through a corresponding first communication channel or bus (preferably a 32 bit one operating up to 66MHz), respectively 6 and 7, to a respective SDRAM memory partition, respectively 8 and 9 (preferably contained in two SDRAM memory banks of 256 MB with EDAC - Error Detection And Correction - operating up to 100 MHz), and to respective partitions of a pair of (preferably 4 MB) Flash non-volatile memories, respectively 10-11 and 12-13.
  • the FPGA device 3 is connected, through the buses 6 and
  • Each one of the two system controllers 4 and 5 is further connected, through a respective second bus 14 or 15 (preferably a 64 bit one operating up to 66MHz), to an EEPROM memory, respectively 16 and 17 (preferably of 256 byte), to an AD (analog-to-digital) converter, respectively 18 and 19, and to a DA (digital-to-analog) converter, respectively 20 and 21.
  • a respective second bus 14 or 15 preferably a 64 bit one operating up to 66MHz
  • an EEPROM memory respectively 16 and 17 (preferably of 256 byte)
  • AD analog-to-digital converter
  • DA digital-to-analog converter
  • Each one of the two system controllers 4 and 5 is still connected, through a respective third PCI bus 23 and 24 (preferably a 32 bit one operating up to 66MHz), to a respective adaptor for additional PMC (PCI Mezzanine Card) module, respectively 25 and 26 (i.e. to connectors for additional module with PMC form factor).
  • Such third PCI buses 23 and 24 are further connected to the FPGA device 3.
  • the system controller 4 of the first node 1 is further connected through the respective third bus 23 to a fast Ethernet 10/100 communication controller 27 and to a MIL-STD communication controller 28 with double redundancy 1553/1760 (i.e., the controllers 27 and 28 are mapped onto the PCI bus 23 of the controller 4 of the first node 1).
  • the third bus 24 of the system controller 5 of the second node 2 is then connected also to a first cPCI (compact PCI - Peripheral Component Interconnect) connector 29.
  • the PMC boards 25 and 26, the fast Ethernet 10/100 controller 27, and the MIL-STD 1553 controller 28 are connected to a second cPCI connector 30.
  • the two connectors 29 and 30 forms, when combined, a cPCI connector.
  • the FPGA device 3 incorporates two RS 232 interface units, represented by the block 31 , two RS 422/485 interface units, represented by the block 32, and a general purpose digital interface unit, preferably in
  • LVTTL technology with 12 input ports and 6 output ports, represented by the block 33.
  • the FPGA device 3 is connected to an ARINC 429 communication unit 34, provided with a transmission channel and a reception channel connected to the second cPCI connector 30.
  • Figure 2 shows the architecture scheme of the FPGA device 3 of Figure 1 (preferably a Xilinx XQ2V6000-4CF1144M).
  • the FPGA device 3 comprises: a corresponding PCI communication unit (or PCI Agent), respectively 301 and 302, connected to the corresponding system controller, respectively 4 and 5; a control unit, respectively 303 and 304, between the respective third PCI bus and the respective RS232 interface unit; a control unit, respectively 305 and 306, between the respective third PCI communication unit (or PCI Agent), respectively 301 and 302, connected to the corresponding system controller, respectively 4 and 5; a control unit, respectively 303 and 304, between the respective third PCI bus and the respective RS232 interface unit; a control unit, respectively 305 and 306, between the respective third
  • the units 301 , 303, 305 and 307 related to the first node 1 are connected to each other through a fourth bus 309, whereas the units 301 , 303, 305 and 307 related to the first node 1 are connected to each other through a fifth bus 310.
  • a further unit 311 of control between the PCI bus 23 of the first node 1 and the ARINC 429 communication channel is connected to the fourth bus 309, comprising the state machines and the registers necessary for the operations of interface between the PCI bus 23 and the ARINC 429 communication unit 34.
  • a unit 312 of control between the PCI bus 23 of the first node 1 and the general purpose digital interface unit is also connected to the same fourth bus 309, comprising the state machines and the registers necessary for the operations of interface between the PCI bus 23 and the digital interface unit 33.
  • the FPGA device 3 also implements the communication between the first node 1 and the second node 2 through a shared memory architecture, comprising a shared memory unit 313, preferably comprising a 256KB SRAM, accessible by both PCI buses 23 and 24 of the two nodes through an arbiter 314 to which two respective memory managers, respectively 315 and 316, connected to the fourth and fifth bus 309 and 310, connects.
  • a shared memory architecture comprising a shared memory unit 313, preferably comprising a 256KB SRAM, accessible by both PCI buses 23 and 24 of the two nodes through an arbiter 314 to which two respective memory managers, respectively 315 and 316, connected to the fourth and fifth bus 309 and 310, connects.
  • accesses to the shared memory 313 are managed by the arbiter 314 according to a round robin scheduling algorithm.
  • Figure 3 that is immediately comprehensible to those skilled in the art, shows the just illustrated architecture of communication between the two nodes 1 and 2, wherein the memory managers 315 and 316 operate as control interface between the respective PCI bus 23 or 24 and the shared memory 313.
  • the arbiter 314 and the memory managers 315 and 316 are implemented on programmable logic device (FPGA) by means of the VHDL language.
  • FPGA programmable logic device
  • the preferred embodiment of the system according to the invention further comprises a system logic reset unit 317, a power management unit 318, and two units 319 and 320 for checking operation of the nodes 1 and 2, respectively connected to the fourth and fifth buses 309 and 310.
  • the FPGA device 3 of Figure 2 preferably comprises a board-to-board wide band communication unit 321, for connecting the system of Figure 1 to another identical system, exploiting the processing power of two systems according to the invention connected in parallel.
  • 64 pins of the FPGA device 3 are connected to the second cPCI connector 30 of Figure 1.
  • FIG. 1 Other embodiments of the system according to the invention may provide the presence of only one processing node, instead of the two shown in Figure 1.
  • the FPGA device 3 only comprises the interface and communication units (comprising, e.g., the units 301 and the bus 309 and one or more of the units 303, 305, 307, 311 , and 312).
  • removal of one of the two nodes transforms the system into a single node system, eliminating the communication between the nodes as illustrated in Figure 3.
  • the single node system according to the invention comprises the interface units of only one of the nodes illustrated in Figure 1.
  • the single node system according to the invention may comprise the interface units of both nodes illustrated in Figure 1 , mapping the interface units of the eliminated node on the remaining node (or connecting them to the PCI bus of the latter), thus implementing a single node system with the same interface units of the double node system of Figure 1.
  • a heatsink plate In order to reduce the temperature of the system according to the invention during operation, it is provided with a heatsink plate, shaped and sized in such a way to operate as passive cooling structure. It has to be capable to create "thermal paths" (e.g., through selection of variable thicknesses on the plate) for heat generated by the "hot spots" of the board onto which the system electronics is mounted.
  • the heatsink plate made of aluminium, allows the system according to the invention to operate in environment with temperature up to 70 0 C.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Navigation (AREA)
  • Multi Processors (AREA)

Abstract

The present invention relates to an electronic processing system for aid to unmanned navigation, in particular unmanned air navigation, comprising one or more processing nodes (1, 2), each connected to a respective system controller (4, 5), in turn connected to memory means (8, 9, 10, 11, 12, 13) through a first communication channel or bus (6, 7), characterised in that the system controller (4, 5) of each one of said one or more nodes (1, 2) is connected, through a respective PCI bus (23, 24), to a FPGA device (3) incorporating first I/O interface means (31, 32, 33), the FPGA device (3) further comprising, for each one of said one or more nodes (1, 2), a PCI communication unit (301) connected to the corresponding system controller (4, 5), and first means (303, 304, 305, 306, 312) of control between the respective PCI bus (23, 24) and said first I/O interface means (31, 32, 33).

Description

ELECTRONIC PROCESSING SYSTEM FOR AID TO UNMANNED NAVIGATION, IN PARTICULAR UNMANNED AIR NAVIGATION
The present invention relates to an electronic processing system for aid to unmanned navigation, in particular unmanned air navigation, that allows, in an efficient, flexible, and reliable way, to automatically provide aid to navigation of a vehicle, in particular an aircraft.
Presently, there exist many OBS (On Board System) on board systems installed, in particular, on aircrafts, which allow to automatically provide aid to navigation of the aircraft once the mission to carry out has been set.
However, the bulk of necessary processing is so large that reliability and precision of these systems is not always satisfactory.
Hence, it is an object of the present invention to provide an efficient, flexible, and reliable electronic system of automatic control for aid to navigation of a vehicle, in particular an aircraft.
It is still an object of the present invention to avoid the overheating of the electronic system during its operation.
It is specific subject matter of this invention an processing system for aid to unmanned navigation, in particular unmanned air navigation, comprising one or more processing nodes, each connected to a respective system controller, in turn connected to memory means through a first communication channel or bus, characterised in that the system controller of each one of said one or more nodes is connected, through a respective PCI bus, to a FPGA device incorporating first I/O interface means, the FPGA device further comprising, for each one of said one or more nodes, a PCI communication unit connected to the corresponding system controller, and first means of control between the respective PCI bus and said first I/O interface means. Always according to the invention, said processing nodes may be at least two independent from each other, and in that the FPGA device implements communication between said at least two nodes through a shared memory architecture, comprising a shared memory unit, preferably integrated in said memory means, accessible by the PCI buses of said at least two nodes through an arbiter to which respective memory managers, operating as interfaces of control between the respective PCI buses of said at least two nodes and the shared memory unit, connect.
Still according to the invention, the arbiter may manage accesses of said memory managers to the shared memory unit according to a round robin scheduling algorithm.
Furthermore according to the invention, the arbiter and said memory managers may be implemented on programmable logic device (FPGA) by means of the VHDL language.
Always according to the invention, the FPGA device may further comprise a system logic reset unit and/or a power management unit and/or at least one unit for checking operation of said one or more nodes.
Still according to the invention, the FPGA device may further comprises a board-to-board wide band communication unit, for carrying out the connection with at least one external, preferably identical, system, more preferably connected so as to execute processing in parallel.
Furthermore according to the invention, said first I/O interface means comprises or consists in one or more units selected from the group comprising RS 232 interface unit, RS 422/485 interface unit, and general purpose digital interface unit, preferably in LVTTL technology, more preferably with 12 input ports and 6 output ports, said first control means of the FPGA device comprising state machines and registers necessary to operations of interface between the respective PCI bus and said one or more units
Always according to the invention, each one of said one or more nodes may be provided with at least one CPU, preferably operating up to 1 GHz, more preferably an ATMEL PowerPC 7447A CPU with AltiVec Technology. Still according to the invention, each first bus may be a 32 bit one, preferably operating up to 66MHz.
Furthermore according to the invention, said memory means may comprise or consist of one or more, preferably two, banks of 256 MB
SDRAM memory with EDAC - Error Detection And Correction, more preferably operating up to 100 MHz, and/or of one or more, preferably two,
Flash non-volatile memories, more preferably of 4 MB
Always according to the invention, each PCI bus may be a 32 bit one, preferably operating up to 66MHz.
Still according to the invention, the FPGA device may be a Xilinx XQ2V6000-4CF1144M.
Furthermore according to the invention, the system may comprise cPCI connectors means, to which said first I/O interface means is connected.
Always according to the invention, at least one PCI bus may be connected to said cPCI connectors means.
Still according to the invention, said board-to-board communication unit may be connected to said cPCI connectors means, preferably through 64 pins of the FPGA device
Furthermore according to the invention, the FPGA device may be connected to second communication means and may further comprise, for at least one processing node, second means of control between the respective PCI bus and said second communication means.
Always according to the invention, said second communication means may comprise or consist of at least one ARINC 429 communication unit, preferably provided with a transmission channel and with a reception channel, said first second of control of the FPGA device comprising state machines and registers necessary to operations of interface between the respective PCI bus and said at least one ARINC 429 communication unit.
Still according to the invention, said second communication means may be connected to said cPCI connectors means.
Furthermore according to the invention, the system may comprise at least one PMC (PCI Mezzanine Card) board connected to a system controller through the respective PCI bus
Always according to the invention, said at least one PMC board may be connected to said cPCI connectors means.
Still according to the invention, the system may comprise at least one fast Ethernet 10/100 communication controller connected to a system controller through the respective PCI bus.
Furthermore according to the invention, said at least one fast Ethernet 10/100 communication controller may be connected to said cPCI connectors means. Always according to the invention, the system may comprise at least one MIL-STD communication controller with double redundancy 1553/1760, connected to a respective PCI bus, the FPGA device comprising at least one management unit managing the communication of the E MIL-1553 xceivers (transceivers - trasmitters-receivers). Still according to the invention, said at least one MIL-STD communication controller with double redundancy 1553/1760 may be connected to said cPCI connectors means. Furthermore according to the invention, each system controller may be further connected, through a respective second bus, preferably a
64 bit one, more preferably operating up to 66MHz, to an EEPROM memory, preferably of 256 byte, to an AD (analog-to-digital) converter, and to a DA (digital-to-analog) converter.
Always according to the invention, each system controller may be further connected, through the respective second bus, to at least one ' clock signal generator.
Still according to the invention, the system may be mounted onto a heatsink plate, preferably of aluminium, shaped and sized in such a way to operate as passive cooling structure capable to create "thermal paths" for heat generated by "hot spots" of the board onto which the system electronics is mounted.
The present invention will be now described, by way of illustration and not by way of limitation, according to its preferred embodiments, by particularly referring to the Figures of the enclosed drawings, in which:
Figure 1 shows a circuit logic scheme of the preferred embodiment of the system according to the invention; Figure 2 shows the architecture of the FPGA device of the system of Figure 1 ; and
Figure 3 shows the architecture of communication among the nodes of the system of Figure 1.
In the Figures, alike elements are indicated by same reference numbers.
The inventors have developed a specific circuit architecture of the electronic system according to the invention that allows fast execution of the necessary processing for aid to navigation.
With reference to Figure 1 , it may be observed that the preferred embodiment of the electronic system according to the invention comprises a first processing unit, or node, 1 and a second processing node 2, identical to each other and both provided with CPU (preferably
ATMEL PowerPC 7447A CPU with AltiVec Technology operating up to 1
GHz). The two processing nodes 1 and 2 are independent from each other and they are symmetrically located with respect to a FPGA device 3 operating as unit for interconnecting the nodes 1 and 2 with some I/O
(input/output) control interfaces. In particular, the two nodes 1 and 2 are connected to a respective system controller, respectively 4 and 5, that is in turn connected, through a corresponding first communication channel or bus (preferably a 32 bit one operating up to 66MHz), respectively 6 and 7, to a respective SDRAM memory partition, respectively 8 and 9 (preferably contained in two SDRAM memory banks of 256 MB with EDAC - Error Detection And Correction - operating up to 100 MHz), and to respective partitions of a pair of (preferably 4 MB) Flash non-volatile memories, respectively 10-11 and 12-13. Also the FPGA device 3 is connected, through the buses 6 and
7 of the memories, to the SDRAM memory banks (of which it manages a memory partition shared by the two nodes, as it will be illustrated later) and to the Flash memories.
Each one of the two system controllers 4 and 5 is further connected, through a respective second bus 14 or 15 (preferably a 64 bit one operating up to 66MHz), to an EEPROM memory, respectively 16 and 17 (preferably of 256 byte), to an AD (analog-to-digital) converter, respectively 18 and 19, and to a DA (digital-to-analog) converter, respectively 20 and 21. Finally, through the respective second bus 14 and 15, both the system controllers 4 and 5 are connected to the same clock signal generator 22 (although in Figure 1 this is represented with two different blocks).
Each one of the two system controllers 4 and 5 is still connected, through a respective third PCI bus 23 and 24 (preferably a 32 bit one operating up to 66MHz), to a respective adaptor for additional PMC (PCI Mezzanine Card) module, respectively 25 and 26 (i.e. to connectors for additional module with PMC form factor). Such third PCI buses 23 and 24 are further connected to the FPGA device 3.
The system controller 4 of the first node 1 is further connected through the respective third bus 23 to a fast Ethernet 10/100 communication controller 27 and to a MIL-STD communication controller 28 with double redundancy 1553/1760 (i.e., the controllers 27 and 28 are mapped onto the PCI bus 23 of the controller 4 of the first node 1).
The third bus 24 of the system controller 5 of the second node 2 is then connected also to a first cPCI (compact PCI - Peripheral Component Interconnect) connector 29. The PMC boards 25 and 26, the fast Ethernet 10/100 controller 27, and the MIL-STD 1553 controller 28 are connected to a second cPCI connector 30. Advantageously, the two connectors 29 and 30 forms, when combined, a cPCI connector.
The FPGA device 3 incorporates two RS 232 interface units, represented by the block 31 , two RS 422/485 interface units, represented by the block 32, and a general purpose digital interface unit, preferably in
LVTTL technology with 12 input ports and 6 output ports, represented by the block 33.
Finally, the FPGA device 3 is connected to an ARINC 429 communication unit 34, provided with a transmission channel and a reception channel connected to the second cPCI connector 30.
Figure 2 shows the architecture scheme of the FPGA device 3 of Figure 1 (preferably a Xilinx XQ2V6000-4CF1144M).
For each one of the two nodes 1 and 2, the FPGA device 3 comprises: a corresponding PCI communication unit (or PCI Agent), respectively 301 and 302, connected to the corresponding system controller, respectively 4 and 5; a control unit, respectively 303 and 304, between the respective third PCI bus and the respective RS232 interface unit; a control unit, respectively 305 and 306, between the respective third
PCI bus and the respective RS 422/485 interface unit; and a management unit, respectively 307 and 308, managing the communication of the E MIL-
1553 xceivers (transceivers - trasmitters-receivers).
The units 301 , 303, 305 and 307 related to the first node 1 are connected to each other through a fourth bus 309, whereas the units 301 , 303, 305 and 307 related to the first node 1 are connected to each other through a fifth bus 310.
A further unit 311 of control between the PCI bus 23 of the first node 1 and the ARINC 429 communication channel is connected to the fourth bus 309, comprising the state machines and the registers necessary for the operations of interface between the PCI bus 23 and the ARINC 429 communication unit 34.
A unit 312 of control between the PCI bus 23 of the first node 1 and the general purpose digital interface unit is also connected to the same fourth bus 309, comprising the state machines and the registers necessary for the operations of interface between the PCI bus 23 and the digital interface unit 33.
As already said, the FPGA device 3 also implements the communication between the first node 1 and the second node 2 through a shared memory architecture, comprising a shared memory unit 313, preferably comprising a 256KB SRAM, accessible by both PCI buses 23 and 24 of the two nodes through an arbiter 314 to which two respective memory managers, respectively 315 and 316, connected to the fourth and fifth bus 309 and 310, connects. In particular, accesses to the shared memory 313 are managed by the arbiter 314 according to a round robin scheduling algorithm.
Figure 3, that is immediately comprehensible to those skilled in the art, shows the just illustrated architecture of communication between the two nodes 1 and 2, wherein the memory managers 315 and 316 operate as control interface between the respective PCI bus 23 or 24 and the shared memory 313. Preferably, the arbiter 314 and the memory managers 315 and 316 are implemented on programmable logic device (FPGA) by means of the VHDL language. Still with reference to Figure 2, it may be observed that the preferred embodiment of the system according to the invention further comprises a system logic reset unit 317, a power management unit 318, and two units 319 and 320 for checking operation of the nodes 1 and 2, respectively connected to the fourth and fifth buses 309 and 310. Furthermore, the FPGA device 3 of Figure 2 preferably comprises a board-to-board wide band communication unit 321, for connecting the system of Figure 1 to another identical system, exploiting the processing power of two systems according to the invention connected in parallel. To this end, 64 pins of the FPGA device 3 are connected to the second cPCI connector 30 of Figure 1.
Other embodiments of the system according to the invention may be not provided with the units 318, 320, and 321.
Other embodiments of the system according to the invention may provide the presence of only one processing node, instead of the two shown in Figure 1. In these embodiments the FPGA device 3 only comprises the interface and communication units (comprising, e.g., the units 301 and the bus 309 and one or more of the units 303, 305, 307, 311 , and 312). In particular, removal of one of the two nodes transforms the system into a single node system, eliminating the communication between the nodes as illustrated in Figure 3.
Preferably, the single node system according to the invention comprises the interface units of only one of the nodes illustrated in Figure 1. Alternatively, the single node system according to the invention may comprise the interface units of both nodes illustrated in Figure 1 , mapping the interface units of the eliminated node on the remaining node (or connecting them to the PCI bus of the latter), thus implementing a single node system with the same interface units of the double node system of Figure 1.
In order to reduce the temperature of the system according to the invention during operation, it is provided with a heatsink plate, shaped and sized in such a way to operate as passive cooling structure. It has to be capable to create "thermal paths" (e.g., through selection of variable thicknesses on the plate) for heat generated by the "hot spots" of the board onto which the system electronics is mounted. The heatsink plate, made of aluminium, allows the system according to the invention to operate in environment with temperature up to 70 0C. The preferred embodiments have been above described and some modifications of this invention have been suggested, but it should be understood that those skilled in the art can make other variations and changes, without so departing from the related scope of protection, as defined by the attached claims.

Claims

1. Electronic processing system for aid to unmanned navigation, in particular unmanned air navigation, comprising one or more processing nodes (1 , 2), each connected to a respective system controller (4, 5), in turn connected to memory means (8, 9, 10, 11 , 12, 13) through a first communication channel or bus (6, 7), characterised in that the system controller (4, 5) of each one of said one or more nodes (1, 2) is connected, through a respective PCI bus (23, 24), to a FPGA device (3) incorporating first I/O interface means (31 , 32, 33), the FPGA device (3) further comprising, for each one of said one or more nodes (1, 2), a PCI communication unit (301) connected to the corresponding system controller (4, 5), and first means (303, 304, 305, 306, 312) of control between the respective PCI bus (23, 24) and said first I/O interface means (31 , 32, 33). 2. System according to claim 1 , characterised in that said processing nodes (1 , 2) are at least two independent from each other, and in that the FPGA device (3) implements communication between said at least two nodes (1 , 2) through a shared memory architecture, comprising a shared memory unit (313), preferably integrated in said memory means (8, 9, 10, 11 , 12, 13), accessible by the PCI buses (23, 24) of said at least two nodes (1 , 2) through an arbiter (314) to which respective memory managers (315, 316), operating as interfaces of control between the respective PCI buses (23, 24) of said at least two nodes (1 ,
2) and the shared memory unit (313), connect.
3. System according to claim 2, characterised in that the arbiter
(314) manages accesses of said memory managers (315, 316) to the shared memory unit (313) according to a round robin scheduling algorithm.
4. System according to claim 2 or 3, characterised in that the arbiter (314) and said memory managers (315, 316) are implemented on programmable logic device (FPGA) by means of the VHDL language.
5. System according to any one of the preceding claims, characterised in that the FPGA device (3) further comprises a system logic reset unit (317) and/or a power management unit (318) and/or at least one unit (319, 320) for checking operation of said one or more nodes (1 , 2).
6. System according to any one of the preceding claims, characterised in that the FPGA device (3) further comprises a board-to- board wide band communication unit (321), for carrying out the connection with at least one external, preferably identical, system, more preferably connected so as to execute processing in parallel.
7. System according to any one of the preceding claims, ' characterised in that said first I/O interface means comprises or consists in one or more units selected from the group comprising RS 232 interface unit (31), RS 422/485 interface unit (32), and general purpose digital interface unit (33), preferably in LVTTL technology, more preferably with 12 input ports and 6 output ports, said first control means (303, 304, 305, 306, 312) of the FPGA device (3) comprising state machines and registers necessary to operations of interface between the respective PCI bus (23, 24) and said one or more units.
8. System according to any one of the preceding claims, characterised in that each one of said one or more nodes (1 , 2) is provided with at least one CPU, preferably operating up to 1 GHz, more preferably an ATMEL PowerPC 7447A CPU with AltiVec Technology.
9. System according to any one of the preceding claims, characterised in that each first bus (6, 7) is a 32 bit one, preferably operating up to 66MHz.
10. System according to any one of the preceding claims, characterised in that said memory means comprises or consists of one or more, preferably two, banks (8, 9) of 256 MB SDRAM memory with EDAC - Error Detection And Correction, more preferably operating up to 100 MHz, and/or of one or more, preferably two, Flash non-volatile memories (10, 11 , 12, 13), more preferably of 4 MB.
11. System according to any one of the preceding claims, characterised in that each PCI bus (23, 24) is a 32 bit one, preferably operating up to 66MHz.
12. System according to any one of the preceding claims, characterised in that the FPGA device (3) is a Xilinx XQ2V6000-
4CF1144M.
13. System according to any one of the preceding claims, characterised in that it comprises cPCI connectors means (29, 30), to which said first I/O interface means (31 , 32, 33) is connected.
14. System according to claim 13, characterised in that at least one PCl bus (24) is connected to said cPCI connectors means (29, 30),
15. System according to claim 13 or 14, when depending on claim 6, characterised in that said board-to-board communication unit (321) is connected to said cPCI connectors means (29, 30), preferably through 64 pins of the FPGA device (3).
16. System according to any one of the preceding claims, characterised in that the FPGA device (3) is connected to second communication means (34) and further comprises, for at least one processing node (1), second means (311) of control between the respective PCI bus (6) and said second communication means (34).
17. System according to claim 16, characterised in that said second communication means (34) comprises or consists of at least one
ARINC 429 communication unit (34), preferably provided with a transmission channel and with a reception channel, said first second (311) of control of the FPGA device (3) comprising state machines and registers necessary to operations of interface between the respective PCI bus (23, 24) and said at least one ARINC 429 communication unit (34).
18. System according to claim 16 or 17, when depending on claim 14, characterised in that said second communication means (34) are connected to said cPCI connectors means(29, 30).
19. System according to any one of the preceding claims, characterised in that it comprises at least one PMC (PCI Mezzanine Card) board (25, 26) connected to a system controller (4, 5) through the respective PCI bus (23, 24).
20. System according to claim 19, when depending on claim 14, characterised in that said at least one PMC board (25, 26) is connected to said cPCI connectors means (29, 30).
21. System according to any one of the preceding claims, characterised in that it comprises at least one fast Ethernet 10/100 communication controller (27) connected to a system controller (4, 5) through the respective PCI bus (23, 24).
22. System according to claim 21 , when depending on claim 14, characterised in that said at least one fast Ethernet 10/100 communication controller (27) is connected to said cPCI connectors means (29, 30).
23. System according to any one of the preceding claims, characterised in that it comprises at least one MIL-STD communication controller (28) with double redundancy 1553/1760, connected to a respective PCI bus (23), the FPGA device (3) comprising at least one management unit (307, 308) managing the communication of the E MIL- 1553 xceivers (transceivers - trasmitters-receivers).
24. System according to claim 23, when depending on claim 14, characterised in that said at least one MIL-STD communication controller (28) with double redundancy 1553/1760 is connected to said cPCI connectors means (29, 30).
25. System according to any one of the preceding claims, characterised in that each system controller (4, 5) is further connected, through a respective second bus (14, 15), preferably a 64 bit one, more preferably operating up to 66MHz, to an EEPROM memory (16, 17), preferably of 256 byte, to an AD (analog-to-digital) converter (18, 19), and to a DA (digital-to-analog) converter (20, 21).
26. System according to claim 25, characterised in that each system controller (4, 5) is further connected, through the respective second bus (14, 15), to at least one clock signal generator (22).
27. System according to any one of the preceding claims, characterised in that it is mounted onto a heatsink plate, preferably of aluminium, shaped and sized in such a way to operate as passive cooling structure capable to create "thermal paths" for heat generated by "hot spots" of the board onto which the system electronics is mounted.
PCT/IT2009/000160 2008-04-18 2009-04-10 Electronic processing system for aid to unmanned navigation in particular unmanned air navigation Ceased WO2009128112A1 (en)

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IT000208A ITRM20080208A1 (en) 2008-04-18 2008-04-18 ELECTRONIC PROCESSING SYSTEM FOR NAVIGATION ASSISTANCE, IN PARTICULAR AIR, WITHOUT CREW
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