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WO2009125250A1 - Integrated circuit package, method of manufacturing an integrated circuit package and printed circuit board - Google Patents

Integrated circuit package, method of manufacturing an integrated circuit package and printed circuit board Download PDF

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Publication number
WO2009125250A1
WO2009125250A1 PCT/IB2008/051381 IB2008051381W WO2009125250A1 WO 2009125250 A1 WO2009125250 A1 WO 2009125250A1 IB 2008051381 W IB2008051381 W IB 2008051381W WO 2009125250 A1 WO2009125250 A1 WO 2009125250A1
Authority
WO
WIPO (PCT)
Prior art keywords
cover
lead
die
integrated circuit
circuit package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2008/051381
Other languages
French (fr)
Inventor
Robert Bauer
Anton Kolbeck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to PCT/IB2008/051381 priority Critical patent/WO2009125250A1/en
Publication of WO2009125250A1 publication Critical patent/WO2009125250A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H10W70/421
    • H10W70/457
    • H10W74/014
    • H10W74/019
    • H10W74/111
    • H10W72/0198
    • H10W72/07504
    • H10W74/00
    • H10W90/756

Definitions

  • This invention relates to an integrated circuit package, to a method of manufacturing an integrated circuit package and to a printed circuit board.
  • Integrated circuit (IC) package are typically manufactured by providing an integrated circuit on a die and packaging the die into a package.
  • IC packages such as the Quad Flat package No Leads (QFN) package, are known which are manufactured by e.g. a MAP (Molded Array Package) process.
  • MAP process includes providing a lead frame which includes an array of die attach flag and leads. Dies are placed onto the die attach flags in the frame and contacts on the dies are connected to the leads part surrounding the respective die of by bond-wires. A cover is moulded on the die side of the lead frame. The dies are thus is at one side covered by the moulded cover and at the other side by the die attach flag.
  • the present invention provides an integrated circuit package, a method of manufacturing an integrated circuit package and a printed circuit board as described in the accompanying claims.
  • Figure 1 schematically shows a top view of an example of an embodiment of a lead frame.
  • Figures 2-6 show cross-sectional views of an example of an embodiment of an integrated circuit package in different stages of manufacturing, taken along the line N-Il in FIG.1 .
  • Figures 7-10 show cross-sectional views of an example of an embodiment of an integrated circuit package illustrating a first example of dicing thereof.
  • Figures 11-14 show cross-sectional views of an example of an embodiment of an integrated circuit package illustrating a second example of dicing thereof.
  • Figures 15-16 show cross-sectional views of another example of an embodiment of an integrated circuit package.
  • one or more leads 14 may be provided, which are electrically connected to at least a part of a die 18, in this example via bond-wires 20.
  • the lead 14 may have one or more than one exposed surface 24 at the side where the cover 26 has been separated from a body 22.
  • the lead 14 may for example be provided by providing a lead plate, e.g in this example lead frame 10.
  • the lead frame 10 may be a frame of an electrically conducting material, e.g. a metal, as shown in FIG. 2, provided on a film 16.
  • the lead frame may be a leadless leadframe, such as a Quad Flat No Lead (QFN) lead frame.
  • the lead frame 10 may include an array, in this example a two-dimensional array, i.e. a matrix, of elements (in FIGs. 1-4, the dashed lines indicate the separation between the elements).
  • the elements in the matrix may include parts of the lead frame which may be formed into leads 14 (in the figures, the parts and the lead are indicated with the same reference number, to facilitate the understanding of the processing).
  • the elements may each include a die pad, in this example die attach flag 12.
  • the die attach flag may be used to provide cooling to the die and/or to provide current to the die.
  • a die 18 may be provided on a respective die pad and the lead may be connected electrically to at least a part of the die.
  • the dies 18 may be provided on a the respective die attach flags 12 and be attached to the die attach flags 12 using a known processing. As shown in FIG. 3, the backside of the die 18 may be in contact with the die attach flag 12.
  • the dies may for instance be made of a semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
  • an integrated circuit (not shown) may be present, for example manufactured using known semiconductor processing techniques.
  • the integrated circuit may be electrically connected the leads 14, for example by connecting pads on the die (not shown) to the leads 14 via bond-wires 20, which in this example are provided to extend from the front-side of the die to a respective lead 14, as shown in FIG. 3.
  • the cover 26 may for example be formed by moulding a body 22 on the array of leads and dies and separating the body in two or more covers. Each of the covers may cover one or more than one die and one or more than one lead.
  • the lead may be formed by cutting the lead plate to obtain a lead in a first integrated circuit package and a lead in a second integrated circuit package.
  • parts of the lead frame 10 may be separated to form the leads.
  • the parts which will form the leads may have a comb like structure with fingers and an interconnecting part which connects the fingers.
  • the part may be divided into sub-parts by cutting through the fingers, thus obtaining a plurality of separate fingers, each of which forms a lead, in one element and a part with protrusions in the abutting element, which forms another lead 14.
  • the method may include the formation of a cover 26 from a body 22.
  • the covers may be formed separating the cover 26 from other parts of the body 22.
  • the packages may be singulated by cutting the cover 26 and the leads 14 at the appropriate place, e.g. as indicated with the vertical dashed lines in FIGs. 2-4 thereby separating the cover from the body and separating the leads 14 from the lead frame 10.
  • the cover 26 has a cut-off side.
  • the body 22 may for example be a moulded block formed by moulding a mouldable compound on the lead frame 10 and the dies 18. As shown in FIG.
  • the body 22 may for example be formed on the die side of the lead frame 10, thus covering the dies 18 (as well as the leads 14 and bond-wires 20). As shown, the leads 14 and the die attach flag 12 cover a part of the bottom-surface of the body 22. As is shown in FIG. 4, the dies 18 are thus covered at the front-side by the body 22, whereas at their back-side the dies 18 are covered by the die attach flag 12. After forming the body 22, the film 16 may be removed, thus exposing the die attach flag 21 and the leads 14 at the bottom of the body 22.
  • the leads 14 have an exposed surface 24 at the side where the cover has been separated from the body.
  • the exposed surface 24 may be provided with a surface protection layer 25 which protects the exposed surface against oxidation.
  • the surface protection layer 25 may be made of solderable material.
  • an example of an integrated circuit package 1 may be obtained which includes a cover 26 formed from a body 22.
  • the integrated circuit package 1 is mounted on a printed circuit board (PCB) 35.
  • the package 1 is mounted to electrically conducting layer 34, for example a copper layer, via a solder joint 28 which provides an electrical connection between the leads 14 and the layer 34.
  • the PCB may further provided with an base layer 32 which provides a support for the copper layer 34 and the package or packages mounted thereon.
  • the cover 26 has a side (with an outer surface 27) where the cover has been separated from another part of the body.
  • a die 18 is at least partially covered by the cover and a lead 14 is electrically connected to at least a part of the die 18.
  • the lead has one or more than one exposed surface 24 at the side where the cover 26 has been separated from another part of the body 22.
  • the exposed surface 24 is provided with a surface protection layer 25 which protects the exposed surface against oxidation.
  • the surface protection layer is made of a solderable material.
  • Soldering can be simplified because the surface protection layer on the one hand prevents the exposed surface 24 of the lead 14 from oxidizing.
  • the lead 14 will be of bare copper, on which an a oxide layer is rapidly build up when exposed to air.
  • soldering an oxidized exposed surface is difficult, as the oxide layer inhibits proper wetting.
  • no visible solder meniscus will be formed, and visual inspection of the solder joint is not possible, thus complication inspection of the solder joint and requiring other means of inspection, such as the application of x-ray systems.
  • solderable since the exposed surface 24 solderable, a solder layer will be formed on the exposed surface 24, and hence at the part of this surface 24 at the side of where the cover 26 has been separated from the body 22. Accordingly, visual inspection of the solder joint will be visible and the inspection can be relatively simple.
  • the exposed surface 24 may be flush with the outer surface 27 as for example in a QFN package or other type of no lead package.
  • the cover 26 may be made from a non-solderable material.
  • the cover 26 may for example be made of a material that inhibits wetting of the surface 27. Thereby, the flow of the solder at the side where the cover 26 has been separated will be confined to the exposed surface 24, facilitating a visual inspection of the solder joint.
  • the lead 14 and/or the die 12 may be provided at a backside surface of the cover 26, while a front side of the cover 26 covers at least a front side surface of the die 12.
  • the cover (and the leads) may be separated from the other part of the body, and in the example of figs.
  • the lead plate may be cut firsts and separating the cover from other parts of the body may be performed after the lead plate has been cut provided with the exposed surface with the surface protection layer.
  • a method for separating the compounds 26 from the body 22 is shown.
  • the lead 14 may for example be cut from the back side of the cover towards the front-side of the cover 26.
  • the lead 14 is partially cut by making an incision in the lead 14 with a saw 40.
  • the saw may cut from the backside towards the front-side.
  • the depth of the incision is less than the thickness of the lead 14 at the position of the incision.
  • the walls of the incision may be provided with a surface protection layer 24 which protects against oxidation and is solderable.
  • the surface protection layer 24 may for example be applied by electroplating and for example be a metal. As shown in FIG.
  • the body 22 and the lead 14 may then be fully cut, for example in a direction (as indicated with the arrows) from the front-side towards the backside or in a direction from the backside towards the front-side, resulting in a cover 26 separated from the other parts of the body 22, as shown in FIG. 10.
  • the saw 42 used for the final cut may make an incision which is smaller than or has the same width as the partial incision made with the saw 40. For example, if the final cutting is done from top to bottom, the saw width may be the same for the partial cut and the final cut and if final cutting is done from bottom to top, the blade may be smaller than the blade used for the partial cut.
  • the lead 14 is fully cut by making an incision in the lead 14 with a saw 40 (and the body 22 may be not cut at all or be partially cut).
  • the depth of the incision is at least as much as the thickness of the lead 14 at the position of the incision and may be less than the combined thickness of the lead 14 and the body 22 at that position.
  • the saw 40 may cut from the backside towards the front-side.
  • the walls of the incision may be provided with a surface protection layer 24 which protects against oxidation and is solderable.
  • the surface protection layer 24 may for example be applied by electroless plating or coating the walls of the incision, for example with an OSP (organic surface protection). As shown, the process used may be such that the surface protection layer 24 does not stick to the part of the walls that are in the body 22. As shown in FIG. 13, the body 22 may then be fully cut, for example (as indicated with the arrows) in a direction from the front-side towards the backside or in a direction from the backside towards the front-side, resulting in a cover 26 separated from the other parts of the body 22, as shown in FIG. 14. As illustrated in FIG. 13, the saw 42 used for the final cut may make an incision which is smaller than or has the same width as the partial incision made with the saw 40. . For example, if the final cutting is done from top to bottom, the saw width may be the same for the partial cut and the final cut and if final cutting is done from bottom to top, the blade may be smaller than the blade used for the partial cut.
  • OSP organic surface protection
  • the bottom surface of the lead 14 facing away from the backside may be provided with a protection layer 29 prior to separating the compounds 26, as is illustrated in FIG. 15.
  • a protection layer may be present already on the lead frame 10 from the start on.
  • the bottom surface may for example be provided with a preplated protection layer, for example made of nickel/palladium (NiPd).
  • NiPd nickel/palladium
  • the material for the additional protection layer 24 may for example deposits on the bare, cutted surface only, and for instance selectively attach to copper and not to NiPd.
  • the additional protective layer 24 may be only present on the surface of the lead 14 that forms a part of the wall of the incision, whereas the bottom surface of the lead 14 remains covered by the pre-plated protection layer 29.
  • connections may be an type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise the connections may for example be direct connections or indirect connections. Also, instead of a single die, multiple dies may be provided in the package and, for example, be electrically connected in a manner suitable to provide a desired functionality.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim.
  • the terms "a” or "an,” as used herein, are defined as one or more than one.

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

An integrated circuit package (1 ) may include a cover (26) formed from a body (22), the cover having a side where the cover has been separated from another part of the body. A die (18) is at least partially covered by the cover. A lead (14) is electrically connected to at least a part of the die, the lead having at least one exposed surface at the side, the exposed surface being provided with a surface protection layer (24) which protects the exposed surface against oxidation, the surface protection layer being made of solderable material.

Description

Title : INTEGRATED CIRCUIT PACKAGE, METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE AND PRINTED CIRCUIT BOARD
Description
Field of the invention
This invention relates to an integrated circuit package, to a method of manufacturing an integrated circuit package and to a printed circuit board.
Background of the invention
Integrated circuit (IC) package are typically manufactured by providing an integrated circuit on a die and packaging the die into a package. IC packages, such as the Quad Flat package No Leads (QFN) package, are known which are manufactured by e.g. a MAP (Molded Array Package) process. Known MAP process includes providing a lead frame which includes an array of die attach flag and leads. Dies are placed onto the die attach flags in the frame and contacts on the dies are connected to the leads part surrounding the respective die of by bond-wires. A cover is moulded on the die side of the lead frame. The dies are thus is at one side covered by the moulded cover and at the other side by the die attach flag. Thereafter, packages are singulated or diced out of the array by sawing or punching the package out of the mould. However, a disadvantage of such a process is that is difficult to solder the package on to a printed circuit board (PCB) in the following solder PCB process.
Summary of the invention
The present invention provides an integrated circuit package, a method of manufacturing an integrated circuit package and a printed circuit board as described in the accompanying claims.
Specific embodiments of the invention are set forth in the dependent claims.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
Brief description of the drawings
Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Figure 1 schematically shows a top view of an example of an embodiment of a lead frame. Figures 2-6 show cross-sectional views of an example of an embodiment of an integrated circuit package in different stages of manufacturing, taken along the line N-Il in FIG.1 .
Figures 7-10 show cross-sectional views of an example of an embodiment of an integrated circuit package illustrating a first example of dicing thereof.
Figures 11-14 show cross-sectional views of an example of an embodiment of an integrated circuit package illustrating a second example of dicing thereof. Figures 15-16 show cross-sectional views of another example of an embodiment of an integrated circuit package.
Detailed description of the preferred embodiments
Referring to the example of FIGs. 4-5, an example of a method of manufacturing an integrated circuit package is illustrated. As shown in FIG. 4, one or more leads 14 may be provided, which are electrically connected to at least a part of a die 18, in this example via bond-wires 20. As shown in FIG. 5, the lead 14 may have one or more than one exposed surface 24 at the side where the cover 26 has been separated from a body 22.
As shown in FIG. 1 , the lead 14 may for example be provided by providing a lead plate, e.g in this example lead frame 10. The lead frame 10 may be a frame of an electrically conducting material, e.g. a metal, as shown in FIG. 2, provided on a film 16. The lead frame may be a leadless leadframe, such as a Quad Flat No Lead (QFN) lead frame. The lead frame 10 may include an array, in this example a two-dimensional array, i.e. a matrix, of elements (in FIGs. 1-4, the dashed lines indicate the separation between the elements). The elements in the matrix may include parts of the lead frame which may be formed into leads 14 (in the figures, the parts and the lead are indicated with the same reference number, to facilitate the understanding of the processing).
As shown, the elements may each include a die pad, in this example die attach flag 12. The die attach flag may be used to provide cooling to the die and/or to provide current to the die. A die 18 may be provided on a respective die pad and the lead may be connected electrically to at least a part of the die. The dies 18 may be provided on a the respective die attach flags 12 and be attached to the die attach flags 12 using a known processing. As shown in FIG. 3, the backside of the die 18 may be in contact with the die attach flag 12. The dies may for instance be made of a semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. On the front-side of the dies, an integrated circuit (not shown) may be present, for example manufactured using known semiconductor processing techniques. The integrated circuit may be electrically connected the leads 14, for example by connecting pads on the die (not shown) to the leads 14 via bond-wires 20, which in this example are provided to extend from the front-side of the die to a respective lead 14, as shown in FIG. 3.
The cover 26 may for example be formed by moulding a body 22 on the array of leads and dies and separating the body in two or more covers. Each of the covers may cover one or more than one die and one or more than one lead. The lead may be formed by cutting the lead plate to obtain a lead in a first integrated circuit package and a lead in a second integrated circuit package. In the shown examples for instance, when separating, parts of the lead frame 10 may be separated to form the leads. For instance, as shown in FIG. 1 , the parts which will form the leads, may have a comb like structure with fingers and an interconnecting part which connects the fingers. As indicated, the part may be divided into sub-parts by cutting through the fingers, thus obtaining a plurality of separate fingers, each of which forms a lead, in one element and a part with protrusions in the abutting element, which forms another lead 14.
As illustrated in FIGs. 4 and 5, the method may include the formation of a cover 26 from a body 22. The covers may be formed separating the cover 26 from other parts of the body 22. For instance, as shown in FIG. 5, the packages may be singulated by cutting the cover 26 and the leads 14 at the appropriate place, e.g. as indicated with the vertical dashed lines in FIGs. 2-4 thereby separating the cover from the body and separating the leads 14 from the lead frame 10. As indicated, at the place where the cover is cut from the body, the cover 26 has a cut-off side. The body 22 may for example be a moulded block formed by moulding a mouldable compound on the lead frame 10 and the dies 18. As shown in FIG. 4, the body 22 may for example be formed on the die side of the lead frame 10, thus covering the dies 18 (as well as the leads 14 and bond-wires 20). As shown, the leads 14 and the die attach flag 12 cover a part of the bottom-surface of the body 22. As is shown in FIG. 4, the dies 18 are thus covered at the front-side by the body 22, whereas at their back-side the dies 18 are covered by the die attach flag 12. After forming the body 22, the film 16 may be removed, thus exposing the die attach flag 21 and the leads 14 at the bottom of the body 22.
As shown in FIG. 5, after separating the cover 26 from other parts of the body 22, the leads 14 have an exposed surface 24 at the side where the cover has been separated from the body.. The exposed surface 24 may be provided with a surface protection layer 25 which protects the exposed surface against oxidation. The surface protection layer 25 may be made of solderable material.
As shown in FIG. 6, with the above described example of a method an example of an integrated circuit package 1 may be obtained which includes a cover 26 formed from a body 22. in the example of FIG. 6, the integrated circuit package 1 is mounted on a printed circuit board (PCB) 35. As shown, the package 1 is mounted to electrically conducting layer 34, for example a copper layer, via a solder joint 28 which provides an electrical connection between the leads 14 and the layer 34. As shown, the PCB may further provided with an base layer 32 which provides a support for the copper layer 34 and the package or packages mounted thereon.
As shown in the example of FIG. 6, the cover 26 has a side (with an outer surface 27) where the cover has been separated from another part of the body. A die 18 is at least partially covered by the cover and a lead 14 is electrically connected to at least a part of the die 18. The lead has one or more than one exposed surface 24 at the side where the cover 26 has been separated from another part of the body 22. The exposed surface 24 is provided with a surface protection layer 25 which protects the exposed surface against oxidation. The surface protection layer is made of a solderable material.
Soldering can be simplified because the surface protection layer on the one hand prevents the exposed surface 24 of the lead 14 from oxidizing. (Typically, the lead 14 will be of bare copper, on which an a oxide layer is rapidly build up when exposed to air.) It will be apparent that soldering an oxidized exposed surface is difficult, as the oxide layer inhibits proper wetting. In addition, since in case of oxidisation solder is not present on the exposed surface 24 no visible solder meniscus will be formed, and visual inspection of the solder joint is not possible, thus complication inspection of the solder joint and requiring other means of inspection, such as the application of x-ray systems. Furthermore, since the exposed surface 24 solderable, a solder layer will be formed on the exposed surface 24, and hence at the part of this surface 24 at the side of where the cover 26 has been separated from the body 22. Accordingly, visual inspection of the solder joint will be visible and the inspection can be relatively simple.
As shown in FIG. 6, the exposed surface 24 may be flush with the outer surface 27 as for example in a QFN package or other type of no lead package. The cover 26 may be made from a non-solderable material. The cover 26 may for example be made of a material that inhibits wetting of the surface 27. Thereby, the flow of the solder at the side where the cover 26 has been separated will be confined to the exposed surface 24, facilitating a visual inspection of the solder joint. As shown in FIG. 6, the lead 14 and/or the die 12 may be provided at a backside surface of the cover 26, while a front side of the cover 26 covers at least a front side surface of the die 12. The cover (and the leads) may be separated from the other part of the body, and in the example of figs. 1-6 from the other elements in the matrix, in any manner suitable for the specific implementation. For example, the lead plate may be cut firsts and separating the cover from other parts of the body may be performed after the lead plate has been cut provided with the exposed surface with the surface protection layer. Referring to figs. 7-10, an example of a method for separating the compounds 26 from the body 22 is shown.
As shown in FIG. 7, for example, the lead 14 may for example be cut from the back side of the cover towards the front-side of the cover 26. In this example, the lead 14 is partially cut by making an incision in the lead 14 with a saw 40. As indicated with the arrow, the saw may cut from the backside towards the front-side. The depth of the incision is less than the thickness of the lead 14 at the position of the incision. As shown in FIG. 8, the walls of the incision may be provided with a surface protection layer 24 which protects against oxidation and is solderable. The surface protection layer 24 may for example be applied by electroplating and for example be a metal. As shown in FIG. 9, the body 22 and the lead 14 may then be fully cut, for example in a direction (as indicated with the arrows) from the front-side towards the backside or in a direction from the backside towards the front-side, resulting in a cover 26 separated from the other parts of the body 22, as shown in FIG. 10. As illustrated in FIG. 9, the saw 42 used for the final cut may make an incision which is smaller than or has the same width as the partial incision made with the saw 40. For example, if the final cutting is done from top to bottom, the saw width may be the same for the partial cut and the final cut and if final cutting is done from bottom to top, the blade may be smaller than the blade used for the partial cut.
Referring to figs. 11-14, another example of a method for separating the compounds 26 from the body 22 is shown. In this example, the lead 14 is fully cut by making an incision in the lead 14 with a saw 40 (and the body 22 may be not cut at all or be partially cut). The depth of the incision is at least as much as the thickness of the lead 14 at the position of the incision and may be less than the combined thickness of the lead 14 and the body 22 at that position. As indicated with the arrow, the saw 40 may cut from the backside towards the front-side. As shown in FIG. 12, the walls of the incision may be provided with a surface protection layer 24 which protects against oxidation and is solderable. The surface protection layer 24 may for example be applied by electroless plating or coating the walls of the incision, for example with an OSP (organic surface protection). As shown, the process used may be such that the surface protection layer 24 does not stick to the part of the walls that are in the body 22. As shown in FIG. 13, the body 22 may then be fully cut, for example (as indicated with the arrows) in a direction from the front-side towards the backside or in a direction from the backside towards the front-side, resulting in a cover 26 separated from the other parts of the body 22, as shown in FIG. 14. As illustrated in FIG. 13, the saw 42 used for the final cut may make an incision which is smaller than or has the same width as the partial incision made with the saw 40. . For example, if the final cutting is done from top to bottom, the saw width may be the same for the partial cut and the final cut and if final cutting is done from bottom to top, the blade may be smaller than the blade used for the partial cut.
Referring to the examples of FIGs. 15 and 16, the bottom surface of the lead 14 facing away from the backside may be provided with a protection layer 29 prior to separating the compounds 26, as is illustrated in FIG. 15. For example, a protection layer may be present already on the lead frame 10 from the start on. The bottom surface may for example be provided with a preplated protection layer, for example made of nickel/palladium (NiPd). After cutting the lead 14, the exposed surface of the lead 14 forming the wall of the incision may be provided with an additional protection layer 24.
The material for the additional protection layer 24 may for example deposits on the bare, cutted surface only, and for instance selectively attach to copper and not to NiPd. Thus, as illustrated in FIG. 16, the additional protective layer 24 may be only present on the surface of the lead 14 that forms a part of the wall of the incision, whereas the bottom surface of the lead 14 remains covered by the pre-plated protection layer 29.
In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, the connections may be an type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise the connections may for example be direct connections or indirect connections. Also, instead of a single die, multiple dies may be provided in the package and, for example, be electrically connected in a manner suitable to provide a desired functionality.
The terms "front," "back," "top," "bottom," "over," "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an." The same holds true for the use of definite articles. Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

Claims
1. An integrated circuit package (1 ), including: a cover (26) formed from a body (22), said cover having a side where the cover has been separated from another part of the body; a die (18) at least partially covered by said cover; a lead (14) electrically connected to at least a part of said die, said lead having at least one exposed surface at said side, said exposed surface being provided with a surface protection layer (24) which protects said exposed surface against oxidation, said surface protection layer being made of solderable material.
2. An intergrated circuit package as claimed in claim 1 , wherein said cover (26) is made from a non-solderable material.
3. An intergrated circuit package as claimed in claim 1 or 2, wherein said exposed surface is flush with an outer surface (27) of the cover (26) at said side.
4. An integrated circuit package as claimed in any one of the preceding claims, wherein said cover has a backside surface on which said lead and/or said die are provided, said cover having a front side covering at least a front side surface of said die .
5. An integrated circuit package as claimed in any one of the preceding claims, wherein the integrated circuit package has been separated from an array by: separating said lead from another part of a lead body, thereby creating said exposed surface; providing said exposed surface with said surface protection layer; and separating said cover from said body.
6. An integrated circuit package as claimed in claim 3 and 4, wherein said cover has been separated from said body by cutting through said body from said backside after said exposed surface has been provided with said surface protection layer.
7. An integrated circuit package as claimed in claim 3 and 4, wherein said cover has been separated from said body by cutting through said body from said front-side.
8. A method of manufacturing an integrated circuit package, including: forming a cover (260 from a body (22), said forming including separating said cover from other parts of said body thus creating a side where the cover has been separated from another part of said body; covering a die (18) at least partially with said cover; providing a lead (14) which is electrically connected to at least a part of said die, said lead having at least one exposed surface at said side; providing said exposed surface with a surface protection layer which protects said exposed surface against oxidation, said surface protection layer being made of solderable material.
9. A method as claimed in claim 8, including: providing said die on a die pad; and connecting said lead to at least a part of said die.
10. A method as claimed in claim 8 or 9, wherein forming a cover from a body includes: moulding said body on an array of leads and dies; separating said body in at least two covers, each of said covers covering at least one die and at least one lead.
11. A method as claimed in any one of claims 8-10, wherein providing said leads includes providing a lead plate and including: cutting said lead plate to obtain a lead in a first integrated circuit package and a lead in a second integrated circuit package
12. A method as claimed in the preceding claims, wherein cutting said lead plate includes providing an incision in said body.
13. A method as claimed in claims 11 or 12, wherein separating said cover from other parts of said body is performed after cutting said lead plate and providing said exposed surface with said surface protection layer.
14. A method as claimed in any one of claims 8-13, wherein said die and said lead are provided on a backside of said cover and separating said cover from other parts of said body includes: cutting said body in a direction from a front-side towards said backside.
15. A method as claimed in any one of claims 8-14, wherein said die and said lead are provided on a backside of said cover and separating said cover from other parts of said body includes: cutting said body in a direction from said backside towards a front-side.
16. A method as claimed in any one of claims 8-15, including: providing a lead frame including said lead and providing said die on a die pad.
17. A printed circuit board (35) provided with an integrated circuit package (1 ) as claimed in any one of claims 1-7.
PCT/IB2008/051381 2008-04-11 2008-04-11 Integrated circuit package, method of manufacturing an integrated circuit package and printed circuit board Ceased WO2009125250A1 (en)

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US12500150B2 (en) * 2016-05-19 2025-12-16 Stmicroelectronics S.R.L. Semiconductor package with wettable flank
US20210143089A1 (en) * 2016-05-19 2021-05-13 Stmicroelectronics S.R.L. Semiconductor package with wettable flank
US9847283B1 (en) 2016-11-06 2017-12-19 Nexperia B.V. Semiconductor device with wettable corner leads
EP3355348A1 (en) * 2017-01-26 2018-08-01 Sensirion AG Method for manufacturing a semiconductor package
US11127660B2 (en) 2018-12-31 2021-09-21 Microchip Technology Incorporated Surface-mount integrated circuit package with coated surfaces for improved solder connection
WO2020142263A3 (en) * 2018-12-31 2020-08-13 Microchip Technology Incorporated Surface-mount integrated circuit package with coated surfaces for improved solder connection
US11101200B2 (en) 2018-12-31 2021-08-24 Microchip Technology Incorporated Surface-mount integrated circuit package with coated surfaces for improved solder connection
WO2020185193A1 (en) 2019-03-08 2020-09-17 Siliconix Incorporated Semiconductor package having side wall plating
JP2022531059A (en) * 2019-03-08 2022-07-06 シリコニックス インコーポレイテッド Semiconductor package with side wall plating layer
EP3935663A4 (en) * 2019-03-08 2022-11-02 Siliconix Incorporated SEMICONDUCTOR PACKAGE HAVING SIDE WALL PLATING
JP7473560B2 (en) 2019-03-08 2024-04-23 シリコニックス インコーポレイテッド Semiconductor package having sidewall plating layer
US12211704B2 (en) 2019-03-08 2025-01-28 Siliconix Incorporated Semiconductor package having side wall plating
US12224232B2 (en) 2019-03-08 2025-02-11 Siliconix Incorporated Semiconductor package having side wall plating
IL285950B1 (en) * 2019-03-08 2025-03-01 Siliconix Incorporated Semiconductor package having side wall plating
IL285950B2 (en) * 2019-03-08 2025-07-01 Siliconix Incorporated Semiconductor package with coating on the side walls
CN112289749A (en) * 2019-07-24 2021-01-29 英飞凌科技股份有限公司 Selective corrosion protected package with electrical connection structure

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