WO2009110136A1 - 表示装置用基板、その製造方法、表示装置、多層配線の形成方法及び多層配線基板 - Google Patents
表示装置用基板、その製造方法、表示装置、多層配線の形成方法及び多層配線基板 Download PDFInfo
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- WO2009110136A1 WO2009110136A1 PCT/JP2008/069689 JP2008069689W WO2009110136A1 WO 2009110136 A1 WO2009110136 A1 WO 2009110136A1 JP 2008069689 W JP2008069689 W JP 2008069689W WO 2009110136 A1 WO2009110136 A1 WO 2009110136A1
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- insulating film
- display device
- film
- inorganic insulating
- inorganic
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/02—Details
- H05B33/04—Sealing arrangements, e.g. against humidity
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates to a display device substrate, a manufacturing method thereof, a display device, a multilayer wiring formation method, and a multilayer wiring substrate. More specifically, it has a terminal portion provided with a connection terminal for FPC connection and the like, and has a multilayer wiring structure, that is, a lower layer side of the terminal portion in the frame region, a peripheral circuit, a circuit in the pixel region, etc.
- a substrate for a display device suitable for a liquid crystal display panel or an organic EL panel which can increase the degree of integration and lead to narrowing of the panel, pixel memory, and the like by routing the wiring of the multilayer structure, and a method for manufacturing the same
- the present invention relates to a display device, a method for forming a multilayer wiring, and a multilayer wiring substrate.
- FIG. 7A and 7B are schematic cross-sectional views in a frame region of a conventional liquid crystal display device, where FIG. 7A shows a terminal portion and FIG. 7B shows a peripheral circuit region.
- a conventional liquid crystal display device 600 has a structure in which a TFT substrate 111 that is a substrate for a display device and an FPC substrate 170 are connected to each other by an ACF 180 at a terminal portion.
- the TFT substrate 111 has a base coat film 122, a gate insulating film 124, a gate electrode 125, and an inorganic insulating film functioning as an interlayer insulating film on the insulating substrate 121 in the terminal portion.
- a connection terminal (external connection terminal) 126 including the first wiring layer 161, and an organic insulating film 151a functioning as a protective film are stacked in this order from the insulating substrate 121 side.
- a pad portion 127 is provided at the end of the connection terminal 126.
- the TFT substrate 111 has a base coat film 122, a semiconductor layer 123, a gate insulating film 124, a gate electrode 125, and an interlayer on the insulating substrate 121 in the peripheral circuit region.
- An inorganic insulating film 141 that functions as an insulating film, a source / drain electrode 128 and a lead wiring 130 a made of the first wiring layer 161, an organic insulating film 151 a that functions as an interlayer insulating film, and a lead wiring made of the second wiring layer 162 130b and the organic insulating film 151 functioning as a protective film are stacked in this order from the insulating substrate 121 side.
- the steps of the first wiring layer 161 and the TFT 129 on the lower layer side can be reduced, and the second wiring layer 162 on the upper layer side can be routed.
- a technique for preventing the second wiring layer 162 from being short-circuited has been proposed.
- an aluminum film used for wiring in a panel region that is, a pixel region (display region) is connected to a metal film located on the lower side of the aluminum film inside the panel, and the panel is formed using this metal film
- a metal film located on the lower side of the aluminum film inside the panel and the panel is formed using this metal film
- the side surface of the through-hole opening of the interlayer insulating film is prevented from being damaged during the O 2 plasma treatment to increase the hygroscopicity, and the lower first wiring and the upper layer are suppressed.
- the through-hole portion is formed before the resist is removed after the through-hole is formed in the insulating film.
- a method of forming a multilayer wiring including a step of filling a hole with an organic film, treating with O 2 plasma, and then treating with a resist stripping solution to remove the organic film filled with the resist is disclosed (for example, Patent Documents). 2). Japanese Patent Laid-Open No. 3-58019 JP-A-3-183756
- the method for forming the contact hole (via hole) 131c in the organic insulating film 151a is not a method using photosensitive etching that does not require a resist mask, but has a high fine processing accuracy.
- a method using a resist mask such as dry etching is employed, both the resist mask and the organic insulating film 151a are organic films, and the selection ratio between them is approximately the same. Therefore, in the resist mask ashing (peeling) step, The selectivity between the mask and the organic insulating film 151a cannot be obtained, and etching may not be performed properly. Specifically, when the resist mask is ashed, even the organic insulating film 151a may be removed by ashing.
- the organic insulating film 151a is formed using a photosensitive resin, the contact hole 131c is formed without using a resist mask, and the second wiring layer 162 immediately above the organic insulating film 151a is wet. Patterned using a process. As described above, in the conventional technique, there is room for improvement in terms of enabling fine processing of the wiring and suppressing the occurrence of poor connection between the upper and lower wirings. Further, even when an inorganic flattening film is used instead of the organic insulating film 151a, the same problem occurs.
- the organic film such as the organic insulating film 151a has a lower mechanical strength such as peel strength and hardness than the inorganic film (scratches are easily caused by external pressure).
- the film 151a When the film 151a is peeled off or damaged, the wiring located under the organic insulating film 151a is exposed, and as a result, the FPC substrate 170 is caused by corrosion due to moisture or the like, or by residue of the peeled organic insulating film 151a. Connection failure may occur, and there is room for improvement in terms of reliability. It is conceivable that the organic insulating film 151a is removed only at the terminal portion and the first wiring layer 161 is disposed as the uppermost layer. In this case, however, the reliability of the first wiring layer 161 is also affected by the influence of moisture from the outside. There is concern about the deterioration of sex.
- the present invention has been made in view of the above-described present situation, and can provide a display device substrate, a manufacturing method thereof, a display device, and a multi-layer wiring capable of miniaturizing wiring, suppressing connection failure, and improving the reliability of a display device.
- An object of the present invention is to provide a method for forming a multilayer wiring board and a multilayer wiring board.
- the inventors of the present invention are various about a display device substrate, a manufacturing method thereof, a display device, a method of forming a multilayer wiring, and a multilayer wiring substrate that are capable of miniaturizing wiring, suppressing connection failure, and improving the reliability of the display device.
- attention was paid to an organic insulating film used as an interlayer insulating film and a planarizing film.
- the organic insulating film alone is found to have inferior processability and mechanical strength compared to the inorganic insulating film, and more specifically, by using the organic insulating film in combination with the inorganic insulating film, more specifically, the organic insulating film
- the organic insulating film By using an organic / inorganic film laminate with an inorganic insulating film laminated directly on top, we found that it was possible to improve the workability and mechanical strength while utilizing the flatness of the organic insulating film. Thus, the present invention has been achieved.
- the present invention provides a display device substrate comprising at least one of a terminal portion provided with a connection terminal for connecting another external connection component and a peripheral circuit region provided with a peripheral circuit on an insulating substrate.
- the display device substrate is a display device substrate having an organic / inorganic film laminate in which an inorganic insulating film is laminated directly on an organic insulating film.
- the organic insulating film can be protected by the inorganic insulating film having excellent mechanical strength. Therefore, by disposing the organic / inorganic film laminate in the terminal portion, the organic insulating film can be used even when it is necessary to rework in the process of connecting the display device substrate to another circuit board or element, for example, an FPC board. Can be prevented from peeling off or being damaged. For this reason, the wiring layer located under the organic insulating film is exposed, and corrosion of the wiring layer due to moisture or the like can be suppressed. In addition, it is possible to suppress the occurrence of contact failure between the terminal and the external connection component such as the FPC due to the residue of the peeled organic insulating film. That is, according to the display device substrate of the present invention, a liquid crystal display device having excellent reliability can be realized.
- the inorganic insulating film can be used as a stopper material for resist mask ashing, as a method of forming a contact hole in the organic / inorganic film stack, a method including an ashing process, that is, a dry process with high microfabrication accuracy.
- a method using a resist mask such as etching becomes possible, and the wiring located in the lower layer of the organic / inorganic film stack, especially the wiring such as the routing wiring provided in the peripheral circuit area where fine processing is required, is fine and highly accurate. Can be formed.
- the organic insulating film can be made less susceptible to damage due to ashing, it is possible to suppress the occurrence of connection failure between the wirings disposed in the upper layer and the lower layer of the organic / inorganic film stack.
- upper means a side farther from the insulating substrate
- lower means a side closer to the insulating substrate. That is, the upper layer means a layer farther from the insulating substrate, while the lower layer means a layer closer to the insulating substrate.
- the configuration of the substrate for a display device of the present invention is not particularly limited as long as such a component is formed as essential, and other components may or may not be included. is not.
- a preferred embodiment of the display device substrate of the present invention will be described in detail below. The various forms shown below may be combined as appropriate.
- the display device substrate preferably includes the terminal portion and the peripheral circuit region. That is, the display device substrate preferably includes a terminal portion provided with a connection terminal for connecting another external connection component and a peripheral circuit region provided with a peripheral circuit on the insulating substrate. As a result, it is possible to finely process the wiring and improve the reliability of the display device.
- the external connection component is not particularly limited as long as it is a circuit board or an element that can be connected to a display panel configured using the display device substrate, and is an FPC (Flexible Printed Circuits) substrate, TCP (Tape Carrier Package). ), COG (Chip on Glass), resistive element, capacitive element, etc., among which an FPC board is suitable.
- FPC Flexible Printed Circuits
- TCP Transmission Carrier Package
- COG Chip on Glass
- resistive element capacitive element, etc., among which an FPC board is suitable.
- the display device substrate preferably includes the organic / inorganic film laminate in the terminal portion. Thereby, as described above, the reliability of the display device can be improved.
- the display device substrate preferably has the organic / inorganic film laminate in the peripheral circuit region. Thereby, as described above, a peripheral circuit including a finely processed wiring can be formed.
- the display device substrate preferably includes a plurality of the organic / inorganic film laminates. Thereby, multilayering of wiring becomes possible.
- the display device substrate may have the plurality of organic / inorganic film laminates in the terminal portion. At this time, the display device substrate is provided between the plurality of organic / inorganic film laminates. It is preferable that the connection terminal includes a wiring layer excluding the wiring layer located closest to the insulating substrate (lower layer side) among the plurality of wiring layers. Thereby, it is possible to form the wiring under the connection terminal while ensuring the reliability of the display device.
- the display device substrate includes a plurality of wiring layers provided between layers of the plurality of organic / inorganic film laminates, and the connection terminal is a wiring located on the uppermost layer side of the plurality of wiring layers. More preferably, it is configured to include a layer. Thereby, more wirings can be formed under the connection terminals while ensuring the reliability of the display device.
- the display device substrate may have a region in which the inorganic insulating film is laminated immediately above the connection terminal in the terminal portion, or the terminal portion is not provided with the organic insulating film. May be. As a result, the mechanical reliability of the display device can be particularly improved.
- the terminal portion more specifically includes a conductive material (preferably an ACF (anisotropic) for connecting the display device substrate of the present invention to another external connection component (preferably a circuit substrate).
- a conductive material preferably an ACF (anisotropic) for connecting the display device substrate of the present invention to another external connection component (preferably a circuit substrate).
- An anisotropic conductive material (such as conductive film) is preferably disposed in the region.
- the inorganic insulating film covers the organic insulating film so that the organic insulating film is not at least in contact with the conductive material.
- the display device substrate preferably has the plurality of organic / inorganic film laminates in the peripheral circuit region. As a result, a peripheral circuit having fine and multi-layered wiring can be formed.
- the inorganic insulating film is preferably provided so as to cover at least the upper layer surface of the organic insulating film in the peripheral circuit region. Further, the inorganic insulating film may be provided so as to cover all the organic insulating films except for at least a part of the wall surface of the opening of the organic insulating film in the peripheral circuit region, In the peripheral circuit region, the organic insulating film may be provided so as to cover all the organic insulating films including the wall surface of the opening of the organic insulating film.
- the opening of the organic insulating film is covered with an upper layer wiring than the inorganic insulating film.
- the opening of the organic insulating film can be covered with the upper wiring, and the region not covered with the upper wiring of the organic insulating film can be covered with the inorganic insulating film. You can avoid taking damage. As a result, it is possible to suppress the occurrence of poor connection between the wirings arranged in the upper and lower layers of the organic / inorganic film laminate.
- the organic insulating film preferably contains a photosensitive resin. Thereby, it is possible to more effectively suppress the occurrence of wiring connection failure.
- the present invention is also a method for manufacturing a substrate for a display device according to the present invention, wherein the manufacturing method includes an organic insulating film etching step for etching the organic insulating film containing the photosensitive resin, and the organic insulating film etching step.
- Manufacturing a substrate for a display device comprising: an inorganic insulating film forming step for forming the inorganic insulating film; and an inorganic insulating film etching step for etching the inorganic insulating film after the inorganic insulating film forming step. It is also a method (hereinafter also referred to as “the first method for producing a substrate for a display device of the present invention”). Thereby, it is possible to finely process the wiring while suppressing the occurrence of poor connection of the wiring.
- the first method for producing a substrate for a display device of the present invention is not particularly limited by other steps as long as the method includes the above steps.
- a preferred embodiment in the first method for producing a substrate for a display device of the present invention will be described in detail below.
- the various aspects shown below may be combined as appropriate.
- the inorganic insulating film etching step the inorganic insulating film is preferably dry-etched through a first resist. Thereby, the fine processing of wiring can be performed more reliably.
- the inorganic insulating film etching step it is preferable to etch away the inorganic insulating film in a region overlapping with a region where the organic insulating film containing the photosensitive resin is removed by etching. Thereby, a fine contact hole can be formed.
- the method for manufacturing a substrate for a display device preferably includes an organic insulating film photosensitive step of exposing the organic insulating film through a first photomask before the organic insulating film etching step. Thereby, it can suppress more reliably that the connection defect of wiring generate
- the organic insulating film is preferably subjected to photosensitivity and etching (development), that is, photoetching.
- the method for manufacturing a display device substrate includes an organic insulating film photosensitive step of exposing the organic insulating film through a first photomask before the organic insulating film etching step
- the display device substrate The manufacturing method includes: a resist film forming process for forming a second resist on the inorganic insulating film after the inorganic insulating film forming process; and a first photomask after the resist film forming process. It is more preferable to include a resist exposure step for exposing the second resist.
- a common first photomask can be used in the organic insulating film exposure step and the resist exposure step, so that the number of necessary photomasks in the manufacturing process can be reduced by one, and the manufacturing cost can be reduced.
- the positions of the openings of the organic insulating film and the inorganic insulating film may be shifted due to the difference in the finish between the different photomasks. It is possible to suppress the positional deviation of the openings of the organic insulating film and the inorganic insulating film.
- the present invention is also a method for manufacturing a substrate for a display device according to the present invention, wherein the manufacturing method includes an inorganic insulating film etching step of etching the inorganic insulating film by wet etching using a resist as a mask, and the inorganic insulating film etching.
- a method for manufacturing a substrate for a display device comprising: a resist removing step for removing the resist after the step; and an organic insulating film etching step for etching the organic insulating film using the inorganic insulating film as a mask after the resist removing step. (Hereinafter also referred to as “second method for manufacturing a substrate for a display device of the present invention”).
- the resist can be stripped by a stripping solution instead of ashing treatment. Therefore, ashing damage is not given to the wall surface portion of the organic insulating film exposed in the contact hole. As a result, it is possible to suppress the occurrence of wiring connection failure.
- the second method for producing a substrate for a display device of the present invention is not particularly limited by the other steps as long as it has the above steps.
- the present invention is also a method for manufacturing a substrate for a display device according to the present invention, wherein the manufacturing method includes an inorganic insulating film etching step of etching the inorganic insulating film by dry etching using a resist as a mask, and the inorganic insulating film etching. After the step, the resist is removed by ashing by dry etching, and the organic insulating film is etched using the inorganic insulating film as a mask (hereinafter referred to as “third of the present invention”). It is also referred to as “a manufacturing method of a display device substrate”.
- the resist removal (ashing) and the organic insulating film etching (opening) are performed simultaneously, the total damage given to the organic insulating film by dry etching can be reduced. As a result, it is possible to suppress the occurrence of wiring connection failure.
- substrate for display apparatuses of this invention is not specifically limited by another process.
- the present invention is also a display device including the display device substrate of the present invention.
- the present invention is also a display device including the display device substrate manufactured by the display device substrate manufacturing method of the present invention. According to these, it is possible to narrow the frame, increase the functionality, and improve the reliability.
- the present invention is also a method for forming a multilayer wiring having an organic / inorganic film laminate in which an inorganic insulating film is laminated directly on an organic insulating film containing a photosensitive resin, the forming method comprising: Etching the organic insulating film, etching the inorganic insulating film after the organic insulating film etching process, and etching the inorganic insulating film after the inorganic insulating film forming process And a method for forming a multilayer wiring including an inorganic insulating film etching step (hereinafter, also referred to as “first multilayer wiring formation method of the present invention”).
- first multilayer wiring formation method of the present invention a method for forming a multilayer wiring including an inorganic insulating film etching step
- the method for forming the first multilayer wiring of the present invention is not particularly limited by the other steps as long as it has the above steps.
- a preferred embodiment of the first multilayer wiring forming method of the present invention will be described in detail below.
- the various aspects shown below may be combined as appropriate.
- the inorganic insulating film etching step the inorganic insulating film is preferably dry-etched through a first resist. Thereby, the fine processing of wiring can be performed more reliably.
- the inorganic insulating film etching step it is preferable to etch away the inorganic insulating film in a region overlapping with a region where the organic insulating film containing the photosensitive resin is removed by etching. Thereby, a fine contact hole can be formed.
- the method for forming the multilayer wiring includes an organic insulating film photosensitive step of exposing the organic insulating film through a first photomask before the organic insulating film etching step.
- the organic insulating film is preferably exposed and etched (photosensitive etching).
- the multilayer wiring forming method includes: A resist film forming step for forming a second resist on the inorganic insulating film after the inorganic insulating film forming step; and the second resist via the first photomask after the resist film forming step. It is more preferable to include a resist sensitizing step for sensitizing. As a result, a common first photomask can be used in the organic insulating film exposure step and the resist exposure step, so that the number of necessary photomasks in the manufacturing process can be reduced by one, and the manufacturing cost can be reduced.
- the positions of the openings of the organic insulating film and the inorganic insulating film may be shifted due to the difference in the finish between the different photomasks. It is possible to suppress the positional deviation of the openings of the organic insulating film and the inorganic insulating film.
- the present invention further relates to a method of forming a multilayer wiring having an organic / inorganic film laminate in which an inorganic insulating film is laminated directly on an organic insulating film, wherein the forming method includes performing the above-mentioned inorganic insulation by wet etching using a resist as a mask.
- a method for forming a multilayer wiring including an organic insulating film etching step (hereinafter also referred to as “second multilayer wiring formation method of the present invention”).
- the method for forming the second multilayer wiring of the present invention is not particularly limited by the other steps as long as it has the above steps.
- the present invention is also a method for forming a multilayer wiring having an organic / inorganic film laminate in which an inorganic insulating film is laminated directly on an organic insulating film, wherein the forming method includes dry etching using a resist as a mask to form the inorganic insulating film.
- It is also a multilayer wiring formation method (hereinafter also referred to as “third multilayer wiring formation method of the present invention”).
- the resist removal (ashing) and the organic insulating film etching (opening) are performed simultaneously, the total damage given to the organic insulating film by dry etching can be reduced. As a result, it is possible to suppress the occurrence of wiring connection failure.
- the third multilayer wiring forming method of the present invention is not particularly limited by other steps as long as it has the above steps.
- the present inventors have also found that not only an organic insulating film but also a planarizing film made of an inorganic insulating film alone is damaged by ashing or dry etching of a resist mask, and the planarizing film is inorganically insulated. It has been found that the occurrence of poor connection can be suppressed by using in combination with a film and further covering at least a part of the wall surface of the opening of the planarizing film with an inorganic insulating film.
- a multilayer wiring board partially covered with the inorganic insulating film is also one aspect of the present invention.
- the inorganic insulating film is patterned using wet etching, and the planarization film can be prevented from being damaged by ashing or dry etching. As a result, it is possible to suppress the occurrence of connection failure between the wirings arranged in the upper layer and the lower layer of the planarized film / inorganic film laminate.
- a planarization film is a film having a planarization function of planarizing (smallening) a step.
- the surface of the planarization film is preferably substantially flat, but may have a step of about 500 nm (preferably 200 nm) or less.
- the planarizing film has a stepped portion on the surface, the radius of curvature of the stepped portion is preferably larger than the height of the stepped portion, which causes an etching residue during etching to form an upper wiring layer. Can be effectively suppressed.
- the planarizing film may be a so-called (SOG: Spin on Glass) film.
- the configuration of the multilayer wiring board of the present invention is not particularly limited as long as such components are formed as essential, and may or may not include other components. Absent. A preferred embodiment of the multilayer wiring board of the present invention will be described in detail below. The various forms shown below may be combined as appropriate.
- the inorganic insulating film may be provided so as to cover all of the planarization film except at least a part on the lower layer side of the wall surface of the planarization film opening. It is preferable to be provided so as to cover all the planarization films including the wall surface. Thus, it is more preferable that the entire wall surface of the opening of the planarization film is covered with the inorganic insulating film.
- a resist mask such as dry etching with high microfabrication accuracy
- an organic insulating film and an inorganic insulating film are suitable, and the organic insulating film more preferably contains a photosensitive resin. Thereby, the multilayer wiring board of the present invention can be easily realized.
- the opening of the planarization film is covered with an upper layer wiring than the inorganic insulating film.
- the opening of the planarization film can be covered with the upper layer wiring, and the region not covered with the upper wiring of the planarization film can be covered with the inorganic insulating film, so that the planarization film is formed by ashing or dry etching. You can avoid taking damage. As a result, it is possible to suppress the occurrence of connection failure between the wirings arranged in the upper layer and the lower layer of the planarized film / inorganic film laminate.
- the multilayer wiring board is preferably a display device substrate. Thereby, the reliability of the display device substrate, that is, the display device can be improved.
- the multilayer wiring formed by the first to third multilayer wiring forming methods of the present invention and the multilayer wiring substrate of the present invention sandwich an organic / inorganic film laminate or a planarized film / inorganic film laminate, respectively.
- the wiring in the multilayer wiring board formed by the first to third multilayer wiring forming methods of the present invention and the multilayer wiring board of the present invention is sufficient if it includes at least two wiring layers (upper and lower wirings). The number of layers is not particularly limited.
- the manufacturing method thereof, the display device, the multilayer wiring formation method, and the multilayer wiring substrate of the present invention it is possible to finely process the wiring, suppress connection failure, and improve the reliability of the display device.
- FIG. 1A and 1B are schematic cross-sectional views of a frame region of the liquid crystal display device according to the first embodiment, in which FIG. 1A shows a terminal portion and FIG. 1B shows a peripheral circuit region.
- FIG. 13 is a schematic cross-sectional view of a pixel region of the liquid crystal display device according to the third embodiment.
- a TFT substrate 11 that is a substrate for a display device and an FPC substrate 70 that is another circuit substrate are connected by an ACF 80 at a terminal portion. It has a structure.
- a black matrix made of a light shielding member, red, green and blue color filters, an overcoat layer, a common electrode made of a transparent conductive film, and an alignment film are insulated on an insulating substrate.
- a CF substrate (not shown) is formed in this order from the substrate side and is disposed opposite to the TFT substrate 11, and a liquid crystal material is filled between the TFT substrate 11 and the CF substrate.
- the TFT substrate 11 has an inorganic insulating film that functions as a base coat film 22, a gate insulating film 24, a gate electrode 25, and an interlayer insulating film on an insulating substrate 21 in a terminal portion.
- a connection terminal (external connection terminal) 26 composed of the first wiring layer 61
- a laminated body of an organic insulating film 51a and an inorganic insulating film 41a functioning as a protective film which are stacked in this order from the insulating substrate 21 side.
- connection terminal 26 Have Further, the organic insulating film 51a and the inorganic insulating film 41a on the end portion of the connection terminal 26 are removed, and a pad portion (contact portion with the conductive fine particles 81 in the ACF 80) is formed on the end portion of the connection terminal 26. 27 is provided.
- the TFT substrate 11 and the FPC substrate 70 are connected and fixed when the pad portion 27 and the connection terminal 71 of the FPC substrate 70 are in contact with the conductive fine particles 81 in the ACF 80.
- a connection terminal (external connection terminal) 26 made of the first wiring layer 61 is connected to a gate electrode (gate wiring) 25 through a contact hole 31 a provided in the inorganic insulating film 41.
- the TFT substrate 11 has a base coat film 22, a semiconductor layer 23, a gate insulating film 24, a gate electrode 25, and an interlayer on the insulating substrate 21 in the peripheral circuit region.
- the organic wiring film 30b including the second wiring layer 62 and the organic insulating film 51 functioning as a protective film are stacked in this order from the insulating substrate 21 side.
- the TFT 29 including the semiconductor layer 23, the gate insulating film 24 and the gate electrode 25 and constituting a peripheral circuit such as a driver circuit is directly formed on the insulating substrate 21 constituting the TFT substrate 11, the TFT 29 including the semiconductor layer 23, the gate insulating film 24 and the gate electrode 25 and constituting a peripheral circuit such as a driver circuit is directly formed. .
- the source / drain electrodes 28 formed of the first wiring layer 61 are connected to the source / drain regions of the semiconductor layer 23 through contact holes 31 b provided in the inorganic insulating film 41 and the gate insulating film 24.
- the routing wiring 30b made of the second wiring layer 62 is connected to the source / drain electrode 28 made of the first wiring layer 61 and the routing through the contact hole (via hole) 31c provided in the organic insulating film 51a and the inorganic insulating film 41a. It is connected to the wiring 30a.
- the peripheral circuit is not particularly limited, and in addition to a driver circuit including a circuit such as a transmission gate, a latch circuit, a timing generator, an inverter such as a power supply circuit, a buffer circuit, a digital-analog conversion circuit (DAC circuit), a shift register A circuit such as a sampling memory may be used.
- a driver circuit including a circuit such as a transmission gate, a latch circuit, a timing generator, an inverter such as a power supply circuit, a buffer circuit, a digital-analog conversion circuit (DAC circuit), a shift register A circuit such as a sampling memory may be used.
- the TFT substrate 11 includes a base coat film 22, a semiconductor layer 23, a gate insulating film 24, and a gate on an insulating substrate 21 in a pixel area (a display area in which a plurality of pixels are arranged).
- a pixel electrode 36 provided for each pixel and an alignment film (not shown) provided so as to cover the pixel region are laminated in this order from the insulating substrate 21 side. With an elephant.
- the TFT 29 including the semiconductor layer 23, the gate insulating film 24, and the gate electrode 25 and functioning as a pixel switching element is directly formed for each pixel on the insulating substrate 21 constituting the TFT substrate 11.
- a pixel auxiliary capacitance 68a including the semiconductor layer 23 that also functions as an auxiliary capacitance lower electrode, the gate insulating film 24, and the auxiliary capacitance upper electrode 66a is directly formed for each pixel.
- the source electrode 34 and the drain electrode 35 made of the first wiring layer 61 are connected to the source / drain regions of the semiconductor layer 23 through contact holes 31 f provided in the inorganic insulating film 41 and the gate insulating film 24.
- the drain wiring 65 is connected to the drain electrode 35 formed of the first wiring layer 61 via a contact hole (via hole) 31g provided in the organic insulating film 51a and the inorganic insulating film 41a. Further, the pixel electrode 36 is connected to a drain wiring 65 composed of the second wiring layer 62 through a contact hole (via hole) 31 j provided in the organic insulating film 51.
- the organic film constituting the organic insulating film 51a and the like is soft and easily peeled off or scratched, but has excellent flatness.
- the inorganic film constituting the inorganic insulating film 41a and the like has poor flatness but is hard to be peeled off and not easily damaged.
- the interlayer insulating layer and / or the planarizing layer includes the organic / inorganic stacked body in which the inorganic insulating film 41a is stacked directly on the organic insulating film 51a.
- the organic insulating film 51a (at least the upper layer surface of the organic insulating film 51a) is covered with the inorganic insulating film 41a, whereby the organic insulating film 51a can be protected by the inorganic insulating film 41a. Therefore, even when it is necessary to rework in the process of connecting the panel and the FPC substrate 70, more specifically, the TFT substrate 11 and the FPC substrate 70, the organic insulating film 51a may be peeled off or damaged.
- the first wiring layer 61 (connection terminal 26) located under the organic insulating film 51a is exposed, and the first wiring layer 61 can be prevented from being corroded by moisture or the like. Further, it is possible to suppress the occurrence of contact failure of the FPC board 70 due to the residue of the peeled organic insulating film 51a. That is, according to the liquid crystal display device 100, the reliability can be improved.
- the inorganic insulating film 41a can be used as a stopper material for resist mask ashing, a method including an ashing process as a method of forming the contact holes 31c and 31g in the organic insulating film 51a and the inorganic insulating film 41a, that is, , A method using a resist mask such as dry etching with high microfabrication accuracy is possible, and the wiring located in the lower layer of the laminated body of the organic insulating film 51a and the inorganic insulating film 41a, especially the peripheral circuit region where fine processing is required Wiring such as the lead-out wiring 30a provided in can be formed finely and with high accuracy.
- the steps of the first wiring layer 61 and the TFT 29 on the lower layer side are reduced, and a short circuit is effectively generated.
- the second wiring layer 62 can be routed to the upper layer side while suppressing.
- the manufacturing method of the liquid crystal display device of Embodiment 1 is demonstrated. First, cleaning and pre-annealing are performed on the insulating substrate 21 as pretreatment. Although it does not specifically limit as the insulating substrate 21, From a viewpoint of cost etc., a glass substrate, a resin substrate, etc. are suitable. Next, the following steps (1) to (17) are performed.
- a 50 nm thick SiON film and a 100 nm thick SiO x film are formed in this order on the insulating substrate 21 by a plasma enhanced chemical vapor deposition (PECVD) method.
- a base coat film 22 is formed.
- the source gas for forming the SiON film include a mixed gas of monosilane (SiH 4 ), nitrous oxide gas (N 2 O), and ammonia (NH 3 ).
- the SiO x film is preferably formed by using tetraethyl orthosilicate (TEOS) gas as a source gas.
- the base coat film 22 may include a silicon nitride (SiN x ) film formed using a mixed gas of monosilane (SiH 4 ) and ammonia (NH 3 ) as a source gas.
- amorphous silicon (a-Si) film having a thickness of 50 nm is formed by PECVD.
- the source gas for forming the a-Si film include SiH 4 and disilane (Si 2 H 6 ). Since the a-Si film formed by the PECVD method contains hydrogen, a process (dehydrogenation process) for reducing the hydrogen concentration in the a-Si film is performed at about 500 ° C. Subsequently, laser annealing is performed to melt, cool and crystallize the a-Si film, thereby forming a p-Si film. For laser annealing, for example, an excimer laser is used.
- a metal catalyst such as nickel is applied without dehydrogenation, and solidified by heat treatment. Phase growth may be performed. Further, as the crystallization of the a-Si film, only solid phase growth by heat treatment may be performed. Next, dry etching using a mixed gas of carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) is performed to pattern the p-Si film, thereby forming the semiconductor layer 23.
- CF 4 carbon tetrafluoride
- O 2 oxygen
- a gate insulating film 24 made of silicon oxide having a thickness of 45 nm is formed using TEOS gas as a source gas.
- the material of the gate insulating film 24 is not particularly limited, and a SiN x film, a SiON film, or the like may be used.
- Examples of the source gas for forming the SiN x film and the SiON film include the same source gases as those described in the base coat film forming step.
- the gate insulating film 24 may be a stacked body made of the plurality of materials.
- the semiconductor layer 23 is doped with an impurity such as boron by an ion doping method, an ion implantation method or the like. More specifically, after doping an impurity such as boron into a semiconductor layer to be an N-channel TFT and a P-channel TFT (first doping step), the semiconductor layer to be a P-channel TFT is masked with a resist. In this state, the N-channel semiconductor layer is further doped with an impurity such as boron (second doping step). Note that when the threshold control of the P-channel TFT is not necessary, the first doping step may not be performed.
- Step of forming gate electrode and storage capacitor upper electrode a sputtering method is used to form a tantalum nitride (TaN) film with a thickness of 30 nm and a tungsten (W) film with a thickness of 370 nm in this order.
- a resist mask is formed by patterning a resist film into a desired shape by photolithography, and then argon (Ar), sulfur hexafluoride (SF 6 ), carbon tetrafluoride (CF 4 ), oxygen ( Dry etching is performed using an etching gas whose mixed gas content is adjusted such as O 2 ) and chlorine (Cl 2 ) to form the gate electrode 25 and the auxiliary capacitor upper electrode 66a.
- a refractory metal having a flat surface and stable characteristics such as tantalum (Ta), molybdenum (Mo), and molybdenum tungsten (MoW), aluminum (Al), and the like are used. A low resistance metal is mentioned. Further, the gate electrode 25 and the storage capacitor upper electrode 66a may be a stacked body made of the plurality of materials.
- an impurity such as phosphorus is added to the semiconductor layer 23 with respect to the semiconductor layer 23 using the gate electrode 25 as a mask.
- impurities such as boron are doped at a high concentration by an ion doping method, an ion implantation method, or the like.
- an LDD (Lightly Doped Drain) region may be formed.
- a thermal activation process is performed at about 700 ° C. for 6 hours. Thereby, the electrical conductivity of the source / drain region can be improved.
- an activation method an excimer laser irradiation method or the like can be used.
- an SiN x film having a thickness of 100 to 400 nm (preferably 200 to 300 nm) and a thickness of 500 to 1000 nm (preferably) are formed on the entire surface of the insulating substrate 21 by PECVD. , 600 to 800 nm) to form an inorganic insulating film 41.
- a SiON film or the like may be used as the inorganic insulating film 41.
- a thin cap film for example, a TEOS film or the like
- a thin cap film for example, a TEOS film or the like
- the gate insulating film 24 and the inorganic insulating film are formed using a hydrofluoric acid-based etching solution. 41 is wet-etched to form contact holes 31a, 31b, 31f. Note that dry etching may be used for the etching.
- connection terminal (external connection terminal) 26, the source / drain electrode 28, the routing wiring 30a, the source electrode 34, and the drain electrode 35 are formed.
- the metal constituting the first wiring layer 61 an Al—Si alloy or the like may be used instead of Al.
- Al is used for reducing the resistance of the wiring.
- the gate electrode material Ta, Mo, MoW, W, TaN, etc. described above may be used.
- a photosensitive resin such as a photosensitive acrylic resin film having a thickness of 1 to 5 ⁇ m (preferably 2 to 3 ⁇ m) is formed on the entire surface of the insulating substrate 21 by spin coating or the like. Is formed (coated) to form the organic insulating film 51a.
- a non-photosensitive resin such as a non-photosensitive acrylic resin, a photosensitive or non-photosensitive polyalkylsiloxane-based, polysilazane-based, or polyimide-based parylene-based resin may be used.
- Examples of the material for the organic insulating film 51a include methyl-containing polysiloxane (MSQ) -based materials and porous MSQ-based materials.
- MSQ methyl-containing polysiloxane
- the photosensitive resin film is exposed (exposed) and etched (development processing) before the inorganic insulating film 41a is formed, and the organic insulating film 51a is patterned. It can also be formed.
- a SiN x film having a film thickness of 10 to 200 nm (preferably 20 to 100 nm) or a film thickness of 10 to 200 nm (preferably using TEOS gas as a source gas) is formed on the entire surface of the insulating substrate 21 by sputtering or PECVD. , by depositing an SiO 2 film of 20 ⁇ 100 nm), to form the inorganic insulating film 41a.
- An SiON film or the like may be used as the inorganic insulating film 41a.
- a sputtering method, a CAT-CVD method, and an ICP plasma CVD method for example, a method using an ICP-CVD apparatus manufactured by Cellbach
- ozone oxidation e.g., Meidensha Corporation, a method using a Meiden pure ozone generator
- SiO 2 film or SiN film formed by such an organic / inorganic laminate in which the inorganic insulating film 41a is laminated on the organic insulating film 51a is formed.
- the organic insulating film 51a and the inorganic insulating film 41a may be formed by stacking a plurality of films made of different materials.
- the inorganic insulating film 41a may be formed to cover at least the organic insulating film 51a in the terminal portion, the peripheral circuit region, and the pixel region, and is not necessarily formed on the entire surface of the insulating substrate 21.
- the wall surface of the opening of the organic insulating film 51a exposed in the contact holes 31c and 31g is simultaneously ashed, and the wall surface of the opening of the organic insulating film 51a is the upper layer.
- the contact holes 31c and 31g are overhanged with respect to the wall surface of the opening of the inorganic insulating film 41a, and an upper second wiring layer 62 and a lower first wiring layer 61 are formed through the contact holes 31c and 31g. There is concern about disconnection.
- a titanium (Ti) film with a thickness of 100 nm, an aluminum (Al) film with a thickness of 500 nm, and a Ti film with a thickness of 100 nm are formed in this order by sputtering or the like.
- the film is formed.
- the Ti / Al / Ti metal laminated film is patterned by dry etching to form the second wiring layer 62.
- the lead wiring 30b and the drain wiring 65 are formed.
- the metal constituting the second wiring layer 62 an Al—Si alloy or the like may be used instead of Al.
- Al is used for reducing the resistance of the wiring.
- the metal constituting the second wiring layer 62 the above-described gate electrode material (Ta, Mo, MoW, W, TaN, etc.) may be used.
- the opening of the organic insulating film 51a which is also a planarizing film, is covered with the second wiring layer 62, which is a wiring above the inorganic insulating film 41a. Accordingly, the opening of the organic insulating film 51a can be covered with the second wiring layer 62, and the region of the organic insulating film 51a that is not covered with the second wiring layer 62 can be covered with the inorganic insulating film 41a.
- the film 51a can be prevented from being damaged by ashing or dry etching. As a result, it is possible to suppress the occurrence of poor connection between the wirings arranged in the upper and lower layers of the organic / inorganic film laminate.
- the organic insulating film 51 is formed by forming a photosensitive acrylic resin film having a film thickness of 1 to 3 ⁇ m (preferably 2 to 3 ⁇ m) by spin coating or the like. Form. More specifically, a photosensitive acrylic resin having a film thickness of 1 to 5 ⁇ m (preferably 2 to 3 ⁇ m), for example, a naphthoquinonediazide-based ultraviolet curable resin is applied to the entire surface of the substrate 21 by spin coating or the like. An organic insulating film 51 is formed.
- the organic insulating film 51 is exposed (exposed) through a photomask on which a light-shielding pattern having a desired shape is formed, and then etched (development processing) to remove the organic insulating film 51 in a region to be the contact hole 31j To do. Then, the baking process (for example, 200 degreeC, 30 minutes) of the organic insulating film 51 is performed. Thereby, the shape of the opening (hole) of the organic insulating film 51 becomes gentle, and the aspect ratio of the contact hole 31j can be reduced. In addition, when the contact portion (portion that becomes the contact hole 31j) of the organic insulating film 51 is first removed, an ashing (peeling) step is not required.
- a non-photosensitive resin film such as a non-photosensitive acrylic resin film, a photosensitive or non-photosensitive polyalkylsiloxane-based, polysilazane-based, polyimide-based parylene-based resin, or the like may be used.
- the material for the organic insulating film 51 include a methyl-containing polysiloxane (MSQ) material and a porous MSQ material.
- Step of forming pad portion and pixel portion an ITO film or an IZO film having a film thickness of 50 to 200 nm (preferably 100 to 150 nm) is formed by sputtering or the like, and then desired by photolithography. Patterning into a shape forms the pad portion 27 and the pixel portion. Thereby, the pixel electrode 36 is formed on the organic insulating film 51 in the display region corresponding to each pixel. Thereafter, an alignment film (not shown) is applied to the display region and the alignment film is subjected to an alignment process, whereby the TFT substrate 11 is completed.
- an alignment film (not shown) is applied to the display region and the alignment film is subjected to an alignment process, whereby the TFT substrate 11 is completed.
- a liquid crystal display is performed by performing a bonding process of the TFT substrate 11 and the CF substrate, a liquid crystal material injection process, and a polarizing plate bonding process.
- the liquid crystal mode of the liquid crystal display panel is not particularly limited, and examples thereof include a TN (Twisted Nematic) mode, an IPS (In Plane Switching) mode, a VATN (Vertical Alignment Twisted Nematic) mode, and a PSA mode.
- the liquid crystal display panel may be one obtained by orientation division.
- the liquid crystal display panel may be a transmissive type, a reflective type, or a transflective type (reflective / transparent type).
- the driving method of the liquid crystal display panel may be a simple matrix type.
- the following steps are performed as a panel bonding and liquid crystal injection step. That is, first, a sealing material is applied to the outer periphery of the pixel region of the TFT substrate 11, and then a liquid crystal material obtained by adding a polymerizable component to liquid crystal molecules having a negative dielectric constant is dropped inside the sealing material using a dispenser or the like. .
- the material that can be used as the polymerizable component is not particularly limited, and for example, a photopolymerizable monomer or a photopolymerizable oligomer can be used.
- a CF substrate is bonded to the TFT substrate 11 onto which the liquid crystal material is dropped. The steps so far are performed in a vacuum.
- the liquid crystal material diffuses between the bonded substrates by atmospheric pressure.
- UV light is irradiated to the sealing material while moving the UV light source along the application region of the sealing material to cure the sealing material. In this way, the diffused liquid crystal material is sealed between the two substrates to form a liquid crystal layer.
- a liquid crystal injection port may be provided on the sides of both substrates, the liquid crystal material may be injected therefrom, and then the liquid crystal injection port may be sealed with an ultraviolet curable resin or the like. Good.
- the light irradiation process of a polymeric component is performed.
- an alternating voltage is applied between the source electrode 34 and the common electrode of the CF substrate in a state where a voltage for turning on the TFT 29 is applied to the gate electrode 25, and the liquid crystal layer is tilted from the TFT substrate 11 side while tilting the liquid crystal molecules. Irradiate with UV light.
- the photopolymerizable monomer added to the liquid crystal material is polymerized, and a polymer that defines the pretilt angle of the liquid crystal molecules is formed on the liquid crystal layer side surface of the alignment film.
- FCP substrate affixing step an ACF (anisotropic conductive film) 80 in which conductive fine particles 81 are dispersed in a resin adhesive (for example, a thermosetting resin such as a thermosetting epoxy resin). Then, the TFT substrate 11 and the FPC substrate 70 are thermocompression bonded. Thereby, the TFT substrate 11 and the FPC substrate 70 are connected and fixed. At this time, even if it is necessary to rework, since the organic insulating film 51a is protected by the inorganic insulating film 41a and is not in direct contact with the ACF 80, the organic insulating film 51a is prevented from being peeled off or damaged. be able to.
- a resin adhesive for example, a thermosetting resin such as a thermosetting epoxy resin
- the first wiring layer 61 located under the organic insulating film 51a is exposed, and the first wiring layer 61 can be prevented from being corroded by moisture or the like. Further, it is possible to suppress the occurrence of contact failure of the FPC board 70 due to the residue of the peeled organic insulating film 51a.
- the liquid crystal display device 100 of this embodiment can be completed by attaching polarizing plates to the outside of the TFT substrate 11 and the CF substrate, and further combining the liquid crystal display panel and the backlight unit.
- liquid crystal display device 100 of the present embodiment it is possible to improve the reliability and finely process the wiring.
- the inorganic insulating film 41a that functions as a gas barrier insulating film is provided between the organic insulating film 51a and the pixel electrode 36, it is possible to suppress the occurrence of defects due to gas or bubbles in the PSA mode. That is, even if the organic insulating film 51a or the like is formed of a photosensitive resin and the organic insulating film 51a or the like is irradiated with UV light in the light irradiation process of the polymerizable component and gas is generated from the lower layer of the pixel electrode 36, the organic insulating film The inorganic insulating film 41a can prevent the gas generated from the lower layer than the film 51a from entering the liquid crystal layer. Therefore, generation of bubbles in the liquid crystal layer can be suppressed.
- the organic insulating film 51a and the organic insulating film 51 may be a planarizing film (inorganic planarizing film) made of an inorganic insulating film.
- Si—H containing polysiloxane (MSQ) is used.
- a film made of a system material or a porous silica film may be used.
- the liquid crystal display device 100 according to the present embodiment may include a planarization film / inorganic film laminate in which an inorganic insulating film is laminated directly on a planarization film.
- FIG. 14 is a schematic cross-sectional view showing a peripheral circuit region of a modification according to the liquid crystal display device of the first embodiment.
- FIG. 15 is a schematic cross-sectional view illustrating a pixel region of a modification according to the liquid crystal display device of Embodiment 1.
- the organic insulating film 51a is formed by photosensitive etching using a photosensitive resin. More specifically, the photosensitive resin film is exposed (exposed) and etched (development processing) before the inorganic insulating film 41a is formed, and the organic insulating film 51a is patterned.
- the baking process for example, 200 degreeC, 30 minutes
- the shape of the opening (hole) of the organic insulating film 51a becomes gentle, and the aspect ratio of the contact holes 31c and 31g can be reduced.
- an ashing (peeling) step is not necessary.
- an inorganic insulating film 41a is formed, and by dry etching using carbon tetrafluoride (CF 4 ) or the like, the inorganic regions in the regions to be the contact holes 31c and 31g are overlapped with the regions from which the organic insulating film 51a has been removed.
- the insulating film 41a is removed.
- the contact holes 31c and 31g can be finely processed, and the first wiring layer 61 in the lower layer can be miniaturized.
- the resist mask is removed by ashing with O 2 plasma using the inorganic insulating film 41a as a stopper material. Thereby, contact holes 31c and 31g penetrating the organic insulating film 51a and the inorganic insulating film 41a are formed.
- the inorganic insulating film 41a (passivation film) on the organic insulating film 51a made of a photosensitive resin, it is possible to suppress the occurrence of damage due to the dry process. More specifically, when the inorganic insulating film 41a is etched by dry etching, the entire surface of the organic insulating film 51a on the liquid crystal layer side is covered with the inorganic insulating film 41a. That is, the upper surface and the side surface (for example, the wall surface of the opening) of the organic insulating film 51a on the liquid crystal layer side are covered with the inorganic insulating film 41a. Therefore, it is possible to prevent the organic insulating film 51a from being damaged by dry etching.
- the organic insulating film 51a is possible to prevent the organic insulating film 51a from being damaged by oxygen plasma during resist ashing in the process of forming the contact holes 31c and 31g. From such a viewpoint, it is preferable that the entire wall surface of the opening of the organic insulating film 51a is covered with the inorganic insulating film 41a.
- the inorganic insulating film 41a may be wet-etched.
- the resist mask may be stripped with a stripping solution. Therefore, the organic insulating film 51a can be prevented from being damaged by ashing or dry etching.
- FIG. 16 is a schematic cross-sectional view illustrating a modification of the liquid crystal display device according to the first embodiment.
- FIG. 16A illustrates a terminal portion in the frame region
- FIG. 16B illustrates a peripheral circuit portion in the frame region.
- FIG. 17 is a schematic cross-sectional view illustrating a pixel region of a modification according to the liquid crystal display device of Embodiment 1.
- an inorganic insulating film 41 c that functions as a gas barrier insulating film is formed on the organic insulating film 51 in the same manner as the inorganic insulating film 41 a. That is, a stacked body of the organic insulating film 51 and the inorganic insulating film 41c is formed in the same manner as the stacked body of the organic insulating film 51a and the inorganic insulating film 41a.
- the inorganic insulating films 41a and 41c functioning as gas barrier insulating films are provided below the pixel electrode 36, the occurrence of defects due to gas and bubbles in the PSA mode can be further suppressed. That is, even if the organic insulating films 51a and 51 are formed of a photosensitive resin and the organic insulating films 51a and 51 are irradiated with UV light in the light irradiation process of the polymerizable component, gas is generated from the lower layer of the pixel electrode 36.
- the inorganic insulating films 41a and 41c can almost completely prevent the gas generated from the lower layer than the pixel electrode 36 from entering the liquid crystal layer. Therefore, generation of bubbles in the liquid crystal layer can be further suppressed.
- the inorganic insulating film 41c is directly laminated on the inorganic insulating film 41a in the terminal portion.
- the mechanical strength of the film can be improved as compared with the case of the single layer of the inorganic insulating film 41a. Therefore, it is possible to more effectively suppress various defects caused by rework during the thermocompression bonding of the FPC board 70.
- the pad portion 27 formed from the uppermost wiring layer (a transparent conductive film such as an ITO film or an IZO film) that is the same layer as the pixel electrode 36, a wiring layer (the nearest lower layer) immediately below the uppermost wiring layer is formed.
- a wiring layer 69, in this embodiment a second wiring layer 62) is arranged. Thereby, the terminal resistance of the pad part 27 can be reduced.
- the uppermost wiring layer is usually a transparent conductive film such as an ITO film and has a high sheet resistance, but the lower resistance wiring layer (first wiring) It can be expected that the sheet resistance value of the pad portion 27 is reduced by adopting a laminated structure with the layer 61 and the second wiring layer 62).
- the nearest lower wiring layer 69 is removed by dry etching or the like, the surface of the wiring layer below the nearest lower wiring layer 69 (the first wiring layer 61 in this embodiment) is subjected to etching damage.
- the contact resistance between the wiring layer (first wiring layer 61) under the nearest lower wiring layer 69 and the uppermost wiring layer (transparent conductive film) increases, and as a result, the terminal resistance increases. Therefore, it is preferable to leave the nearest lower wiring layer 69 under the uppermost wiring layer of the pad portion 27.
- FIG. 18 is a schematic cross-sectional view illustrating a modification of the liquid crystal display device according to the first embodiment.
- FIG. 18A illustrates a terminal portion in the frame region
- FIG. 18B illustrates a peripheral circuit portion in the frame region.
- FIG. 19 is a schematic cross-sectional view illustrating a pixel region of a modification according to the liquid crystal display device of the first embodiment.
- an inorganic insulating film 41c that functions as a gas barrier insulating film similar to the inorganic insulating film 41a is formed on the organic insulating film 51 instead of forming the inorganic insulating film 41a. Is formed.
- the inorganic insulating film 41c that functions as a gas barrier insulating film is provided below the pixel electrode 36, the occurrence of defects due to bubbles in the PSA mode can be suppressed. That is, even if the organic insulating films 51a and 51 are formed of a photosensitive resin and the organic insulating films 51a and 51 are irradiated with UV light in the light irradiation process of the polymerizable component, gas is generated from the lower layer of the pixel electrode 36.
- the inorganic insulating film 41c can almost completely prevent the gas generated from the lower layer than the pixel electrode 36 from entering the liquid crystal layer. Therefore, generation of bubbles in the liquid crystal layer can be further suppressed. Moreover, since the formation process of the inorganic insulating film 41a can be reduced, the manufacturing process can be simplified.
- an inorganic insulating film 41c is stacked on the organic insulating film 51a, and a stacked body of the organic insulating film 51a and the inorganic insulating film 41c is provided.
- a nearest lower wiring layer 69 is provided below the uppermost wiring layer of the pad portion 27.
- the organic insulating film 51a is formed by photosensitive etching using a photosensitive resin.
- FIG. 20 is a schematic cross-sectional view illustrating a pixel region of a modification according to the liquid crystal display device of the first embodiment.
- this modification has the same configuration as the example shown in FIG. 19 except that the organic insulating film 51 is formed by photosensitive etching using a photosensitive resin. That is, the photosensitive resin film is exposed (exposed) and etched (developed) before the inorganic insulating film 41c is formed, and the organic insulating film 51 is formed in a pattern. Then, the baking process (for example, 200 degreeC, 30 minutes) of the organic insulating film 51 is performed. Thereby, the shape of the opening (hole) of the organic insulating film 51 becomes gentle, and the aspect ratio of the contact hole 31j can be reduced.
- the baking process for example, 200 degreeC, 30 minutes
- an ashing (peeling) step is not required. Thereafter, an inorganic insulating film 41c is formed, and an inorganic insulating film in a region to be the contact hole 31j so as to overlap the region from which the organic insulating film 51 has been removed by dry etching using carbon tetrafluoride (CF 4 ) or the like. 41c is removed.
- the contact hole 31j can be finely processed, and the second wiring layer 62 in the lower layer can be miniaturized.
- the resist mask is removed by ashing with O 2 plasma using the inorganic insulating film 41c as a stopper material. Thereby, a contact hole 31j penetrating the organic insulating film 51 and the inorganic insulating film 41c is formed.
- the inorganic insulating film 41c passivation film
- the organic insulating film 51 made of a photosensitive resin it is possible to suppress the occurrence of damage due to the dry process. More specifically, when the inorganic insulating film 41c is etched by dry etching, the entire surface of the organic insulating film 51 on the liquid crystal layer side is covered with the inorganic insulating film 41c. That is, the upper surface and the side surface (for example, the wall surface of the opening) of the organic insulating film 51 on the liquid crystal layer side are covered with the inorganic insulating film 41c. Therefore, it is possible to prevent the organic insulating film 51 from being damaged by dry etching.
- the organic insulating film 51 it is possible to prevent the organic insulating film 51 from being damaged by oxygen plasma at the time of resist ashing in the step of forming the contact hole 31j. From such a viewpoint, it is preferable that the entire wall surface of the opening of the organic insulating film 51 is covered with the inorganic insulating film 41c.
- the inorganic insulating film 41c may be wet-etched.
- the resist mask may be stripped with a stripping solution. Therefore, the organic insulating film 51 can be prevented from being damaged by ashing or dry etching.
- FIG. 21 is a schematic cross-sectional view illustrating a modified example of the liquid crystal display device according to the first embodiment.
- FIG. 21A illustrates a terminal portion in the frame region
- FIG. 21B illustrates a peripheral circuit portion in the frame region.
- FIG. 22 is a schematic cross-sectional view illustrating a pixel region of a modification according to the liquid crystal display device of Embodiment 1.
- the organic insulating film 51a is etched back as shown in FIGS. More specifically, after the organic insulating film 51a is formed, the organic insulating film 51a is etched back by dry etching until the first wiring layer 61 is exposed.
- an inorganic insulating film 41a is formed, and the inorganic insulating film 41a in the regions to be the contact holes 31c and 31g is removed by dry etching using carbon tetrafluoride (CF 4 ) or the like.
- CF 4 carbon tetrafluoride
- the level difference between the pad portion 27 and the region other than the pad portion 27 is reduced by the thickness of the organic insulating film 51a, and therefore the conductive fine particles in the ACF 80 in the pad portion 27 and the region other than the pad portion 27.
- the amount of deformation of 81 is relaxed, and the contact property of ACF can be further improved.
- a nearest lower wiring layer 69 is provided under the uppermost wiring layer of the pad portion 27.
- FIG. 23 is a schematic cross-sectional view illustrating a modification of the liquid crystal display device according to the first embodiment.
- FIG. 23A illustrates a terminal portion in the frame region
- FIG. 23B illustrates a peripheral circuit portion in the frame region.
- FIG. 24 is a schematic cross-sectional view illustrating a pixel region of a modification according to the liquid crystal display device of Embodiment 1.
- the second auxiliary capacitance lower electrode 67 formed by the first wiring layer 61 and the second wiring layer 62 are formed in the region overlapping the auxiliary capacitance upper electrode 66a.
- a second auxiliary capacitance upper electrode 66b is also provided. Then, the organic insulating film 51a in the region where the auxiliary capacitance lower electrode 67 and the auxiliary capacitance upper electrode 66b overlap is removed, and the auxiliary capacitance lower electrode 67 and the auxiliary capacitance upper electrode 66b are disposed to face each other via the inorganic insulating film 41a. .
- each pixel includes not only the pixel auxiliary capacitance 68a including the semiconductor layer 23, the gate insulating film 24, and the auxiliary capacitance upper electrode 66a, but also the auxiliary capacitance lower electrode 67, the inorganic insulating film 41a, and the auxiliary capacitance upper electrode 66b.
- a second pixel auxiliary capacitor 68b is provided. Accordingly, the size (area) of the pixel auxiliary capacitor 68a and the pixel auxiliary capacitor 68b can be reduced as compared with the case where only one pixel auxiliary capacitor 68a is formed in one pixel. Can be improved.
- the organic insulating films 51a and 51 are formed by photosensitive etching using a photosensitive resin, and then the inorganic insulating films 41a and 41c are formed and etched to form a pattern.
- a stacked body of inorganic insulating films 41a and 41c is stacked on the organic insulating film 51a.
- a nearest lower wiring layer 69 is provided under the uppermost wiring layer of the pad portion 27.
- FIG. 2A and 2B are schematic cross-sectional views in the frame region of the liquid crystal display device according to the second embodiment.
- FIG. 2A shows a terminal portion
- FIG. 2B shows a peripheral circuit region.
- the description about the content which overlaps with this embodiment and Embodiment 1 is abbreviate
- a stacked body of the organic insulating film 51b and the inorganic insulating film 41b is further formed on the stacked body of the organic insulating film 51a and the inorganic insulating film 41 in the liquid crystal display device of the first embodiment. It has a structure.
- the TFT substrate 12 of the present embodiment includes a stacked layer of an organic insulating film 51a and an inorganic insulating film 41a that function as an interlayer insulating film and a planarizing film in the terminal portion.
- On the body there is a structure in which the routing wiring 30c composed of the second wiring layer 62 and the stacked body of the organic insulating film 51b and the inorganic insulating film 41b functioning as a protective film are further stacked in this order from the insulating substrate 21 side.
- the routing wiring 30c made of the second wiring layer 62 is connected to the connection terminal (external connection terminal) 26 made of the first wiring layer 61 through the contact hole (via hole) 31d provided in the organic insulating film 51a and the inorganic insulating film 41a. It is connected.
- the TFT substrate 12 includes an organic insulating film 51b and an inorganic insulating film 41b that function as an interlayer insulating film and a planarizing film on the second wiring layer 62 in the peripheral circuit region.
- the stacked body and the routing wiring 30d made of the third wiring layer 63 are further stacked in this order from the insulating substrate 21 side.
- the lead wiring 30d made of the third wiring layer 63 is connected to the lead wiring 30b made of the second wiring layer 62 through a contact hole (via hole) 31e provided in the organic insulating film 51b and the inorganic insulating film 41b.
- liquid crystal display device 200 of the present embodiment it is possible to further increase the number of wiring lines that can be finely processed.
- the number of added wiring layers and the stacked body of the organic insulating film and the inorganic insulating film is not particularly limited, and may be set as appropriate in accordance with a desired layout.
- the liquid crystal display device 200 includes (11) an organic / inorganic laminate forming step, (12) a contact hole forming step, and (13) a wiring layer (second wiring layer) according to the first embodiment. It is possible to fabricate the film by repeatedly performing the above-described forming step as necessary.
- the film thicknesses of the organic insulating film 51b and the inorganic insulating film 41b may be 1 to 4 ⁇ m (preferably 2 to 3 ⁇ m) and 10 to 200 nm (preferably 20 to 100 nm), respectively. .
- the organic insulating film 51b and the inorganic insulating film 41b may be formed by stacking a plurality of films made of different materials, like the organic insulating film 51a and the inorganic insulating film 41a. Furthermore, the organic insulating film 51a and the organic insulating film 51b, and the inorganic insulating film 41a and the inorganic insulating film 41b may be formed of different materials.
- the organic insulating film 51a, the organic insulating film 51b, and the organic insulating film 51 may be a planarizing film (inorganic planarizing film) made of an inorganic insulating film.
- a film made of a polysiloxane (MSQ) material or a porous silica film may be used.
- the liquid crystal display device 200 according to the present embodiment may include a planarization film / inorganic film laminate in which an inorganic insulating film is laminated directly on a planarization film.
- FIG. 25 is a schematic cross-sectional view illustrating a modification of the liquid crystal display device according to the second embodiment.
- FIG. 25A illustrates a terminal portion in the frame region
- FIG. 25B illustrates a peripheral circuit portion in the frame region.
- the organic insulating films 51a and 51b are formed by photosensitive etching using a photosensitive resin, and then the inorganic insulating films 41a and 41b are formed and etched to form a pattern. Is formed.
- the nearest lower wiring layer 69 is provided under the pad portion 27 formed by the uppermost wiring layer.
- FIG. 3 is a schematic cross-sectional view of a terminal portion of the liquid crystal display device according to the third embodiment.
- the description about the content which overlaps with this embodiment and Embodiment 1 and 2 is abbreviate
- the liquid crystal display device 300 according to the present embodiment is the same as the liquid crystal according to the second embodiment except that the connection terminal (external connection terminal) 26 is formed not from the first wiring layer 61 but from the upper second wiring layer 62. It has the same form as the display device 200.
- the TFT substrate 13 of the present embodiment includes a lead-out wiring 30e formed of the first wiring layer 61, an interlayer insulating film, and a flat surface on the inorganic insulating film 41 in the terminal portion.
- a laminated body of the organic insulating film 51a and the inorganic insulating film 41a functioning as a conversion film, a connection terminal (external connection terminal) 26 composed of the second wiring layer 62, and an organic insulating film 51b and an inorganic insulating film 41b functioning as a protective film Are stacked in this order from the insulating substrate 21 side.
- connection terminal (external connection terminal) 26 made of the second wiring layer 62 is connected to the lead wiring 30e made of the first wiring layer 61 via the contact hole (via hole) 31d provided in the organic insulating film 51a and the inorganic insulating film 41a. It is connected.
- the conductivity in the ACF 80 in the pad portion 27 and the region other than the pad portion 27 increases as the stacked structure of the laminated body of the organic insulating film and the inorganic insulating film and the wiring layer is increased. Since the difference in the deformation amount of the fine particles 81 increases, the stress becomes non-uniform, and as a result, there is a concern that the connection between the TFT substrate 12 and the FPC substrate 70 may be poor.
- the wiring layer directly below the upper layer preferably the uppermost layer of the inorganic insulating film and the organic insulating film (preferably the second layer in the present embodiment).
- the connection terminal 26 By forming the connection terminal 26 by the wiring layer 62), the groove of the pad portion 27 is reduced, and the difference in deformation amount of the conductive fine particles 81 in the ACF 80 between the pad portion 27 and the region other than the pad portion 27 is reduced. Therefore, it is possible to suppress the occurrence of poor connection due to stress nonuniformity.
- the organic insulating film 51a and the organic insulating film 51b may be a planarizing film (inorganic planarizing film) made of an inorganic insulating film.
- Si—H containing polysiloxane (MSQ) is used.
- a film made of a system material or a porous silica film may be used.
- the liquid crystal display device 300 according to the present embodiment may include a planarization film / inorganic film laminate in which an inorganic insulating film is laminated directly on a planarization film.
- FIG. 26 is a schematic cross-sectional view showing a modification of the liquid crystal display device of Embodiment 3, and shows a terminal portion in a frame region.
- the organic insulating films 51a and 51b are formed by photosensitive etching using a photosensitive resin, and then the inorganic insulating films 41a and 41b are formed and etched to form a pattern. Is formed.
- FIG. 27 is a schematic cross-sectional view showing a modification of the liquid crystal display device according to the third embodiment.
- FIG. 27A shows a terminal portion in the frame region
- FIG. 27B shows a peripheral circuit portion in the frame region.
- FIG. 28 is a schematic cross-sectional view illustrating a pixel region of a modification according to the liquid crystal display device of Embodiment 3. As shown in FIG. 27A, the organic insulating film 51 b is removed at the terminal portion, and the inorganic insulating film 41 b is formed directly on the connection terminal 26.
- the level difference between the pad portion 27 and the region other than the pad portion 27 is reduced by the thickness of the organic insulating film 51b, and therefore the conductive fine particles in the ACF 80 in the pad portion 27 and the region other than the pad portion 27.
- the amount of deformation of 81 is further relaxed, and the contact property of ACF can be further improved.
- a nearest lower wiring layer 69 is provided below the uppermost wiring layer of the pad portion 27. Further, as shown in FIGS. 27B and 28, the organic insulating films 51a and 51b are formed by photosensitive etching using a photosensitive resin, and then the inorganic insulating films 41a and 41b are formed and etched. The pattern is formed by.
- FIG. 4 is a schematic cross-sectional view of a terminal portion of the liquid crystal display device according to the fourth embodiment. Note that the description of the same contents in the present embodiment and the first to third embodiments is omitted.
- the liquid crystal display device 400 of the present embodiment has the same form as the liquid crystal display device 100 of the first embodiment except that the organic insulating film is completely removed from the terminal portion.
- the TFT substrate 14 has an inorganic insulating film 41 a that functions as a protective film directly on the connection terminal (external connection terminal) 26 formed of the first wiring layer 61 in the terminal portion.
- an inorganic insulating film 41 a that functions as a protective film directly on the connection terminal (external connection terminal) 26 formed of the first wiring layer 61 in the terminal portion.
- the liquid crystal display device 300 can suppress the occurrence of connection failure due to the non-uniform stress, but the pad portion is also equal to the thickness of the organic insulating film 51b and the inorganic insulating film 41b. 27 and a region other than the pad portion 27, the deformation amount of the conductive fine particles 81 in the ACF 80 in the pad portion 27 and the region other than the pad portion 27 is not completely the same. There is room for improvement in terms of contact.
- the liquid crystal display device 400 of the present embodiment has a structure in which there is no organic insulating film that causes a problem in the rework in the terminal portion, and therefore, the reliability degradation caused by the rework described above can be completely improved. Can do. Further, since the level difference between the pad portion 27 and the region other than the pad portion 27 is reduced by the thickness of the organic insulating film, the deformation amount of the conductive fine particles 81 in the ACF 80 in the pad portion 27 and the region other than the pad portion 27 is reduced. Is further relaxed, and the contact property of ACF can be further improved.
- the liquid crystal display device 400 of the present embodiment can be manufactured in the same manner as the liquid crystal display device 100 of the first embodiment, except that no organic insulating film is provided in the terminal portion.
- the organic insulating film is not formed at least in a region where an anisotropic conductive material such as ACF80 is provided.
- FIG. 29 is a schematic cross-sectional view showing a modification of the liquid crystal display device of Embodiment 4, and shows a terminal portion in a frame region.
- a nearest lower wiring layer 69 is provided under the uppermost wiring layer of the pad portion 27.
- FIG. 5 is a schematic cross-sectional view of a terminal portion of a modification of the liquid crystal display device according to the fourth embodiment.
- the TFT substrate 14 has a connection terminal (external connection terminal) 26 made of the same layer as the gate electrode (gate wiring) 25 extending to the terminal portion, a first wiring layer 61, an ITO You may have the pad part 27 comprised from transparent conductive films, such as a film
- the liquid crystal display device 400 of the present embodiment has the same form as the liquid crystal display device 300 of the third embodiment shown in FIG. 3 except that the organic insulating film 51b is removed from the terminal portion. May be. That is, in the TFT substrate 14 of the present embodiment, in the terminal portion, on the inorganic insulating film 41, the lead wiring 30e made of the first wiring layer 61, the organic insulating film 51a functioning as an interlayer insulating film and a planarizing film, and the inorganic film The insulating film 41a, the connection terminal (external connection terminal) 26 composed of the second wiring layer 62, and the inorganic insulating film 41b functioning as a protective film may be laminated in this order from the insulating substrate 21 side.
- the organic insulating film 51a may be a flattened film (inorganic flattened film) made of an inorganic insulating film.
- a film made of Si—H containing polysiloxane (MSQ) -based material or a porous film may be used.
- MSQ polysiloxane
- a porous silica film may be used.
- the liquid crystal display device 400 according to the present embodiment may include a planarization film / inorganic film laminate in which an inorganic insulating film is laminated directly on a planarization film.
- FIG. 6 is a schematic cross-sectional view in the peripheral circuit region of the liquid crystal display devices according to the first to fourth embodiments.
- FIGS. 8A to 8D and FIGS. 8B to 8G are schematic cross-sectional views in the peripheral circuit region of the liquid crystal display devices according to Embodiments 1 to 4 in the manufacturing process. . Note that the description of the same contents in the following embodiment and the first to fourth embodiments is omitted.
- the contact hole is formed by performing dry etching on the stacked body of the organic insulating film and the inorganic insulating film after the organic insulating film and the inorganic insulating film are stacked, as in the manufacturing method described in the first embodiment.
- the film thickness of the organic insulating film is, for example, as thick as 2 ⁇ m or more, and the aspect ratio of the contact hole formed in the laminate of the organic insulating film and the inorganic insulating film is increased, and it is difficult to make contact between the upper and lower wiring layers. is there. Further, since the organic insulating film is exposed on the inner wall of the contact hole during dry etching and resist ashing, the organic insulating film may be damaged by etching and resist ashing as described above.
- the liquid crystal display device 500 of the present embodiment uses a photosensitive resin film as a material for the organic insulating film 51a and the organic insulating film 51, and is manufactured by the following method.
- the steps up to (10) the first wiring layer forming step of the first embodiment are performed.
- a photosensitive resin such as a photosensitive acrylic resin film is formed (coated) on the entire surface of the insulating substrate by spin coating or the like in the same manner as in the first embodiment.
- To form the organic insulating film 51a As a result, the first wiring layer 61 is covered with the organic insulating film 51a, and the surface of the TFT substrate is flattened.
- photosensitive etching of the organic insulating film 51a is performed. That is, as shown in FIG. 8B, the organic insulating film 51a is exposed (exposed) through a photomask 32a on which a light-shielding pattern having a desired shape is formed, and then etching (development processing) is performed. Thus, the organic insulating film 51a in the region to be the contact hole 31c is removed.
- a baking process (approximately 200 ° C., 30 minutes) of the organic insulating film 51a (photosensitive resin film) is performed. Thereby, as shown in FIG. 8C, the shape of the opening (hole) of the organic insulating film 51a becomes gentle, and the aspect ratio of the contact hole 31c can be reduced.
- the inorganic insulating film 41a (SiN x film or SiO 2 film) is formed on the entire surface of the insulating substrate by sputtering or PECVD in the same manner as in the method of the first embodiment.
- the inorganic insulating film 41a is preferably formed by a sputtering method that allows film formation in a state where the substrate temperature is low. Thereby, the film quality of the inorganic insulating film 41a can be improved. This is because organic components are scattered during high-temperature treatment, which may cause deterioration of film performance and contamination of the chamber of the apparatus.
- a resist is patterned by photolithography. Specifically, as shown in FIG. 8-2 (e), after the resist 33a is exposed with a photomask 32b different from the photomask 32a and developed, a region to be the contact hole 31c of the resist 33a is formed. Remove.
- the resist 33a is ashed with O 2 plasma, while wet etching is used. Removes the resist 33a with a stripping solution.
- the photosensitive resin is used as the material of the organic insulating film 51a, an ashing (peeling) step is not required when the contact portion (the portion that becomes the contact hole 31c) of the organic insulating film 51a is first removed. Therefore, the contact portion (opening portion) of the organic insulating film 51a formed by this photosensitive etching is finished in a gentle shape as compared with the case where it is formed by a dry process, as shown in FIG. Therefore, the aspect ratio of the contact hole 31c can be reduced, and occurrence of a disconnection failure in the second wiring layer 62 laminated on the upper layer can be effectively suppressed.
- the inorganic insulating film 41a laminated after the photosensitive etching of the organic insulating film 51a can utilize dry etching or the like that can be made finer than the photosensitive etching. Therefore, by this method as well, the contact hole 31c can be finely processed, and the first wiring layer 61 in the lower layer can be miniaturized.
- the photosensitive resin is used as the material of the organic insulating film 51a, when this embodiment is applied to the fourth embodiment, the organic insulation of the terminal portion that does not require high microfabrication is required before the inorganic insulating film 41a is stacked. The film can be easily removed.
- FIG. 12 is a schematic cross-sectional view of another form of the peripheral circuit region shown in FIG. 8-2 (g).
- the inorganic insulating film 41a is wet-etched, by making the opening of the inorganic insulating film 41a larger than the opening of the organic insulating film 51a, as shown in FIG. 12, the wall surface of the opening of the organic insulating film 51a A part of the lower layer side may be exposed. This also prevents the organic insulating film 51a from being damaged by ashing or dry etching.
- the organic insulating film 51a is photosensitively etched, the organic insulating film 51a is baked, and the inorganic insulating film 41a is formed by the above-described method (FIG. 8-1).
- a resist is patterned with a photomask different from the photomask 32a, and then the organic insulating film 51a is etched by wet etching using hydrofluoric acid (HF) or the like using the resist as a mask.
- a contact hole may be formed by etching the inorganic insulating film 41a so that a part of the lower wall side of the wall surface of the opening is exposed, and finally the resist may be stripped with a stripping solution.
- FIGS. 9-1 (a) to (d) and FIGS. 9-2 (e) to (h) are schematic cross-sectional views in the peripheral circuit region of the modification example of the liquid crystal display device according to Embodiments 1 to 4 in the manufacturing process. is there.
- the process up to (10) the first wiring layer forming process of the first embodiment is performed.
- a photosensitive resin such as a photosensitive acrylic resin film is formed (applied) on the entire surface of the insulating substrate by spin coating or the like in the same manner as in the first embodiment.
- the organic insulating film 51a As a result, the first wiring layer 61 is covered with the organic insulating film 51a, and the surface of the TFT substrate is flattened.
- photosensitive etching of the organic insulating film 51a is performed. That is, as shown in FIG. 9-1 (b), the organic insulating film 51a is exposed through a photomask 32c on which a light-shielding pattern having a desired shape is formed, and then developed to form a contact hole 31c. The organic insulating film 51a in the region is removed. At this time, the organic insulating film 51a is overexposed so that the opening (contact part) of the organic insulating film 51a is larger than the opening (contact part) of the inorganic insulating film 41a described later.
- an inorganic insulating film 41a (SiN x film or SiO 2 film) is formed on the entire surface of the insulating substrate by sputtering or PECVD. Form.
- the inorganic insulating film 41a is preferably formed by a sputtering method that allows film formation in a state where the substrate temperature is low. Thereby, the film quality of the inorganic insulating film 41a can be improved. This is because organic components are scattered during high-temperature treatment, which may cause deterioration of film performance and contamination of the chamber of the apparatus.
- a resist is patterned by photolithography. Specifically, as shown in FIG. 9-2 (e), the resist 33b is exposed with a photomask 32c used for exposure of the organic insulating film 51a, and then developed, so that the contact hole 31c of the resist 33b is exposed. The area to be removed is removed. At this time, the resist 33b is exposed with a normal exposure amount so that the opening of the inorganic insulating film 41a is smaller than the opening of the organic insulating film 51a.
- the inorganic insulating film 41a is etched so as to overlap the region from which the organic insulating film 51a has been removed, thereby forming a contact hole 31c.
- the organic insulating film 51a is covered with the inorganic insulating film 41a as shown in FIG. 9-2 (g) which is an enlarged view of the vicinity of the region surrounded by the dotted line in FIG. 9-2 (f). Therefore, it is possible to prevent damage during the etching and during ashing described later.
- dry etching or the like that can be made finer than photosensitive etching can be used for etching the inorganic insulating film 41a. Therefore, by this method as well, the contact hole 31c can be finely processed, and the first wiring layer 61 in the lower layer can be miniaturized.
- the resist 33b is ashed with O 2 plasma, while wet etching is used. Removes the resist 33b with a stripping solution.
- the same photomask 32c is used for the exposure of the organic insulating film 51a and the resist 33b, so that the number of necessary photomasks can be reduced by one, and the manufacturing cost can be reduced. Can do.
- FIGS. 10A to 10C and FIGS. 10B to 10D are schematic cross-sectional views in the peripheral circuit region of the modification examples of the liquid crystal display devices according to Embodiments 1 to 4 in the manufacturing process. is there.
- the process up to (10) the first wiring layer forming process of the first embodiment is performed.
- a photosensitive resin such as a photosensitive acrylic resin film is formed (applied) over the entire surface of the insulating substrate by spin coating or the like in the same manner as in the first embodiment.
- the organic insulating film 51a As a result, the first wiring layer 61 is covered with the organic insulating film 51a, and the surface of the TFT substrate is flattened.
- the organic insulating film 51a may be a photosensitive resin or a non-photosensitive resin.
- the inorganic insulating film 41a (SiN x film or SiO 2 film) is formed on the entire surface of the insulating substrate by sputtering, PECVD, or the like in the same manner as in the first embodiment.
- the inorganic insulating film 41a is preferably formed by a sputtering method that allows film formation in a state where the substrate temperature is low. Thereby, the film quality of the inorganic insulating film 41a can be improved. This is because organic components are scattered during high-temperature treatment, which may cause deterioration of film performance and contamination of the chamber of the apparatus.
- a resist is patterned by photolithography. Specifically, as shown in FIG. 10C, the resist 33c is exposed with a photomask 32d and then developed to remove a region that becomes the contact hole 31c of the resist 33c.
- the region to be the contact hole 31c of the inorganic insulating film 41a is removed by wet etching using hydrofluoric acid (HF) or the like using the resist 33c as a mask.
- HF hydrofluoric acid
- the resist 33c is stripped with a stripping solution using the inorganic insulating film 41a as a stopper material.
- the organic insulating film 51a is etched by dry etching using O 2 plasma or the like using the inorganic insulating film 41a as a mask to form a contact hole 31c.
- the resist 33c can be stripped by the stripper instead of the ashing process. Therefore, ashing damage is not caused to the wall surface of the opening of the organic insulating film 51a exposed in the contact hole 31c.
- FIGS. 11A and 11B are schematic cross-sectional views in the peripheral circuit region of a modification of the liquid crystal display device according to Embodiments 1 to 4 in the manufacturing process.
- the region to be the contact hole 31c of the inorganic insulating film 41a is removed by dry etching using carbon tetrafluoride (CF 4 ) or the like using the resist 33c as a mask.
- CF 4 carbon tetrafluoride
- ashing of the resist 33b and etching of the organic insulating film 51a are performed by dry etching using O 2 plasma or the like using the inorganic insulating film 41a as a stopper material, and contact is performed. Hole 31c is formed.
- the removal (ashing) of the resist 33b and the etching (opening) of the organic insulating film 51a are performed at the same time, so that the total damage given to the organic insulating film 51a by dry etching is reduced. can do.
- the organic insulating film 51a and the organic insulating film 51 may be a planarizing film (inorganic planarizing film) made of an inorganic insulating film.
- Si—H containing polysiloxane (MSQ) is used.
- a film made of a system material or a porous silica film may be used.
- the liquid crystal display device 500 according to the present embodiment may include a planarization film / inorganic film laminate in which an inorganic insulating film is laminated directly on a planarization film.
- the substrate for a display device of the present invention may have a form in which the peripheral circuit region is not provided and the organic / inorganic film laminate is provided only in the terminal portion, or an organic insulating film is provided in the terminal portion.
- the organic / inorganic film stack may be provided only in the peripheral circuit region.
- the present invention has been described by taking a liquid crystal display device as an example.
- the present invention is also applicable to a display device other than the liquid crystal display device, such as an organic EL display.
- the multilayer wiring forming method and multilayer wiring board of the present invention can be applied to a semiconductor substrate used for, for example, a semiconductor integrated circuit, a wiring board such as an FPC board, and the like other than a display device.
- FIG. 2A and 2B are schematic cross-sectional views in a frame region of the liquid crystal display device according to the first embodiment, in which FIG. 1A shows a terminal portion, and FIG. FIG. 5 is a schematic cross-sectional view of a frame region of the liquid crystal display device of Embodiment 2, where (a) shows a terminal portion and (b) shows a peripheral circuit region.
- 6 is a schematic cross-sectional view of a terminal portion of a liquid crystal display device of Embodiment 3.
- FIG. 6 is a schematic cross-sectional view of a terminal portion of a liquid crystal display device of Embodiment 4.
- FIG. 10 is a schematic cross-sectional view of a terminal portion of a modification of the liquid crystal display device of Embodiment 4.
- FIG. 6 is a schematic cross-sectional view in the peripheral circuit region of the liquid crystal display devices according to Embodiments 1 to 4. It is a cross-sectional schematic diagram in the frame area
- (A) to (d) are schematic cross-sectional views in the peripheral circuit region of the liquid crystal display device according to Embodiments 1 to 4 in the manufacturing process.
- (E) to (g) are schematic cross-sectional views in the peripheral circuit region of the liquid crystal display device according to Embodiments 1 to 4 in the manufacturing process.
- (A)-(d) is a cross-sectional schematic diagram in the peripheral circuit area
- (E) to (h) are schematic cross-sectional views in a peripheral circuit region of a modification of the liquid crystal display device according to Embodiments 1 to 4 in the manufacturing process.
- (A)-(c) is a cross-sectional schematic diagram in the peripheral circuit area
- D) to (f) are cross-sectional schematic diagrams in a peripheral circuit region of a modification of the liquid crystal display device according to Embodiments 1 to 4 in the manufacturing process.
- FIG. 8B is a schematic cross-sectional view of another form of the peripheral circuit region shown in FIG. 8-2 (g).
- 3 is a schematic cross-sectional view in a pixel region of the liquid crystal display device of Embodiment 1.
- FIG. 6 is a schematic cross-sectional view showing a peripheral circuit region of a modification according to the liquid crystal display device of Embodiment 1.
- FIG. 6 is a schematic cross-sectional view illustrating a pixel region of a modification example according to the liquid crystal display device of Embodiment 1.
- FIG. 6 is a schematic cross-sectional view illustrating a modification example of the liquid crystal display device according to the first embodiment, in which (a) illustrates a terminal portion in the frame region and (b) illustrates a peripheral circuit portion in the frame region.
- FIG. 6 is a schematic cross-sectional view illustrating a pixel region of a modification example according to the liquid crystal display device of Embodiment 1.
- FIG. 6 is a schematic cross-sectional view illustrating a modification example of the liquid crystal display device according to the first embodiment, in which (a) illustrates a terminal portion in the frame region and (b) illustrates a peripheral circuit portion in the frame region.
- FIG. 6 is a schematic cross-sectional view illustrating a pixel region of a modification example according to the liquid crystal display device of Embodiment 1.
- FIG. 6 is a schematic cross-sectional view illustrating a pixel region of a modification example according to the liquid crystal display device of Embodiment 1.
- FIG. 6 is a schematic cross-sectional view illustrating a modification example of the liquid crystal display device according to the first embodiment, in which (a) illustrates a terminal portion in the frame region and (b) illustrates a peripheral circuit portion in the frame region.
- FIG. 6 is a schematic cross-sectional view illustrating a pixel region of a modification example according to the liquid crystal display device of Embodiment 1.
- FIG. 1 is a schematic cross-sectional view illustrating a pixel region of a modification example according to the liquid crystal display device of Embodiment 1.
- FIG. 6 is a schematic cross-sectional view illustrating a modification example of the liquid crystal display device according to the first embodiment, in which (a) illustrates a terminal portion in the frame region and (b) illustrates a peripheral circuit portion in the frame region.
- FIG. 6 is a schematic cross-sectional view illustrating a pixel region of a modification example according to the liquid crystal display device of Embodiment 1. It is a cross-sectional schematic diagram which shows the modification concerning the liquid crystal display device of Embodiment 2, (a) shows the terminal part in a frame area
- FIG. 10 is a schematic cross-sectional view illustrating a pixel region of a modification example according to the liquid crystal display device of Embodiment 3. It is a cross-sectional schematic diagram which shows the modification concerning the liquid crystal display device of Embodiment 4, and shows the terminal part in a frame area
- TFT substrate 21 Insulating substrate 22: Base coat film 23: Semiconductor layer 24: Gate insulating film 25: Gate electrode (gate wiring) 26: Connection terminal (external connection terminal) 27: Pad portion 28: Source / drain electrode 29: TFT 30a, 30b, 30c, 30d, 30e: routing wires 31a, 31b, 31c, 31d, 31e, 31f, 31g, 31j: contact holes 32a, 32b, 32c, 32d: photomasks 33a, 33b, 33c: resist 34: source Electrode 35: Drain electrode 36: Pixel electrodes 41, 41a, 41b, 41c: Inorganic insulating films 51, 51a, 51b: Organic insulating film 61: First wiring layer 62: Second wiring layer 63: Third wiring layer 65: Drain Wiring 66a, 66b: Auxiliary capacitance upper electrode 67: Auxiliary capacitance lower electrode 68a, 68b: Pixel auxiliary capacitance 69: Nearest lower wiring layer
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Abstract
Description
図1は、実施形態1の液晶表示装置の額縁領域における断面模式図であり、(a)は、端子部を示し、(b)は、周辺回路領域を示す。図13は、実施形態3の液晶表示装置の画素領域における断面模式図である。本実施形態の液晶表示装置100は、図1(a)に示すように、表示装置用基板であるTFT基板11と、他の回路基板であるFPC基板70とが端子部においてACF80により接続された構造を有する。
まず、絶縁基板21に対して、前処理として、洗浄とプレアニールとを行う。絶縁基板21としては特に限定されないが、コスト等の観点からは、ガラス基板、樹脂基板等が好適である。次に、以下(1)~(17)の工程を行う。
絶縁基板21上に、プラズマ化学気相成長(Plasma Enhanced Chemical Vapor Deposition:PECVD)法により膜厚50nmのSiON膜と、膜厚100nmのSiOx膜とをこの順に成膜し、ベースコート膜22を形成する。SiON膜形成のための原料ガスとしては、モノシラン(SiH4)、亜酸化窒素ガス(N2O)及びアンモニア(NH3)の混合ガス等が挙げられる。なお、SiOx膜は、原料ガスとして正珪酸四エチル(Tetra Ethyl Ortho Silicate:TEOS)ガスを用いて形成されることが好ましい。また、ベースコート膜22は、原料ガスとしてモノシラン(SiH4)及びアンモニア(NH3)の混合ガス等を用いて形成された窒化シリコン(SiNx)膜を含んでもよい。
PECVD法により、膜厚50nmのアモルファスシリコン(a-Si)膜を形成する。a-Si膜形成のための原料ガスとしては、例えば、SiH4、ジシラン(Si2H6)等が挙げられる。PECVD法により形成したa-Si膜には水素が含まれているため、約500℃でa-Si膜中の水素濃度を低減する処理(脱水素処理)を行う。続いて、レーザアニールを行い、a-Si膜を溶融、冷却及び結晶化させることにより、p-Si膜を形成する。レーザアニールには、例えば、エキシマレーザを用いる。p-Si膜の形成には、レーザアニールの前処理として、(連続粒界結晶シリコン(CG-シリコン)化するため)、脱水素処理せずニッケル等の金属触媒を塗布して、熱処理による固相成長を行ってもよい。また、a-Si膜の結晶化としては、熱処理による固相成長のみを行ってもよい。次に、四フッ化炭素(CF4)及び酸素(O2)の混合ガスによるドライエッチングを行い、p-Si膜をパターニングし、半導体層23を形成する。
次に、原料ガスとしてTEOSガスを用いて、膜厚45nmの酸化シリコンからなるゲート絶縁膜24を形成する。ゲート絶縁膜24の材質としては特に限定されず、SiNx膜、SiON膜等を用いてもよい。SiNx膜及びSiON膜形成のための原料ガスとしては、ベースコート膜の形成工程で述べたものと同様の原料ガスが挙げられる。また、ゲート絶縁膜24は、上記複数の材料からなる積層体でもよい。
TFT29の閾値を制御するために、イオンドーピング法、イオン注入法等により、半導体層23に対してボロン等の不純物をドーピングする。より具体的には、Nチャネル型TFT及びPチャネル型TFTとなる半導体層に対してボロン等の不純物をドーピングした後(第一のドーピング工程)、Pチャネル型TFTとなる半導体層をレジストによりマスクした状態で、Nチャネル型となる半導体層に対して更にボロン等の不純物をドーピングする(第二のドーピング工程)。なお、Pチャネル型TFTの閾値制御が必要でない場合は、第一のドーピング工程は行わなくてもよい。
次に、スパッタリング法を用いて、膜厚30nmの窒化タンタル(TaN)膜と膜厚370nmのタングステン(W)膜とをこの順に成膜し、続いて、フォトリソグラフィ法によりレジスト膜を所望の形状にパターニングすることによってレジストマスクを形成した後、アルゴン(Ar)、六フッ化硫黄(SF6)、四フッ化炭素(CF4)、酸素(O2)、塩素(Cl2)等の混合ガス分量を調整したエッチングガスを用いてドライエッチングを行い、ゲート電極25及び補助容量上電極66aを形成する。ゲート電極25及び補助容量上電極66aの材料としては、タンタル(Ta)、モリブデン(Mo)、モリブデンタングステン(MoW)等の表面が平坦で特性の安定した高融点金属や、アルミニウム(Al)等の低抵抗金属が挙げられる。また、ゲート電極25及び補助容量上電極66aは、上記複数の材料からなる積層体であってもよい。
次に、TFT29のソース・ドレイン領域を形成するため、ゲート電極25をマスクとして、半導体層23に対して、Nチャネル型TFTではリン等の不純物を、Pチャネル型TFTではボロン等の不純物をイオンドーピング法、イオン注入法等により高濃度にドーピングする。このとき、必要に応じて、LDD(Lightly Doped Drain)領域を形成してもよい。続いて、半導体層23中に存在している不純物イオンを活性化させるために、約700℃、6時間の熱活性化処理を行う。これにより、ソース・ドレイン領域の電気伝導性を向上させることができる。なお、活性化の方法としては、エキシマレーザを照射する方法等も挙げられる。
次に、絶縁基板21全面にPECVD法により、膜厚100~400nm(好適には、200~300nm)のSiNx膜と、膜厚500~1000nm(好適には、600~800nm)のTEOS膜とを成膜することによって、無機絶縁膜41を形成する。無機絶縁膜41としては、SiON膜等を用いてもよい。また、トランジェント劣化等によりTFT特性が低下するのを抑制するとともに、TFT29の電気特性を安定化するため、無機絶縁膜41の下層には50nm程度の薄いキャップ膜(例えば、TEOS膜等)を形成してもよい。
次に、フォトリソグラフィ法によりレジスト膜を所望の形状にパターニングすることによってレジストマスクを形成した後、フッ酸系のエッチング溶液を用いてゲート絶縁膜24及び無機絶縁膜41のウェットエッチングを行い、コンタクトホール31a、31b、31fを形成する。なお、エッチングには、ドライエッチングを用いてもよい。
次に、無機絶縁膜41のSiNx膜から供給される水素によって結晶Siの欠陥補正を行うため、約400℃で1時間、熱処理を行う。
次に、スパッタ法等で、膜厚100nmのチタン(Ti)膜と、膜厚500nmのアルミニウム(Al)膜と、膜厚100nmのTi膜とをこの順で成膜する。次に、フォトリソグラフィ法によりレジスト膜を所望の形状にパターニングすることによってレジストマスクを形成した後、ドライエッチングによりTi/Al/Tiの金属積層膜をパターニングし、第一配線層61を形成する。これにより、接続端子(外部接続端子)26、ソース・ドレイン電極28、引き回し配線30a、ソース電極34及びドレイン電極35が形成される。なお、第一配線層61を構成する金属としては、Alに代えてAl-Si合金等を用いてもよい。なお、ここでは、配線の低抵抗化のためにAlを用いたが、高耐熱性が必要であり、かつ抵抗値のある程度の増加が許される場合(例えば、短い配線構造にする場合)は、第一配線層61を構成する金属として、上述したゲート電極材料(Ta、Mo、MoW、W、TaN等)を用いてもよい。
次に、絶縁基板21全面にスピンコート法等により、膜厚1~5μm(好適には、2~3μm)の感光性アクリル樹脂膜等の感光性樹脂を成膜(塗布)することによって、有機絶縁膜51aを形成する。有機絶縁膜51aの材料としては、非感光性アクリル樹脂等の非感光性樹脂や、感光性又は非感光性のポリアルキルシロキサン系やポリシラザン系、ポリイミド系パレリン系の樹脂等を用いてもよい。また、有機絶縁膜51aの材料としては、メチル含有ポリシロキサン(MSQ)系材料や多孔質MSQ系材料も挙げられる。有機絶縁膜51aの材料として、感光性樹脂を用いることによって、無機絶縁膜41aを形成するよりも先に感光性樹脂膜の感光(露光)及びエッチング(現像処理)し、有機絶縁膜51aをパターン形成することもできる。続いて、絶縁基板21全面にスパッタ法やPECVD法により膜厚10~200nm(好適には、20~100nm)のSiNx膜、又は、TEOSガスを原料ガスとして膜厚10~200nm(好適には、20~100nm)のSiO2膜を成膜することによって、無機絶縁膜41aを形成する。無機絶縁膜41aとしては、SiON膜等を用いてもよい。その他、無機絶縁膜41aとしては、低温で高品質な膜の形成が可能であるスパッタ法、CAT-CVD法、ICPプラズマCVD法(例えば、セルバック社製、ICP-CVD装置を用いる方法)、オゾン酸化法(例えば、明電舎社製、明電ピュアオゾンジェネレータを用いる方法)等により形成されたSiO2膜やSiN膜を成膜してもよい。これにより、有機絶縁膜51a上に無機絶縁膜41aが積層されたの有機・無機積層体が形成される。なお、有機絶縁膜51a及び無機絶縁膜41aはそれぞれ、異なる材料からなる複数の膜が積層されてもよい。また、無機絶縁膜41aは、少なくとも端子部、周辺回路領域及び画素領域における有機絶縁膜51aを覆うように形成されればよく、必ずしも絶縁基板21全面に形成される必要はない。
次に、フォトリソグラフィ法によりレジスト膜を所望の形状にパターニングすることによってレジストマスクを形成した後、四フッ化炭素(CF4)及び酸素(O2)の混合ガスを用い、かつ両ガスの流量を調整しながらドライエッチングを行い、コンタクトホール31c、31gを形成するとともに、パッド部27が設けられる領域の有機絶縁膜51a及び無機絶縁膜41aを除去する。そして、無機絶縁膜41aをストッパ材として、レジストマスクのアッシング(剥離)を行う。これにより、コンタクトホール31c、31gの微細加工が可能になることから、下層にある第一配線層61の微細化が可能になる。
次に、スパッタ法等により、膜厚100nmのチタン(Ti)膜と、膜厚500nmのアルミニウム(Al)膜と、膜厚100nmのTi膜とをこの順で成膜する。次に、フォトリソグラフィ法によりレジスト膜を所望の形状にパターニングすることによってレジストマスクを形成した後、ドライエッチングによりTi/Al/Tiの金属積層膜をパターニングし、第二配線層62を形成する。これにより、引き回し配線30b及びドレイン配線65が形成される。なお、第二配線層62を構成する金属としては、Alに代えてAl-Si合金等を用いてもよい。なお、ここでは、配線の低抵抗化のためにAlを用いたが、高耐熱性が必要であり、かつ抵抗値のある程度の増加が許される場合(例えば、短い配線構造にする場合)は、第二配線層62を構成する金属として、上述したゲート電極材料(Ta、Mo、MoW、W、TaN等)を用いてもよい。
次に、スピンコート法等により、膜厚1~3μm(好適には、2~3μm)の感光性アクリル樹脂膜を成膜することによって、有機絶縁膜51を形成する。より詳細には、基板21全面にスピンコート法等により、膜厚1~5μm(好適には、2~3μm)の感光性アクリル樹脂、例えばナフトキノンジアジド系の紫外線硬化型樹脂を塗布することによって、有機絶縁膜51を形成する。続いて、所望の形状の遮光パターンが形成されたフォトマスクを通して有機絶縁膜51を感光(露光)した後、エッチング(現像処理)を行うことによってコンタクトホール31jとなる領域の有機絶縁膜51を除去する。続いて、有機絶縁膜51のベーク工程(例えば、200℃、30分間)を行う。これにより、有機絶縁膜51の開口部(孔部)の形状がなだらかとなり、コンタクトホール31jのアスペクト比を低減することができる。また、有機絶縁膜51のコンタクト部(コンタクトホール31jとなる部分)を最初に除去する際、アッシング(剥離)工程が不要になる。有機絶縁膜51としては、非感光性アクリル樹脂膜等の非感光性樹脂膜や、感光性又は非感光性のポリアルキルシロキサン系やポリシラザン系、ポリイミド系パレリン系の樹脂等を用いてもよい。また、有機絶縁膜51の材料としては、メチル含有ポリシロキサン(MSQ)系材料や多孔質MSQ系材料も挙げられる。
次に、スパッタリング法等によって、膜厚50~200nm(好適には、100~150nm)のITO膜やIZO膜を形成した後、フォトリソグラフィ法によって所望の形状にパターニングし、パッド部27及び画素部を形成する。これにより、表示領域の有機絶縁膜51上には、各画素に対応して画素電極36が形成される。その後、表示領域に配向膜(図示せず)を塗布するとともに、配向膜の配向処理を行うことにより、TFT基板11が完成する。
次に、従来公知の方法と同様にして、TFT基板11及びCF基板の貼り合わせ工程と、液晶材料の注入工程と、偏光板の貼り付け工程とを行うことによって液晶表示パネルを作製する。なお、液晶表示パネルの液晶モードとして特に限定されず、例えば、TN(Twisted Nematic)モード、IPS(In Plane Switching)モード、VATN(Vertical Alignment Twisted Nematic)モード、PSAモード等が挙げられる。また、液晶表示パネルは、配向分割されたものであってもよい。更に、液晶表示パネルは、透過型であってもよしい、反射型であってもよしい、半透過型(反射透過両用型)であってもよい。そして、液晶表示パネルの駆動方式は、単純マトリクス型であってもよい。
次に、樹脂接着剤(例えば、熱硬化性エポキシ系樹脂等の熱硬化性樹脂)中に導電性微粒子81が分散されたACF(異方性導電膜)80を介して、TFT基板11とFPC基板70とを熱圧着する。これにより、TFT基板11とFPC基板70とが接続及び固定される。このとき、リワークする必要が生じたとしても、有機絶縁膜51aは、無機絶縁膜41aにより保護され、ACF80に直接接していないため、有機絶縁膜51aが剥れたり傷付いたりするのを抑制することができる。そのため、有機絶縁膜51aの下層に位置する第一配線層61が剥き出しになり、第一配線層61が水分等により腐食するのを抑制することができる。また、剥れた有機絶縁膜51aのカスに起因してFPC基板70の接触不良が発生するのも抑制することができる。
図14は、実施形態1の液晶表示装置に係る変形例の周辺回路領域を示す断面模式図である。図15は、実施形態1の液晶表示装置に係る変形例の画素領域を示す断面模式図である。
本変形例において、有機絶縁膜51aは、図14、15に示すように、感光性樹脂を用いて感光エッチングにより形成されている。より具体的には、無機絶縁膜41aを形成するよりも先に感光性樹脂膜の感光(露光)及びエッチング(現像処理)し、有機絶縁膜51aをパターン形成する。続いて、有機絶縁膜51aのベーク工程(例えば、200℃、30分間)を行う。これにより、有機絶縁膜51aの開口部(孔部)の形状がなだらかとなり、コンタクトホール31c、31gのアスペクト比を低減することができる。また、有機絶縁膜51aのコンタクト部(コンタクトホール31c、31gとなる部分)を最初に除去する際、アッシング(剥離)工程が不要になる。その後、無機絶縁膜41aを成膜し、四フッ化炭素(CF4)等を用いたドライエッチングにより、有機絶縁膜51aが除去された領域と重なるようにコンタクトホール31c、31gとなる領域の無機絶縁膜41aを除去する。無機絶縁膜41aをドライエッチングによりパターニングすることによって、コンタクトホール31c、31gの微細加工が可能になるとともに、下層にある第一配線層61の微細化が可能になる。その後、無機絶縁膜41aをストッパ材として、O2プラズマによりレジストマスクをアッシング除去する。これにより、有機絶縁膜51a及び無機絶縁膜41aを貫通するコンタクトホール31c、31gが形成される。
図16(b)、17に示すように、本変形例において、有機絶縁膜51上には、無機絶縁膜41aと同様にガスバリア絶縁膜として機能する無機絶縁膜41cが形成される。すなわち、有機絶縁膜51a及び無機絶縁膜41aの積層体と同様に、有機絶縁膜51及び無機絶縁膜41cの積層体が形成される。
本変形例において、図18(b)、19に示すように、無機絶縁膜41aが形成されない代わりに、有機絶縁膜51上に無機絶縁膜41aと同様のガスバリア絶縁膜として機能する無機絶縁膜41cが形成される。
本変形例は、図20に示すように、有機絶縁膜51が感光性樹脂を用いて感光エッチングにより形成されていること以外は、図19で示した例と同じ構成を有する。すなわち、無機絶縁膜41cを形成するよりも先に感光性樹脂膜の感光(露光)及びエッチング(現像処理)し、有機絶縁膜51をパターン形成する。続いて、有機絶縁膜51のベーク工程(例えば、200℃、30分間)を行う。これにより、有機絶縁膜51の開口部(孔部)の形状がなだらかとなり、コンタクトホール31jのアスペクト比を低減することができる。また、有機絶縁膜51のコンタクト部(コンタクトホール31jとなる部分)を最初に除去する際、アッシング(剥離)工程が不要になる。その後、無機絶縁膜41cを成膜し、四フッ化炭素(CF4)等を用いたドライエッチングにより、有機絶縁膜51が除去された領域と重なるようにコンタクトホール31jとなる領域の無機絶縁膜41cを除去する。無機絶縁膜41cをドライエッチングによりパターニングすることによって、コンタクトホール31jの微細加工が可能になるとともに、下層にある第二配線層62の微細化が可能になる。その後、無機絶縁膜41cをストッパ材として、O2プラズマによりレジストマスクをアッシング除去する。これにより、有機絶縁膜51及び無機絶縁膜41cを貫通するコンタクトホール31jが形成される。
本変形例において、有機絶縁膜51aは、図21、22に示すように、エッチバックされている。より具体的には、有機絶縁膜51aを成膜した後、第一配線層61が露出するまで有機絶縁膜51aをドライエッチングによりエッチバックする。続いて、無機絶縁膜41aを成膜し、四フッ化炭素(CF4)等を用いたドライエッチングによりコンタクトホール31c、31gとなる領域の無機絶縁膜41aを除去する。本変形例では、有機絶縁膜51aの厚さ分だけパッド部27とパッド部27以外の領域とにおける段差が低減するため、パッド部27とパッド部27以外の領域とにおけるACF80中の導電性微粒子81の変形量が緩和され、ACFの接触性をより向上することができる。
図2は、実施形態2の液晶表示装置の額縁領域における断面模式図であり、(a)は、端子部を示し、(b)は、周辺回路領域を示す。なお、本実施形態と実施形態1とで重複する内容についての説明は省略する。
本変形例において、有機絶縁膜51a、51bは、図25に示すように、感光性樹脂を用いて感光エッチングにより形成され、その後、無機絶縁膜41a、41bが成膜及びエッチングされることによってパターン形成されている。また、端子部においては、図25(a)に示すように、最上層配線層により形成されたパッド部27の下には最近接下層配線層69が設けられている。
図3は、実施形態3の液晶表示装置の端子部における断面模式図である。なお、本実施形態と実施形態1及び2とで重複する内容についての説明は省略する。
本変形例において、有機絶縁膜51a、51bは、図26に示すように、感光性樹脂を用いて感光エッチングにより形成され、その後、無機絶縁膜41a、41bが成膜及びエッチングされることによってパターン形成されている。
有機絶縁膜51bは、図27(a)に示すように、端子部において除去され、接続端子26上には直接、無機絶縁膜41bが形成されている。本変形例では、有機絶縁膜51bの厚さ分だけパッド部27とパッド部27以外の領域とにおける段差が低減するため、パッド部27とパッド部27以外の領域とにおけるACF80中の導電性微粒子81の変形量が更に緩和され、ACFの接触性をより向上することができる。
図4は、実施形態4の液晶表示装置の端子部における断面模式図である。なお、本実施形態と実施形態1~3とで重複する内容についての説明は省略する。
本変形例は、図29に示すように、パッド部27の最上層配線層の下に最近接下層配線層69が設けられている。
TFT基板14は、図5に示すように、ゲート電極(ゲート配線)25と同一層からなる接続端子(外部接続端子)26が端子部にまで延伸されるとともに、第一配線層61と、ITO膜等の透明導電膜とから構成されるパッド部27を有してもよい。これにより、無機絶縁膜41aを端子部に設けずとも、無機絶縁膜41を保護膜として機能されることができるので、図4で示した場合と同様の効果を奏することができる。
図6は、実施形態1~4に係る液晶表示装置の周辺回路領域における断面模式図である。また、図8-1(a)~(d)及び図8-2(e)~(g)は、製造工程における実施形態1~4に係る液晶表示装置の周辺回路領域における断面模式図である。なお、以下の実施形態と実施形態1~4とで重複する内容についての説明は省略する。
21:絶縁基板
22:ベースコート膜
23:半導体層
24:ゲート絶縁膜
25:ゲート電極(ゲート配線)
26:接続端子(外部接続端子)
27:パッド部
28:ソース・ドレイン電極
29:TFT
30a、30b、30c、30d、30e:引き回し配線
31a、31b、31c、31d、31e、31f、31g、31j:コンタクトホール
32a、32b、32c、32d:フォトマスク
33a、33b、33c:レジスト
34:ソース電極
35:ドレイン電極
36:画素電極
41、41a、41b、41c:無機絶縁膜
51、51a、51b:有機絶縁膜
61:第一配線層
62:第二配線層
63:第三配線層
65:ドレイン配線
66a、66b:補助容量上電極
67:補助容量下電極
68a、68b:画素補助容量
69:最近接下層配線層
70:FPC基板
71:接続端子
80:ACF
81:導電性微粒子
100、200、300、400、500:液晶表示装置
Claims (36)
- 絶縁基板上に、他の外部接続部品を接続するための接続端子が設けられた端子部と、周辺回路が設けられた周辺回路領域との少なくとも一方を備える表示装置用基板であって、
該表示装置用基板は、有機絶縁膜の直上に無機絶縁膜が積層された有機・無機膜積層体を有することを特徴とする表示装置用基板。 - 前記表示装置用基板は、前記端子部及び前記周辺回路領域を備えることを特徴とする請求項1記載の表示装置用基板。
- 前記表示装置用基板は、前記端子部に前記有機・無機膜積層体を有することを特徴とする請求項1又は2記載の表示装置用基板。
- 前記表示装置用基板は、前記周辺回路領域に前記有機・無機膜積層体を有することを特徴とする請求項1~3のいずれかに記載の表示装置用基板。
- 前記表示装置用基板は、前記有機・無機膜積層体を複数有することを特徴とする請求項1~4のいずれかに記載の表示装置用基板。
- 前記表示装置用基板は、前記端子部に前記複数の有機・無機膜積層体を有することを特徴とする請求項5記載の表示装置用基板。
- 前記表示装置用基板は、前記複数の有機・無機膜積層体の層間に設けられた複数の配線層を有し、
前記接続端子は、該複数の配線層のうち、最も絶縁基板側に位置する配線層を除く配線層を含んで構成されることを特徴とする請求項5又は6記載の表示装置用基板。 - 前記表示装置用基板は、前記複数の有機・無機膜積層体の層間に設けられた複数の配線層を有し、
前記接続端子は、該複数の配線層のうち、最も上層側に位置する配線層を含んで構成されることを特徴とする請求項5~7のいずれかに記載の表示装置用基板 - 前記表示装置用基板は、前記周辺回路領域に前記複数の有機・無機膜積層体を有することを特徴とする請求項5記載の表示装置用基板。
- 前記表示装置用基板は、前記端子部において、前記接続端子の直上に前記無機絶縁膜が積層された領域を有することを特徴とする請求項1~9のいずれかに記載の表示装置用基板。
- 前記表示装置用基板は、前記端子部に前記有機絶縁膜が設けられていないことを特徴とする請求項1又は2記載の表示装置用基板。
- 前記有機絶縁膜の開口部は、前記無機絶縁膜より上層の配線により覆われることを特徴とする請求項1~11のいずれかに記載の表示装置用基板。
- 前記有機絶縁膜は、感光性樹脂を含むことを特徴とする請求項1~12のいずれかに記載の表示装置用基板。
- 請求項13記載の表示装置用基板の製造方法であって、
該製造方法は、前記感光性樹脂を含む前記有機絶縁膜をエッチングする有機絶縁膜エッチング工程と、
該有機絶縁膜エッチング工程の後に、前記無機絶縁膜を成膜する無機絶縁膜成膜工程と、
該無機絶縁膜成膜工程の後に、前記無機絶縁膜をエッチングする無機絶縁膜エッチング工程とを含むことを特徴とする表示装置用基板の製造方法。 - 前記無機絶縁膜エッチング工程は、第一レジストを介して前記無機絶縁膜をドライエッチングすることを特徴とする請求項14記載の表示装置用基板の製造方法。
- 前記無機絶縁膜エッチング工程は、前記感光性樹脂を含む前記有機絶縁膜のエッチング除去された領域と重なる領域の前記無機絶縁膜をエッチング除去することを特徴とする請求項14又は15記載の表示装置用基板の製造方法。
- 前記表示装置用基板の製造方法は、前記有機絶縁膜エッチング工程の前に、第一フォトマスクを介して前記有機絶縁膜を感光する有機絶縁膜感光工程を含むことを特徴とする請求項14~16のいずれかに記載の表示装置用基板の製造方法。
- 前記表示装置用基板の製造方法は、前記無機絶縁膜成膜工程の後に、前記無機絶縁膜上に第二レジストを成膜するレジスト成膜工程と、
該レジスト成膜工程の後に、前記第一フォトマスクを介して該第二レジストを感光するレジスト感光工程とを含むことを特徴とする請求項17記載の表示装置用基板の製造方法。 - 請求項1~13のいずれかに記載の表示装置用基板の製造方法であって、
該製造方法は、レジストをマスクとしてウェットエッチングにより前記無機絶縁膜をエッチングする無機絶縁膜エッチング工程と、
該無機絶縁膜エッチング工程の後に、該レジストを除去するレジスト除去工程と、
該レジスト除去工程の後に、前記無機絶縁膜をマスクとして前記有機絶縁膜をエッチングする有機絶縁膜エッチング工程とを含むことを特徴とする表示装置用基板の製造方法。 - 請求項1~13のいずれかに記載の表示装置用基板の製造方法であって、
該製造方法は、レジストをマスクとしてドライエッチングにより前記無機絶縁膜をエッチングする無機絶縁膜エッチング工程と、
該無機絶縁膜エッチング工程の後に、ドライエッチングにより、該レジストをアッシング除去するとともに、前記無機絶縁膜をマスクとして前記有機絶縁膜をエッチングする工程とを含むことを特徴とする表示装置用基板の製造方法。 - 請求項1~13のいずれかに記載の表示装置用基板を備えることを特徴とする表示装置。
- 請求項14~20のいずれかに記載の表示装置用基板の製造方法により作製された表示装置用基板を備えることを特徴とする表示装置。
- 感光性樹脂を含む有機絶縁膜の直上に無機絶縁膜が積層された有機・無機膜積層体を有する多層配線の形成方法であって、
該形成方法は、該有機絶縁膜をエッチングする有機絶縁膜エッチング工程と、
該有機絶縁膜エッチング工程の後に、該無機絶縁膜を成膜する無機絶縁膜成膜工程と、
該無機絶縁膜成膜工程の後に、該無機絶縁膜をエッチングする無機絶縁膜エッチング工程とを含むことを特徴とする多層配線の形成方法。 - 前記無機絶縁膜エッチング工程は、第一レジストを介して前記無機絶縁膜をドライエッチングすることを特徴とする請求項23記載の多層配線の形成方法。
- 前記無機絶縁膜エッチング工程は、前記感光性樹脂を含む前記有機絶縁膜のエッチング除去された領域と重なる領域の前記無機絶縁膜をエッチング除去することを特徴とする請求項23又は24記載の多層配線の形成方法。
- 前記多層配線の形成方法は、前記有機絶縁膜エッチング工程の前に、第一フォトマスクを介して前記有機絶縁膜を感光する有機絶縁膜感光工程を含むことを特徴とする請求項23~25のいずれかに記載の多層配線の形成方法。
- 前記多層配線の形成方法は、前記無機絶縁膜成膜工程の後に、前記無機絶縁膜上に第二レジストを成膜するレジスト成膜工程と、
該レジスト成膜工程の後に、前記第一フォトマスクを介して該第二レジストを感光するレジスト感光工程とを含むことを特徴とする請求項26記載の多層配線の形成方法。 - 有機絶縁膜の直上に無機絶縁膜が積層された有機・無機膜積層体を有する多層配線の形成方法であって、
該形成方法は、レジストをマスクとしてウェットエッチングにより該無機絶縁膜をエッチングする無機絶縁膜エッチング工程と、
該無機絶縁膜エッチング工程の後に、該レジストを除去するレジスト除去工程と、
該レジスト除去工程の後に、該無機絶縁膜をマスクとして該有機絶縁膜をエッチングする有機絶縁膜エッチング工程とを含むことを特徴とする多層配線の形成方法。 - 有機絶縁膜の直上に無機絶縁膜が積層された有機・無機膜積層体を有する多層配線の形成方法であって、
該形成方法は、レジストをマスクとしてドライエッチングにより該無機絶縁膜をエッチングする無機絶縁膜エッチング工程と、
該無機絶縁膜エッチング工程の後に、ドライエッチングにより、該レジストをアッシング除去するとともに、該無機絶縁膜をマスクとして該有機絶縁膜をエッチングする工程とを含むことを特徴とする多層配線の形成方法。 - 絶縁基板上に、平坦化膜の直上に無機絶縁膜が積層された平坦化膜・無機膜積層体を有する多層配線基板であって、
該平坦化膜の開口部の壁面の少なくとも上層側の一部は、該無機絶縁膜で覆われていることを特徴とする多層配線基板。 - 前記平坦化膜の開口部の壁面の全部は、前記無機絶縁膜で覆われていることを特徴とする請求項30記載の多層配線基板。
- 前記平坦化膜は、有機絶縁膜であることを特徴とする請求項30又は31記載の多層配線基板。
- 前記有機絶縁膜は、感光性樹脂を含むことを特徴とする請求項32記載の多層配線基板。
- 前記平坦化膜は、無機絶縁膜であることを特徴とする請求項30又は31記載の多層配線基板。
- 前記平坦化膜の開口部は、前記無機絶縁膜より上層の配線により覆われることを特徴とする請求項30~34のいずれかに記載の多層配線基板。
- 前記多層配線基板は、表示装置用基板であることを特徴とする請求項30~35のいずれかに記載の多層配線基板。
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| JP2007288127A (ja) * | 2005-10-18 | 2007-11-01 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
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| JP2846351B2 (ja) | 1989-07-27 | 1999-01-13 | 株式会社日立製作所 | 液晶表示装置 |
| JPH03183756A (ja) | 1989-12-13 | 1991-08-09 | Sumitomo Chem Co Ltd | 多層配線形成方法 |
| JP2003114646A (ja) * | 2001-08-03 | 2003-04-18 | Semiconductor Energy Lab Co Ltd | 表示装置及びその駆動方法。 |
| US20050109533A1 (en) * | 2002-08-27 | 2005-05-26 | Fujitsu Limited | Circuit board and manufacturing method thereof that can easily provide insulating film between projecting electrodes |
| JP2004119016A (ja) | 2002-09-20 | 2004-04-15 | Semiconductor Energy Lab Co Ltd | 発光装置 |
| EP1581010A1 (en) * | 2004-03-26 | 2005-09-28 | Sony Deutschland GmbH | Image generation unit |
| JP4952425B2 (ja) * | 2006-08-21 | 2012-06-13 | ソニー株式会社 | 液晶装置および電子機器 |
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2008
- 2008-10-29 CN CN200880127511.2A patent/CN101971235B/zh not_active Expired - Fee Related
- 2008-10-29 WO PCT/JP2008/069689 patent/WO2009110136A1/ja not_active Ceased
- 2008-10-29 US US12/920,849 patent/US8710375B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005352498A (ja) * | 2002-01-16 | 2005-12-22 | Seiko Epson Corp | 表示装置、電子機器、および表示装置の製造方法 |
| JP2007288127A (ja) * | 2005-10-18 | 2007-11-01 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102162945A (zh) * | 2010-02-22 | 2011-08-24 | 索尼公司 | 液晶显示面板 |
| JP2011170233A (ja) * | 2010-02-22 | 2011-09-01 | Sony Corp | 液晶表示パネル |
| US8823915B2 (en) | 2010-02-22 | 2014-09-02 | Japan Display West Inc. | Liquid crystal display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101971235A (zh) | 2011-02-09 |
| US20110000705A1 (en) | 2011-01-06 |
| US8710375B2 (en) | 2014-04-29 |
| CN101971235B (zh) | 2013-09-18 |
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