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WO2009151077A1 - Procédé de fabrication de plaque de silicium monocristalline, et plaque de silicium monocristalline - Google Patents

Procédé de fabrication de plaque de silicium monocristalline, et plaque de silicium monocristalline Download PDF

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Publication number
WO2009151077A1
WO2009151077A1 PCT/JP2009/060620 JP2009060620W WO2009151077A1 WO 2009151077 A1 WO2009151077 A1 WO 2009151077A1 JP 2009060620 W JP2009060620 W JP 2009060620W WO 2009151077 A1 WO2009151077 A1 WO 2009151077A1
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Prior art keywords
wafer
single crystal
heat treatment
silicon single
igbt
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Japanese (ja)
Inventor
渉 杉村
敏昭 小野
成志 三田
孝明 塩多
亘 伊藤
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Sumco Corp
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Sumco Corp
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    • H10P36/20—
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20—Controlling or regulating
    • C30B15/203—Controlling or regulating the relationship of pull rate (v) to axial thermal gradient (G)
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs

Definitions

  • the present invention relates to a method for manufacturing a silicon single crystal wafer and a silicon single crystal wafer, and in particular, from a wafer having a DZ layer having a thickness of about 150 ⁇ m or more applicable to the manufacture of an insulated gate bipolar transistor (IGBT) to a normal device.
  • IGBT insulated gate bipolar transistor
  • a silicon single crystal wafer manufactured under conditions of heat treatment (RTA treatment) by rapid heating and rapid cooling is subjected to oxygen precipitate formation heat treatment (hereinafter referred to as “precipitation heat treatment”), thereby enabling wafers applicable to IGBT manufacturing and general
  • RTA treatment heat treatment
  • precipitation heat treatment oxygen precipitate formation heat treatment
  • IGBT Insulated Gate Bipolar Transistor
  • the IGBT is a gate voltage-driven switching element suitable for controlling high power, and is used in inverters for trains, hybrid cars, air conditioners, refrigerators, etc. It has been.
  • the IGBT is provided with three electrodes, ie, an emitter E, a collector C, and a gate G.
  • the gate is formed on the surface side of the element through an insulating oxide film SiO 2.
  • the current between the emitter E on the device surface side and the collector C on the back surface side is controlled by the applied voltage.
  • the IGBT is an element that controls current with a gate insulated by an oxide film
  • the quality of the gate oxide film (Gate Oxide Integrity, hereinafter referred to as GOI) is important. If a defect is included in the silicon single crystal wafer, the defect is taken into the gate oxide film and causes a dielectric breakdown of the oxide film.
  • a general device such as an LSI used for a memory or the like is an element that uses only the vicinity of the wafer surface in the lateral direction.
  • the IGBT is an element that uses the wafer in the vertical direction (thickness direction). Therefore, the thickness of the defect-free layer (hereinafter referred to as “DZ layer”) in the vicinity of the surface is generally It is necessary to set it thicker than that of other devices.
  • DZ layer defect-free layer
  • the IGBT is not an element that uses only the vicinity of the surface of the wafer in the horizontal direction like an LSI such as a memory, but is an element that uses the wafer in the vertical direction (thickness direction) as shown in FIGS. 5A to 5C.
  • Properties are affected by the bulk quality of the wafer.
  • recombination lifetime and resistivity are important qualities. Since the recombination lifetime is reduced by crystal defects in the substrate, it is necessary to control so that no crystal defects occur even after the device process. Regarding the resistivity, uniformity and stability are required.
  • the wafer is uniform not only in the plane of the wafer but also between the wafers, that is, in the length direction of the silicon ingot, and does not change even after the device thermal process. If a plurality of received elements on the wafer plane, that is, a plurality of elements are provided in parallel, if the resistivity differs between these elements, a large current concentrates on the low resistivity element and breaks. Therefore, the uniformity and stability of the resistivity are important. As described above, when a plurality of elements are miniaturized in parallel, a large current is concentrated due to the difference in resistivity, and the current is concentrated on a specific element, resulting in damage. It is important that the process does not change.
  • an epitaxy wafer (hereinafter referred to as an epi wafer) is used as a substrate for a so-called punch through (hereinafter referred to as PT) IGBT in which a depletion layer contacts the collector side when the current is turned off.
  • PT punch through
  • the PT type IGBT has a problem of high cost because it uses an epi-wafer. Also, switching loss increases at high temperatures for lifetime control. For this reason, the ON voltage decreases at a high temperature, and current may concentrate on a specific element during parallel use, causing damage.
  • NPT non-punch through
  • FZ floating zone method
  • the FZ wafer is cheaper than the epi wafer, it is necessary to increase the diameter of the wafer in order to further reduce the manufacturing cost of the IGBT.
  • Patent Document 1 describes that the entire surface is grown by the CZ method and doped with nitrogen.
  • a wafer is disclosed.
  • Patent Document 2 discloses a method for producing a silicon single crystal that is pulled using the Czochralski method while being doped with oxygen and nitrogen, and 6.5 ⁇ 10 17 atoms / A method for producing a silicon single crystal doped with oxygen at a concentration of less than cm 3 and nitrogen at a concentration of more than 5 ⁇ 10 13 atoms / cm 3 is disclosed. Further, in Patent Document 3, a nitrogen concentration of 2 ⁇ 10 14 atoms / cm 3 or more and 2 ⁇ 10 16 atoms / cm 3 or less grown from a melt added with nitrogen by the Czochralski method, and 7 ⁇ 10 17 atoms is used.
  • a silicon semiconductor substrate is disclosed in which the defect density is LSTD ⁇ 1 ⁇ 10 5 / cm 3 and the oxide film breakdown voltage characteristics are TZDB high C mode pass rate ⁇ 90% and TDDB pass rate ⁇ 90%.
  • JP 2001-146498 A Japanese Patent Laid-Open No. 2000-7486 JP 2002-29891 A JP 2004-87592 A JP 2003-297839 A
  • a polycrystalline silicon layer (EG layer) is formed as a gettering layer on the back side of the wafer to remove heavy metal contamination in the manufacturing process of general devices and IGBTs.
  • EG layer polycrystalline silicon layer
  • the distance between the DZ layer and the IG layer near the surface used as the device is as short as possible. That is, the IG layer is preferably located near the surface.
  • the IGBT is an element that uses the wafer in the vertical direction (thickness direction), and its characteristics are easily affected by the bulk quality of the wafer. Therefore, in the IGBT wafer, the IG layer is preferably positioned at the center of the wafer in the thickness direction.
  • wafer specifications can be changed at the end of these conditions from wafers for IGBTs that require different BMD density distributions to wafers for normal devices such as memories, regardless of pulling conditions and RTA conditions. There was a demand to do it. In addition, there is a demand for reducing the wafer manufacturing cost by making it possible to change the specifications of the product wafer during the manufacturing process.
  • wafers with different specifications can be manufactured from wafers manufactured under the same single crystal pulling conditions and RTA processing conditions, the single crystal pulling conditions and RTA processing conditions are set for each product. There is no need, and the production volume of wafers with different specifications can be flexibly adjusted according to demand. Furthermore, it is possible to immediately respond to a request from a device manufacturer to change the specification of a wafer.
  • the present invention changes the heat treatment temperature and heat treatment time of the precipitation heat treatment process for wafers manufactured under the same single crystal ingot pulling conditions and the same RTA processing conditions. It is an object of the present invention to provide a silicon single crystal wafer manufacturing method and a silicon single crystal wafer capable of manufacturing wafers having different specifications such as a wafer applicable to manufacture and a wafer applicable to manufacture of a general device.
  • the present invention has a thickness 5 that can be applied to the manufacture of a normal device from a wafer having a DZ layer of about 150 ⁇ m or more that can be applied to the manufacture of an insulated gate bipolar transistor (IGBT).
  • IGBT insulated gate bipolar transistor
  • the method for producing a silicon single crystal wafer according to the present invention includes a pulling step of pulling up a silicon single crystal ingot at a pulling speed capable of pulling a silicon single crystal ingot having no grown-in defect by the Czochralski method, An RTA process for performing heat treatment (RTA process) by rapid heating and rapid cooling in a nitrogen-containing atmosphere on the wafer obtained by slicing, and a distribution of oxygen precipitate density in the thickness direction of the wafer after the RTA process
  • RTA process for performing heat treatment
  • the silicon single crystal ingot is pulled at a pulling speed capable of pulling a silicon single crystal ingot having no grown-in defect by the Czochralski method. Since there is no defect such as COP inside the wafer obtained by slicing from this single crystal ingot, it is necessary to separately perform heat treatment for removing the defect such as COP existing in the vicinity of the wafer surface before performing the RTA process. As a result, the manufacturing process is shortened and the manufacturing cost is reduced. In addition, a wafer obtained by slicing a silicon single crystal ingot having no grown-in defects is suitable as a raw material for IGBT.
  • the RTA process of the wafer is performed in a nitrogen-containing atmosphere, a distribution of the vacancy concentration is obtained in the thickness direction of the wafer so that the vacancy concentration peak injected by the RTA process exists in the vicinity of the wafer surface. It is done.
  • the density distribution of oxygen precipitates in the thickness direction of the wafer By changing the temperature and time of the precipitation heat treatment, the density distribution of oxygen precipitates in the thickness direction of the wafer And a desired oxygen precipitate density can be obtained in the thickness direction of the wafer.
  • FIG. 1 by combining the heat treatment temperature and the heat treatment time, the following four types of oxygen precipitate density distributions can be obtained as shown in FIG. (P1) Distribution having a peak only in the central portion in the thickness direction of the wafer (p2) Distribution having a peak in the surface portion in the thickness direction and the central portion of the wafer (p3) Peak near the surface in the thickness direction of the wafer Distribution (p4) Uniform distribution from near the wafer surface to the center
  • the distribution of (p1) is suitable for an IGBT wafer because the thickness of the DZ layer formed on the wafer surface layer is thick.
  • the distribution of the above (p2), (p3) and (p4) is suitable for a general device because the thickness of the DZ layer formed on the wafer surface layer is thinner than the above (p1). Also, since the density of oxygen precipitates is high near the surface of the wafer, a proximity gettering effect is obtained, and the device formation region (DZ layer) is contaminated with heavy metals even when the heat treatment in the device process is performed at a low temperature. Can be prevented.
  • (p2) has a high density of oxygen precipitates in the central portion in the wafer thickness direction
  • (p4) has a high density of oxygen precipitates in the entire thickness direction of the wafer excluding the surface layer portion. In either case, the IG effect is higher than in (p3).
  • the method for producing a silicon single crystal wafer of the present invention is a method for producing a silicon single crystal wafer obtained by growing a silicon single crystal by the Czochralski method, A pulling step of pulling up the silicon single crystal; A hole injection step of subjecting a wafer sliced from the silicon single crystal to an RTA treatment at 1000 to 1250 ° C. in a hole injection effect gas atmosphere; A vacancy control heat treatment step for controlling a vacancy density distribution in the thickness direction of the wafer by performing a heat treatment in a temperature range of 600 ° C. to 1150 ° C.
  • the oxygen precipitate density distribution after the hole control heat treatment is (P1) Precipitates only at the center of the bulk in the wafer thickness direction (p2) Precipitates near the wafer surface and the bulk center (p3) Precipitates only near the wafer surface (p4) 4 Precipitates uniformly from the vicinity of the wafer surface to the bulk Control is performed so that one state selected from the pattern is obtained.
  • the oxygen precipitate density distribution after the pore control heat treatment is (P1)
  • the heat treatment temperature T (° C.) and the heat treatment time t (hour) are shown in the attached drawing FIG.
  • P2 set to a value within the range surrounded by the point F (950, 1), the point B (750, 4), the point C (600, 10), the point H (600, 18), and the point G (950, 3)
  • Heat treatment condition or The oxygen precipitate density distribution after the pore control heat treatment is (P3)
  • the heat treatment temperature T (° C.) and the heat treatment time t (hours) are indicated by the points (T, t) in FIG.
  • the oxygen precipitate density distribution after the pore control heat treatment is (P4)
  • the heat treatment temperature T (° C.) and the heat treatment time t (time) are indicated by the points (T, t) in FIG. like, A range surrounded by a point H (600, 18), a point G (950, 3), a point J (950, 16), and / or a point K (1050, 16), a point L (1050, 1), a point
  • the pore control heat treatment may have a first step of 600 to 1100 ° C. for 0 to 8 hours and a second step of 1000 to 1100 ° C. for 10 to 20 hours.
  • the pulling step the pulling rate of the silicon single crystal is such that the grown-in defect-free silicon single crystal can be pulled, and the interstitial oxygen concentration is 1 ⁇ 10 17 atoms / cm 3 or more and 15 ⁇ 10 A single crystal of 17 atoms / cm 3 or less can be grown.
  • the silicon single crystal wafer of the present invention can be manufactured by any of the manufacturing methods described above.
  • the method for producing a silicon single crystal wafer of the present invention is a method for producing a silicon single crystal wafer obtained by growing a silicon single crystal by the Czochralski method, A pulling step of pulling up the silicon single crystal; A hole injection step of subjecting a wafer sliced from the silicon single crystal to an RTA treatment at 1000 to 1250 ° C. in a hole injection effect gas atmosphere; A vacancy control heat treatment step for controlling a vacancy density distribution in the thickness direction of the wafer by performing a heat treatment in a temperature range of 600 ° C. to 1150 ° C.
  • the oxygen precipitate density distribution after the hole control heat treatment is (P1) Precipitates only at the center of the bulk in the wafer thickness direction (p2) Precipitates near the wafer surface and the bulk center (p3) Precipitates only near the wafer surface (p4) 4 Precipitates uniformly from the vicinity of the wafer surface to the bulk
  • the cooling rate is preferably set to 3 to 10 ° C./min or about 5 ° C./min. This is a cooling rate that does not inject holes.
  • the method for producing a silicon single crystal wafer of the present invention is a method for producing a silicon single crystal wafer obtained by growing a silicon single crystal by the Czochralski method, A pulling step of pulling up the silicon single crystal; A hole injection step of subjecting a wafer sliced from the silicon single crystal to an RTA treatment at 1000 to 1250 ° C. in a hole injection effect gas atmosphere; A vacancy control heat treatment step for controlling a vacancy density distribution in the thickness direction of the wafer by performing a heat treatment in a temperature range of 600 ° C. to 1150 ° C.
  • the oxygen precipitate density distribution after the hole control heat treatment is (P1) Precipitates only at the center of the bulk in the wafer thickness direction (p2) Precipitates near the wafer surface and the bulk center (p3) Precipitates only near the wafer surface (p4) 4 Precipitates uniformly from the vicinity of the wafer surface to the bulk Control is performed so that one state selected from the pattern is obtained.
  • the oxygen precipitate density distribution after the pore control heat treatment is (P1)
  • the heat treatment temperature T (° C.) and the heat treatment time t (hour) are shown in the attached drawing FIG.
  • P2 set to a value within the range surrounded by the point F (950, 1), the point B (750, 4), the point C (600, 10), the point H (600, 18), and the point G (950, 3)
  • Heat treatment condition or The oxygen precipitate density distribution after the pore control heat treatment is (P3)
  • the heat treatment temperature T (° C.) and the heat treatment time t (hours) are indicated by the points (T, t) in FIG.
  • P3 heat treatment conditions set to values within a range surrounded by point A (750, 1), point B (750, 4), point F (950, 1),
  • the oxygen precipitate density distribution after the pore control heat treatment is (P4)
  • the heat treatment temperature T (° C.) and the heat treatment time t (time) are indicated by the points (T, t) in FIG.
  • a first step of 600 to 1100 ° C. for 0 to 8 hours and a second step of 1000 to 1100 ° C. for 10 to 20 hours are set as described above.
  • the thickness of the DZ layer (P1) About 10 to 20 ⁇ m, or about 100 to 200 ⁇ m, or about 150 ⁇ m or more for wafer (p2) 2 to 20 ⁇ m for wafer (P3) 2 to 20 ⁇ m on the wafer (P4) With a wafer, it becomes possible to realize about 2 to 20 ⁇ m, about 100 to 200 ⁇ m, or about 150 ⁇ m or more.
  • the peak value of BMD density serving as a gettering site can be 5 ⁇ 10 5 pieces / cm 2 or more and about 1 ⁇ 10 6 to 1 ⁇ 10 7 pieces / cm 2 in each wafer. It becomes.
  • FIG. 2 is a model diagram comparing the BMD density distribution after the precipitation heat treatment between a one-step heat treatment at 1000 ° C. for 16 hours (hr) and a two-step heat treatment including a heat treatment at less than 1000 ° C. before this one-step treatment.
  • a region where the hatched portion BMD is deposited is shown.
  • the vacancy concentration distribution immediately after vacancies injection there is a result of measuring the impurity concentration in the depth direction by DLTS using the Pt diffusion method (FIG. 3), and the RTA treatment in the NH 3 atmosphere peaks 50 ⁇ m from the surface layer.
  • the vacancy concentration distribution is distributed like a mountain.
  • a compressive stress is applied at the interface between the matrix Si and the nitride film due to the formation of the surface nitride film. It is thought that this is due to the injection of holes.
  • the surface layer deposition proceeds faster than the bulk deposition because the surface layer has a high degree of vacancy supersaturation, and therefore it is considered that interstitial Si is injected into the interior accompanying the surface layer deposition.
  • the supersaturation degree of interstitial Si around the precipitation nuclei is high, so that the precipitation is suppressed, and a BMD density distribution in which precipitation occurs only on the surface layer is obtained.
  • oxygen outdiffusion becomes remarkable as compared with low temperature heat treatment such as 800 ° C., so that oxygen precipitation in the vicinity of the surface layer does not occur. Therefore, it is considered that interstitial Si is not injected into the inside, and as a result, it is deposited only in the bulk center.
  • the pulling rate of the silicon single crystal is such that the grown-in defect-free silicon single crystal can be pulled, and the interstitial oxygen concentration is 1 ⁇ 10 17 atoms / cm 3 or more and 15 ⁇ 10
  • the interstitial oxygen concentration is preferably 10 ⁇ 10 17 atoms / cm 3 to 15 ⁇ 10 17 atoms / cm 3 for a wafer having a proximity gettering effect, which is a concentration at which proximity gettering can be expected.
  • the interstitial oxygen is preferably 2 ⁇ 10 17 atoms / cm 3 to 8.5 ⁇ 10 17 atoms / cm 3 in a power device wafer such as an IGBT wafer.
  • Patent Documents 1 to 3 disclose a method for manufacturing a wafer free from crystal defects, the wafer characteristics necessary for the IGBT are not clarified.
  • a quartz crucible is rotated. The speed and the rotation speed of the crystal need to be significantly changed from the conventional conditions, and the pulling speed margin for growing defect-free crystals is reduced, resulting in a decrease in yield.
  • a polycrystalline silicon layer as a gettering layer is formed on the back side of the wafer to remove heavy metal contamination in the IGBT manufacturing process.
  • This polysilicon layer formation is a work process. It is preferable not to do this because it increases and increases manufacturing costs.
  • the IGBT device process it is necessary to have gettering capability, and an IGBT silicon single crystal wafer having IG capability without being subjected to EG has been demanded.
  • the present invention is capable of expanding the pulling speed margin in a wafer requiring an oxygen precipitate density distribution for IGBT, and does not require EG treatment, and has a sufficient thickness as an IGBT wafer.
  • An IGBT silicon single crystal wafer manufacturing method and an IGBT silicon single crystal wafer capable of manufacturing a wafer having a layer and having an IG capability and a small variation in resistivity can be provided.
  • a silicon single crystal wafer requiring an oxygen precipitate density distribution for IGBT is manufactured by the Czochralski method (hereinafter sometimes referred to as CZ method)
  • CZ method a large-diameter wafer having a diameter of about 300 mm can be manufactured.
  • the wafers manufactured by the CZ method were not suitable for IGBT wafers for the following reasons.
  • COP defects Crystal Originated Particles
  • a gate oxide film is formed on the wafer surface.
  • the silicon single crystal wafer manufactured by the CZ method contains excess oxygen of about 1 ⁇ 10 18 atoms / cm 3 , and such a wafer has a low temperature of about 1 hour at 450 ° C.
  • the resistivity of a silicon single crystal wafer manufactured by the CZ method can be controlled by the amount of dopant added to the silicon melt, and phosphorus is added to the IGBT wafer as a dopant, but phosphorus has a segregation coefficient. Since it is small, the concentration greatly changes along the length direction of the silicon single crystal. Therefore, within a single silicon single crystal, the range of wafers having a resistivity that matches the design specifications is narrow.
  • the silicon single crystal wafer manufactured by the CZ method contains excess oxygen of about 1 ⁇ 10 18 atoms / cm 3. Oxygen precipitates as SiO 2 and degrades the recombination lifetime.
  • CZ silicon contains about 10 ⁇ 10 17 atoms / cm 3 of oxygen, and oxygen donors are generated when subjected to low-temperature heat treatment at 450 ° C. for about 1 hour in the IGBT device process. The rate will change.
  • the nitrogen-doped crystal is subjected to a heat treatment (typically 650 ° C. ⁇ 30 minutes) for eliminating the oxygen donor.
  • a heat treatment typically 650 ° C. ⁇ 30 minutes
  • an Al wiring sintering process is performed at a temperature around 450 ° C. Therefore, there is a problem that the resistivity in the device region where the IGBT device is formed becomes higher than the resistivity at the time of wafer shipment when the device manufacturing process is performed.
  • the oxygen precipitate BMD does not exist in the device region which is about 100 to 200 ⁇ m in the depth direction from the uppermost surface of the wafer.
  • IG gettering
  • the present inventors have conducted extensive research. As a result, by adopting the following configuration, a wafer having wafer characteristics necessary for the IGBT is obtained. It was found that it can be manufactured by the method.
  • the silicon single crystal wafer for IGBT of the present invention is a silicon single crystal wafer for IGBT composed of a silicon single crystal grown by the Czochralski method, A device region provided on the entire surface of the wafer and having an IGBT device formed on the front surface side, and a gettering region located on the back side of the device region and removed after device formation;
  • the thickness direction dimension of the device region is 100 to 200 ⁇ m, COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, the interstitial oxygen concentration is 8.5 ⁇ 10 17 atoms / cm 3 or less, and the variation in resistivity within the wafer surface is 5% or less. It is characterized by.
  • the oxygen precipitate density of 20 nm or more is 5 ⁇ 10 3 pieces / cm 3 or less after the device process heat treatment for IGBT in the device region, and 20 nm after the device process heat treatment for IGBT in the gettering region.
  • the oxygen precipitate density can be 5 ⁇ 10 4 pieces / cm 3 or more and 1 ⁇ 10 7 pieces / cm 3 or less.
  • the silicon single crystal may have 5 ⁇ 10 12 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less, or 1 ⁇ 10 13 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less. Nitrogen can be doped.
  • the silicon single crystal is grown at a pulling speed capable of pulling a grown-in defect-free silicon single crystal when grown by the Czochralski method, and the silicon after pulling
  • the single crystal may be formed by neutron irradiation to be doped with phosphorus.
  • the method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, A pulling step of growing a single crystal having an interstitial oxygen concentration of 8.5 ⁇ 10 17 atoms / cm 3 or less at a speed capable of pulling a silicon single crystal at a growth rate of a grown-in defect-free silicon single crystal; A hole injection step of performing RTA treatment of a wafer sliced from the single crystal at 1175 ° C. or higher; After the hole injecting step, heat treatment is performed at a temperature range of 1000 ° C. to 1100 ° C.
  • the silicon single crystal can be doped with nitrogen of 5 ⁇ 10 12 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less.
  • a hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less can be introduced into the atmospheric gas in the CZ furnace.
  • an n-type dopant is added to the silicon melt, or phosphorus is added to the silicon melt at 2.9 ⁇ 10 13 atoms / cm 3 or more and 2.9.
  • a p-type dopant having a segregation coefficient smaller than that of phosphorus is 10 ⁇ 15 atoms / cm 3 or less, and the concentration in the crystal is 1 ⁇ 10 13 atoms / cm 3 or more and 1 ⁇ 10 15 atoms / cm 3 according to the segregation coefficient.
  • Phosphorus can be doped by adding to the following or by irradiating the pulled silicon single crystal with neutrons.
  • the silicon single crystal wafer for IGBT of the present invention is a silicon single crystal wafer for IGBT composed of a silicon single crystal grown by the Czochralski method, A device region provided on the entire surface of the wafer and having an IGBT device formed on the front surface side, and a gettering region located on the back side of the device region and removed after device formation;
  • the thickness direction dimension of the device region is 100 to 200 ⁇ m, COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, the interstitial oxygen concentration is 8.5 ⁇ 10 17 atoms / cm 3 or less, and the variation in resistivity within the wafer surface is 5% or less.
  • BMD does not occur in the device area where the IGBT is formed (wafer outermost surface to hundreds of tens of ⁇ m), and the bulk area (other than a few tens of ⁇ m from the front and back surfaces) in the thickness area removed by back grinding )
  • BMD is intentionally made by RTA processing.
  • the device region there is no change in resistivity that affects the device characteristics as being defect-free, and EG processing is performed without performing EG processing, and handling capability in the device process is improved. It is possible to improve and prevent heavy metal contamination that affects device manufacturing.
  • vacancy existing in the surface layer is stable when low-temperature heat treatment from 600 ° C to 900 ° C is performed for a long time during the initial device process.
  • a BMD is formed at a high density in a device region having a thickness of 100 to 200 ⁇ m or 150 ⁇ m from the surface layer in a subsequent heat treatment step in the device process, which causes deterioration in IGBT characteristics. Therefore, by subjecting the vacancies in the vicinity of the surface layer injected by the vacancy injection RTA process to a heat treatment of about 1 to 16 hours at a temperature of 1000 ° C. to 1100 ° C.
  • the device region can be protected from metal contamination by the gettering (IG) effect of BMD included in a deep position of 150 ⁇ m or more from the outermost surface.
  • the completed IGBT element does not include the BMD, and hence the IGBT characteristics are not deteriorated by the BMD.
  • the silicon single crystal wafer for IGBT according to the present invention has IG capability in the wafer from the beginning in the device process, the manufacturing cost can be reduced by omitting the EG processing such as polysilicon film formation processing (PBS) on the back surface. Is also possible.
  • PBS polysilicon film formation processing
  • the oxygen precipitate density of 20 nm or more is 5 ⁇ 10 3 pieces / cm 3 or less after the device process heat treatment for IGBT in the device region, and 20 nm after the device process heat treatment for IGBT in the gettering region.
  • the oxygen precipitate density is 5 ⁇ 10 4 pieces / cm 3 or more and 1 ⁇ 10 7 pieces / cm 3 or less, a gettering region having sufficient gettering capability on the device region side inside the gettering region It is possible to provide a wafer having a device region that is homogeneous in the wafer thickness direction inside the device region and has a device region in which the IGBT characteristics do not deteriorate after the IGBT device process.
  • oxygen deposition does not occur in the wafer thickness direction from the outermost surface of the wafer through the IGBT device process, that is, a device region having a uniform thickness dimension of about 100 to 200 ⁇ m in which BMD is not detected,
  • the BMD In contact with the device region, through the IGBT device process, the BMD is approximately homogeneous in the wafer thickness direction and the density of oxygen precipitates of 20 nm or more is 5 ⁇ 10 4 pieces / cm 3 or more and 1 ⁇ 10 7 pieces / cm 3 or less.
  • a wafer having a layer and a back side region having the same characteristics as the device region from the BMD layer to the back surface of the wafer can be obtained.
  • the silicon single crystal wafer for IGBT of the present invention is an IGBT silicon single crystal wafer made of silicon single crystal grown by the Czochralski method, and COP defects and dislocation clusters are eliminated in the entire crystal diameter direction.
  • the interstitial oxygen concentration is 8.5 ⁇ 10 17 atoms / cm 3 or less, and the variation in resistivity within the wafer surface is 5% or less.
  • the silicon single crystal is grown at a pulling speed capable of pulling up the grown-in defect-free silicon single crystal when grown by the Czochralski method. It is preferable that the silicon single crystal after pulling is irradiated with neutron and doped with phosphorus.
  • the silicon single crystal wafer for IGBT of the present invention when the silicon single crystal is grown by the Czochralski method, the grown-in defect free from the silicon melt doped with the n-type dopant. It is preferable that the silicon single crystal is grown at a pulling speed capable of pulling up. Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the silicon single crystal is preferably doped with nitrogen of 5 ⁇ 10 12 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less.
  • the pass rate of TZDB at a breakdown electric field of 8 MV / cm is 90% or more, and oxygen donors generated when heat treatment is performed at 450 ° C. for 1 hour.
  • the density is 9.8 ⁇ 10 12 pieces / cm 3 or less, and the density of BMD precipitated when two-stage heat treatment is performed at 800 ° C. for 4 hours and 1000 ° C. for 16 hours is 5 ⁇ 10 7 pieces / cm 3.
  • the recombination lifetime when the two-stage heat treatment is performed is preferably 100 ⁇ sec or more.
  • phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus are 1 ⁇ 10 13 atoms / cm 3 or more and 1 ⁇ 10 15 atoms / cm 3, respectively. It is preferably contained in the following concentrations.
  • the LPD density on the wafer surface is 0.1 piece / cm 2 or less, and the light etching defect density is 1 ⁇ 10 3 pieces / cm 2 or less. Is preferred.
  • the variation in resistivity is measured at a total of three locations: the wafer center, a position between the wafer center and the periphery, and a position 5 mm from the wafer periphery.
  • Select the maximum value and the minimum value and use the value obtained by the formula (maximum value ⁇ minimum value) ⁇ 100 / minimum value.
  • the OSF region means that the temperature is raised from 900 ° C. to 1000 ° C. in a dry oxygen atmosphere at a heating rate of 5 ° C./min, then 1000 ° C. for 1 hour in a dry oxygen atmosphere, and then a wet oxygen atmosphere After heating at 1000 ° C. to 1150 ° C. at a rate of temperature increase of 3 ° C./min, heat treatment is performed at 1150 ° C.
  • the OSF region is formed for 2 hours in a wet oxygen atmosphere and then to 900 ° C., and then 2 ⁇ m light etching is performed to form the OSF region.
  • the Pv region and the Pi region are silicon single crystal ingots grown by the Czochralski method, and a region where interstitial silicon type point defects exist predominantly in the ingot is defined as an I region,
  • a region in which defects exist predominantly is a V region, and a region in which no interstitial silicon type point defect aggregates and no vacancy type point defect aggregates exist is a P region
  • the region below the lowest interstitial silicon concentration that belongs to the P region and can form interstitial dislocations is defined as the Pi region, and the region that is adjacent to the OSF region and that is below the vacancy concentration that can belong to the P region and form COP is defined as Pv. This is an area.
  • a silicon wafer is produced by pulling up an ingot from a silicon melt in a furnace with a predetermined pulling speed profile based on the Boronkov theory by the CZ method, and then cutting out the ingot.
  • point defects and agglomerates of point defects are generated as defects in the silicon single crystal. Will occur.
  • a vacancy is one in which one silicon atom leaves one of its normal positions in the silicon crystal lattice.
  • silicon atoms existing at positions (interstitial sites) other than the lattice points of the silicon crystal are interstitial silicon atoms.
  • Point defects are generally formed at the contact surface between a silicon melt (molten silicon) and an ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface begins to cool as it is pulled up. During cooling, vacancies or interstitial silicon atoms diffuse to form dislocation clusters that are COPs or interstitial agglomerates of vacancy agglomerates. In other words, the aggregate is a three-dimensional structure generated due to the merge of point defects.
  • the agglomerates of vacancy-type point defects include defects called LSTD (Laser Scattering Tomograph Defects) or FPD (Flow Pattern Defects) in addition to the above-mentioned COP. Contains a defect called.
  • LSTD is a source that generates a scattered light having a refractive index different from that of silicon when an infrared ray is irradiated into a silicon single crystal.
  • the V region, the OSF region, the Pv region, the Pi region, and the I region are in this order.
  • G (° C./mm) specific to the pulling apparatus is calculated by electrothermal analysis software, a pulling experiment in which the pulling speed is gradually reduced is carried out, and the single crystal pulling length defect obtained thereby
  • V (mm / min) necessary for obtaining the Pv region, the Pi region, and the I region can be calculated.
  • V / G varies depending on each actual machine, such as the structure of the hot zone in the upper part of the pulling furnace, but by measuring the COP density, OSF density, BMD density, LSTD density or FPD, light etching defect density, etc. It can be determined.
  • Light etching defects means that an As-Grown silicon single crystal wafer is immersed in an aqueous copper sulfate solution, then air-dried, and subjected to Cu decoration in which a heat treatment is performed at 900 ° C. for about 20 minutes in a nitrogen atmosphere. In order to remove the Cu silicide layer on the surface of the specimen, it was immersed in a HF / HNO 3 mixed solution, and the surface layer was etched and removed by several tens of microns, and then the wafer surface was etched by 2 ⁇ m light etching (chromic acid etching). And defects detected using an optical microscope.
  • the dislocation clusters formed at the time of crystal growth can be revealed by Cu decoration, and the dislocation clusters can be detected with high sensitivity. That is, the light etching defect includes a dislocation cluster.
  • the “LPD density” is a density of defects of 0.1 ⁇ m size or more detected using a laser light scattering particle counter (SP1 (surfscan SP1): manufactured by KLA-Tencor).
  • TZDB is an abbreviation for Time Zero Dielectric Breakdown, and is one of the indexes representing GOI.
  • the pass rate of TZDB in the present invention was determined by measuring the current-voltage curve at about 416 locations across the wafer under the conditions that the electrode area of the measurement electrode was 8 mm 2 and the judgment current was 1 mA. The probability of not having occurred is taken as the pass rate of TZDB. This pass rate is also called a C-mode pass rate.
  • the gettering region which is homogeneous and has sufficient gettering capability over the entire region in the wafer surface direction, and is uniform over the entire region in the wafer surface direction and after the IGBT device process during and after the IGBT device process. It has a device region in which the characteristics are not deteriorated, and COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, so that it is suitable as a wafer for IGBT which is an element that uses the wafer in the vertical direction.
  • the concentration of oxygen donor generated after the heat treatment of the wafer can be suppressed to 9.8 ⁇ 10 12 atoms / cm 3 or less.
  • the change in the resistivity of the wafer can be prevented, and the quality of the silicon single crystal wafer can be stabilized.
  • the reason why the oxygen donor concentration is 9.8 ⁇ 10 12 atoms / cm 3 or less is as follows. An n-type wafer having a resistivity of 40 to 70 ⁇ ⁇ cm is used for the high voltage IGBT.
  • the allowable donor concentration is 9.8 ⁇ 10 12 ions / cm 3 or less.
  • the temperature at which oxygen donors due to oxygen are most likely to be generated is 450 ° C.
  • FIG. 1 shows the results of examining the oxygen concentration dependence of the oxygen donor concentration generated when heat treatment is performed at 450 ° C. for 1 hour. From FIG. 1, in order to suppress the oxygen donor concentration to 9.8 ⁇ 10 12 atoms / cm 3 or less, the interstitial oxygen concentration of the wafer must be controlled to 8.5 ⁇ 10 17 atoms / cm 3 or less. I understand that. For these reasons, in the present invention, the interstitial oxygen concentration can be 8.5 ⁇ 10 17 atoms / cm 3 or less.
  • the MCZ method is used to grow a single crystal by applying a magnetic field.
  • the interstitial oxygen concentration can be 8.5 ⁇ 10 17 atoms / cm 3 or less.
  • the interstitial oxygen concentration can also be reduced by reducing the rotation speed of the quartz crucible and the single crystal to be pulled up. Specifically, as shown in FIG. 8, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) As shown by the points (R1, R2) in FIG.
  • Point A (0.1,1), Point B (0.1,7), Point C (0.5,7), Point D (0.7,6), Point E (1,6), Point F It can be set to a value within a range surrounded by (2, 2) and point G (2, 1). Thereby, a single crystal having an interstitial oxygen concentration of 4 ⁇ 10 17 atoms / cm 3 or less can be grown.
  • the range is R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, When R1: 0.5 or more and 0.7 or less, R2 ⁇ 7-5 (R1-0.5) is satisfied, and when R1: 0.7 or more and 1 or less, R2 ⁇ 6 is satisfied, and R1: 1 In the case of 2 or less, it can be set in a range satisfying R2 ⁇ 6-4 (R1-1). In this case, a silicon single crystal having a low oxygen concentration can be grown by setting the interstitial oxygen concentration in the single crystal to 4.0 ⁇ 10 17 atoms / cm 3 or less.
  • the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) As shown by the points (R1, R2) in FIG. Point A (0.1,1), point B (0.1,7), point L (0.2,7), point K (0.3,7), point J (0.5,6), Pulling up the silicon single crystal by setting the value within the range surrounded by point I (0.7,6), point H (1,5), point N (1,3), and point M (1,1)
  • a silicon single crystal having a lower oxygen concentration can be grown by setting the interstitial oxygen concentration in the single crystal to 3.5 ⁇ 10 17 atoms / cm 3 or less.
  • the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, provided that R1: 0.
  • R1: 0.1 or more and 2 or less R2: 1 or more and 7 or less, provided that R1: 0.
  • R1: 0.5 or more and 0.7 or less R2 ⁇ 6 is satisfied, and R1: 0.
  • R2 ⁇ 6-3.4 (R1-0.7) a silicon single crystal having a low oxygen concentration can be provided by setting the interstitial oxygen concentration in the single crystal to 3.5 ⁇ 10 17 atoms / cm 3 or less.
  • the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) As shown by the points (R1, R2) in FIG. Point A (0.1,1), point B (0.1,7), point L (0.2,7), point Q (0.3,6), point J (0.5,6),
  • the silicon single crystal may be pulled up by setting a value within a range surrounded by the points P (0.7, 5), N (1, 3), and M (1, 1).
  • the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 1 or less, R2: 1 or more and 7 or less, provided that R1: 0.
  • R2 ⁇ 7-10 (R1-0.2) is satisfied, and when R1: 0.3 or more and 0.5 or less, R2 ⁇ 6 is satisfied, and R1: 0.5
  • R2 ⁇ 6-5 (R1-0.5) is satisfied.
  • R1: 0.7 or more and 1 or less R2 ⁇ 5-6.7 (R1-0.7) Can be set in a range that satisfies the above.
  • a silicon single crystal having an interstitial oxygen concentration of 3.0 ⁇ 10 17 atoms / cm 3 or less in the single crystal can be grown, and a silicon single crystal having a lower oxygen concentration can be grown.
  • Table 1 shows the relationship among the quartz crucible rotation speed R1 (rpm), the crystal rotation speed R2 (rpm), and the interstitial oxygen concentration.
  • the magnetic field applied to the silicon melt can be a horizontal magnetic field, a cusp magnetic field, or the like.
  • the strength of the horizontal magnetic field is 3000 to 5000 G (0.3 T to 0.5 T). it can.
  • the magnetic field strength is below the above range, the effect of suppressing convection of the silicon melt is not sufficient, and the shape of the solid-liquid interface cannot be made preferable, and the oxygen concentration cannot be lowered sufficiently, which is not preferable.
  • the magnetic field strength is increased beyond the above range, convection is suppressed too much, and the high-temperature silicon melt advances the deterioration of the inner surface of the quartz crucible, and the dislocation-free rate of the crystal is lowered.
  • the magnetic field center position and the melt surface position during crystal pulling are preferably ⁇ 75 to +50 mm, more preferably 20 to 45 mm.
  • the magnetic field center position means a height position where the center of the magnetic field generating coil is located in a horizontal magnetic field
  • ⁇ 75 mm means 75 mm above the melt surface.
  • the manufacturing method of the silicon single crystal wafer for IGBT of the present invention realizes an unprecedented level of oxygen concentration of 4 ⁇ 10 17 atoms / cm 3 (oldASTM) or less in a CZ silicon single crystal of ⁇ 8 inches or more.
  • a silicon single crystal that is COP-free and has an oxygen concentration of 4 ⁇ 10 17 atoms / cm 3 or less is a crystal located between the CZ crystal and the FZ crystal, which is a conventional crystal.
  • the oxygen concentration is set to 4 ⁇ 10 17 atoms / cm 3 or less, it is possible to eliminate the concern about the generation of oxygen donors during the heat treatment in the device manufacturing process, and furthermore, almost no oxygen-induced defects peculiar to CZ crystals are observed.
  • the melt amount of the quartz crucible is reduced by suppressing the convection of the silicon melt, and the impurity concentration in the quartz crucible is reduced by using the synthetic quartz crucible, so that a CZ crystal having a quality closer to that of the FZ crystal can be grown.
  • the synthetic quartz crucible means that at least the inner surface in contact with the raw material melt is formed of the following synthetic quartz.
  • Synthetic quartz is a chemically synthesized and manufactured raw material, and synthetic quartz glass powder is amorphous. Since the raw material of synthetic quartz is gas or liquid, it can be easily purified, and synthetic quartz powder can have a higher purity than natural quartz powder.
  • Synthetic quartz glass raw materials are derived from gaseous raw materials such as carbon tetrachloride and liquid raw materials such as silicon alkoxide. In synthetic quartz powder glass, it is possible to make all impurities 0.1 ppm or less.
  • the synthetic quartz glass which transmits ultraviolet rays up to a wavelength of about 200 nm well and is made from carbon tetrachloride used for ultraviolet optical applications. It is considered that the characteristics are close to. In a glass obtained by melting synthetic quartz glass powder, when a fluorescence spectrum obtained by excitation with ultraviolet rays having a wavelength of 245 nm is measured, a fluorescence peak like a melted product of natural quartz powder is not observed.
  • the glass material was natural quartz by measuring the concentration of impurities contained, measuring the amount of silanol, or measuring the light transmittance, or measuring the fluorescence spectrum obtained by excitation with ultraviolet light having a wavelength of 245 nm. It can be determined whether it was quartz.
  • the MCZ method makes it easier to grow an 8-inch ⁇ silicon single crystal than the FZ method, and the use of a quartz crucible makes it possible to increase the charge, thereby reducing the raw material cost compared to the FZ method. At the same time, the yield can be improved.
  • the pressure in the furnace in order to control the gas flow state on the surface of the silicon melt, is 1333 Pa or more, preferably 4000 Pa to 26660 Pa.
  • the upper limit of the pressure in the furnace is that when the pressure in the furnace increases, the gas flow rate on the melt of inert gas such as Ar decreases, so that it is difficult to exhaust the reactant gas such as SiO evaporated from the melt.
  • the oxygen concentration in the crystal becomes higher, and SiO aggregates in the upper part of the melt in the furnace at about 1100 ° C. or at a temperature lower than this, thereby generating dust and dropping into the melt.
  • the upper limit of the pressure is defined in order to prevent these.
  • the pressure in the furnace is 10 torr (1.3 kPa) or more, preferably 30 to 200 torr (4.0 to 27 kPa), more preferably 30 to 70 torr (4.0 to 9.3 kPa) is desirable.
  • the upper limit of the pressure in the furnace is that when the pressure in the furnace increases, the gas flow rate on the melt of inert gas such as Ar decreases, so that it is difficult to exhaust the reactant gas such as SiO evaporated from the melt.
  • the oxygen concentration in the crystal increases, and SiO aggregates in the upper part of the melt in the furnace at about 1100 ° C. or at a lower temperature, thereby generating dust and dropping into the melt.
  • the upper limit of the pressure was specified to prevent these.
  • the atmospheric gas flow rate supplied into the CZ furnace is set to 100 to 200 liters / min or more
  • the pressure in the CZ furnace is set to 6700 pa or less
  • SiO evaporated from the melt surface is effectively discharged out of the apparatus.
  • foreign matter drifting on the surface of the melt can be driven to the crucible wall, and the oxygen concentration in the crystal can be prevented from increasing.
  • the variation in resistivity within the wafer surface is 5% or less, so that the quality of the IGBT can be stabilized.
  • the resistivity of a silicon single crystal wafer manufactured by the CZ method can be controlled by the amount of dopant contained in the silicon single crystal, but phosphorus often used as a dopant for an IGBT substrate has a small segregation coefficient, so that the silicon single crystal The concentration varies greatly over the length direction. Therefore, the range in which a wafer having a resistivity that meets the design specifications in one single crystal is obtained is narrow.
  • neutron irradiation addition of an n-type dopant to the silicon melt, addition of a predetermined amount of p-type dopant having a segregation coefficient smaller than phosphorus and phosphorus, and various other means are employed.
  • a silicon single crystal is grown without adding a dopant for adjusting the resistivity to the silicon melt, and irradiating this non-doped silicon single crystal with neutrons results in 30 Si in the crystal.
  • the resistivity can also be controlled by adding an n-type dopant to the silicon melt.
  • the DLCZ method is a method for suppressing a change in concentration in the crystal axis direction of a dopant having a small segregation coefficient such as phosphorus. This method is disclosed in, for example, Japanese Patent Laid-Open No. 5-43384.
  • the CZ method all the polycrystalline silicon is once dissolved in a crucible to form a silicon melt, phosphorus is added, and the temperature at the bottom of the crucible is lowered.
  • Dopant concentration incorporated into the single crystal by solidifying the silicon melt upward from the bottom to form a silicon solidified layer and growing the crystal while gradually dissolving the silicon solidified layer from the top toward the bottom This is a method of keeping the constant almost constant.
  • the change in resistivity in the crystal axis direction of the silicon single crystal can also be suppressed by adopting the DLCZ method.
  • the resistivity change in the crystal axis direction of the silicon single crystal can also be suppressed by adding a predetermined amount of phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus.
  • This is called a so-called double doping method, which is disclosed in, for example, Japanese Patent Laid-Open No. 2002-128591, and is a method for suppressing a change in resistivity in the axial direction of a crystal doped with a dopant having a small segregation coefficient such as phosphorus. .
  • Phosphorus concentration change is compensated for by doping p-type dopant (eg, Al, Ga, In) having a segregation coefficient smaller than that of phosphorus as a counter dopant.
  • FIG. 2 shows the change in resistivity in the crystal axis direction when only phosphorus is doped and when phosphorus and aluminum are simultaneously doped.
  • the yield is improved about three times by simultaneously doping with phosphorus and aluminum. The yield is the highest when the concentration ratio of aluminum to phosphorus at the upper end of the single crystal is about 50%.
  • phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus are contained at a concentration of 1 ⁇ 10 13 atoms / cm 3 or more and 1 ⁇ 10 15 atoms / cm 3 or less, respectively.
  • the change in resistivity in the crystal axis direction can be suppressed.
  • a so-called CCZ method can also be applied.
  • This method is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-36197, and by adding polycrystalline silicon containing no dopant to a silicon melt containing phosphorus during single crystal growth, In this method, the concentration of the incorporated dopant is kept almost constant. Furthermore, in the case of single crystal growth in which a dopant is added to a silicon melt as in the DLCZ method or CCZ method, the crystal rotation speed during crystal growth is rotated fast in order to suppress resistivity variation in the wafer surface.
  • the crystal rotation speed In the case of growing a single crystal having a diameter of 200 mm or less, it is desirable to rotate the crystal rotation speed in the range of 15 to 30 rpm, and in the case of a diameter of 300 mm or more, in the range of 8 to 15 rpm. Normally, when the crystal rotation speed is increased, the pulling speed margin width for obtaining a grow-in defect-free crystal is narrowed, and it becomes difficult to grow a single crystal itself. By growing the silicon single crystal in the atmosphere containing the gas, a pulling speed margin for obtaining a grow-in defect free crystal can be sufficiently secured.
  • 5 ⁇ 10 12 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less, or 1 ⁇ 10 13 atoms / cm 3 or more and 2 ⁇ 10 15 atoms / cm 3 or less are more preferable.
  • the silicon single crystal is 1 ⁇ 10 13 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less, or 1 ⁇ 10 14 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less, more preferably By doping nitrogen of 1 ⁇ 10 14 atoms / cm 3 or more and 9 ⁇ 10 14 atoms / cm 3 or less, or 1 ⁇ 10 14 atoms / cm 3 or more and 5 ⁇ 10 14 atoms / cm 3 or less, COP Elimination of defects and dislocation clusters is facilitated.
  • the controllable range of V / G is narrow, and there is a possibility that COP defects and dislocation clusters will not be completely eliminated. This is not preferable because crystals cannot be grown.
  • the effect of promoting oxygen precipitation by doping nitrogen is clear, and if it is below the above range, it may hinder single crystallization at the time of single crystal pulling, It does not cause instability of continuous operation.
  • the pass rate of TZDB is 90% or more, and the concentration of oxygen donors generated when heat treatment is performed at 450 ° C. for 1 hour is 9.8 ⁇ 10 12 pieces. / cm 3 or less, and a density of BMD that occurs when performing a two-stage heat treatment of 16 hours at 4 hours and 1000 ° C. at 800 ° C. is 5 ⁇ 10 7 / cm 3 or less, were two-stage heat treatment Since the recombination lifetime in this case is 100 ⁇ sec or more, the characteristics required for a silicon single crystal wafer for IGBT can be satisfied.
  • the recombination lifetime is deteriorated by interstitial oxygen contained in the silicon single crystal being precipitated as SiO 2 through a device formation process.
  • the recombination lifetime can be 100 ⁇ sec or more.
  • the method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, A pulling step of growing a single crystal having an interstitial oxygen concentration of 8.5 ⁇ 10 17 atoms / cm 3 or less at a speed capable of pulling a silicon single crystal at a growth rate of a grown-in defect-free silicon single crystal; A hole injection step of performing RTA treatment of a wafer sliced from the single crystal at 1175 ° C. or higher; After the hole injecting step, heat treatment is performed at a temperature range of 1000 ° C. to 1100 ° C.
  • a BMD oxygen precipitate
  • the temperature increase rate and the temperature decrease rate of the heat treatment in the pore control heat treatment step are 3 to 50 ° C./min and 3 to 20 ° C./min, respectively. Therefore, a lamp annealing furnace can be used, but can be processed by a horizontal furnace.
  • the temperature increase / decrease rate is less than 3 ° C.
  • nucleation occurs and density control is difficult.
  • rate of temperature rise exceeds 50 ° C./min
  • a large thermal stress may be applied to the wafer and it may break.
  • temperature lowering rate exceeds 20 ° C./min, holes are injected into the wafer by the hole control heat treatment, which makes density control difficult.
  • the vacancies near the surface layer injected by the vacancy injection RTA treatment are subjected to a heat treatment at a temperature of 1000 ° C. to 1100 ° C. for about 1 to 16 hours after the RTA treatment, for example, 800 ° C.
  • a heat treatment condition of 4 hr + 1000 ° C. for 16 hr oxygen precipitation does not occur in the device region of about 150 ⁇ m from the wafer outermost surface, and the oxygen precipitate density is 5 ⁇ 10 3 pieces / cm 3 or less. It is possible to provide an IGBT silicon single crystal wafer in which oxygen precipitation occurs at a deeper position and the density of oxygen precipitates is 5 ⁇ 10 4 pieces / cm 3 or more and 1 ⁇ 10 7 pieces / cm 3 or less.
  • the portion on the back side deeper than the device region is removed and the thickness is reduced before the thinning step (back grinding step).
  • the device region (device active region) can be protected from metal contamination by the gettering (IG) effect of BMD included in a deep position of 150 ⁇ m or more from the outermost surface. Since the portion of the deep region including the BMD is removed by the back grinding, the completed IGBT element does not include the BMD, and hence the IGBT characteristics are not deteriorated by the BMD.
  • the silicon single crystal wafer for IGBT according to the present invention has IG capability in the wafer from the beginning in the device process, the manufacturing cost can be reduced by omitting the EG processing such as polysilicon film formation processing (PBS) on the back surface. Is also possible.
  • PBS polysilicon film formation processing
  • the relationship between the treatment time and temperature is as follows. As shown in FIG. 8, the heat treatment temperature of the hole control heat treatment process is plotted on the horizontal axis, and the heat treatment time of the hole control heat treatment process is plotted on the vertical axis. In this case, it is preferable to set the Z region above the straight line connecting the point of 700 ° C. and 8 (hr) time and the point of 1000 ° C. for 1 hour. That is, the relationship between the processing time t (hr) and the processing temperature d (° C.) is t ⁇ -7d / 300 + 73/3 It becomes.
  • BMD is also undesirably deposited in the device region.
  • the X region below the Y region is not preferable because BMD is deposited only in the device region.
  • the method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, and in an atmosphere gas in a CZ furnace. Introducing a hydrogen atom-containing substance with a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less to increase the silicon single crystal pulling rate at a rate at which a grown-in defect-free silicon single crystal can be pulled. Is grown to a single crystal of 8.5 ⁇ 10 17 atoms / cm 3 or less, and the silicon single crystal after pulling can be irradiated with neutrons to be doped with phosphorus.
  • the manufacturing method of the silicon single crystal wafer for IGBT of this invention is a manufacturing method of the silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, Comprising: An n-type dopant is added to a silicon melt. And introducing a hydrogen atom-containing substance having a hydrogen gas partial pressure in the range of 40 Pa or more and 400 Pa or less into the atmospheric gas in the CZ furnace, and increasing the pulling rate of the silicon single crystal to a grown-in defect-free silicon single crystal Can grow a single crystal having an interstitial oxygen concentration of 8.5 ⁇ 10 17 atoms / cm 3 or less.
  • the method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, wherein phosphorus is added to the silicon melt.
  • Degrees can be grown to 8.5 ⁇ 10 17 atoms / cm 3 or less of a single crystal. Furthermore, in the manufacturing method of the silicon single crystal wafer for IGBT of the present invention, nitrogen is 5 ⁇ 10 12 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less with respect to the silicon single crystal by the Czochralski method. It is preferable to add at a concentration.
  • the hydrogen-containing substance is a substance containing hydrogen atoms in its molecule, and is a gaseous substance that generates hydrogen gas by being thermally decomposed when dissolved in the silicon melt.
  • This hydrogen-containing substance includes hydrogen gas itself.
  • the hydrogen-containing substance include inorganic compounds containing hydrogen atoms such as hydrogen gas, H 2 O, and HCl, hydrocarbon atoms such as silane gas, CH 4 and C 2 H 2 , hydrogen atoms such as alcohol and carboxylic acid.
  • the organic compound can be exemplified, but it is particularly preferable to use hydrogen gas.
  • inexpensive argon gas is preferable, and various rare gases such as helium, neon, krypton, and xenon, or a mixed gas thereof can be used.
  • concentration of the hydrogen containing substance in hydrogen containing atmosphere is made into the range of 40 Pa or more and 400 Pa or less by hydrogen gas conversion partial pressure.
  • the hydrogen gas equivalent partial pressure is because the amount of hydrogen atoms obtained by thermal decomposition of the hydrogen-containing material depends on the number of hydrogen atoms originally contained in the hydrogen-containing material. .
  • 1 mole of H 2 O contains 1 mole of H 2
  • 1 mole of HCl contains only 0.5 mole of H 2 . Therefore, in the present invention, a hydrogen-containing substance is used so that an atmosphere equivalent to this reference atmosphere can be obtained on the basis of a hydrogen-containing atmosphere in which hydrogen gas is introduced into an inert gas at a partial pressure of 40 to 400 Pa.
  • the preferable pressure of the hydrogen-containing substance at this time is defined as a partial pressure in terms of hydrogen gas. That is, in the present invention, it is assumed that a hydrogen-containing substance is dissolved in a silicon melt and thermally decomposed in a high-temperature silicon melt to be converted into hydrogen atoms, and then converted into hydrogen gas equivalents in the atmosphere after conversion.
  • the addition amount of the hydrogen-containing substance may be adjusted so that the pressure is in the range of 40 to 400 Pa.
  • a grown-in defect-free silicon single crystal is obtained.
  • the allowable range of the pullable speed can be widened, whereby a wafer from which COP defects and dislocation clusters are eliminated in the entire crystal diameter direction can be easily manufactured.
  • the non-doped silicon single crystal after the pulling is irradiated with neutrons to dope phosphorus, or an n-type dopant such as phosphorus is added to the silicon melt, thereby reducing the variation in resistivity in the plane of the wafer. % Or less.
  • the reduction in resistivity variation can also be achieved by adding phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus to the silicon melt. Further, by adding nitrogen to the silicon melt, the allowable range of the speed at which a grown-in defect-free silicon single crystal can be pulled can be further widened, and the elimination of COP defects and dislocation clusters in the wafer is facilitated. . As a result, it is possible to increase the pulling speed margin, no EG treatment is required, the DZ layer has a sufficient thickness as an IGBT wafer and has IG capability, and there is a variation in resistivity.
  • the manufacturing method of the silicon single crystal wafer for IGBT which can manufacture a small wafer, and the silicon single crystal wafer for IGBT can be provided.
  • the oxygen precipitate density can be changed, and as a result, wafers having different specifications such as a wafer applicable to the manufacture of an IGBT and a wafer applicable to the manufacture of a general device can be manufactured.
  • a thickness of about 150 ⁇ m or more applicable to manufacture of an insulated gate bipolar transistor (IGBT) a thickness of 5 to several tens ⁇ m applicable to manufacture of a normal device.
  • a silicon single crystal wafer manufacturing method and a silicon single crystal wafer capable of supporting wafers with different oxygen precipitate densities under the same pulling conditions and vacancy injection conditions up to wafers having a degree of DZ layer are provided. can do.
  • FIG. 1 is a graph showing the relationship between the treatment time and the treatment temperature in the pore control heat treatment step.
  • FIG. 2 is a model diagram of interstitial Si implantation into the bulk center.
  • FIG. 3 is a graph showing the hole density distribution in the wafer thickness direction at the time of hole injection.
  • FIG. 4 is a schematic vertical cross-sectional view of a CZ furnace used in carrying out the method for producing a silicon single crystal wafer according to the embodiment of the present invention.
  • FIG. 5A is a schematic cross-sectional view showing an IGBT element.
  • FIG. 5B is a schematic cross-sectional view showing an IGBT element.
  • FIG. 5C is a schematic cross-sectional view showing an IGBT element.
  • FIG. 5A is a schematic cross-sectional view showing an IGBT element.
  • FIG. 5B is a schematic cross-sectional view showing an IGBT element.
  • FIG. 5C is a schematic cross-sectional view showing an IGBT element.
  • FIG. 6 is a flowchart showing the manufacturing method and IGBT manufacturing process of the present invention.
  • FIG. 7A is a process diagram in the production method of the present invention.
  • FIG. 7B is a process diagram in the production method of the present invention.
  • FIG. 7C is a process diagram in the production method of the present invention.
  • FIG. 7D is a process diagram in the manufacturing method of the present invention.
  • FIG. 8 is a graph showing the relationship among the quartz crucible rotation speed, crystal rotation speed, and interstitial oxygen concentration.
  • FIG. 9 is a graph showing the relationship between the wafer depth and the BMD density in the example of the present invention.
  • FIG. 10 is a graph showing the relationship between the wafer depth and the BMD density in the example of the present invention.
  • FIG. 11 is a graph showing the relationship between the wafer depth and the BMD density in the example of the present invention.
  • FIG. 12 is a graph showing the relationship between the wafer depth and the BMD density in the example of the present invention.
  • FIG. 13 is a graph showing the relationship between wafer depth and BMD density in an example of the present invention.
  • FIG. 14 is a graph showing the relationship between wafer depth and BMD density in an example of the present invention.
  • FIG. 15 is a graph showing the relationship between the wafer depth and the BMD density in the example of the present invention.
  • FIG. 16 is a schematic cross-sectional view showing a peripheral portion of a silicon single crystal wafer according to an embodiment of the present invention.
  • FIG. 4 is a longitudinal sectional view of a CZ furnace suitable for carrying out the method for producing a silicon single crystal wafer in the embodiment of the present invention.
  • the CZ furnace shown in FIG. 4 includes a crucible 1 disposed in the center of the chamber, a heater 2 disposed outside the crucible 1, and a magnetic field supply device 9 disposed outside the heater 2.
  • the crucible 1 has a double structure in which a quartz crucible 1a containing a silicon melt 3 inside is held by an outer graphite crucible 1b, and is rotated and moved up and down by a support shaft 1c called a pedestal.
  • a cylindrical heat shield 7 is provided above the crucible 1.
  • the heat shield 7 has a structure in which an outer shell is made of graphite and the inside thereof is filled with graphite felt.
  • the inner surface of the heat shield 7 is a tapered surface whose inner diameter gradually decreases from the upper end to the lower end.
  • the upper outer surface of the heat shield 7 is a tapered surface corresponding to the inner surface, and the lower outer surface is formed in a substantially straight surface so as to gradually increase the thickness of the heat shield 7 downward.
  • the silicon single crystal 6 can be formed by immersing the seed crystal T attached to the seed chuck 5 in the silicon melt 3 and pulling up the seed crystal T while rotating the crucible 1 and the pulling shaft 4. .
  • the heat shield 7 blocks the radiant heat from the heater 2 and the silicon melt 3 surface to the side surface of the silicon single crystal 6, surrounds the side surface of the growing silicon single crystal 6, and the silicon melt 3. It surrounds the surface.
  • An example of the specification of the heat shield 7 is as follows.
  • the width W in the radial direction is, for example, 50 mm
  • the inclination ⁇ of the inner surface, which is the inverted truncated cone surface, with respect to the vertical direction is, for example, 21 °
  • the height H1 from the melt surface at the lower end of the heat shield 7 is, for example, 60 mm.
  • the magnetic field supplied from the magnetic field supply device 9 can be a horizontal magnetic field, a cusp magnetic field, or the like.
  • the horizontal magnetic field strength is 2000 to 4000 G (0.2 T to 0.4 T), more preferably 2500. 3500G (0.25T to 0.35T), and the magnetic field center height is set to be within a range of ⁇ 150 to +100 mm, more preferably ⁇ 75 to +50 mm with respect to the melt surface.
  • FIG. 6 is a flowchart showing a method for manufacturing a silicon single crystal wafer and a manufacturing process of an IGBT or memory device
  • FIGS. 7A to 7D show a method for manufacturing a silicon single crystal wafer for IGBT and the IGBT. It is process drawing which shows a manufacturing process.
  • a pulling step S01 for pulling a single crystal by a CZ (Czochralski) method and slicing the wafer from the pulled single crystal.
  • Slicing step S02 for forming a wafer by performing surface treatment such as etching, grinding, polishing, etc. hole injection step S03 for RTA treatment of wafer W at 1175 ° C. or higher, and 600 ° C. to 1150 after hole injection step S03
  • a hole control heat treatment step S04 in which the hole density distribution in the thickness direction of the wafer is controlled by heat treatment in a temperature range of ° C. and a treatment time of 0.25 to 24 hours.
  • an IGBT device process SD1, a back grinding process SD2, and a device finishing process SD3 are presented as IGBT manufacturing processes
  • a memory device process SM1 and a device finishing process SM2 are provided as memory device manufacturing processes. And present.
  • a pulling step S01 for pulling a single crystal by the Czochralski method, and slicing the wafer from the pulled single crystal and performing surface treatment such as etching, grinding, and polishing Slicing step S02 for producing a wafer, RTA processing step S03 for injecting holes by RTA treatment of the wafer, and a temperature range of 600 ° C. to 1150 ° C. and a treatment time of 0.25 to 24 hours after the RTA treatment step.
  • an IGBT device process SD1 as an IGBT manufacturing process
  • a memory device process SM1 as a memory device manufacturing process.
  • the silicon single crystal ingot is pulled by a Czochralski method at a pulling speed at which a silicon single crystal ingot having no grown-in defects can be pulled.
  • a silicon wafer having a CVD film made of, for example, silicon nitride is introduced as a nitrogen source. Adjusting the nitrogen concentration in the silicon melt so that the nitrogen concentration in the silicon crystal is 5 ⁇ 10 12 atoms / cm 3 or more and 1 ⁇ 10 13 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less. Is preferred.
  • the CZ furnace has a hydrogen-containing atmosphere composed of a mixed gas of a hydrogen-containing substance and an inert gas
  • the atmosphere pressure is set to 1333 Pa to 13330 Pa (10 to 100 torr)
  • the concentration of the hydrogen-containing substance in the atmosphere gas is hydrogen gas. Adjust so that the converted partial pressure is about 40 to 400 Pa.
  • the hydrogen gas partial pressure may be 40 to 400 Pa.
  • the concentration of hydrogen gas is in the range of 0.3% to 31%.
  • it can also be set as the atmosphere only of the inert gas which does not contain hydrogen gas.
  • the hydrogen gas equivalent partial pressure of the hydrogen-containing substance is less than 40 Pa, the allowable range of the pulling rate is reduced, and generation of COP defects and dislocation clusters cannot be suppressed. Further, the higher the hydrogen gas equivalent concentration (hydrogen concentration) of the hydrogen-containing substance, the greater the effect of suppressing dislocation generation. However, if the hydrogen gas equivalent partial pressure exceeds 400 Pa, the risk of explosion or the like increases when an oxygen leak occurs in the CZ furnace, which is not preferable for safety.
  • the hydrogen gas equivalent partial pressure of the hydrogen-containing substance is more preferably in the range of 40 Pa to 250 Pa, and particularly preferably the hydrogen gas equivalent partial pressure is in the range of 40 Pa to 135 Pa.
  • a horizontal magnetic field of, for example, 3000 G (0.3 T) is supplied from the magnetic field supply device 9 so that the center height of the magnetic field is ⁇ 75 to +50 mm with respect to the melt surface, and the polycrystalline silicon is heated by the heater 2. Heat to make silicon melt 3.
  • the seed crystal T attached to the seed chuck 5 is immersed in the silicon melt 3, and the crystal is pulled up while rotating the crucible 1 and the pulling shaft 4.
  • the growth rate of the single crystal is V (mm / min), and the ratio V / G (mm) when the temperature gradient G (° C./mm) is 1350 ° C. from the melting point during single crystal growth.
  • the rotation speed of the quartz crucible is 5 to 0.2 rpm
  • the rotation speed of the single crystal is 20 to 10 rpm
  • the pressure of the argon atmosphere is 1333 to 26660 Pa or 30 Torr
  • the magnetic field strength is 3000 to A condition such as 5000 Gauss can be exemplified.
  • the rotation speed of the quartz crucible by setting the rotation speed of the quartz crucible to 5 rpm or less, diffusion of oxygen atoms contained in the quartz crucible into the silicon melt can be prevented, and the interstitial oxygen concentration in the silicon single crystal can be reduced. it can.
  • the variation in resistivity within the silicon single crystal can be reduced by setting the rotation speed of the single crystal to 5 rpm or more.
  • the interstitial oxygen concentration in the silicon single crystal is 1 ⁇ 10 17 atoms / cm 3 or more and 15 ⁇ 10 17 atoms / cm 3 or less, or 8.5 ⁇ 10 17 atoms / cm 3.
  • the neutron beam is irradiated to the single crystal silicon to which the dopant for adjusting the formed resistivity is not added.
  • a part of silicon atoms is converted into phosphorus, whereby the single crystal silicon can be uniformly doped with phosphorus, and single crystal silicon with a uniform resistivity can be obtained.
  • the irradiation conditions of the neutron beam may be, for example, irradiation at a position where the neutron beam flux is 3.0 ⁇ 10 12 pieces / cm 2 / s ⁇ 1 for about 80 hours at a crystal rotation of about 2 rpm.
  • the resistivity of the silicon ingot irradiated with the neutron beam is about 48 ⁇ ⁇ cm to 52 ⁇ ⁇ cm.
  • n-type (P, As, Sb, etc.) dopant may be added to the silicon melt in advance.
  • the segregation coefficient is small, the length direction of the silicon single crystal The resistivity changes greatly.
  • the above-described DLCZ method, double doping method, or CCZ method may be employed.
  • a wafer is cut out from the pulled single crystal silicon, and lapping, etching, or the like is performed as necessary.
  • lapping in order to prevent the wafer from cracking, it is preferable to form a front side chamfered portion at the peripheral portion of the front surface of the wafer and a back side chamfered portion at the peripheral portion of the rear surface of the wafer.
  • FIG. 16 shows a cross section of the peripheral edge of the wafer after completion of the wafer processing.
  • the front surface 22 of the wafer is provided with a main surface 23 that is a flat surface and a surface side chamfer 24 formed at the peripheral edge.
  • the back surface 26 is provided with a main surface 27 which is a flat surface and a back surface side chamfered portion 28 formed at the peripheral edge.
  • the front side chamfered portion 24 has a width A1 in the direction from the peripheral edge 29 inward in the wafer radial direction, and a width A2 in the direction from the peripheral edge 29 in the backside chamfered portion 28 inward in the wafer radial direction. It is narrowed.
  • the width A1 of the surface chamfer 24 is preferably in the range of 50 ⁇ m to 200 ⁇ m.
  • the width A2 of the back side chamfer 28 is preferably in the range of 200 ⁇ m to 300 ⁇ m.
  • the front side chamfered portion 24 has the first inclined surface 11 that is inclined with respect to the main surface 23 of the front surface 22, and the back surface side chamfered portion 28 is a first inclined surface that is inclined with respect to the main surface 27 of the back surface 26.
  • Two inclined surfaces 12 are provided.
  • the inclination angle ⁇ 1 of the first inclined surface 11 is preferably in the range of 10 ° to 50 °
  • the inclination angle ⁇ 2 of the second inclined surface 12 is preferably in the range of 10 ° to 30 °
  • ⁇ 1 ⁇ ⁇ 2 is satisfied. preferable.
  • a first curved surface 13 is provided between the first inclined surface 11 and the peripheral edge 29 to connect them.
  • a second curved surface 14 is provided between the second inclined surface 12 and the peripheral edge 29 to connect them.
  • the range of the radius of curvature R1 of the first curved surface 13 is preferably in the range of 80 ⁇ m to 250 ⁇ m, and the range of the radius of curvature R2 of the second curved surface 14 is preferably in the range of 100 ⁇ m to 300 ⁇ m.
  • the RTA process is performed as the hole injection step S03 on the wafer W0 after the slicing step S02 shown in FIG. 7A.
  • a heat treatment can be performed at 1150 ° C. to 1250 ° C. for 1 second or longer in a nitriding gas (N 2 , NH 3 , hydrazine) or a mixed atmosphere of a nitriding gas and an inert gas.
  • a nitriding gas N 2 , NH 3 , hydrazine
  • both the temperature increase / decrease rate is 50 to 100 ° C./min
  • Nitrogen or ammonia is used in a single wafer annealing furnace such as lamp annealing as a gas atmosphere having a hole injection effect.
  • vacancy injection is performed by nitriding the surface in a gas atmosphere having a low decomposition temperature such as ammonia at a low temperature of about 1050 to 1150 ° C., only the injection of the vacancies from the wafer surface by surface nitriding is performed. Predominate.
  • a hole control heat treatment step S04 is performed.
  • the vacancy density distribution in the thickness direction of the wafer is controlled by heat treatment in a temperature range of 600 ° C. to 1150 ° C. and a treatment time of 0.25 to 24 hours.
  • the oxygen precipitate density distribution after the hole control heat treatment is (P1) Precipitates only in the central part of the bulk in the wafer thickness direction (p2) Precipitates in the vicinity of the wafer surface and in the central part of the bulk (p3) Precipitates only in the vicinity of the wafer surface (p4) Precipitates uniformly from the vicinity of the wafer surface to the bulk part Control is performed so that one state selected from the pattern is obtained.
  • the oxygen precipitate density distribution after the pore control heat treatment is (P1)
  • the heat treatment temperature T (° C.) and the heat treatment time t (hour) are shown in the attached drawing FIG.
  • P2 set to a value within the range surrounded by the point F (950, 1), the point B (750, 4), the point C (600, 10), the point H (600, 18), and the point G (950, 3)
  • Heat treatment condition or The oxygen precipitate density distribution after the pore control heat treatment is (P3)
  • the heat treatment temperature T (° C.) and the heat treatment time t (hours) are indicated by the points (T, t) in FIG.
  • the oxygen precipitate density distribution after the pore control heat treatment is (P4)
  • the heat treatment temperature T (° C.) and the heat treatment time t (time) are indicated by the points (T, t) in FIG. like, A range surrounded by a point H (600, 18), a point G (950, 3), a point J (950, 16), and / or a point K (1050, 16), a point L (1050, 1), a point A heat treatment condition selected from p4 heat treatment conditions set to a value within a range surrounded by M (1150, 1) and point N (1150, 1) is included.
  • the pore control heat treatment S04 has a first step of 600 to 1100 ° C. for 0 to 8 hours and a second step of 1000 to 1100 ° C. for 10 to 20 hours.
  • the precipitation heat treatment as the pore control heat treatment S04 can be composed of a first heat treatment at 600 to 900 ° C. for 0.25 to 8 hours and a second heat treatment at 1000 to 1100 ° C. for 10 to 20 hours.
  • the wafer having the distribution of (p1) can increase the thickness of the device region (DZ layer), it is suitable for a silicon single crystal wafer for IGBT.
  • a device region W1 where an IGBT device having a thickness direction dimension of 100 to 200 ⁇ m is formed, and a gettering region W2 which is removed after the device is formed on the back side of the device region W1.
  • This gettering region W2 corresponds to a peak of oxygen precipitate density in the central portion in the thickness direction of the wafer.
  • the device region W1 has a thickness of about 100 to 200 ⁇ m, preferably about 140 to 160 ⁇ m, more preferably about 150 ⁇ m from the surface WS1, and the vacancies injected into the wafer in the RTA processing step are diffused out by the precipitation heat treatment step. It is reduced to such an extent that it can be regarded as almost disappearing due to bonding with interstitial silicon. For this reason, it is an area
  • the gettering regions W2 and W3 are substantially the same as the device region W1 on the wafer W rear surface WS2 side, and the center region W2 in which the vacancy concentration is distributed at a high concentration in a substantially uniform state in the thickness direction at the center in the wafer thickness direction. And the rear surface side region W3.
  • the device region W1 has a thickness of about 100 to 200 ⁇ m, preferably about 140 to 160 ⁇ m, more preferably about 150 ⁇ m from the surface WS1.
  • the heat treatment in the hole control heat treatment step S04 causes the holes to be diffused outward and interstitial silicon. It is reduced to such an extent that it can be considered that it has almost disappeared. For this reason, it is in the state which can suppress the oxygen precipitation by the heat processing in a post process.
  • the gettering regions in the central region W2, the high concentration state of the vacancies is maintained, and oxygen precipitation is sufficiently possible in the heat treatment in the subsequent process.
  • the back side region W3 is in the same state as the device region.
  • the silicon single crystal wafer for IGBT of this embodiment can be manufactured.
  • the (p1) wafer a wafer having a thin DZ layer and a proximity gettering (IG) effect necessary for a device such as a memory can be manufactured.
  • IG proximity gettering
  • the (p2) wafer is deposited in the vicinity of the surface and in the center of the bulk, an epitaxial wafer substrate or the like on which an epitaxial layer is grown on the wafer surface can be manufactured.
  • the (p3) wafer a wafer having a thin DZ layer and having the proximity gettering (IG) effect necessary for a device such as a memory can be manufactured.
  • IG proximity gettering
  • the rate at which a grown-in defect-free silicon single crystal can be pulled up by introducing a hydrogen atom-containing material having a hydrogen gas equivalent partial pressure in the range of 40 Pa to 400 Pa. Therefore, a wafer in which COP defects and dislocation clusters are eliminated in the entire crystal diameter direction can be easily manufactured. Also, the silicon single crystal after pulling is irradiated with neutrons to dope phosphorus, or an n-type dopant such as phosphorus is added to the silicon melt to reduce the resistivity variation within 5% of the wafer surface. Can be.
  • the reduction in resistivity variation can also be achieved by adding phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus to the silicon melt. Further, by adding nitrogen to the silicon melt, the allowable range of the speed at which a grown-in defect-free silicon single crystal can be pulled can be further widened, and the elimination of COP defects and dislocation clusters in the wafer is facilitated. .
  • the silicon single crystal wafer manufactured as described above has COP defects and dislocation clusters eliminated in the entire crystal diameter direction, and the interstitial oxygen concentration is 8.5 ⁇ 10 17 atoms / cm 3 or less. In-plane resistivity variation is 5% or less. The resistivity itself is about 48 ⁇ ⁇ cm to 52 ⁇ ⁇ cm. Further, the silicon single crystal wafer is doped with nitrogen of 5 ⁇ 10 12 atoms / cm 3 or more and 5 ⁇ 10 15 atoms / cm 3 or less.
  • the pass rate of TZDB at a breakdown electric field of 8 MV / cm is 90% or more
  • the concentration of oxygen donor that precipitates when heat treatment is performed at 450 ° C. for 1 hour is 9 .8 ⁇ 10 12 pieces / cm ⁇ 3 or less
  • the density of BMD generated when the two-stage heat treatment at 800 ° C. for 4 hours and 1000 ° C. for 16 hours is 5 ⁇ 10 7 pieces / cm ⁇ 3 or less.
  • the recombination lifetime when the two-stage heat treatment is performed is 100 ⁇ sec or more.
  • the LPD density of 0.1 ⁇ m or more on the wafer surface is 0.1 piece / cm 2 or less, and the light etching defect density is 1 ⁇ 10 3 pieces / cm 2 or less. It has become.
  • a polycrystalline silicon layer having a thickness of 50 nm or more and 2000 nm or less is formed on the back surface side, and a surface chamfered portion is formed on the peripheral edge of the wafer surface.
  • a back side chamfer may be formed on the peripheral edge of the back side.
  • an IGBT device process SD1 having a heat treatment condition as shown in Table 3 is applied to the IGBT silicon single crystal wafer W of the present embodiment.
  • the device D is formed in the region W1. In the figure, device D is schematically shown.
  • the back grinding process SD2 thins the back side of the wafer W by a technique such as polishing to remove the back grinding regions W2 and W3.
  • the IGBT element shown in FIG. 5 is completed by a device finishing process SD3 such as cutting into chips and back surface processing.
  • the hole distribution in the wafer W is controlled by the hole control heat treatment step S04, and the device region W1 and the back grind region W2 are controlled.
  • W3 oxygen deposition does not occur in the device region W1 which is about 100 to 200 ⁇ m, preferably about 140 to 160 ⁇ m, more preferably about 150 ⁇ m from the surface WS1 even after going through the IGBT device process SD1, and 20 nm.
  • the BMD (oxygen precipitate) density is not formed at a high density of 5 ⁇ 10 3 pieces / cm 3 or more, the BMD density can be 1 ⁇ 10 3 pieces / cm 3 or less, and the IGBT characteristics Will not deteriorate.
  • the back grind region W2 adjacent to the device region W1 at a depth of 150 ⁇ m or more or 200 ⁇ m or more from the surface WS1 oxygen deposition occurs after the IGBT device process SD1, and the BMD (oxygen precipitate) density is increased. 5 ⁇ 10 4 pieces / cm 3 or more and 1 ⁇ 10 7 pieces / cm 3 or less, and the device region W1 can be protected from metal contamination during the IGBT device process SD1 by the gettering (IG) effect of the BMD. it can.
  • the back-grind regions W2 and W3 are removed by the back-grinding process SD2 the completed IGBT element does not include BMD in the entire thickness direction (emitter-collector direction).
  • the silicon single crystal wafer for IGBT is subjected to EG processing such as polysilicon film formation processing on the wafer back surface WS2. Omission can reduce manufacturing cost.
  • the (p1) or (p2) wafer W of this embodiment is applied to the device region which is the DZ layer by the memory device process SM1 similar to or different from the IGBT device process. Form the device. Thereafter, a device element for memory or the like is completed by a device finishing process SM3 such as cutting into chips and back surface processing.
  • COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, so that the gate oxide film on the wafer surface in the IGBT manufacturing process At the time of forming, COP defects are not taken into the gate oxide film, and GOI is not deteriorated. Furthermore, since the OSF region is eliminated and there is no region where the density of OSF is 10 / cm 2 or more, COP defects are taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process. The GOI is not deteriorated. In addition, leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 90% or more.
  • the wafer can be suitably used as an IGBT wafer that is an element that uses the wafer in the vertical direction. That is, since COP defects and dislocation clusters are eliminated, the quality of the wafer bulk becomes excellent, and the recombination lifetime, which is an important characteristic for an IGBT wafer, can be improved. Further, since the interstitial oxygen concentration is 8.5 ⁇ 10 17 atoms / cm 3 or less, the concentration of oxygen donor generated after the heat treatment of the wafer can be suppressed to 9.8 ⁇ 10 12 atoms / cm 3 or less. Thus, the change in the resistivity of the wafer can be prevented, and the quality of the silicon single crystal wafer can be stabilized.
  • the wafer having the oxygen precipitate density distribution of (p2), (p3) and (p4) has a device region (DZ layer) as compared with the wafer having the oxygen precipitate density distribution of (p1). Since the thickness is small, it is suitable for a general device such as a memory. In addition, since the density of oxygen precipitates is high near the surface in the thickness direction of the wafer, the proximity gettering effect can be obtained, and even when the heat treatment in the device process is performed at a low temperature, the device formation region is contaminated with heavy metals. Can be prevented.
  • (p2) has a high density of oxygen precipitates in the central portion in the wafer thickness direction
  • (p4) has a high density of oxygen precipitates in the entire thickness direction of the wafer excluding the surface layer portion. In either case, the IG effect is higher than in (p3).
  • the silicon single crystal wafer of the present invention since the variation in resistivity within the wafer surface is 5% or less, the quality of the silicon single crystal wafer can be stabilized. Furthermore, by doping the silicon single crystal with nitrogen within the above range, COP defects and dislocation clusters can be easily eliminated. If the doping amount of nitrogen is less than the above range, COP defects and dislocation clusters may not be completely eliminated, and if it exceeds the above range, nitrides are generated and a silicon single crystal cannot be grown. Further, the pass rate of TZDB is 90% or more, the concentration of oxygen donor generated when heat treatment is performed at 450 ° C. for 1 hour is 9.8 ⁇ 10 12 ions / cm 3 or less, and 4% at 800 ° C.
  • the density of BMD precipitated when performing a two-stage heat treatment at 1000 ° C. for 16 hours at 5 ° C. is 5 ⁇ 10 7 pieces / cm 3 or less, and the recombination lifetime when performing the two-stage heat treatment is 100 ⁇ sec or more. Therefore, the characteristics required for a silicon single crystal wafer for IGBT can be satisfied.
  • the conditions in the vacancy control heat treatment step S04 are set, that is, the vacancy injection RTA conditions are the same, and among the subsequent heat treatment conditions, the first step of heat treatment is performed at 700 ° C. or more and 1000 ° C.
  • the vacancies in the vicinity of the injected surface layer are stabilized, a precipitation nucleus is formed in the surface layer in a later device process, and a wafer having a desired BMD density distribution and DZ layer thickness is obtained.
  • a silicon single crystal wafer W can be produced. Thereby, the manufacturing process time can be greatly shortened, and the manufacturing cost can be reduced.
  • BMD density results which are oxygen precipitate density distributions in the thickness direction of wafers subjected to one-step heat treatment at 1000 ° C. for 16 hours and 1100 ° C. for 16 hours.
  • the precipitation heat treatment levels are shown in Table 4.
  • the first heat treatment is performed at 600 ° C. for 4 hours and 8 hours, and then the second heat treatment is performed at 1000 ° C. for 16 hours, only in the central portion in the thickness direction of the wafer.
  • a distribution (p1) in which oxygen precipitates precipitate is obtained.
  • the first heat treatment at 600 to 900 ° C. and the second heat treatment at 1000 ° C. for the purpose of promoting the formation of oxygen precipitates from the oxygen precipitation nuclei grown from the vacancies injected by the RTA treatment. I do.
  • the second heat treatment at 1000 ° C.
  • the vacancies do not diffuse outward but become oxygen precipitation nuclei, and oxygen precipitates are formed around the oxygen precipitation nuclei.
  • interstitial silicon is not released toward the center of the wafer, the density of oxygen precipitates in the center of the wafer increases, so that (p1) distribution is obtained.
  • the vacancies injected in the RTA treatment process become oxygen precipitation nuclei, and further, oxygen precipitation occurs around the oxygen precipitation nuclei by the second heat treatment at 1000 ° C. for 16 hours.
  • the density of oxygen precipitates in the vicinity of the wafer surface is increased corresponding to the distribution of the vacancies injected in the RTA process in the vicinity of the wafer surface.
  • some of the vacancies near the surface become oxygen precipitation nuclei, and the vacancies that do not become oxygen precipitation nuclei diffuse outwardly by the second heat treatment at 1000 ° C. for 16 hours.
  • the density of oxygen precipitates increases in the center of the wafer. From the above, it is considered that the p2 distribution is obtained when the first heat treatment is performed at 700 ° C. for 8 hours and then the second heat treatment is performed at 1000 ° C. for 16 hours.
  • a first heat treatment at 900 ° C. for 1 hour results in the p3 region (for the same reason as the first heat treatment at 800 ° C. for 1 hour and 2 hours).
  • a first heat treatment at 900 ° C. for 2 hours results in the p2 region (for the same reason as the first heat treatment at 800 ° C. for 4 hours).
  • the first heat treatment at 900 ° C. for 4 hours and 8 hours results in the p4 region (for the same reason as the first heat treatment at 800 ° C. for 8 hours). Note that FIG.
  • FIG. 13 shows oxygen in the wafer thickness direction when a first heat treatment is performed at 900 ° C. for 0.25 hour, 0.5 hour, or 1 hour, and then a second heat treatment is performed at 1000 ° C. for 16 hours.
  • the precipitate density distribution is shown, it can be seen that the p3 distribution is obtained when the first heat treatment is performed at 900 ° C. for 1 hour or less.
  • FIG. 14 shows the distribution of oxygen precipitate density in the thickness direction of the wafer when one-step heat treatment is performed at 1000 ° C. for 16 hours and at 1100 ° C. for 16 hours.
  • the (p1) distribution is obtained as described in FIG.
  • voids implanted by interstitial oxygen and RTA treatment diffuse outwardly, resulting in a decrease in void concentration across the entire wafer thickness direction.
  • the pore concentration distribution becomes almost uniform. For this reason, it is considered that the distribution of oxygen precipitate density is uniform at a low concentration level throughout the entire thickness direction of the wafer. From this result, it is understood that the maximum temperature of the precipitation heat treatment should be suppressed to 1050 ° C.
  • FIG. 1 shows the relationship between the precipitation heat treatment temperature and the precipitation heat treatment time and the oxygen precipitate density distribution based on the results of FIGS.
  • the point of filling is the thickness direction of the wafer when the first heat treatment is performed at a temperature of 600 ° C. to 900 ° C. for 1 hour to 8 hours and then the second heat treatment is performed at 1000 ° C. for 16 hours.
  • the white dots are the drawings showing the oxygen precipitation distribution in the thickness direction of the wafer in the range of p1 to p4 when a one-step heat treatment is performed at 1000 ° C. for 16 hours and 1100 ° C. for 16 hours. From FIG.
  • the heat treatment temperature and heat treatment time corresponding to the range of p1 are used, and when manufacturing a wafer suitable for a general device such as a memory, p2 and p3.
  • the precipitation heat treatment may be performed by selecting the heat treatment temperature and the heat treatment time corresponding to the range of p4.
  • the heat treatment at 700 ° C. is 8 hours or more, 800 ° C. is 1 hr or more, and 900 ° C. is 15 min or more. It was found that the surface layer deposition can be secured by the heat treatment. Further, as shown in FIG. 13, it was found that the surface layer deposition did not occur at a temperature of 1000 ° C., but occurred only in the central part of the bulk, and the deposition did not occur in the wafer depth direction at a temperature of 1100 ° C.
  • heat treatment may be performed at a temperature of 700 ° C. or higher and lower than 1000 ° C. for a time of 15 minutes or longer and 480 minutes or shorter. If it exceeds 480 min, nucleation occurs on the surface layer, so that there is a problem that the DZ layer disappears and precipitates penetrate into the surface layer in the device process. Furthermore, as shown in FIG. 13, the stability of the surface vacancies is lost at a temperature of 1000 ° C. Since precipitation does not occur in the wafer depth direction at a temperature of 1100 ° C. or higher, the thermal stability of the bulk vacancies is lost, so the second heat treatment is performed at a temperature condition of 1000 ° C. or higher and 1050 ° C. or lower. Precipitation at the bulk center can be ensured and no precipitation occurs on the surface layer, so a wide range of DZ thickness can be ensured.
  • the DZ layer thickness depends on the heat treatment time at 900 ° C., and the longer the processing time, the thinner the DZ layer thickness. On the other hand, in the case of 1000 ° C. for 16 hours, precipitation occurs only in the central part of the bulk. From the above results, it is understood that the heat treatment time may be controlled if it is desired to obtain a desired DZ layer thickness.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Thermal Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une plaque de silicium monocristalline qui se compose d'une étape de tirage consistant au tirage d'un lingot de silicium monocristallin par la méthode de Czochralski à une vitesse où un lingot de silicium monocristallin ne comportant aucun défaut interne peut être tiré ; une étape de recuit thermique rapide (RTA) consistant à effectuer un traitement thermique (RTA) sur une plaque obtenue par découpage du lingot de silicium monocristallin, par chauffage/refroidissement rapide de la plaque sous atmosphère contenant de l'azote ; et une étape de traitement thermique de précipitation consistant à effectuer un traitement thermique sur la plaque de façon à contrôler la répartition de la densité de précipité d'oxygène dans le sens de l'épaisseur de la plaque après l'étape de recuit thermique rapide (RTA).
PCT/JP2009/060620 2008-06-10 2009-06-10 Procédé de fabrication de plaque de silicium monocristalline, et plaque de silicium monocristalline Ceased WO2009151077A1 (fr)

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CN102605433A (zh) * 2012-01-09 2012-07-25 浙江大学 一种消除掺氮直拉单晶硅片中原生氧沉淀的方法
JP2013010678A (ja) * 2011-06-30 2013-01-17 Siltronic Ag シリコン基板の製造方法およびシリコン基板
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JP2019062189A (ja) * 2017-08-18 2019-04-18 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ Ｃｚ半導体ボディを含む半導体装置およびｃｚ半導体ボディを含む半導体装置を製造する方法
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