WO2009150611A1

WO2009150611A1 - Digital detector and digital automatic gain control system for radio receivers

Info

Publication number: WO2009150611A1
Application number: PCT/IB2009/052447
Authority: WO
Inventors: Yann Le Guillou; Jan Van Sinderen
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2008-06-09
Filing date: 2009-06-09
Publication date: 2009-12-17
Anticipated expiration: 2010-12-09

Abstract

An entropy-based digital detector and the implementation or use thereof in digital automatic gain control system (AGC) is disclosed. The digital entropy-based detector (D) for detecting overloading of an analog-to-digital converter (60) by monitoring a single-bit output bit-stream (ya) of the converter, by means of a counter unit (A, T) which is configured to count a run length of sequences in the single-bit stream (ya) of consecutive identical binary symbols and to provide an counter value (ES) at an output (out) of the detector (D). A digital automatic gain control system (410) for control of the gain of at least one amplifier (30, 50) in a front end of a radio receiver (400) can be implemented by means of the entropy-based detector (D) together with a quantizer unit (Q) configured to compare the detector output with adjustable upper and lower trigger values, to generate an up- or down-stepping pulse, respectively, when the detector output passes a respective trigger value, and to provide the respective up- and down-stepping pulses at a quantizer output. Thus, a respective gain control unit can be configured to produce gain control signals in accordance with the up-/down- stepping pulses from the quantizer output. The detector is particular suitable for software- defined radio receivers being part of a modem of a device for mobile, portable, terrestrial, cable or satellite data communication, or for communication devices adapted for Bluetooth, Wireless LAN, WiMax connection links or alike, or for devices for mobile television, or for devices for mobile cellular communications.

Description

Digital detector and digital automatic gain control system for radio receivers

FIELD OF THE INVENTION

The present invention relates in general to software-defined radio receivers.

In particular, the present invention relates to digital detector and digital automatic gain control system for software-defined radio receiver. More particular, the present invention relates an entropy-based digital detector and digital automatic gain control system for software-defined radio receiver.

BACKGROUND OF THE INVENTION

Today, there is a trend to digitize broadband receiver. Consequently, analog selectivity is being exchanged for digital processing. Further, the border between analog and digital domain, i.e. the point of analog-to-digital conversion, is gradually moving towards the antenna of a receiver.

This development is typically observable in Software Defined Radio (SDR) systems, which are in general radio communication systems where components that have conventionally been implemented in hardware, such as mixers, filters, amplifiers, modulators/demodulators, detectors and so on, are more and more implemented using software executed by programmable digital circuitry, e.g. a computer. Accordingly, a simple SDR consists of a personal computer (PC) with an analog-to-digital converter, preceded by some kind of radio frequency (RF) front end for reception of the desired RF input signal. Thus, a significant part of signal processing is handed over to programmable hardware, e.g. the PC, rather than using specialized hardware. Advantageously, a SDR can receive signals modulated in accordance with different radio protocols just by running different, i.e. respectively adapted software. Hence, in the long term, software-defined radio is expected to become the dominant technology in radio communications. Obviously, every wireless receiver must adjust its gain to the strength of the wanted channel, which can vary over orders of magnitude. Traditionally, amplification with gain control is fully assigned to the analog front-end with amplifiers whose gain is either programmable in discrete steps, or is continuously variable; usually, there is a mixture of both, as described e.g. in WO 2004/109909. In the context of being digital as much as possible, it is also desirable to make use of digitally controlled programmable gain amplifier. In contrast to analog controlled PGA (Programmable Gain Amplifier), the gain of a digitally controlled PGA is controlled in steps. This has the advantage that for each discrete gain setting the amplifier can be optimized for such parameters as linearity, noise Figure and magnitude of the step. For instance, at small signal levels the gain should be high with low noise factor while the linearity is not of primary importance. In contradistinction therewith at large signal levels the gain should be low with optimal linearity while the noise Figure is of minor interest.

The broadband nature of SDR receivers asks for a radio frequency front-end with at least one amplifier with automatic gain control (AGC) that can handle an entire band of channels. Moreover, the AGC-system should be able to properly measure and control the amplitude of the entire band of communication channels. This means that the signal to be detected by the AGC-system may consist of a wanted channel surrounded by number of adjacent channels, which also may be of substantially higher strength. To prevent the ΣΔ ADC from overloading due to the presence of strong adjacent channels, a detector must measure the total, i.e. the wanted as well as the unwanted signal power, and then, adjust the programmable gain accordingly.

WO 2004/047323 discloses a radio receiver with analog and digital portions, where an A/D converter is arranged between the analog and digital portions. An AGC sets a first variable gain amplifier (VGA) to low gain upon determination that a wide-band power estimation exceeds a wide-band threshold, where the wide-band threshold is selected to reduce the occurrence of A/D converter saturation. If the wide-band power estimation is less than the wide-band threshold, then for each VGA in the analog portion, a determination is made whether a narrow band power estimate exceeds a narrow-band threshold, corresponding to that VGA, plus a hysteresis value, in which case that VGA is set to low gain, or whether the narrow-band energy estimate is less than the narrow-band threshold minus a hysteresis value, in which case that VGA is set to high gain. ΣΔ A/D conversion architectures are used for estimating wide-band power by taking a signal from an intermediate point in the decimation and filtering processing chain. More particularly, Fig. 6 of WO 2004/047323 shows one channel of a typical decimation and filtering scheme, wherein each decimation and filtering stage reduces the bandwidth while increasing the resolution of the signal. Due to noise shaping in the ΣΔ A/D converter, several stages of decimation and filtering are needed to reduce the impact of high frequency quantization noise. However, choosing a particular point in the decimation chain for power estimation is a compromise, which aims to avoid excessive domination by quantization noise, while ensuring sufficient bandwidth for detecting out-of-band inter ferers. Moreover, since the first decimation filtering is performed before the level detection, information is lost, which is needed for preventing ADC overloading under all conditions.

SUMMARY OF THE INVENTION

Accordingly, it is one object of the present invention to provide a method and an implementation, which enables detecting of an overloading situation of an analog-to- digital converter under all conditions. The object is achieved by a digital entropy-based detector for detecting overloading of an analog-to-digital converter by monitoring a single-bit output bit-stream of the converter according to claim 1.

Accordingly, the detector comprises a counter unit configured to count a run length of sequences in the single-bit stream of consecutive identical binary symbols and to provide a counter value at an output of the detector.

In certain embodiments, the analog-to-digital converter is a one-bit sigma- delta analog-to-digital converter. The analog-to-digital converter and the detector are clocked with the same frequency.

The object is further achieved by digital automatic gain control system for control of the gain of at least one amplifier in a radio receiver front end according to claim 4. Accordingly the system comprises the entropy-based detector of the invention, a quantizer unit configured to compare the output of the detector with adjustable upper and lower trigger values, to generate an up- or down-stepping pulse, respectively, when the detector output passes a respective trigger value, and to provide the respective up- and down- stepping pulses at a quantizer output, and a gain control unit configured, upon receiving the up-/down-stepping pulses from the quantizer output, to produce an gain control signal for increasing the gain, when the detector output is below the lower trigger value, and to produce a gain control pulse for decreasing the gain, when the detector output is above the upper trigger value. In certain embodiments of the AGC system, the gain control unit is configured to produce no gain control pulse, when the detector output remains between the upper and the lower trigger value.

The AGC system is especially suitable to be implemented as full digital monolithic integrated circuitry. In preferred embodiments of the AGC system the detector can be configured by setting of the predetermined trigger values in the quantizer unit so that the detector is configured as a pseudo-peak mode detector, i.e. it is not to be understood as ideal peak detector because this would require to detect the signal level in an infinity small time, or a root means square mode detector.

The object is further achieved by radio receiver according to claim 8.

Accordingly, the radio receiver comprises an analog front end having at least one amplifier for amplification of a received signal, wherein after the front end the received signal is supplied in a analog-to-digital converter for converting the received analog signal into a corresponding digital signal, and wherein the radio receiver further comprises a digital automatic gain control (AGC) system of the invention for control of the gain of the at least one amplifier.

In a certain embodiment, the radio receiver is implemented as a software- defined radio receiver. The radio receiver is applicable as part of a modem of a device for mobile, portable, terrestrial, cable or satellite data communication, or as part of a communication device adapted for connection links via Bluetooth (IEEE Standards of the 802.15 family), Wireless LAN (IEEE Standards of the 802.11 family), Worldwide Interoperability for Microwave Access (WiMax, IEEE Standards of the 802.16 family), or mobile WiMax (wireless broadband, WiBro), or as part of a devices for mobile television (DVB-H, ETSI standard EN 302 304), or is part of a device for mobile cellular communications. It is understood that these are only a few examples.

The object is further achieved by a method for entropy based detection of overloading of an analog-to-digital converter outputting a single-bit output bit-stream according to claim 11.

Accordingly, the method comprises: receiving and temporally storing a symbol from the single-bit stream, comparing the symbol with the preceding symbol of the bit-stream, determining, if the current symbol, i.e. current bit of the bit stream, and the preceding symbol, i.e. preceding bit of the bit stream, are identical, and upon determination that the current bit and the preceding bit are identical increasing a counter value representing the run- length of consecutive identical bits, upon determination that the symbol and the preceding bit are not identical resetting the counter value to zero.

The object is further achieved by a method for entropy based automatic gain control of the gain of at least one amplifier in the front end of a radio receiver, wherein the method comprises detecting, by the method according to claim 11, overloading of an analog- to-digital converter located after the analog front end of the radio receiver and configured for outputting a single-bit output bit-stream.

Accordingly, the method further comprises comparing the detector output with upper and lower trigger values and generating up- or down-stepping pulse, respectively, when the detector output passes a respective trigger value, and controlling the gain based on the up- and down-stepping pulses by producing a gain control signal for increasing the gain, when the detector output is below the lower trigger value, and by producing a gain control signal for decreasing the gain, when the detector output is above the upper trigger value. The basic idea of the invention resides in the concept of an entropy-based digital detector. Such a detector enables to build digital pseudo-peak or RMS detectors despite a single-bit bit-stream input.

Further, an entropy-based digital detector in accordance with the present invention can be located just after the 1-bit ΣΔ ADC, so that the detector measures the entropy of the full 1-bit bit-stream. Consequently, such a digital entropy-based detector is suitable to detect when the ADC is overloading under any conditions.

Furthermore, in case of overload detection a digital AGC system set up on the entropy-based detector of the invention may react accordingly. For instance, the AGC system may decrease the gain of an amplifier in the analog RF front end of a receiver, e.g. the gain of the LNA 30 of the analog RF front end of the SDR receiver 100 depicted in Fig. 1.

Moreover, since the entropy-based digital detector can be located before the first decimation filter, e.g. the filter 71 or 72, respectively, of the SDR receiver 100 of Fig. 1, the detector of the invention is also capable to detect ADC overloading by adjacent channels that are f/R distant from the wanted channel. In particular, the solution of the invention does not need to make a trade-off as done in WO 2004/04732, i.e. a compromise in choosing a particular point in the decimation chain for power estimation, in order to ensure sufficient bandwidth for detecting out-of-band interferers. As a result, by the detector of the present invention the full input bandwidth can be detected such that overloading of the ADC, such as a 1-bit CT ΣD-ADC, can be avoided under all, in particular blocking, conditions.

Preferred embodiments and further developments of the invention are defined in the dependent claims of the independent claims. It shall be understood that the apparatus and the method of the invention have similar and/or identical preferred embodiments and advantages. BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. In the following drawings, the Figures are schematically drawn and not true to scale, and identical reference numerals in different Figures, if any, may refer to corresponding elements. It will be clear for those skilled in the art that alternative but equivalent embodiments of the invention are possible without deviating from the true inventive concept, and that the scope of the invention is limited by the claims only. Fig. 1 illustrates a simplified block diagram of a software-defined radio built with ΣΔ ADC;

Fig. 2 depicts an example for time domain input and output signal of a 1-bit ΣΔ ADC;

Fig. 3 is a simplified block diagram of the entropy-based detector according to the present invention;

Fig. 4 shows a preferred application of the entropy-based digital detector of the present invention for implementation of an AGC system, in particular suitable for a SDR receiver built with ΣΔ ADC;

Fig. 5 illustrates max run length of 'all-1 ' or 'all-0' sequences according to the 1 MHz wanted level without interferer and in presence of N+5, N+l 1, N+17 interferers; and

Fig. 6 is a flow chart of the entropy-based detecting method according to the invention.

DETAILED DESCRIPTION OF EMBODIMENTS Fig. 1 illustrates a simplified block diagram of a SDR receiver 100. A radio frequency (RF) signal S_RF is received by an antenna 10 of the analog RF front-end 110. The analog RF front end comprises an antenna filter 20 connected to a low noise amplifier (LNA) 30 for amplifying the received RF signal SRf. The LNA 30 is followed by two signal branches for processing in-phase (I) and quadrature (Q) components of the received signal S_RF. The I- and Q-branch, respectively, comprise respective mixers 41 and 42, respectively, for down mixing or down converting the signal S_RF into respective base band signals S_BB,_I and S_BB,_Q, followed by a respective first order low pass filters 51 and 52, respectively. It goes without saying that also only one branch may be enough depending of the respective used modulation protocol employed in the signal of interest. The RF front end 110 is followed for the desired receiver digitization by respective analog-to-digital converters (ADC) 61 and 62, respectively. The ADCs 61, 62 are the border between analog domain and digital domain of the signal processing of the received base band signal SBB, I or SBB, Q, respectively. Accordingly, the base band signals SBB,I and S_BB,_Q of the I- and Q-branch are digitized by the respective ADCs 61, 62.

The digitalized base band signals SBB,I and SBB,Q of the I- and Q-branch are supplied into respective decimation filters 71 and 72, respectively. The decimation filters 71, 72 serve to isolate the channel of interest and to lower the raw ADC output rate to one channel's symbol rate. Moreover, the same digital filter 71 or 72, respectively, filters out both quantization noise and interferers.

At the end of the receiver chain is located a programmable digital circuitry, e.g. a digital signal processor (DSP) 80, which is configured for further processing of the signal of interest according to well-known principles.

For implementation of the analog-to-digital converter 61 and 62, respectively, Sigma-Delta (ΣΔ) ADCs are well suited due to fact that adjacent channel interferers fall into the same band as the shaped quantization noise; this is illustrated in the signal frequency diagrams in the upper part of Fig. 1; where shading 1* denotes the desired channel in the radio frequency input signal RF, shading 2* denotes the adjacent channels, shading 3* denotes a first alternate channel, shading 4* denotes a second alternate channel, and shading 5* denotes out of band interferers. The black arrows at the top of Fig. 1 define the portions of the SDR receiver where the signal is in the radio frequency RF area and where the signal is in the base band BB area. The black arrows at the top of Fig. 1 point to the respective functional element in the receiver chain and illustrates the transfer characteristic of the respective referenced element in the receiver chain, e.g. diagram 20' reflects the transfer characteristic of the antenna filter 20.

It is worth noting that the single-bit, continuous-time (CT) ΣΔ ADCs 61, 62 achieve a large dynamic range (DR) as described e.g. by Y. Le Guillou in "Project A&B continuous-time ΣΔ ADC anti-aliasing properties" NXP, BL TV Front-End & Media Interfaces, version 0.1, January 2007. Furthermore, the ΣΔ ADCs have excellent linearity while their power consumption remains low as described e.g. by Y. Le Guillou in "Analyzing Sigma-Delta ADC's in deep sub-micron technologies" RF Design , pp. 18-26, Feb. 2005.

As discussed above, the low noise amplifier LNA 30 in the signal chain of the RF front end need an AGC-system, also called automatic level control (ALC) system, which properly measures and controls the amplitude of the entire band of communication channels. For the purpose of power measurement, a detector can be used to monitor the output of a circuit. The detector has to consider the total, i.e. the wanted as well as the unwanted signal power, and, based on this, the programmable gain of a PGA, e.g. the LNA 30, may be adjusted accordingly, in order to prevent the ΣΔ ADCs 61, 62 from overloading, when in the received RF signal strong adjacent channels are present.

A peak type detector enables to quickly detect that the output of a circuit, such as an amplifier, mixer, filter, and/or ADC, is overloaded, i.e. clipping. In turn, the RMS type detector is suitable to prevent repeated switching between two gain settings that may modulate the output signal of the controlled amplifier. The RMS detector creates an output, e.g. a dc voltage, proportional to the root means square (RMS) value of the signal. RMS detectors have a quadratic detection characteristic and the resulting power P measurement is based on signal strength variance estimation of the digitized stream ya:

(Equation I) According to Equation 1, the variance estimation of a 1-bit digital stream is always equal to 1. Therefore detectors based on variance estimation cannot be located just after a single-bit continuous-time sigma-delta analog-to-digital converter (1-bit CT ΣΔ ADC) but after the first stage of the decimation filter, as done e.g. in WO 2004/047323.

The first stage of such decimation filter can be a flexible FIR- filter, i.e. a filter with finite impulse response (FIR), where the order of the filter is denoted by L. The decimation ratio R is an integer or a fractional value. Decimation means reducing the number of samples in a discrete-time signal, wherein the decimation is a two-step process comprising low-pass (anti-aliasing) filtering and down-sampling. Accordingly, the output of such Lth- order FIR-filter is sampled at f/R the clock rate f_s, e.g. a typical value may be 448 MHz, of the input. The transfer function of the decimation filter is:

(Equation !)

The decimation filter nulls input frequencies at the down-sampled rate f/R and every multiple. This guarantees that after down sampling nothing aliases to DC. However, there is the disadvantage of filtering adjacent channels that are f/R distant from the wanted channel. Consequently, in SDR or in broadband receivers built with single-bit ΣΔ ADC, it becomes obvious that digital detector based on variance estimation will not help in detecting the potential ADC overloading due to strong adjacent interferer located at f/R.

Now with reference to Fig. 2, in which the time domain output bit-stream of a single-bit ΣΔ ADC is illustrated, when the input signal is an analog sine- wave signal. It has been perceived that when the input signal magnitude is high or low, respectively, the number of consecutive digital level Tor O', respectively, is increasing. This means that the number of energy changes in a given time period reduces. This can be considered as the amount of disordered states in the bit-stream going down. From an energy point of view, this means that the entropy of the 1-bit bit-stream is decreasing. The herein proposed digital detector is arranged or configured to exploit this characteristic. Therefore, the detector is herein called entropy-based digital detector.

The basic principle of an AGC-system with a digital entropy-based detector D is depicted in Fig. 3. A run length measurement of 'all- 1' and 'all-0' sequences in the 1-bit stream y is done in the detector D. This is achieved by counting or accumulating consecutive identical symbols, i.e. ' 1 ' or O', in the monitored 1-bit stream y, e.g. the output of a ADC. The accumulated ' all- 1 ' or 'all-0', respectively, value ES is provided at the output of the detector D as an n-bit word. Then, the n-bit word ES is compared in a quantizer Q with adjustable upper and lower trigger values or thresholds T_H and T_L. These trigger values can be implemented as respective comparator-levels. The quantizer Q is configured such that each time that the signal ES corresponding to the accumulated 'all-1 ' or 'all-0', respectively, value passes such a defined trigger value or threshold T_H, T_L an up- or down- stepping pulse is generated and supplied to an up/down pulse generator P.

The up-/down-pulse generator P comprises digital logic gates interconnected such that the generator P upon receiving the up-/down-stepping pulses from the quantizer Q, produces an up-pulse AGC u each time that the signal ES is below the lower comparator level T_L for increasing the gain, e.g. by one step. Further, each time that the signal ES is above the upper comparator level T_H a down-pulse AGC d is produced for decreasing the gain, e.g. by one step. When the level of the signal ES remains in the "dead zone" between the two comparator-levels T_H and T_L, no stepping-pulse is produced, i.e. the gain of the amplifier remains unaltered.

In this connection, it is worth noting that the respective gain step value(s) and/or the associated amplifier selection may depend on the respective employed AGC algorithm. An AGC algorithm can be considered as state machine that decides according to previous and current up-/down-pulses received the gain step value and the gain step sign for each gain controlled amplifier of the system. Further, each amplifier may have a different gain step value. For example, the gain step of one amplifier, e.g. the LNA (Fig. 1 and 4: 30) or 1st order low-pass amplifier (Fig. 1 : 51, 52; Fig. 4: 50), may be partly compensated in the other amplifier to trade-off noise versus linearity requirements.

As will be described in more detail with reference to Fig. 4, an entropy-based

AGC system according to the invention may be implemented as fully digital circuitry.

Further, the AGC system does not require any external components. It is thus very suited to monolithic integration. An embodiment for a fully digital automatic gain control (AGC) system 410 in a SDR receiver 400, based on the entropy-based detector of the present invention is illustrated in Fig. 4.

The herein by way of an example described AGC-system 410 is arranged to monitor a single-bit ΣΔ ADC 60. As mentioned earlier, the input signal of the ADC 60 is amplified by the LNA 30 and the first order low-pass amplifier 50 and comprises a large number of channels. It is understood that the AGC-system 410 may also be used for controlling the analog gain of a receiver handling a single channel.

An output single bit bit-stream ya of the ADC 60 is applied to the digital entropy-based detector D that comprises a counter unit realized by the accumulator A and the pulse generator T. The counter unit is configured such that in the accumulator A the ' all- 1 ' or

'all-0' sequence of the single bit (1-bit) bit-stream ya is counted, i.e. accumulated, in the accumulator A at the sampling frequency rate f_s of the ADC 60.

In Fig. 4, the function of the accumulator A is implemented by means of a digital counter, wherein the sampling frequency f_s is used as clock signal for counter. Thus, the counter increases with each clock pulse of the sampling frequency f_s its output value ES.

The counter further comprises a reset input RST by means of which the output of the counter can be reset to zero.

The pulse generator T is configured to generate a pulse, when a ' 1-0' or '0-1 ' transition occurs in the single-bit bit-stream ya. The positive pulse generated has a T_s=l/f_s duration and resets the accumulated value in the accumulator A via the reset input RST thereof. In the example embodiment of Fig. 4 the function of the pulse generator T is implemented by means of a D-Flip-Flop or Latch F and a XOR-gate. The single bit bit- stream yd is supplied to the input D of the D-Flip-Flop and to one input of the XOR-gate.

Further, the sampling frequency f_s is used as clock signal for the D-Flip-Flop, the output Q of which is supplied to a second input of the XOR-gate. Accordingly, due to the exclusive OR- function of the XOR-gate the pulse generator T produces a positive output pulse each time a '0-1 ' or '1-0' transition occurs in the single bit bit-stream ya, as required.

The accumulated value ES represented as a n-bit word and corresponding to the actual 'all-1 ' or 'all-0' sequence at f_s rate, is subsequently applied to the quantizer Q.

The quantizer Q comprises two digital comparators C2 and C3. Comparator C2 compares the n-bit output signal ES of the detector D with a high threshold T_L and produces logic ' 1 ' when the content of the accumulator A is higher than the threshold T_L. Correspondingly, comparator C3 compares the output signal ES of the detector D with a low threshold T_H and produces a similar second quantizer output signal when the level of the signal is lower than the threshold T_H. That is to say, by increasing or decreasing the difference between the threshold value T_H and T_L the dead zone can be adjusted.

For example, it is assumed that the ADC 60 starts to be overloaded when 'all- r or 'all-0' value is 8, i.e. '100' in binary representation. Therefore, for configuring the entropy-based digital detector D in a pseudo-peak detector mode the threshold T_H has to be set to 8.

By decreasing the threshold value T_H, the digital detector D will start to behave as an RMS detector.

It is worth noting that depending on the channel conditions/estimation, mode selection etc., T_H and T_L can be set dynamically by a respective control unit of the AGC system, e.g. by the DSP 80.

The system of Fig. 4 further comprises the up-/down-pulse generator P that is configured for generation of a sign logic signal SLS and enable logic signal ELS according to the following truth table (Table 1) for the up-/down-pulse generator P. Table 1:

The generated logic signals SLS and ELS are supplied to the AGC-algorithm, which can be implemented as state machine 90 realized in hard-wired logic that decides according to previous and current up-/down-pulses received the gain step value and the gain step sign for each gain controlled amplifier of the system. Accordingly, when the level of the output ES of the detector D is in the "dead zone", i.e. between the levels T_L and T_H of the quantizer Q, the output of the comparator C2 is logic '1 ' and output of the comparator C3 is logic '0'. This results that enable logic signal ELS is set to logic '0'. This information can be used to reset the gain step value predefined in the AGC algorithm of the state machine 90 so that the gain of the controlled amplifiers 30, 50 remains unaltered.

When the output level ES of the detector D is below the level T_L of the quantizer Q, then both enable and sign signals are set to logic ' 1 '. Consequently, the gain of controlled amplifiers, e.g. LNA 30 and/or 1st order low-pass amplifier 50 can be increased by the pre-defined gain step value of the AGC algorithm of the state machine 90. It goes without saying that the gain step value(s) may change according to the mode, channel condition/estimation, etc. and can be set by the respective control unit of the AGC system, e.g. by the DSP 80.

When the level of the output ES of the detector D is above the level T_H of the quantizer Q, then the enable logic signal ELS is set to logic ' 1 ' whereas the sign logic signal SLS is set to logic '0'. Therefore, the amplifier gain is decreased by the pre-defined gain step value of the AGC algorithm in the state machine 90.

To get more insight into T_H and T_L values, some simulations have been performed on the 5th-order 1-bit direct feedforward continuous-time ΣΔ ADC in the DVB- H/T mode as described by Y. Le Guillou, in "Broadband entropy-based digital detector suitable for software defmed-radio", study report, NXP Semiconductors, BL TV Front-End, January 2007. The in-band maximum-stable amplitude (MSA) was simulated at -7 dBVrms.

The maximum run-length of 'all-0' or ' all- 1 ' sequence was tracked for different magnitude of a IMHz sine- wave as the signal of interest with and without the presence of inter ferers. The interferer to carrier ratio (I/C) has been set to 40 dB, as stipulated by IEC62002-1, "Mobile and portable DVB-T/H radio access - Parti : Interface specification ", first edition 2005-10.

As illustrated in Fig. 5, when compared to the 'wanted signal without interferer' case, in presence of interferer 40 dB above the wanted signal (IMHz sine-wave), the maximum run-length of 'all-0' or ' all- 1 ' sequence is increased. A closer look at the output spectrum of the ΣΔ ADC in presence of N+5, N+l lor N+17 interferer enable to determine that the ADC is overloaded when the maximum run-length of 'all-0' or ' all- 1 ' sequence is 8. Consequently, for the DVB-H/T mode, it has been found that it is recommendable to set T_H at 8. Having T_H equal to 8, means that the overload detection is achieved in eight clock cycle of the sample rate f_s. Thus, the maximum overloading detection time tdet when the ADC is clocked at f_s=448MHz, is:

Q t_cda = ~ 18ns . (Equation 3)

As a result, the reliable detection can be achieved during the guard interval for instance.

It is also worth noting that for a given input signal magnitude of the interferer the maximum-run- length of 'all-0' or ' all- 1 ' sequence is not constant whatever the interferer frequency of the signal. This is due to the selectivity introduced in the ΣΔ ADC, as described by Y. Le Guillou, in "Feedforward sigma-delta converter with an optimized built-in filter function" patent application EP05301002.1, filled date 05/12/2005.

The digital entropy-based detector of the present invention is suitable for software defined radio receivers built with built ΣΔ ADC. The described digital AGC system enables to build on-demand trade-off between noise linearity and power consumption. Therefore, the invention is especially applicable to devices that are developed in the field of wireless application, e.g. any kind of receivers, i.e. mobile, portable, terrestrial, satellite, cable, cable modem. Moreover, in the field of connectivity, e.g. in communication devices using Bluetooth, Wireless LAN, WiMax/Wibro. Further, in personal devices for mobile television TvoM. Last but not least in any mobile device for mobile cellular communications, such as GSM, EDGE, UMTS and any future system. Finally yet importantly, in Fig. 6 a flow chart illustrates the steps to be taken in accordance with the entropy-based detection method of the present invention, which is especially useful in detecting signal comprised of a single bit bit-stream at the output of a digital signal processing circuit, such as a analog-to-digital converter (ADC).

In step SlOO a symbol S_t is from the single-bit stream to be monitored, i.e. detected, e.g. the output of a ADC, is received and temporally stored, e.g. in a fϊrst-in- first- out shift register. Then in step S200, the symbol St_-1 is compared with the actual symbol S_t. In step S300 it is determined if the symbol S_t is equal to symbol St_-1.

If determinations results in "YES", the method goes to step S400, in which a counter value ES for consecutive identical symbols, i.e. ' 1 ' or O', is increased by one. That is the number of consecutive identical symbols is accumulated.

If the determination results in 'TSfO", the method goes to step S500, in which the counter value ES for consecutive identical symbols, i.e. '1 ' or O', is reset to zero. Simultaneously with the method steps SlOO to S500, the actual accumulated ' all- 1 ' or 'all-0', respectively, sequence value ES is compared with adjustable upper and lower trigger values or thresholds T_H and T_L. Each time that the value ES passes such a defined trigger value T_H or T_L an up- or down-stepping pulse is generated. Based on reception of the up-/down-stepping pulses an up-pulse AGC u is produced for increasing the gain of respective amplifiers, each time that the signal ES is below the lower comparator level T_L. In turn, each time that the signal ES is above the upper comparator level T_H a down- pulse AGC d is produced for decreasing the gain of respective amplifiers. As long as the level of the signal ES remains in the "dead zone" between the two comparator-levels T_H and T_L, no stepping-pulse is produced, i.e. the gain of the amplifier remains unaltered.

Summarizing, an entropy-based digital detector and the implementation or use thereof in digital automatic gain control system has been disclosed. Such digital entropy- based detector for detecting overloading of an analog-to-digital converter by monitoring a single-bit output bit-stream of the converter comprises a counter unit configured to count a run length of sequences in the single-bit stream of consecutive identical binary symbols and to provide a counter value at an output of the detector. A digital automatic gain control system for control of the gain of at least one amplifier in a front end of a radio receiver can be implemented by means of the entropy-based detector together with a quantizer unit configured to compare the detector output with adjustable upper and lower trigger values, to generate an up- or down-stepping pulse, respectively, when the detector output passes a respective trigger value, and to provide the respective up- and down-stepping pulses at a quantizer output. Thus, a respective gain control unit can be configured to produce gain control signals in accordance with the up-/down-stepping pulses from the quantizer output.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single means or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:

1. A digital entropy-based detector (D) for detecting overloading of an analog-to- digital converter (60) by monitoring a single-bit output bit-stream (ya) of the converter, wherein the detector comprises a counter unit (A, T) configured to count a run length of sequences in the single-bit stream (ya) of consecutive identical binary symbols and to provide a counter value (ES) at an output (out) of the detector (D).

2. Detector according to claim 1, wherein the analog-to-digital converter (60) is a one-bit sigma-delta analog-to-digital converter.

3. Detector according to claim 1 or 2, wherein the analog-to-digital converter (60) and the detector (D) are clocked with the same frequency (fs).

4. Digital automatic gain control system (410) for control of the gain of at least one amplifier (30, 50) in a radio receiver front end, wherein the system comprises a detector (D) according to one of the claims 1 to 3, a quantizer unit (Q) configured to compare the output (ES) of the detector (D) with adjustable upper and lower trigger values (T_H, T_L), to generate an up- or down-stepping pulse, respectively, when the detector output passes a respective trigger value, and to provide the respective up- and down-stepping pulses at a quantizer output, and a gain control unit (P) configured, upon receiving the up-/down-stepping pulses from the quantizer output, to produce a gain control signal for increasing the gain, when the detector output is below the lower trigger value, and to produce a gain control pulse for decreasing the gain, when the detector output is above the upper trigger value.

5. System according to claim 4, wherein the gain control unit (P) is further configured, to produce no gain control pulse, when the detector output remains between the upper and the lower trigger value.

6. System according to claim 4 or 5, wherein the control system is comprised of full digital monolithic integrated circuitry.

7. System according to claim 4 or 5, wherein the detector is configured by setting of the predetermined trigger values (T_H, T_L) in the quantizer unit (Q) so that the detector (D) is configured as a pseudo-peak mode detector or a root means square mode detector.

8. Radio receiver (400) comprising an analog front end having at least one amplifier (30, 50) for amplification of a received signal, wherein after the front end the received signal is supplied in a analog-to-digital converter (60) for converting the received analog signal into a corresponding digital signal, and wherein the radio receiver further comprises a digital automatic gain control system (410) according to one of the claims 5 to 7 for control of the gain of the at least one amplifier (30, 50).

9. Radio receiver according to claim 8, wherein the radio receiver is a software- defined radio receiver.

10. Radio receiver according to claim 8 or 9, wherein radio receiver is part of modem of a device for mobile, portable, terrestrial, cable or satellite data communication, or is part of a communication device adapted for Bluetooth, Wireless LAN, WiMax, or Wibro connection links, or is part of a devices for mobile television, or is part of a device for mobile cellular communications.

11. Method for entropy based detection of overloading of an analog-to-digital converter outputting a single-bit output bit-stream, wherein the method comprises:

(SlOO) receiving and temporally storing a symbol from the single-bit stream,

(S200) comparing the symbol with the preceding symbol of the bit-stream,

(S300) determining, if the symbol and the preceding symbol are identical, and

(S400) upon determination that the symbol and the preceding symbol are identical increasing a counter value representing the run- length of consecutive identical symbols,

(S500) upon determination that the symbol and the preceding symbol are not identical resetting the counter value to zero.

12. Method for entropy based automatic gain control of the gain of at least one amplifier in the front end of a radio receiver, wherein the method comprises detecting, by the method according to claim 11, overloading of an analog-to-digital converter located after the analog front end of the radio receiver and configured for outputting a single-bit output bit-stream, and wherein the method further comprises

- comparing the detector output with upper and lower trigger values and generating up- or down-stepping pulse, respectively, when the detector output passes a respective trigger value, and - controlling the gain based on the up- and down-stepping pulses by producing a gain control signal for increasing the gain, when the detector output is below the lower trigger value, and by produce a gain control signal for decreasing the gain, when the detector output is above the upper trigger value.