WO2009038324A2

WO2009038324A2 - Porous pattern semiconductor structure and semiconductor device and manufacturing method thereof

Info

Publication number: WO2009038324A2
Application number: PCT/KR2008/005464
Authority: WO
Inventors: Yong Hoon Cho
Original assignee: Korea Advanced Institute of Science and Technology KAIST; Chungbuk National Univiversity CBNU
Current assignee: Korea Advanced Institute of Science and Technology KAIST; Chungbuk National Univiversity CBNU
Priority date: 2007-09-18
Filing date: 2008-09-17
Publication date: 2009-03-26
Anticipated expiration: 2010-03-18
Also published as: WO2009038324A3

Abstract

A semiconductor structure, device, and method of manufacturing the same are provided. The manufacturing method includes etching a substrate or the surface of a semiconductor layer formed on the substrate using a wet chemical etching method or a wet photoelectrochemical etching method to form a porous structure, and re-forming a desired semiconductor layer on the porous structure, so that reduced defect density of the re-formed semiconductor layer enables the porous structure to have improved performance and characteristics. Also, the method includes forming a porous structure on a semiconductor emission layer to increase light extraction efficiency of the semiconductor emission layer, and combining a fluorescent or light-emitting material with an internal or peripheral part of the formed porous structure to efficiently emit various colors of light.

Description

[DESCRIPTION] [Invention Title]

POROUS PATTERN SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [Technical Field]

<i> The present invention relates to a semiconductor structure, a semiconductor device, and a method of manufacturing the same, and more particularly, to a semiconductor structure and a semiconductor device having a porous structure in which the porous structure is formed on a substrate or on the surface of a semiconductor layer formed on the substrate and a desired semiconductor layer is formed again on the porous structure so that the reformed semiconductor layer can have reduced defect density, and the porous structure is formed on a semiconductor emission layer formed on the substrate so that light extraction efficiency can be improved, and a method of manufacturing the same. [Background Art]

<2> Generally, a nitride semiconductor formed of indium nitride (InN), gallium nitride (GaN), and aluminum nitride (AlN) has a wide bandgap in a visible-ray region, an infrared region, and an ultraviolet region. Recently, research into the nitride semiconductor has been progressing in connection with the fabrication of blue-purple lasers, optical light emitting diode (e.g., LEDs, etc.), and high-power, high-temperature electronic devices.

<3> In order to fabricate a light emitting device using the nitride semiconductor, nitride semiconductor thin film structures may be grown on a substrate. However, it may be difficult to grow GaN bulk single crystals.

<4> In order to overcome this problem, after a thin buffer layer is grown on a crystalline substrate formed of sapphire (AI2O3), silicon carbide (SiC) or silicon (Si) at a low temperature, heteroepitaxy has commonly been performed to grow a GaN-based material including gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN) and gallium aluminum indium nitride (GaAlInN) on the crystalline substrate at a high temperature of 900^°C to l,100°C using Metalorganic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE) or Hydride Vapor Phase Epitaxy (HVPE).

<5> However, when the GaN layer is formed on the substrate of another material using the conventional method, different lattice constants and thermal expansion coefficients of the substrate and the grown material can cause the grown LED to have a high-density defect structure such as dislocations.

<6> Further, an oxide semiconductor formed of zinc oxide (ZnO), magnesium oxide (MgO) or cadmium oxide (CdO) has the same wide bandgap as the nitride semiconductor, and thus has been widely studied in connection with fabricating a light emitting device in the visible-ray region and the ultraviolet region, and an electronic device. However, as with a nitride semiconductor, since a substrate of another material is mainly used, it is necessary to suppress the formation of defect structures and improve performance.

<7> In the meantime, in order to enhance luminous efficiency of an LED and improve performance of a device, external quantum efficiency given by the product of internal quantum efficiency and light extraction efficiency should be increased.

<8> In order to improve light extraction efficiency, a method of forming a pillar structure or a photonic crystalline structure such as a micro LED on an LED structure surface to reduce total reflection of light from the surface and increase light extraction towards the outside has been developed.

<9> However, since such methods require a specific process including lithography and dry etching, they may be disadvantageous in terms of time and cost .

[Disclosure] [Technical Problem]

<io> The present invention is directed to a semiconductor structure having a porous structure and a method of manufacturing the same in which a semiconductor where a porous structure is formed is used as a substrate or a buffer layer to re-grow a semiconductor single- or multi-layer structure, so that defect density and strain in the re-grown semiconductor single- or multi-layer structure are efficiently reduced.

<ii> The present invention is also directed to a semiconductor device having a porous structure and a method of manufacturing the same in which a porous structure is formed on the top surface of a semiconductor emission layer such as a light emitting diode (LED) to increase light extraction efficiency of the emission layer, and a fluorescent or light-emitting material is combined with an internal or peripheral part of the porous structure formed on the top surface, so that various colors of light are efficiently emitted or a thin metal layer or a metal particle is combined with an internal or peripheral part of the porous structure to efficiently amplify a luminous signal. [Technical Solution]

<12> A first aspect of the present invention provides a semiconductor structure having a porous structure including: a substrate having a porous structure on its top surface; and a semiconductor layer formed on the substrate and formed of at least a single layer.

<i3> A second aspect of the present invention provides a semiconductor device having a porous structure including: a substrate; a first semiconductor layer formed on the substrate, having a porous structure and formed of at least a single layer; and a second semiconductor layer formed on the first semiconductor layer and formed of at least a single layer.

<14> The substrate may be formed of one material selected from the group consisting of sapphire (AI2O3), silicon carbide (SiC), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon (Si), germanium (Ge), gallium arsenic (GaAs), indium phosphorus (InP) and indium arsenic (InAs).

<15> The semiconductor layer, and the first and second semiconductor layers may be formed of one selected from the group consisting of GaN, InN, AlN and an alloy thereof. <i6> The semiconductor layer and the first and second semiconductor layers may be formed of one selected from the group consisting of zinc oxide (ZnO), magnesium oxide (MgO), cadmium oxide (CdO) and an alloy thereof.

<17> A porous structure may be formed on the top surface of the semiconductor layer or the second semiconductor layer.

<i8> The porous structure may be formed by a wet chemical etching method or a wet photoelectrochemical etching method.

<19> A third aspect of the present invention provides a semiconductor device having a porous structure including: a substrate; and an emission layer formed on the substrate and having a porous structure on the top surface.

<20> A fluorescent or light-emitting material, a metal layer formed to a predetermined thickness, or a metal particle may be formed in an inner part or peripheral part of the porous structure.

<2i> A metal layer formed to a predetermined thickness or a metal particle in addition to a fluorescent or light-emitting material may be combined with the inner or peripheral part of the porous structure.

<22> The emission layer may be formed to have a light emitting diode (LED) structure.

<23> A fourth aspect of the present invention provides a method of manufacturing a semiconductor structure having a porous structure, including: forming a porous structure on the top surface of a substrate; and forming a semiconductor layer formed of at least a single layer on the substrate.

<24> A fifth aspect of the present invention provides a method of manufacturing a semiconductor structure having a porous structure, including: forming a first semiconductor layer formed of at least a single layer on a substrate; forming a porous structure on the top surface of the first semiconductor layer; and forming a second semiconductor layer formed of at least a single layer on the first semiconductor layer.

<25> The semiconductor layer and the first and second semiconductor layers may be formed of one selected from the group consisting of gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN) and an alloy thereof. <26> The semiconductor layer and the first and second semiconductor layers may be formed of ZnO, MgO, CdO, or an alloy thereof. <27> The semiconductor layer and the first and second semiconductor layers may be formed using one of a Metalorganic Chemical Vapor Deposition (MOCVD) method, a Molecular Beam Epitaxy (MBE) method and a Hydride Vapor Phase

Epitaxy (HVPE) method. <28> Forming a porous structure on the top surface of the semiconductor layer or the second semiconductor layer may be further included. <29> The porous structure may be formed by a wet chemical etching method or a wet photoelectrochemical etching method. <30> The wet chemical etching method may be performed using a H₃PO₄ solution, a mixture solution of H3PO4 and H2SO4, or a potassium hydroxide (KOH) solution.

<3i> The wet photoelectrochemical etching method may be performed using a H₃PO₄ solution, a mixture solution of H₃PO₄ and H₂SO₄, or a potassium hydroxide

(KOH) solution, and irradiation by light. <32> A sixth aspect of the present invention provides a method of manufacturing a semiconductor device having a porous structure, including: forming an emission layer on a substrate! and forming a porous structure on the top surface of the emission layer. <33> The porous structure may be formed by a wet chemical etching method or a wet photoelectrochemical etching method. <34> The wet chemical etching method may be performed using a H₃PO₄ solution, a mixture solution of H₃PO₄ and H2SO4, or a potassium hydroxide (KOH) solution.

<35> The wet photoelectrochemical etching method may be performed using a H₃PO₄ solution, a mixture solution of H₃PO₄ and H2SO4, or a potassium hydroxide

(KOH) solution, and irradiation by light. <36> Forming a fluorescent or light-emitting material, a metal layer formed to a predetermined thickness, or a metal particle in an internal or peripheral part of the porous structure may be further included.

<37> Combining a fluorescent or light-emitting material, a metal layer formed to a predetermined thickness, or a metal particle with an internal or peripheral part of the porous structure to be formed may be further included.

<38> The porous structure may be formed such that its density and size vary according to etch temperature and time. [Advantageous Effects]

<39> As described above, since a semiconductor structure having a porous structure according to an exemplary embodiment of the present invention uses a wet chemical etching method or a wet photoelectrochemical etching method, the process of forming the porous structure can be simplified. Further, the formed porous structure is used as a new substrate or a buffer layer to re- grow a desired semiconductor structure on its top surface such that characteristics and performance of a semiconductor device can be enhanced.

<40> Moreover, according to the present invention, since characteristics of a nitride semiconductor itself are used without a separate, complicated process, e.g., a conventional lithography or dry etching process, a surface structure can be easily changed using a wet chemical etching method or a wet photoelectrochemical etching method within a short amount of time at low cost. As a result, differences in lattice constant and a defect structure caused by a thermal expansion coefficient between semiconductor thin films formed on a substrate, and remaining stress, can be effectively reduced.

<4i> Furthermore, according to the present invention, a porous structure is formed on the top surface of a semiconductor emission layer formed on the substrate, so that light extraction efficiency of a semiconductor light- emitting material can be increased. Also, a fluorescent or light-emitting material is combined with an internal or peripheral part of the porous structure formed on the top surface of the emission layer, so that various colors of light can be emitted. Alternatively, a thin metal layer or a metal particle may be combined with an internal or peripheral part of the porous structure, so that a luminous signal can be amplified.

[Description of Drawings] <42> FIG. 1 is a cross-sectional view of a semiconductor structure having a porous structure according to a first example embodiment of the present invention. <43> FIG. 2 is a cross-sectional view of a semiconductor structure having a porous structure according to a second exemplary embodiment of the present invention. <44> FIG. 3 is a cross-sectional view of an example of a semiconductor device having a porous structure according to a third exemplary embodiment of the present invention. <45> FIG. 4 is a cross-sectional view of another example of a semiconductor device having a porous structure according to the third exemplary embodiment of the present invention. <46> FIG. 5 is Scanning Electron Microscope (SEM) images illustrating a porous structure on a GaN surface according to etch time using a wet chemical etching method that is applied to exemplary embodiments of the present invention. <47> FIG. 6 is a graph illustrating a change in room-temperature photoluminescence spectra of the ρ-tyρe GaN porous structure that is manufactured by increasing etch time as described in FIG. 5. <48> FIG. 7 is cross-sectional views and light field microscope images for comparing the presence of the porous structure applied to the second exemplary embodiment of the present invention according to the method of FIG.

5. <49> FIG. 8 is a cross-sectional view schematically illustrating the structure of a semiconductor layer for re-growth formed on the two prepared samples of FIG.7. <50> FIG. 9 is a graph illustrating a change in PL spectra versus temperatures of the two samples (Sample A and Sample B) re-grown in FIG.8. <5i> FIG. 10 is a graph illustrating a change in PL spectra of Sample A and Sample B of FIG. 8 measured at 1OR versus power of excitation laser beams.

<52> FIG. 11 is a graph illustrating PL for Sample A and Sample B measured with excitation by a Xe lamp at 1OK, and PL excitation spectra.

<53> FIG. 12 is Transmission Electron Microscope (TEM) images for confirming defect structures of Sample A and Sample B shown in FIG.8.

<54> FIG. 13 is a graph illustrating X-ray diffraction results measured at surfaces (002) and (004) of Sample A and Sample B shown in FIG.8.

<55> FIG. 14 is a graph illustrating X-ray Reciprocal Space Mapping (RSM) results measured at a surface (105) of Sample A and Sample B of FIG.8.

<56> FIG. 15 is a graph illustrating results in which reverse bias current (I)-voltage (V) characteristic curves of LED structures manufactured using Sample A and Sample B are compared.

<57> FIG. 16 is a graph illustrating results in which forward bias I-V characteristic curves of LED structures manufactured using Sample A and Sample B are compared.

<58> FIGS. 17 to 19 show confocal fluorescence and transmission images and PL spectra representing luminous characteristics of a CdSe quantum dot attached to an internal or peripheral part of the porous structure formed on the top surface of the GaN-based semiconductor structure according to the third exemplary embodiment of the present invention.

<59> FIG. 20 is a graph illustrating PL spectra in which porous structures are formed on the GaN-based semiconductor structure manufactured in FIGS. 17 to 19 according to various etch times, and luminous characteristics are compared depending on whether CdSe quantum dots are attached to the porous structures or not . [Mode for Invention]

<60> Hereinafter, example embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the example embodiments disclosed below but can be implemented in various forms. The example embodiments are described to enable those of ordinary skill in the art to which the invention pertains to embody and practice the invention.

<61>

<62> First Exemplary Embodiment

<63> FIG. 1 is a cross-sectional view of a semiconductor structure having a porous structure according to a first example embodiment of the present invention.

<64> Referring to FIG. 1, the semiconductor structure having a porous structure according to the first example embodiment includes a substrate 100 having a porous structure P on a top surface, and a semiconductor layer 110 formed on the substrate 100 and formed of at least a single layer.

<65> Here, the substrate 100 is not limited to a specific substrate, and any substrate suitable for use as a semiconductor substrate may be used. For example, the substrate may be formed of a material selected from the group consisting of sapphire (Al₂O₃), silicon carbide (SiC), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon (Si), germanium (Ge), gallium arsenic (GaAs), indium phosphorus (InP) and indium arsenic (InAs).

<66> Also, the semiconductor layer 110 may be implemented as a nitride semiconductor formed of a material selected from the group consisting of GaN, InN, AlN and an alloy thereof.

<67> In addition, the semiconductor layer 110 may be implemented as a nitride semiconductor formed of a material selected from the group consisting of ZnO, magnesium oxide (MgO), cadmium oxide (CdO) and an alloy thereof.

<68> The semiconductor layer 110 may be formed by Metalorganic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or Hydride Vapor Phase Epitaxy (HVPE).

<69> Meanwhile, the porous structure P formed on the substrate 100 may be formed by a wet chemical etching method or a wet photoelectrochemical etching method to be described in the following process. The density and size of the porous structure P may be varied depending on etch temperature and time.

<70> Additionally, while it is not illustrated in the drawing, a porous structure P may be further formed on the top surface of the semiconductor layer 110. <7i> A method of manufacturing the semiconductor structure having a porous structure according to the first exemplary embodiment will be described be1ow. <72> First, after a substrate 100 for growth having a predetermined size is prepared, a porous structure P is formed on the top surface of the prepared substrate 100 using a wet chemical etching method or a wet photoelectrochemical etching method. <73> Here, the wet chemical etching method or the wet photoelectrochemical etching method has been used to easily and optically observe a defect structure such as dislocations, the density of which is high in a nitride semiconductor. This is because a wet etching solution has selectively high etching efficiency around the defect structure. <74> In the wet chemical etching method, e.g., a high-temperature phosphoric acid (H3PO4) solution, a mixture solution of phosphoric acid (H3PO4) and sulfuric acid (H2SO4), or a potassium hydroxide (KOH) solution is used to form an etch pit in defects of the nitride semiconductor.

<75> Further, the wet photoelectrochemical etching method may include using a solution used in the above-described wet chemical etching method, e.g., a high-temperature phosphoric acid (H3PO4) solution, a mixture solution of phosphoric acid (H3PO4) and sulfuric acid (H2SO4) or a potassium hydroxide

(KOH) solution, and at the same time, irradiation by light. For example, the wet photoelectrochemical etching method performed on the nitride-based semiconductor may include radiating ultraviolet light into the potassium hydroxide (KOH) solution.

<76> The porous structure P may be formed around the defect structure using the wet chemical etching method or the wet photoelectrochemical etching method applied to the present invention, and the porous structure is formed to be used as a new substrate or a buffer layer for obtaining a high-quality semiconductor layer structure in which defect structures are reduced, rather than to observe the defect structures.

<w> The porous structure P is mainly formed by the defect structure, and thus the re-growth of the porous structure P is shown just above or around the defect structure. Accordingly, the conventional defect structure may be modified or its density may be significantly reduced. Furthermore, since the formation of the porous structure P results in reduced strain on the substrate disposed below the structure, the porous structure P may function as a new substrate or a buffer layer having advantages in terms of growth of a semiconductor device.

<78> Afterwards, a semiconductor layer 110 formed of at least a single layer may be formed on the substrate 100 where the porous structure P is formed, so that the semiconductor structure having a porous structure according to the first exemplary embodiment of the present invention is formed.

<79> Here, the semiconductor layer 110 may be formed by one of a MOCVD method, a MBE method and a HVPE method.

<80> Additionally, while it is not illustrated in the drawing, a porous structure P may be further formed on the top surface of the semiconductor layer 110 using the above-described method.

<81>

<82> Second Exemplary Embodiment

<83> FIG. 2 is a cross-sectional view of a semiconductor structure having a porous structure according to a second exemplary embodiment of the present invention.

<84> Referring to FIG. 2, the semiconductor structure having a porous structure according to the second exemplary embodiment of the present invention includes a substrate 200, a first semiconductor layer 210 formed on the substrate 200, having porous structures P on its top surface, and formed of at least a single layer, and a second semiconductor layer 220 formed on the first semiconductor layer 210 and formed of at least a single layer.

<85> Here, since structures and a method of forming of the substrate 200, the first semiconductor layer 210 and the second semiconductor layer 220 are the same as those of the substrate 100 and the semiconductor layer 110 of the above-described first exemplary embodiment of the present invention, a detailed description thereof will not be repeated.

<86> In the meantime, while the porous structure P is directly formed on the top surface of the substrate (100 of FIG. 1) in the above-mentioned first exemplary embodiment of the present invention, in the second exemplary embodiment of the present invention, after the first semiconductor layer 210 is grown on the top surface of the substrate 200, the porous structure P is formed on the top surface of the first semiconductor layer 210.

<87> A method of forming the semiconductor thin film having a porous structure according to the second exemplary embodiment of the present invention will be described below.

<88> First, after the substrate 200 for growth having a predetermined size is prepared, the first semiconductor layer 210 formed of at least a single layer is formed on the prepared substrate 200.

<89> Here, the first semiconductor layer 210 may be formed by a selected one of a MOCVD method, a MBE method, and a HVPE method.

<90> Afterwards, the porous structures P are formed on the top surface of the first semiconductor layer 210 using the wet chemical or photoelectrochemical etching method. Since the wet chemical and photoelectrochemical etching methods are the same as described in the first exemplary embodiment of the present invention, a detailed description thereof will not be repeated.

<9i> Finally, the second semiconductor layer 220 formed of at least a single layer is formed on the first semiconductor layer 210, thus completing the semiconductor structure having a porous structure according to the second exemplary embodiment of the present invention.

<92> Here, the second semiconductor layer 220 may be formed using the same method as the first semiconductor layer 210, i.e., a selected one of the MOCVD method, the MBE method and the HVPE method. <93>

<94> Third Exemplary Embodiment

<95> FIG. 3 is a cross-sectional view of an example of a semiconductor device having a porous structure according to a third exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of another example of a semiconductor device having a porous structure according to the third exemplary embodiment of the present invention.

<96> Referring to FIGS. 3 and 4, the semiconductor device having a porous structure according to a third exemplary embodiment of the present invention includes a substrate 300, and an emission layer 310 formed on the substrate 300 and having a porous structure P on its top surface.

<97> Here, since the substrate 300 and the porous structure P are the same as described in the first exemplary embodiment of the present invention, a detailed description thereof will not be repeated.

<98> Further, the emission layer 310 may be formed to have a semiconductor emitting device structure, e.g., a light emitting diode (LED) structure.

<99> As described above, the porous structure P formed on the top surface of the emission layer 310 that is grown in order to improve light extraction efficiency has various angles on the surface of the emission layer 310, and a degree of total reflection that is generated on the surface of the emission layer 310 may be reduced. As a result, the porous structure contributes to an increase in the amount of light outwardly emitted from a sample. <ioo> In the meantime, as illustrated in FIG. 4, a fluorescent or light- emitting material 400 is combined with an internal or peripheral part of the porous structure P formed on the top surface of the emission layer 310, so that light extraction efficiency is increased, and at the same time, various colors of light are emitted. Furthermore, the fluorescent or light-emitting material 400 may be implemented to re-absorb light generated from the emission layer 310 formed in a semiconductor light emitting structure or to receive energy by means of a resonance energy transfer method to emit light again. <ioi> Here, the fluorescent or light-emitting material 400 may be formed of organic and inorganic semiconductors, colloidal quantum dots or organic and inorganic fluorescent materials.

<iO2> Meanwhile, while it is not illustrated, the internal or peripheral part of the porous structure P formed on the top surface of the emission layer 310 formed in a semiconductor light emitting structure may be combined with a thin metal layer or a metal particle structure. Accordingly, the thin metal layer or the metal particle structure generated from the emission layer 310 receives energy by means of absorption, diffusion, amplification (e.g., the Surface Plasmon Resonance method), etc. to efficiently amplify a luminous signal.

<i03> Moreover, the thin metal layer or the metal particle structure may also be combined with the internal or peripheral part of the porous structure P formed on the top surface of the emission layer 310 formed in a semiconductor light emitting structure, so that energy from light generated in the emission layer 310 can be effectively transferred to the fluorescent or light-emitting material 400 to amplify a luminous signal.

<iO4> A method of manufacturing a semiconductor device having a porous structure according to the third exemplary embodiment will be described below.

<iO5> First, after a substrate 300 for growth having a predetermined size is prepared, an emission layer 310 formed in a semiconductor light emitting device structure (e.g., LED, etc.) is formed on the top surface of the prepared substrate 300.

<iO6> Afterwards, a porous structure P is formed on the top surface of the emission layer 310 using a wet chemical or photoelectrochemical etching method to complete formation of the semiconductor device according to the third exemplary embodiment of the present invention.

<iO7> Here, since the wet chemical or photoelectrochemical etching method is the same as described in the first exemplary embodiment, a detailed description thereof will not be repeated. <i08> Meanwhile, a fluorescent or light-emitting material 400, or a thin metal layer or a metal particle structure (not shown), may be further combined with an internal or peripheral part of the porous structure P formed on the top surface of the emission layer 310 to form the semiconductor device.

<iO9> It is obviously possible to combine both the fluorescent or light- emitting material 400 and the thin metal layer or the metal particle structure to form the semiconductor device.

<110>

<iii> Experimental Example

<ii2> FIG. 5 is Scanning Electron Microscope (SEM) images illustrating a porous structure on a GaN surface according to etch time using a wet chemical etching method that is applied to exemplary embodiments of the present invention.

<ii3> Referring to FIG. 5, it is confirmed that in the wet chemical etching method, when a GaN layer formed to a thickness of about 2μm is immersed in a hot phosphoric acid (H₃PO₄) solution at a temperature of about 150~160^°C , and etch time is increased to 90 minutes, 120 minutes and 180 minutes, a change in the porous structure on the GaN surface is shown as (a), (b) and (c), respectively.

<ii4> Hexagonal etch pits can be seen in the SEM images. Similar results were obtained with respect to undoped GaN, n-type GaN, p-type GaN layer, and InGaN LED structures. The density and size of the porous structure may be varied according to etch temperature and time.

<ii5> FIG. 6 is a graph illustrating a change in room-temperature photoluminescence spectra of the p-type GaN porous structure that is manufactured by increasing etch time as described in FIG. 5. From the graph, it is observed that as the etching progresses, the thickness of the p-type GaN layer is reduced, and accordingly, the intensity of the PL spectra is reduced.

<116> FIG. 7 is cross-sectional views and light field microscope images for comparing the presence of the porous structure applied to the second exemplary embodiment of the present invention according to the method of FIG. 5. FIG. 7-(a) illustrates a case where a porous structure is not formed on a GaN layer grown on a sapphire substrate, and FIG. 7-(b) illustrates a case where a porous structure is formed according to the method of FIG. 5. The case when a porous structure is formed (FIG. 7-(a)) and the case when a porous structure is not formed (FIG. 7-(b)) are regarded as a new substrate or a new buffer layer for the comparison of performance and characteristics, and the next re-growth process is performed.

<ii7> FIG. 8 is a cross-sectional view schematically illustrating the structure of a semiconductor layer for re-growth formed on each of the two prepared samples of FIG. 7. FIG. 8 illustrates an LED structure having a quantum well structure of a nitride semiconductor having InGaN for re-growth as an active layer on the samples where the porous structure is not formed (refer to FIG.7-(a)) and where it is formed (refer to FIG.7-(b)).

<ii8> That is, in order to compare performance and characteristics, the two new substrates or buffer layers excluding the presence of the porous structure are put into a Metal Organic Chemical Vapor Deposition (MOCVD) growth device, and the structures of FIG. 8 are simultaneously grown to manufacture two samples (Sample A and Sample B).

<ii9> FIG. 9 is a graph illustrating a change in PL spectra versus temperatures of the two samples (Sample A and Sample B) re-grown in FIG. 8, FIG. 10 is a graph illustrating a change in PL spectra of Sample A and Sample B of FIG. 8 measured at 1OK versus power of excitation laser beams, and FIG. 11 is a graph illustrating PL for Sample A and Sample B measured with excitation by a Xe lamp at 1OK and PL excitation spectra.

<12O> Referring to FIGS. 9 to 11, a change in InGaN PL peak energy caused by changed strain is observed in Sample B, which is re-grown when the porous structure is formed, and an energy difference between PL energy and an absorption edge of PL excitation with respect to the InGaN PL peak enables Sample B to have a larger Stokes-Like Shift than Sample A. <i2i> FIG. 12 is Transmission Electron Microscope (TEM) images for confirming defect structures of Sample A and Sample B of FIG. 8, and it is observed that dislocation density of Sample B is significantly reduced compared to Sample A.

<i22> FIG. 13 is a graph illustrating X-ray diffraction results measured at surfaces (002) and (004) of Sample A and Sample B of FIG. 8, respectively, and FIG. 14 is a graph illustrating X-ray Reciprocal Space Mapping (RSM) results measured at a surface (105) of Sample A and Sample B of FIG.8.

<123> Referring to FIGS. 13 and 14, it is observed that interfaces of re- grown structures are formed well and coherent strain is formed in Sample B.

<124> FIG. 15 is a graph illustrating results in which reverse bias current (I)-voltage (V) characteristic curves of LED structures manufactured using Sample A and Sample B are compared, and FIG. 16 is a graph illustrating results in which forward bias I-V characteristic curves of LED structures manufactured using Sample A and Sample B are compared.

<125> Referring to FIGS. 15 and 16, results of analyzing two chips are shown, and Sample A corresponds to Al and A2, and Sample B corresponds to Bl and B2.

<126> It is interesting to observe that Sample B shows significantly reduced leakage current in reverse bias I-V characteristics, and also reduced turn-on voltage in forward bias I-V characteristics.

<127> The results are shown by improved structural characteristics including reduced defect density, and the improved structural characteristics cause electrical characteristics to be improved, so that characteristics and performance of a device are enhanced.

<128> FIGS. 17 to 19 show confocal fluorescence and transmission images and PL spectra representing luminous characteristics of a CdSe quantum dot attached to an internal or peripheral part of the porous structure formed on the top surface of the GaN-based semiconductor structure according to the third exemplary embodiment of the present invention.

<129> Referring to FIGS. 17 and 19, the CdSe quantum dots are attached using a spin coating method, and it is observed that the CdSe quantum dots are well distributed around the internal and peripheral part of the hexagonal porous etch pit .

<i30> Meanwhile, since internal surfaces of the hexagonal porous etch pit have different angles from other planar surface areas, emission of light from inside is facilitated. Accordingly, it is anticipated that fluorescent or light-emitting materials attached around the surfaces may have higher photoexcitation efficiency.

<i3i> Therefore, the fluorescent or light-emitting materials are combined with the internal or peripheral part of the porous structure formed on the LED structure, so that a multi-wavelength or a white light source having improved energy transfer efficiency can be developed.

<132> FIG. 20 is a graph illustrating PL spectra in which porous structures are formed on the GaN-based semiconductor structure manufactured in FIGS. 17 to 19 according to various etch times, and luminous characteristics are compared depending on whether CdSe quantum dots are attached to the porous structures or not. In the graph, the porous structures are formed according to various etch times (90 minutes, 120 minutes and 180 minutes), and PL spectra in which luminous characteristics according to whether CdSe quantum dots having an emission wavelength of about 600nm are attached to the porous structures or not are illustrated.

<133> Referring to FIG. 20, when the CdSe quantum dots are attached, a wavelength of about 450nm from the GaN-based semiconductor structure and a wavelength of 600 run from the CdSe quantum dot are both observed.

<134> The above method enables various methods to be combined, e.g. , a blue light LED may be used together with yellow light quantum dots, a blue light LED may be used together with red and yellow light quantum dots, or an ultraviolet ray LED may be used together with red, green and blue light quantum dots. Further, besides the quantum dots, the conventional fluorescent material and new light-emitting materials may be used.

<i35> While the invention has been shown and described with reference to example embodiments of a semiconductor structure and device having a porous structure and a method of manufacturing the same, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

[CLAIMS] [Claim 1]

A semiconductor structure having a porous structure, comprising: a substrate having a porous structure on its top surface; and a semiconductor layer formed on the substrate and formed of at least a single layer.

[Claim 2]

A semiconductor structure having a porous structure, comprising: a substrate! a first semiconductor layer formed on the substrate, having a porous structure and formed of at least a single layer; and a second semiconductor layer formed on the first semiconductor layer and formed of at least a single layer.

[Claim 3]

The semiconductor structure of claim 1 or 2, wherein the substrate is formed of one material selected from the group consisting of sapphire (Al₂O₃), silicon carbide (SiC), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon (Si), germanium (Ge), gallium arsenic (GaAs), indium phosphorus (InP) and indium arsenic (InAs).

[Claim 4]

The semiconductor structure of claim 1 or 2, wherein the semiconductor layer and the first and second semiconductor layers are formed of one selected from the group consisting of GaN, InN, AlN, and an alloy thereof.

[Claim 5]

The semiconductor structure of claim 1 or 2, wherein the semiconductor layer and the first and second semiconductor layers are formed of one selected from the group consisting of zinc oxide (ZnO), magnesium oxide (MgO), cadmium oxide (CdO), and an alloy thereof.

[Claim 6]

The semiconductor structure of claim 1 or 2, further comprising a porous structure formed on the top surface of the semiconductor layer or the second semiconductor layer.

[Claim 7]

The semiconductor structure of claim 1 or 2, wherein the porous structure is formed by a wet chemical etching method or a wet photoelectrochemical etching method.

[Claim 8]

A semiconductor device having a porous structure, comprising: a substrate; and an emission layer formed on the substrate and having a porous structure on the top surface.

[Claim 9]

The semiconductor device of claim 8, wherein the substrate is formed of one selected from the group consisting of sapphire (Al₂O₃), silicon carbide

(SiC), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon (Si), germanium (Ge), gallium arsenic (GaAs), indium phosphorus (InP) and indium arsenic (InAs).

[Claim 10]

The semiconductor device of claim 8, wherein the porous structure is formed by a wet chemical etching method or a wet photoelectrochemical etching method.

[Claim 11]

The semiconductor device of claim 8, further comprising a fluorescent or light-emitting material, a metal layer formed to a predetermined thickness, or a metal particle formed in an inner part or peripheral part of the porous structure.

[Claim 12]

The semiconductor device of claim 8, further comprising a metal layer formed to a predetermined thickness or a metal particle in addition to a fluorescent or light-emitting material combined with the inner or peripheral part of the porous structure.

[Claim 13] The semiconductor device of claim 8, wherein the emission layer is formed to have a light emitting diode (LED) structure.

[Claim 14]

A method of manufacturing a semiconductor structure having a porous structure, comprising: forming a porous structure on the top surface of a substrate; and forming a semiconductor layer formed of at least a single layer on the substrate.

[Claim 15]

A method of manufacturing a semiconductor structure having a porous structure, comprising: forming a first semiconductor layer formed of at least a single layer on a substrate; forming a porous structure on the top surface of the first semiconductor layer", and forming a second semiconductor layer formed of at least a single layer on the first semiconductor layer.

[Claim 16]

The method of claim 14 or 15, wherein the semiconductor layer and the first and second semiconductor layers are formed of one selected from the group consisting of gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and an alloy thereof.

[Claim 17]

The method of claim 14 or 15, wherein the semiconductor layer and the first and second semiconductor layers are formed of ZnO, MgO, CdO, or an alloy thereof.

[Claim 18]

The method of claim 14 or 15, wherein the semiconductor layer and the first and second semiconductor layers are formed using one of a Metalorganic Chemical Vapor Deposition (MOCVD) method, a Molecular Beam Epitaxy (MBE) method, and a Hydride Vapor Phase Epitaxy (HVPE) method.

[Claim 19]

The method of claim 14 or 15, further comprising forming a porous structure on the top surface of the semiconductor layer or the second semiconductor layer.

[Claim 20]

The method of claim 14 or 15, wherein the porous structure is formed by a wet chemical etching method or a wet photoelectrochemical etching method.

[Claim 21]

The method of claim 20, wherein the wet chemical etching method is performed using a H3PO4 solution, a mixture solution of H3PO4 and H2SO4, or a potassium hydroxide (KOH) solution.

[Claim 22]

The method of claim 20, wherein the wet photoelectrochemical etching method is performed using a H3PO4 solution, a mixture solution of H3PO4 and

H₂SO₄, or a potassium hydroxide (KOH) solution, and irradiation by light.

[Claim 23]

A method of manufacturing a semiconductor device having a porous structure, comprising: forming an emission layer on a substrate; and forming a porous structure on the top surface of the emission layer.

[Claim 24]

The method of claim 23, wherein the porous structure is formed by a wet chemical etching method or a wet photoelectrochemical etching method.

[Claim 25]

The method of claim 24, wherein the wet chemical etching method is performed using a H3PO4 solution, a mixture solution of H3PO4 and H2SO4, or a

KOH solution.

[Claim 26]

The method of claim 24, wherein the wet photoelectrochemical etching method is performed using a H3PO4 solution, a mixture solution of H3PO4 and H2SO4, or a KOH solution, and irradiation by light.

[Claim 27]

The method of claim 23, further comprising forming a fluorescent or light-emitting material, a metal layer formed to a predetermined thickness, or a metal particle in an internal or peripheral part of the porous structure. [Claim 28]

The method of claim 23, further comprising combining a fluorescent or light-emitting material, a metal layer formed to a predetermined thickness, or a metal particle with an internal or peripheral part of the porous structure. [Claim 29]

The method of any one of claims 14, 15 and 23, wherein the porous structure is formed such that its density and size vary according to etch temperature and time.