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WO2009034494A1 - Circuit de type à réseau de résistances réglables d'un convertisseur numérique-analogique non récursif (firdac) quotientométrique semi-numérique - Google Patents

Circuit de type à réseau de résistances réglables d'un convertisseur numérique-analogique non récursif (firdac) quotientométrique semi-numérique Download PDF

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Publication number
WO2009034494A1
WO2009034494A1 PCT/IB2008/053425 IB2008053425W WO2009034494A1 WO 2009034494 A1 WO2009034494 A1 WO 2009034494A1 IB 2008053425 W IB2008053425 W IB 2008053425W WO 2009034494 A1 WO2009034494 A1 WO 2009034494A1
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digital
fir
output
voltage
impulse response
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Inventor
Mike Hendrikus Splithof
Edwin Schapendonk
Winand Georgius Van Sloten
Jacobus Adrianus Van Oevelen
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NXP BV
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NXP BV
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
    • H03M3/504—Details of the final digital/analogue conversion following the digital delta-sigma modulation the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC

Definitions

  • the present invention refers to an adjustable-resistor array type circuit of a semi-digital ratiometric finite impulse response digital-to-analog converter (FIRDAC).
  • FIRDAC semi-digital ratiometric finite impulse response digital-to-analog converter
  • the proposed FIRDAC provides an output voltage having an accurate and linear relation to the circuit's supply voltage. This is accomplished by using a linear adaptive finite impulse response (FIR) filter whose weighting coefficients are implemented by means of an array of adjustable ohmic resistors.
  • FIR linear adaptive finite impulse response
  • the accuracy of conversion can easily be enhanced by additionally applying dynamic element matching techniques. This is less complicated than in conventional FIRDACs known from the prior art, which are based on a weighted current approach.
  • the present invention proposes a semi-digital circuit implementation which enables the use of low-voltage transistors in an adjustable-resistor array type FIRDAC whose supply voltage is allowed to exceed the breakdown voltage of integrated low- voltage transistors which are used for switching said ohmic resistors, which will result in a smaller chip size.
  • Another aspect of the present invention is directed to the circuit design of a FIRDAC which employs an array of dummy resistors whose resistance values are chosen such that the FIRDAC circuit's supply current is independent of the digital data stream to be converted to the analog domain. In this way, the analog output voltage of the FIRDAC circuit is less sensitive to a varying series impedance in its supply leads.
  • Digital-to-analog conversion thereby stands for a process in which digital words are applied to the input port of a digital-to-analog converter (DAC), the latter being required for scaling a given reference voltage V REF in such a way that the obtained result yields an analog output voltage V out which consti- tutes an analog representation of the respective digital word.
  • DAC digital-to-analog converter
  • the number of input combinations represented by the input word D is thus given by 2 M . From equation (Ia) it follows that the maximum value of a DACs output voltage V out is limited by the value of reference voltage V REF - For an M-bit input word D, fraction K can be determined by calculating
  • analog output voltage V out can be expressed as
  • V out K ⁇ D ⁇ (Ic, d)
  • D/A converters typically operate by a resistor, capacitor divider, or current steering method to convert digital-to-analog signals or, operate using a sigma-delta conversion method.
  • the basic architecture of a DAC comprises a voltage reference, which can be supplied externally, binary switches, a scaling network, and an output amplifier.
  • the voltage reference, binary switches, and scaling network convert the digital word as either a voltage or current signal, and the output amplifier converts this signal to a voltage signal that can be sampled without affecting the value of conversion.
  • Sigma-delta D/A converters are often preferred because of their inherent feasibility to be manufactured as integrated circuits in standard digital integrated circuit processes.
  • D/A converters utilize oversampled digital data output from an interpolation circuit, which is then converted by DAC circuitry into an analog output.
  • Sigma-delta D/A converters inherently introduce noise outside the passband of the D/A converter circuit. To alleviate this out-of-band noise, various filtering techniques are employed.
  • Oversampled D/A converters generally include the following signal processing blocks: (1) an interpolator filter, or series of filters, which raises the sample rate of the incoming digital signal to a higher sample rate, (2) a digital sigma-delta processor (or noise shaper) which lowers the number of bits representing the signal by shaping the quantization noise in a way that places most of it at higher frequencies, (3) a D/A converter which converts the output of the noise shaper into an analog signal, and (4) an analog low pass filter which removes, or substantially lowers, the noise that was placed at higher frequencies by the noise shaper.
  • an interpolator filter or series of filters, which raises the sample rate of the incoming digital signal to a higher sample rate
  • a digital sigma-delta processor or noise shaper
  • an analog low pass filter which removes, or substantially lowers, the noise that was placed at higher frequencies by the noise shaper.
  • the output currents of each current source may be adjustable such that a desired FIR filter response can be achieved. These output currents are then provided, or steered, to a current summing node or to an alternative current summing node, depending on the logic state of the control bit at the delay line tap associated with each current source. The currents at one or both of the current summing nodes are then converted to a voltage by using standard current-to-voltage conversion techniques. Additional filtering may then be employed to remove high-frequency noise.
  • FIR coefficients may be represented as charges which are stored on a plurality of capacitors. The charge on each capacitor can then be summed by employing a switched capacitor summing amplifier. Once again, additional filtering may be employed to remove any extremely high frequency noise.
  • the FIR coefficients may be represented as currents flowing through an array of ohmic resistors.
  • each resistor is selectively connected to a voltage reference depending on the state of the individual control bit from the delay line tap associated with each individual resistor.
  • the current is then summed and converted to a voltage by means of a feedback resistor in the feedback line of a negative-feedback operational amplifier.
  • additional filtering may be employed to remove high-frequency noise.
  • a sigma-delta digital-to-analog converter receives oversampled input data representative of an analog signal, wherein said data may optionally be interpolated to a higher rate by means of an interpolator.
  • a noise-shaping sigma-delta modulator connected to the output port of the interpolator provides an output signal which is fed to a linear adaptive finite impulse response (FIR) filter having a frequency response characteristic that reduces shaped noise having a tendency to inter-modulate back into the DACs passband as well as aliased components.
  • FIR linear adaptive finite impulse response
  • the filter thereby uses a series of flip-flops functioning as delay elements with well- controlled timing edges.
  • the time-delayed output signals of these concatenated flip- flops are used for controlling a set of current sources whose DC output currents are weighted corresponding to the linear adaptive finite impulse response filter's coefficients.
  • the weighted DC currents supplied by these current sources are then summed and transformed into an analog output voltage.
  • the analog output voltage V out of a FIRDAC is given by a linear ratio of its supply voltage V DD - This property is often described as the output voltage V out being ratiometric to the supply voltage.
  • the filter coefficients ⁇ ak I k € ⁇ 0, 1, 2, ..., N) of the FIRDACs integrated finite impulse response filter are generated by adjustable DC output currents of a set of switchable current sources, wherein said output currents are summed at the inverting input of an output-sided inverting operational amplifier circuit and converted to an analog output voltage V out through a conversion resistor Rp (see Fig.
  • An exemplary embodiment of the present invention is therefore directed to a semi-digital FIRDAC implementation where the filter coefficients are implemented by adjustable ohmic resistors instead of switchable current sources with adjustable output currents.
  • the FIRDACs output voltage can thus be made ratio metric to its supply voltage.
  • the accuracy of conversion from supply voltage to output voltage depends on less variables than in a switched cur- rent source type FIRDAC.
  • a FIRDAC with adjustable ohmic resistors realizing said filter coefficients it is easier to apply dynamic element matching techniques to increase accuracy.
  • a problem of the ratio metric DAC according to the above-described embodiment is the fact that the FIRDACs supply voltage is of- ten much higher than the voltage tolerated by low-voltage transistors. This would imply that an inverter stage, which has to be used at every tap of the FIR filter, would have to be realized by means of high-voltage transistors, which consequently results in a large IC size.
  • adjustable ohmic resistors whose resistance values constitute the filter coefficients of the FIRDAC also leads to the advantage that is possible to avoid using high- voltage transistors in the numerous taps of the FIR filter, which hence results in a FIRDAC with a reduced chip area size.
  • the present invention is thus dedicated to a semi- digital finite impulse response digital-to-analog converter (FIRDAC) circuit which comprises a linear adaptive finite impulse response (FIR) filter including a shift register, said shift register being realized as a tapped delay line with an input port and a plurality of output taps, wherein said input port is supplied with a one-bit digital input stream and each output tap provides a time-delayed version of the one-bit digital input stream, and an output-sided operational amplifier stage comprising at least one operational amplifier in a negative-feedback configuration which provides at its output port an analog voltage representing the digital input stream.
  • FIRDAC semi- digital finite impulse response digital-to-analog converter
  • said semi-digital finite impulse response digital-to-analog converter circuit further comprises an array of selectively adjustable ohmic filter resistors, each filter resistor being respectively connected to a distinct output tap of the finite impulse response filter's shift register, wherein the resistance values of these ohmic filter resistors constitute and are being used as a set of filter coefficients for weighting a corresponding one of the digital input stream stream's time- delayed versions at the shift register's output taps having the same tap index.
  • the resistance values of the adjustable ohmic filter resistors may adap- tively be set such that the resulting analog output voltage representing an analog equivalent of the digital input stream is made ratiometric to the FIRDAC circuit's supply voltage.
  • a further exemplary embodiment of the present invention is directed to a semi-digital FIRDAC implementation where the complete finite impulse response filter is modeled by just one switchable ohmic resistor whose resistance value can be adjusted.
  • the FIRDACs linear adaptive finite impulse response filter may be realized as a single adjustable ohmic resistor serially connected to a switch which is pulsed with the clock signal of the digital input stream, wherein said switch is closed for bits of the one-bit digital input stream carrying a logical one and open for bits of the one-bit digital input stream carrying a logical zero, or vice versa.
  • the herewith proposed FIRDAC circuit may also comprise an array of ohmic dummy resistors, wherein each dummy resistor is serially connected to a distinct one of the shift register's output taps and to the output-sided operational amplifier stage.
  • the dummy resistor at each tap may thereby have a similar or the same resistance value as the corresponding filter resistor having the same tap index.
  • the dummy resistor at each tap may be driven by the bit-inverse of the corresponding one-bit digital input stream's time-delayed version which is weighted by the resistance value of the filter resistor having the same tap index.
  • said one-bit digital input stream may be output from an oversampled sigma-delta converter circuit.
  • the output-sided operational amplifier stage of the proposed FIRDAC circuit may be realized by a differential current-to-voltage conversion circuit, wherein the latter may e.g. comprise a first operational amplifier circuit with a first operational amplifier a negative feedback configuration having an input port connected to a non- inverted current output path beginning from a first current summing node to which the filter resistors of each shift register tap are connected and a second operational amplifier circuit with a second operational amplifier in a negative feedback configuration having an input port connected to an inverted current path beginning from a second current summing node to which the dummy resistors of each shift register tap are connected.
  • the voltage output of said first and said second operational amplifier circuits may thereby be given by a differential analog output voltage.
  • a conversion means for converting said differential analog output voltage to a single-ended voltage may be provided.
  • Fig. Ia shows the block diagrams of a conventional first-order sigma-delta modulator (SDM) supplied with an analog input signal x(t) which provides a digital output signal y[n] in form of a sequence of impulses,
  • SDM first-order sigma-delta modulator
  • Fig. Ib shows the digital counterpart of this circuit
  • Fig. 2 illustrates in a partial block diagram and a partial logic diagram form a conventional finite impulse response digital-to-analog converter (FIRDAC) circuit as known from the prior art
  • Fig. 3 illustrates in a partial block diagram and a partial logic diagram form an implementation of the finite impulse response filter from the FIRDAC circuit as depicted in Fig. 2,
  • Fig. 4 shows a semi-digital finite impulse response digital-to-analog converter circuit whose filter coefficients are provided by switchable current sources with ad- justable DC output currents,
  • Fig. 5 shows a FIRDAC with filter coefficients provided by adjustable ohmic resistors according to an exemplary embodiment of the present invention
  • Fig. 6 shows an inverting operational amplifier stage with an input-sided voltage divider which, according to another exemplary embodiment of the present invention, comprises a switchable resistor for modeling the FIRDAC circuit's finite impulse response filter, which enables the use of low- voltage transistors at every tap of the FIRDACs integrated finite impulse response filter, and
  • Fig. 7 a finite impulse response digital-to-analog converter (FIRDAC) circuit according to an exemplary embodiment of the present invention.
  • FIRDAC finite impulse response digital-to-analog converter
  • Fig. Ia shows a block diagram of a first-order sigma-delta modulator (SDM) as known from the prior art which is supplied with an analog input signal x(t) and provides a digital output signal y[n] in form of a sequence of impulses.
  • the SDM circuit comprises an analog integrator 2 and a one-bit quantizer 3 in a feed- forward line and a one-bit digital-to-analog converter 4 (DAC) in a feedback line as well as a summation element 1 for additively combining analog input signal x(t) with a digital-to- analog converted and inverted version of digital output signal y[n].
  • DAC digital-to-analog converter 4
  • Ib shows the digital counterpart of this circuit, wherein analog integrator 2 is realized by a digital representation whose transfer function is given by the numerator z "1 in the transfer function of loop filter 6 and one-bit quantizer 3 is modeled as an additive white Gaussian noise source providing a noise signal e[n] which is additively combined with the output of said loop filter at summation element 7.
  • An impulse is generated, in time with the clock, whenever the integrated difference between the input and the output is positive. This way the circuit regulates the rate at which impulses occur attempting to keep the average output equal to the average input. Zero input corresponds to no output impulses while maximum input corresponds to impulses generated at the clock rate.
  • the converter By using negative feedback, the converter outputs a binary 1 if the input waveform accumulated over one sampling period T rises above the value accumulated in the negative feedback loop during previous input samples. If the waveform falls below the accumulated value, the converter outputs a binary zero, and otherwise a binary one.
  • Sigma-delta modulators use oversampling and noise shaping (quantization) tech- niques. Oversampling offers two important advantages: the specification of an antialiasing filter is reduced from the Nyquist specification, and the M bits resolution obtained from the ADC can be increased to M+l bits by oversampling the signal by a factor of four.
  • Noise shaping is a technique in which the feedback architecture of a sigma- delta converter allows the analog input signal of interest to pass unfiltered through the converter, while the quantization noise power is shifted to higher frequencies.
  • the quantization noise is high-pass filtered, the baseband signal of interest can be extracted by digital low-pass filtering. Consequently, sigma-delta modulation demands a considerable increase in digital processing compared to traditional methods such as pulse code modulation.
  • the advantages for sigma-delta modulation over other methods far outweigh the disadvantages.
  • sigma-delta modulation is that analog signals are converted using only a one-bit analog-to-digital converter and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter. Furthermore, the circuitry of a sigma-delta analog-to-digital converter only requires analog components of a comparator and an integrating component, making digital signal processor chip devices less costly.
  • the one-bit quantizer of the sigma-delta modulator is replaced by an additive white Gaussian noise source as shown in Fig. Ib, although, in practice, the quantizer may be nonlinear and quantization noise e[n] may be not white. Following the model of Fig. Ib, the modulator output y[n] is given by:
  • CMOS Oversampling D/A Converter with a Current Mode Semidigital Reconstruction Filter (IEEE J. Solid-State Circuits, Vol. 28, pp. 1224-1233, Dec. 1993) by D. Su and B. Wooley.
  • a FIRDAC is a one-bit digital-to-analog converter which is implemented together with a reconstruction filter in one combination, the latter being required to filter out quantization noise.
  • Such a FIRDAC thereby comprises a shift register (realized as a tapped delay line) with a large number of stages, typically more than hundred stages and receives a bitstream input signal of one bit (i.e. a serial data stream with one-bit amplitude resolution).
  • Each of the shift register stages switches a dedicated current source on or off.
  • the DC currents thus generated by all of the shift register stages are added to generate a DC output current of the FIRDAC.
  • the DC output current is applied to a current-to-voltage converter to generate an analog FIRDAC output voltage.
  • Each stage of the FIRDAC hence produces a DC output current contributing to the overall output current of the FIRDAC.
  • the stages of the FIRDAC do not all contribute in the same extent.
  • each stage of the FIRDAC has an associated weighting coefficient, which is constituted by the magnitude of the DC output current of the current source.
  • a digital input stream x[n] is fed to a shift register and traverses through this shift register at each clock cycle.
  • the shift register is typically implemented as a digital tapped delay line, while the filter coefficients are analog.
  • Each intermediate node of the shift register is supplied with a filter coefficient cik (with k ⁇ ⁇ 0, 1, 2, ..., N ⁇ ) whose value can be set by adjusting the DC output current of the corresponding current source at the respective intermediate node.
  • this transfer function can be obtained by applying a one-sided z transform to the output signal's impulse response
  • H(z) is defined for ⁇ z ⁇ e ]r, i?[ with r and i? again being the inner and outer convergence radius of a ring-shaped convergence area r ⁇ ⁇ z ⁇ ⁇ R, respec- tively.
  • the FIRDAC is used in a signal- processing path of a mobile telephone for providing an analog audio signal to a speaker or earphone.
  • the FIRDAC typically receives its input bitstream signal from a noise shaper, which increases the signal-to-noise ratio of the FIRDAC by shifting quantisation noise from the voice band to higher frequencies. Due to spurious influences, noise shap- ers have a tendency of repeating certain patterns, leading to small audible tones, called ,,idle tones".
  • FIG. 2 illustrates in partial block diagram and partial logic diagram of a digital-to-analog converter 10 (DAC) as known from US 5,323,157 A, which is herewith incorporated by reference.
  • DAC 10 is based on CMOS technology and comprises an interpolator 11, a sigma-delta modulator 12, and a digital finite impulse response (FIR) filter 13.
  • Interpolator 11 has an input terminal for receiving digital input data, a first clock input terminal for receiving a clock signal labelled ,,DCLK", a second clock input terminal for receiving a clock signal labelled ,,MCLK", and an output terminal for providing an N-bit output signal.
  • Interpolator 11 receives digital input data at a first sampling rate (the frequency of DCLK), and provides the N-bit output code at the out- put thereof at a second, higher sampling rate (the frequency of MCLK) by performing an interpolation between the samples. Thereby, said digital input data may be provided in an oversampled form.
  • Sigma-delta modulator 12 has an input terminal connected to the output terminal of interpolator 11, a clock input terminal for receiving signal MCLK, and an output terminal for providing output signal AOUT.
  • Sigma-delta modulator 12 shapes the quantization noise in AOUT out-of-band, and thus AOUT is a substantially linear analog representation of the digital input data within the passband.
  • FIR filter 13 has an input terminal connected to the output terminal of sigma-delta modulator 12, and an output terminal for providing an analog output voltage V OUT - FIR filter 13 is single-bit, TV-stage digital filter which eliminates the need for a complex analog smoothing filter at the output of sigma-delta modulator 12.
  • FIR filter 13 reduces the requirements placed on interpolator 11 compared to interpola- tor 23.
  • the filter function and number of tap lengths can be chosen in a way that is optimal for the particular application.
  • FIR filter 13 includes N delay elements each with corresponding amplifier weightings, of which representative delay elements 16-1, 16-2, and 16-N, and representative weighting amplifiers 14-1, 14-2, ..., 14-N are illustrated in Fig. 2.
  • Each delay element has an input terminal connected to a previous delay element, if any, and an output terminal.
  • Amplifiers 14-1, 14-2, .., 14-N have inputs connected to outputs of corresponding delay elements 16-1, 16-2, ..., 16-N, outputs connected to corresponding positive inputs of a summing device 15, and multiply the inputs thereof to implement FIR filter coefficients a ⁇ , ⁇ 2 , ..., ⁇ #, respectively, associated therewith.
  • Summing device 15 sums the outputs of all the amplifiers and has an output terminal for providing output signal V OUT thereon.
  • FIG. 3 illustrates in partial block diagram and partial logic diagram form an implementation 20 of FIR filter 13 of Fig. 2.
  • FIR filter 20 implements an JV-tap FIR filter using N D-type flip-flops (corresponding to the delay elements) and N controlled current sources (corresponding to coefficient weightings). The outputs of the current sources are connected together and to the input of a summing device 30.
  • Fig. 3 illustrates representative portions of FIR filter 20 including D-type flip-flops 21-1, 21-2, and 21 -N, and controlled current sources 22-1, 22-2, and 22-N.
  • Flip-flop 21-1 has a D input connected to the output of sigma-delta modulator 12, a clock input for receiving a signal labelled ,,2MCLK", a Q output for providing a true output signal, and a Q output for providing a complementary output signal.
  • 2MCLK is a digital clock signal having frequency twice that of modulator clock MCLK.
  • Flip-flop 21-2 has a D input connected to the Q output of flip-flop 21-1, a CLK input for receiving 2MCLK, a Q output provided to a subsequent flip-flop (not shown), and a Q output for providing a complementary output signal.
  • Flip-flop 21 -N has a D input connected to the Q output of a preceding flip-flop (not shown), a CLK input for receiving 2MCLK, an unused Q output, and a Q output.
  • Controlled current source 22-1 has a first terminal connected to a common node 23, a second terminal connected to a power supply voltage terminal labelled
  • Controlled current source 22-2 has a first terminal connected to node 23, a second terminal connected to Vss, and an active-low control terminal con- nected to the Q output terminal of flip-flop 21-2.
  • Controlled current source 22-N has a first terminal connected to node 23, a second terminal connected to Vss, and an active- low control terminal connected to the Q output terminal of flip-flop 21 -N.
  • Each controlled current source implements a coefficient weighting by conducting a current equal to the associated coefficient times a reference current, which is conducted in response to the Q output of the corresponding flip-flop.
  • FIR filter 20 uses a symmetrical, raised cosine (Hamming window) weighting because such a weighting gives better alias protection and requires a smaller range for the coefficients compared to other weightings.
  • Himming window raised cosine
  • other filter responses may be desirable for particular applications. Negative coefficients are also possible by utilizing the true (Q) flip-flop outputs instead of the complementary
  • Summing device 30 includes an operational amplifier 31, a capacitor 32, and ohmic resistors 33, 34 and 35.
  • Operational amplifier 31 has a positive input termi- nal connected to the first terminals of each current source, a negative input terminal, and an output terminal for providing signal V out .
  • Capacitor 32 has a first terminal connected to the output terminal of operational amplifier 31, and a second terminal connected to the positive input terminal of operational amplifier 31. Thereby, capacitor 32 is used to provide additional filtering.
  • Ohmic resistor 33 has a first terminal connected to the out- put terminal of operational amplifier 31 , and a second terminal connected to the positive input terminal of operational amplifier 31.
  • Resistor 34 along with IREF set the gain of summing device 30.
  • Ohmic resistor 34 has a first terminal connected to a power supply voltage terminal labelled ,,V DD ⁇ and a second terminal connected to the negative input terminal of operational amplifier 31.
  • V DD is a more-positive power supply voltage ter- minal having a nominal voltage of approximately 5.0 volts.
  • Ohmic resistor 35 has a first terminal connected to the second terminal of resistor 34, and a second terminal connected to Vss- Resistors 34 and 35 are preferably equal-valued to set the voltage at the positive input terminal at mid- supply.
  • summing device 30 is a conventional operational amplifier integrator, but may be implemented in other conven- tional forms in other embodiments.
  • input signal AOUT be chopped with a pattern of alternating zeros and ones, as taught by US 07/860,510.
  • a chop circuit (not shown) is placed between the output of sigma-delta modulator 12 of Fig. 2 and the input of FIR filter 20 which alternates the data with ones or zeros. With the chop circuit, the D flip-flops in FIR filter 20 are clocked by 2MCLK, at twice the modulator clock rate, to allow half of an MCLK cycle to be AOUT and the other half to be chopped to an alternating pattern of ones and zeros.
  • chopping data in this fashion prevents large current spikes by ensuring that there are approximately as many flip-flops switching to a logic high as to a logic low at any clock transition.
  • the chop circuit maintains the integrity of the output pulses, thereby preventing the introduction of additional distortion due to the current spikes.
  • other chop techniques are possible, such as return-to-one and return-to-zero.
  • the hardware of FIR filter 20 may be used to implement a TV-tap FIR filter on unchopped data at the MCLK rate.
  • Fig. 4 shows a further block diagram of a typical FIRDAC implementation as known from the prior art.
  • filter coefficients ⁇ ciu ⁇ k e ⁇ 0, 1, 2, ..., TV ⁇ are generated by adjustable DC output currents Ipi, Ip2, ..., IPN and Im, Im, ⁇ ⁇ ⁇ , INN of a set of switchable current sources, wherein said output currents are summed at the inverting input ports of two inverting operational amplifier circuits and converted to an analog output voltage V out through a conversion resistor Rp.
  • Fig. 5 shows a semi-digital FIRDAC implementation where the filter co- efficients are implemented by adjustable ohmic resistors RFIR 1 , RFIR 2 , ⁇ ⁇ ⁇ , RFIR N instead of switchable current sources.
  • the supply-voltage-to-output-voltage relation now only depends on a resistor matching. If required, the accuracy of conversion could easily be further enhanced by dynamic element matching.
  • the currents generated by these dummy resistors RD 1 , RD 2 , ⁇ ⁇ ⁇ , RD N could be dumped in a reference buffer as indicated by voltage source providing reference voltage V REF, said voltage source being connected between the non- inverting input ports of operational amplifiers OpAmpi and OpAnTp 2 and the ground node of the FIRDAC circuit depicted in Fig. 5.
  • said semi-digital finite impulse response digital-to- analog converter circuit has an output-sided operational amplifier stage which realizes a differential current-to-voltage conversion circuit.
  • the latter thereby comprises a first operational amplifier circuit with a first operational amplifier (OpAmpi) in a negative feedback configuration having an input port connected to a non-inverted current output path beginning from a first current summing node to which the filter resistors (R FIR1 , RFIR 2 , ..., RFIR,, ⁇ ⁇ ⁇ , RFIR N ) of each shift register tap k are connected and a second operational amplifier circuit with a second operational amplifier (OpAmP 2 ) in a negative feedback configuration having an input port connected to an inverted current path beginning from a second current summing node to which the dummy resistors (R D1 , R D2 , ..., R D11 , ..., R DN ) of each shift register tap k are connected.
  • the voltage output with a first operational amplifier (
  • Fig. 6 which shows an inverting operational amplifier stage with an input-sided voltage divider which comprises an adjustable resistor R FIR for modeling the filter coefficients of the FIRDAC circuit's finite impulse response filter
  • low-voltage transistors can be used at every tap of the FIRDACs integrated finite impulse response filter while a higher supply voltage is applied.
  • the complete FIR filter is modeled by just one ohmic resistor (R FIR ) and a single clock-controlled switch (S), wherein said switch is closed for the FIRDACs one-bit digital input stream x[n] carrying a logical one and open for said digital input data signal x[n] carrying a logical zero, or vice versa.
  • reference voltage VREF be equal to VDD/% and real- valued factor ⁇ be given such that V REF is well below the breakdown voltage of the FIRDACs low- voltage transistors. Since voltage V RPIR at the inverting input port of the operational amplifier (OpAmp) will follow V REF , said low-voltage transistors can be used for the numerous switches in the FIR filter. This will result in a FIR filter with reduced chip area.
  • V 11 ⁇ FIR _ ' DD
  • V out V Rpm - R P I [V] and (l ie)
  • R F denotes the resistance value of an ohmic resistor in the feedback line of the depicted FIRDACs output-sided operational amplifier stage, said stage comprises an operational amplifier in a negative-feedback configuration
  • R B and R FIR denote the resistance values of two serially connected adjustable ohmic resistors consti- tuting the aforementioned voltage divider
  • V DD denotes the FIRDACs supply voltage
  • V REF denotes a DC voltage supplied by a DC voltage source connected to the non- inverting input port of the output-sided operational amplifier
  • V RFIR denotes the voltage drop at the adjustable voltage divider resistor R F m
  • voltage V out denotes the resulting analog output voltage representing an analog equivalent of the FIRDACs one-bit digi- tal input stream
  • / denotes the voltage divider's output current.
  • V ' out - V ' DD 1 - - I [V] (18)
  • Fig. 7 shows a further exemplary embodiment of the present invention for the k-th tap (with k e ⁇ 1, 2, ..., N]) of the proposed ratiometric FIRDAC.
  • V REF should scale with the supply voltage V DD , which is achieved by means of a resistive voltage divider constituted by ohmic resistor R B ⁇ (or R B2 , respectively) and ohmic resistor R FIR , , , the latter providing filter coefficient at for this tap.
  • V REF has to be smaller than the breakdown voltage of the low- voltage transistors which are applied in the given IC process.
  • switches Mu, M 2 *, Mn' and M 2 *' in the two single-balanced mixer configurations of the depicted FIR filter implementation can be realized as low-voltage bipolar transistors, low-voltage metal oxide semiconductor field effect transistors (MOSFETs) or low-voltage junction field effect transistors (JFETs), which thus results in a smaller chip size.
  • the proposed FIRDAC circuit can advantageously be applied in high- accuracy (M > 12 bits) low-frequency (f s ⁇ 30 kHz) digital-to-analog interfaces, e.g. in the scope of sigma-delta modulators for class-D power amplifiers in high-fidelity audio equipment or sensor equipment.
  • the present invention may also be used in automotive angular sensors (such as e.g. the KMA200 and the KMAl 99 by Business Line General Applications). In this application, it is required to have an output which is ratiometric to the supply voltage, which is due to the fact that the angular sensor has to replace a potentiometer.

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  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La présente invention concerne un circuit de type à réseau de résistances réglables d'un convertisseur numérique-analogique non récursif (FIRDAC) quotientométrique semi-numérique. Le FIRDAC proposé fournit une tension de sortie (V out) ayant une relation précise et linéaire par rapport à la tension d'alimentation du circuit (V DD). Cela est obtenu à l'aide d'un filtre non récursif (FIR) adaptatif linéaire dont les coefficients de pondération (a 1, a 2,, a k,, a N) sont mis en œuvre au moyen d'un réseau de résistances ohmiques réglables (R FIR 1, R FIR 2,, R FIR k,, R FIR N). La précision de conversion peut facilement être améliorée par l'utilisation supplémentaire de techniques d'adaptation d'éléments dynamiques. Cela est moins sophistiqué que dans les FIRDAC classiques connus dans l'art antérieur, qui sont fondés sur une approche à courant pondéré. En outre, la présente invention propose une mise en œuvre de circuit semi-numérique qui permet l'utilisation de transistors basse tension dans un FIRDAC de type à réseau de résistances réglables dont la tension d'alimentation (V DD) est autorisée à dépasser la tension de claquage de transistors basse tension intégrés qui sont utilisés pour commuter lesdites résistances ohmiques (R FIR 1, R FIR 2,, R FIR k,, R FIR N), ce qui se traduira par une plus petite dimension de puce. Un autre aspect de la présente invention concerne la conception de circuit d'un FIRDAC qui emploie un réseau de résistances fictives (R D 1, R D 2,, R D k,, R D N) dont les valeurs de résistance sont choisies de sorte que le courant d'alimentation du circuit FIRDAC est indépendant du flux de données numériques (x[n]) devant être converties au domaine analogique. De cette façon, la tension de sortie analogique (V out) du circuit FIRDAC est moins sensible à une impédance série variable dans ses conducteurs d'alimentation.
PCT/IB2008/053425 2007-09-11 2008-08-26 Circuit de type à réseau de résistances réglables d'un convertisseur numérique-analogique non récursif (firdac) quotientométrique semi-numérique Ceased WO2009034494A1 (fr)

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EP3453114A1 (fr) * 2016-05-04 2019-03-13 D&M Holdings Inc. Dispositif et procédé de traitement de signal
CN111025951A (zh) * 2018-10-09 2020-04-17 西安智盛锐芯半导体科技有限公司 一种用于进行信号转换的系统
US10673449B1 (en) 2019-04-30 2020-06-02 Qualcomm Incorporated Digital-to-analog converter with glitch-irrelevant reference voltage to increase linearity
CN113938132A (zh) * 2021-10-20 2022-01-14 北京士模微电子有限责任公司 模数转换装置及电子设备
WO2023052803A1 (fr) * 2021-09-29 2023-04-06 Sorbonne Universite Dispositif électronique pour la conversion numérique-analogique d'un flux d'entrée numérique en une sortie analogique différentielle

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3453114A1 (fr) * 2016-05-04 2019-03-13 D&M Holdings Inc. Dispositif et procédé de traitement de signal
CN111025951A (zh) * 2018-10-09 2020-04-17 西安智盛锐芯半导体科技有限公司 一种用于进行信号转换的系统
US10673449B1 (en) 2019-04-30 2020-06-02 Qualcomm Incorporated Digital-to-analog converter with glitch-irrelevant reference voltage to increase linearity
WO2023052803A1 (fr) * 2021-09-29 2023-04-06 Sorbonne Universite Dispositif électronique pour la conversion numérique-analogique d'un flux d'entrée numérique en une sortie analogique différentielle
CN113938132A (zh) * 2021-10-20 2022-01-14 北京士模微电子有限责任公司 模数转换装置及电子设备

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