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WO2009030169A1 - Procédé de commande de lecture-écriture de données dans une mémoire vide statique (sram) et dispositif à cristaux liquides à circuit intégré - Google Patents

Procédé de commande de lecture-écriture de données dans une mémoire vide statique (sram) et dispositif à cristaux liquides à circuit intégré Download PDF

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Publication number
WO2009030169A1
WO2009030169A1 PCT/CN2008/072208 CN2008072208W WO2009030169A1 WO 2009030169 A1 WO2009030169 A1 WO 2009030169A1 CN 2008072208 W CN2008072208 W CN 2008072208W WO 2009030169 A1 WO2009030169 A1 WO 2009030169A1
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WIPO (PCT)
Prior art keywords
read
pulse signal
write
parallel
sram
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Ceased
Application number
PCT/CN2008/072208
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English (en)
Inventor
Bangjun He
Yun Yang
Wei FENG
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BYD Co Ltd
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BYD Co Ltd
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Publication of WO2009030169A1 publication Critical patent/WO2009030169A1/fr
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Definitions

  • the present invention pertains to semiconductor memory field, particularly relates to a method for controlling SRAM data read- write, an integrated circuit and a liquid crystal display device with the integrated circuit.
  • the driver chip has a built-in Static Random Read-write Memory (SRAM), which is configured to store various data and support 16-bit, 18-bit, or 24-bit serial data read- write and parallel read the stored data under control of row decoder, column decoder, write buffer and read/write circuit. Since the time sequence for serial read-write is provided by the read-write clock from an external Micro Control Unit (MCU), and the time sequence for parallel read is provided by the internal scan clock in the SRAM, there is possibility that serial read-write to a memory unit or byte in the SRAM is carried out while the sane memory unit or byte is read out in parallel.
  • MCU Micro Control Unit
  • the read/write operation of SRAM is controlled with a read/write control bus, for example, for a 6-transistor (6T) SRAM, it is difficult to avoid the conflict between serial read- write and parallel read; especially, if serial write to a memory unit is carried out before the data is read from the memory unit in parallel, it is easy to result in data loss.
  • a read/write control bus for example, for a 6-transistor (6T) SRAM
  • FIFO First-In-First-Out
  • FIFO FIFO circuit module
  • FIFO FIFO circuit module
  • the so-called FIFO is a dual-port 8T SRAM.
  • the fundamental principle of the solution shown in Fig.l is: the external MCU writes the data serially to the FIFO through the DATA_BUS at its own serial writing clock rate (i.e., the external clock shown in Fig.l), and the SRAM reads the data sent by the MCU to the FIFO in parallel at its internal scan clock rate (i.e., the internal clock shown in Fig.l).
  • FIFO Since a FIFO is used, the data written into the FIFO in the first will be read out by the SRAM in the first. If the FIFO is already full before the data in the FIFO is read out by the SRAM, FIFO will feed back a SRAM_BUSY signal to the MCU; then, the MCU will not further write data into the FIFO, in order to avoid data loss.
  • Such a solution usually requires that the area of the FIFO must be very small, otherwise the data read- write rate will be limited.
  • the area of the SRAM is usually accounts for 75% of the area of the entire driver chip; in addition, a 8T SRAM that serves as FIFO is much larger than a 6T SRAM; therefore, in terms of data read-write rate and FIFO area, the existing solution can't be used widely in small- size chips.
  • the object of the present invention is to provide a method for controlling SRAM data read-write, an integrated circuit and a LCD device with the integrated circuit, in order to eliminate the conflict of time sequence between serial read-write and parallel read and prevent large chip area caused by application of a FIFO circuit module.
  • the present invention provides a method for controlling SRAM data read-write, comprises following steps: writing data into a SRAM in series when a serial read-write pulse signal is at valid level; performing AND operation or OR operation between the serial read- write pulse signal and an internal scan clock signal in the SRAM to generate a parallel read pulse signal, and setting the valid level of the parallel read pulse signal as reverse to the valid level of the serial read-write pulse signal; and reading out the data from the SRAM in parallel when both the internal scan clock signal and the parallel read pulse signal are at valid levels.
  • the present invention further provides an integrated circuit comprising a SRAM, wherein the integrated circuit further comprising: a read-write control circuit, configured to receive a serial read-write pulse signal and an internal scan clock signal in the SRAM, perform AND operation or OR operation between the serial read-write pulse signal and the internal scan clock signal in the SRAM to generate a parallel read pulse signal, and set the valid level of the parallel read pulse signal as reverse to the valid level of the serial read- write pulse signal, and trigger reading data from the SRAM in parallel when both the internal scan clock signal and the parallel read pulse signal are at valid levels.
  • a read-write control circuit configured to receive a serial read-write pulse signal and an internal scan clock signal in the SRAM, perform AND operation or OR operation between the serial read-write pulse signal and the internal scan clock signal in the SRAM to generate a parallel read pulse signal, and set the valid level of the parallel read pulse signal as reverse to the valid level of the serial read- write pulse signal, and trigger reading data from the SRAM in parallel when both the internal scan clock signal and the parallel read pulse signal
  • the present invention yet provides a liquid crystal display (LCD) device, comprising a drive integrated circuit, wherein the drive integrated circuit is the integrated circuit provided in the present invention.
  • LCD liquid crystal display
  • logical operation between the serial read-write pulse signal from an external MCU and the internal scan clock signal in the SRAM is performed in an read-write control circuit, to obtain a parallel read pulse signal, which has the same waveform as the serial read-write pulse signal when the internal scan clock signal is at valid level; in that way, as long as the valid level of the parallel read pulse signal is set as reverse to the valid level of the serial read- write pulse signal, no time sequence conflict between serial read- write and parallel read will occur, and therefore the correctness of data read-write can be ensured.
  • Fig.l is a schematic diagram of a solution that controls serial read- write asynchronous to parallel read in the prior art
  • Fig.2 is a flow diagram of the method for controlling SRAM data read-write provided in the present invention.
  • Fig.3A is a schematic diagram of processing the internal scan clock signal and the serial read- write pulse signal with an AND gate to generate the parallel read pulse signal;
  • Fig.3B is a schematic diagram of processing the internal scan clock signal and the serial read- write pulse signal with an OR gate to generate the parallel read pulse signal;
  • Fig.4A is a timing sequence diagram of the signals shown in Fig.3A
  • Fig.4B is a timing sequence diagram of the signals shown in Fig.3B;
  • Fig.5 is a signal timing sequence diagram in a preferred embodiment of the present invention
  • Fig.6 is a schematic diagram of connection between the integrated circuit provided in the present invention and external components
  • Fig.7 is a structural diagram of the SRAM applied in the present invention.
  • Fig.2 shows a flow diagram of the method for controlling SRAM data read- write provided in the present invention. The method will be detailed as follows:
  • the valid level of the serial read- write pulse signal can be set as high level or low level as required, which is to say, in step S201, the serial data read/write is performed during the serial read- write pulse signal (read-write clock signal of MCU) is at high level or low level.
  • step S202 AND operation or OR operation is performed between the serial read- write pulse signal and the internal scan clock signal in the SRAM to generate a parallel read pulse signal, and the valid level of the parallel read pulse signal is set as reverse to the valid level of the serial read- write pulse signal.
  • the AND operation/OR operation is accomplished with the AND gate shown in Fig.3A or the OR gate shown in Fig.3B.
  • the internal scan clock signal and the serial read- write pulse signal are inputted to the two input terminals of the AND gate/OR gate, and the parallel read pulse signal is outputted from the output terminals of the AND gate/OR gate.
  • the parallel read pulse signals obtained through AND operation/OR operation are shown in Fig.4A and Fig.4B respectively; wherein, the parallel read pulse signal shown in Fig.4A is obtained through AND operation, while the parallel read pulse signal shown in Fig.4B is obtained through OR operation.
  • the valid level of the internal scan clock signal can be set as high level or low level as required. It is seen from Fig.4A and Fig.4B, during AND operation, the parallel read pulse signal is synchronous to the serial read-write pulse signal when the internal scan clock signal is at high level; whereas, in OR operation, the parallel read pulse signal is synchronous to the serial read-write pulse signal when the internal scan clock signal is at low level. Therefore, the level of the internal scan clock signal shall be set as its valid level when the waveforms are synchronous, i.e., during AND operation, the valid level of the internal scan clock signal is high level; and during OR operation, the valid level of the internal scan clock signal is low level.
  • Case 1 serial data read- write is performed when the external serial read- write pulse signal is at low level, while parallel read is performed when the internal scan clock signal is at low level.
  • OR operation can be performed between the serial read-write pulse signal and the internal scan clock signal in an read-write control circuit to generate a parallel read pulse signal; specifically, the two clock signals are inputted to the OR gate circuit shown in Fig.3B, and the output signal from the OR gate circuit is taken as the parallel read pulse signal.
  • the valid level of the parallel read pulse signal is high level, as shown in Fig.4B, when the internal scan clock signal is at low level, the valid level of the serial read- write pulse signal and the valid level of the parallel read pulse signal occur in alternate; therefore, conflict between serial read- write and parallel read can be avoided.
  • Case 2 serial data read- write is performed when the external serial read-write pulse signal is at low level, while parallel read is performed when the internal scan clock signal is at high level.
  • AND operation can be performed between the external read-write clock signal and the internal scan clock signal in an read- write control circuit to generate a parallel read pulse signal; specifically, the two clock signals are inputted to the AND gate circuit shown in Fig.3A, and the output signal from the AND gate circuit is taken as the parallel read pulse signal.
  • the valid level of the parallel read pulse signal is high level, as shown in Fig.4A, when the internal scan clock signal is at high level, the valid level of the serial read-write pulse signal and the valid level of the parallel read pulse signal occur in alternate; therefore, conflict between serial read-write and parallel read can be avoided.
  • Case 3 This case is essentially similar to Case 1, with the difference as: the valid levels of serial read- write pulse signal and parallel read pulse signal are reverse to those in Case 1; however, they also occur in alternate; therefore, this case will not be described any more.
  • Case 4 This case is essentially similar to Case 2, with the difference as: the valid levels of serial read-write pulse signal and parallel read pulse signal are reverse to those in Case 2; however, they also occur in alternate; therefore, this case will not be described any more.
  • the read- write control circuit (such as the AND gate circuit and the OR gate circuit) can be arranged in a same integrated circuit as the SRAM.
  • the integrated circuit can be used as a drive integrated circuit of a LCD device, and work with a MCU and some peripheral devices to constitute a driver module of the LCD, which controls serial data read-write from/to the SRAM and parallel data read from the SRAM, without the conflict of time sequence.
  • step S203 when the parallel read pulse signal is at valid level, the data in the SRAM is read out in parallel. Since the serial read-write pulse signal is not at valid level when the parallel read pulse signal is at valid level, the case of synchronous serial read- write and parallel read will not occur.
  • step S202 reading data in parallel is performed when the parallel read pulse signal is at valid level in step S203; then, step S201 is repeated to further perform serial data read- write, and then parallel data read will be performed again.
  • serial read-write pulse signal is provided from an external MCU and the speed is very high, but the speed of the internal scan clock signal in SRAM is relatively low, up to one third of the serial read-write speed at the most. Therefore, in a clock cycle of the internal scan clock, the valid level of the serial read- write pulse signal appears several times, as shown in Fig.4A and Fig.4B.
  • SRAM scan address is constant in a same clock cycle of the internal scan clock, parallel data read for a same address will be performed in the same clock cycle; such repeated parallel read will cause severe waste in power consumption.
  • the method provided in the present invention further comprises: reading twice consecutively for the same memory address during reading data from the SRAM in parallel.
  • Fig.5 shows a timing sequence diagram in a preferred embodiment of the present invention, wherein, for example, in Case 1 described in step S202, the preferred embodiment employs a counter to count the pulse signals obtained by logical OR operation between the internal scan clock signal and the serial read-write pulse signal according to the clock signal of the counter, and count twice, i.e., count twice the high level of serial read- write pulse signal when the internal scan clock signal is at low level (valid level), so as to ensure correct data reading and reduce power consumption.
  • the counter can be built in the drive integrated circuit of the LCD device.
  • the reason for counting twice is: in view that the serial read-write pulse signal and the internal scan clock signal are two irrelevant clock signals, it is difficult to ensure the counted first pulse is an entire high level pulse after logical OR operation, as shown in the timing sequence diagram in Fig.5; if the counter only counts once, it is difficult to ensure correct data reading; therefore, the counter must be configured to count twice the clock signal output from the OR gate circuit, to ensure the second high level signal counted by the counter is an entire pulse and ensure the data read out from the memory unit is correct after twice data reading operations.
  • the counter must be configured to count twice the pulse signal output from the logical gate circuit, respectively.
  • Fig.6 is a schematic diagram of the connection between the integrated circuit provided in the present invention and external components; for the convenience of description, only the parts related to the embodiment of the present invention are shown.
  • the integrated circuit provided in the present invention comprises a SRAM; wherein, the integrated circuit further comprises: a read- write control circuit, configured to receive a serial read-write pulse signal and an internal scan clock signal in the SRAM, perform AND operation or OR operation between the serial read- write pulse signal and the internal scan clock signal in the SRAM to generate a parallel read pulse signal, set the valid level of the parallel read pulse signal as reverse to the valid level of the serial read- write pulse signal, and trigger reading data from the SRAM in parallel when both the internal scan clock signal and the parallel read pulse signal are at valid levels.
  • a read- write control circuit configured to receive a serial read-write pulse signal and an internal scan clock signal in the SRAM, perform AND operation or OR operation between the serial read- write pulse signal and the internal scan clock signal in the SRAM to generate a parallel read pulse signal, set the valid level of the parallel read pulse signal as reverse to the valid level of the serial read- write pulse signal, and trigger reading data from the SRAM in parallel when both the internal scan clock signal and the parallel read pulse signal are at valid
  • an external MCU is directly connected to the SRAM, without the need for any FIFO circuit module in the prior art.
  • the MCU performs serial data read-write through a DATA_BUS when the serial read-write clock signal is at valid level; the SRAM performs parallel data reading when both the internal scan clock signal and the parallel read pulse signal are at valid levels, and reads out the data into a data read-out latch.
  • the read-write control circuit mainly comprises a logical gate, which can be an AND gate circuit or an OR gate circuit with two input terminals and one output terminal, wherein, the two input terminals are configured to input the internal scan clock signal and the serial read-write pulse signal and the output terminal is configured to output the parallel read pulse signal.
  • the AND gate circuit/OR gate circuit performs AND operation or OR operation between the internal scan clock signal and the serial read-write pulse signal to generate a parallel read pulse signal.
  • the read- write control circuit further comprises: a counter, configured to count the parallel read pulse signal, so as to control reading twice consecutively for the same address during parallel data reading.
  • a counter configured to count the parallel read pulse signal, so as to control reading twice consecutively for the same address during parallel data reading.
  • the non- valid level of the external serial read- write pulse signal is counted twice by the counter and taken as the parallel read pulse signal, so as to ensure correct parallel data read.
  • a LCD device which comprises a drive integrated circuit, which can be the integrated circuit shown in Fig.6.
  • the SRAM can be built in the drive integrated circuit of the LCD device, while the MCU, driver chip, and some peripheral devices constitute the driver module of the LCD device.
  • the MCU performs serial read-write to the data in the memory units of the SRAM when the serial read- write pulse is at valid level; the driver module of the LCD device reads the data stored in the SRAM in parallel when both the internal scan clock signal and the parallel read pulse signal are at valid levels, and display the data on the LCD screen.
  • the valid levels of the serial read- write pulse signal, the internal scan clock signal, and the parallel read pulse signal are set as described above, and will not be detailed further here.
  • Fig.7 shows the structure of the SRAM applied in the present invention.
  • the SRAM can comprise a plurality of memory units to constitute a matrix memory structure, as shown in Fig.7, wherein the box enclosed by dotted lines represents a memory unit, which is a 6T SRAM. Only one memory unit is shown in Fig.7, and if the SRAM comprises a plurality of memory units, the total storage capacity will be the product of the number of rows and the number of columns of the matrix.
  • serial read-write refers to write the data items one by one serially through the data bus into the memory units selected by word line and bit line at the same time in the SRAM, or read the data items one by one from the memory units through the data bus and then send the data to the MCU, wherein, serial data reading also requires a sensitive comparator.
  • the integrated circuit provided in the present invention only comprises a simple logical gate circuit and a counter, except for a SRAM; therefore, the chip area is reduced greatly, and the cost and power consumption are reduced further.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Procédé de commande de lecture-écriture de données dans une mémoire vide statique (SRAM) et dispositif à cristaux liquides à circuit intégré. Ce procédé englobe les opérations suivantes: écriture de données dans une mémoire SRAM en série lorsqu'un signal impulsionnel d'écriture-lecture série est à un niveau valide; exécution d'une opération ET ou OU entre le signal impulsionnel de lecture-écriture série et un signal d'horloge de balayage interne dans la mémoire SRAM pour générer un signal impulsionnel de lecture parallèle, et détermination du niveau valide du signal impulsionnel de lecture parallèle comme inverse du niveau valide du signal impulsionnel de lecture-écriture série; et lecture des données dans la mémoire SRAM en parallèle avec à la fois le signal d'horloge de balayage interne et le signal impulsionnel de lecture parallèle à des niveaux valides. Avec ce procédé, dans lequel le niveau valide du signal impulsionnel d'écriture-lecture série et le niveau valide du signal impulsionnel de lecture parallèle sont calés pour se produire en alternance, on empêche un conflit de séquence temporelle entre la lecteur-écriture série et la lecture parallèle, ce qui garantit une lecture-écriture correcte.
PCT/CN2008/072208 2007-08-30 2008-08-29 Procédé de commande de lecture-écriture de données dans une mémoire vide statique (sram) et dispositif à cristaux liquides à circuit intégré Ceased WO2009030169A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2007100768270A CN101377952B (zh) 2007-08-30 2007-08-30 一种sram中数据的读写方法及装置
CN200710076827.0 2007-08-30

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WO2009030169A1 true WO2009030169A1 (fr) 2009-03-12

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WO (1) WO2009030169A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9183922B2 (en) 2013-05-24 2015-11-10 Nvidia Corporation Eight transistor (8T) write assist static random access memory (SRAM) cell
GB2614368A (en) * 2021-12-31 2023-07-05 Lg Display Co Ltd Data transmission/reception circuit and display device including the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102541462A (zh) * 2010-12-28 2012-07-04 上海芯豪微电子有限公司 宽带读写存储器装置
US8995210B1 (en) * 2013-11-26 2015-03-31 International Business Machines Corporation Write and read collision avoidance in single port memory devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719644A (en) * 1994-10-13 1998-02-17 Samsung Electronics Co., Ltd. Data collision avoidance circuit used in an image processing FIFO memory
US6181640B1 (en) * 1997-06-24 2001-01-30 Hyundai Electronics Industries Co., Ltd. Control circuit for semiconductor memory device
JP2002025275A (ja) * 2000-07-10 2002-01-25 Toshiba Corp 半導体記憶装置
JP2002093173A (ja) * 2000-09-20 2002-03-29 Mitsubishi Electric Corp 同期型マルチポートメモリ
KR20070071158A (ko) * 2005-12-29 2007-07-04 매그나칩 반도체 유한회사 디스플레이 드라이버 회로에서 ｓｒａｍ을 제어하는 장치및 방법
US20070195617A1 (en) * 2006-02-17 2007-08-23 International Business Machines Corporation Methods and apparatus for read/write control and bit selection with false read suppression in an SRAM

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100414510C (zh) * 2003-12-30 2008-08-27 中国科学院空间科学与应用研究中心 实时差错检测与纠错芯片
US7016235B2 (en) * 2004-03-03 2006-03-21 Promos Technologies Pte. Ltd. Data sorting in memories
CN100353414C (zh) * 2006-01-20 2007-12-05 西北工业大学 液晶显示驱动芯片中静态存储器的控制电路设计方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719644A (en) * 1994-10-13 1998-02-17 Samsung Electronics Co., Ltd. Data collision avoidance circuit used in an image processing FIFO memory
US6181640B1 (en) * 1997-06-24 2001-01-30 Hyundai Electronics Industries Co., Ltd. Control circuit for semiconductor memory device
JP2002025275A (ja) * 2000-07-10 2002-01-25 Toshiba Corp 半導体記憶装置
JP2002093173A (ja) * 2000-09-20 2002-03-29 Mitsubishi Electric Corp 同期型マルチポートメモリ
KR20070071158A (ko) * 2005-12-29 2007-07-04 매그나칩 반도체 유한회사 디스플레이 드라이버 회로에서 ｓｒａｍ을 제어하는 장치및 방법
US20070195617A1 (en) * 2006-02-17 2007-08-23 International Business Machines Corporation Methods and apparatus for read/write control and bit selection with false read suppression in an SRAM

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9183922B2 (en) 2013-05-24 2015-11-10 Nvidia Corporation Eight transistor (8T) write assist static random access memory (SRAM) cell
GB2614368A (en) * 2021-12-31 2023-07-05 Lg Display Co Ltd Data transmission/reception circuit and display device including the same
US11900857B2 (en) 2021-12-31 2024-02-13 Lg Display Co., Ltd. Data transmission/reception circuit and display device including the same
GB2614368B (en) * 2021-12-31 2024-11-27 Lg Display Co Ltd Data transmission/reception circuit and display device including the same

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CN101377952A (zh) 2009-03-04

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