[go: up one dir, main page]

WO2009014291A1 - Procédé de transformation de fourier rapide et processeur pour système wlan mimo-ofdm 4x4 - Google Patents

Procédé de transformation de fourier rapide et processeur pour système wlan mimo-ofdm 4x4 Download PDF

Info

Publication number
WO2009014291A1
WO2009014291A1 PCT/KR2008/000285 KR2008000285W WO2009014291A1 WO 2009014291 A1 WO2009014291 A1 WO 2009014291A1 KR 2008000285 W KR2008000285 W KR 2008000285W WO 2009014291 A1 WO2009014291 A1 WO 2009014291A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
fast fourier
trivial
delay
fourier transform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2008/000285
Other languages
English (en)
Inventor
Jae-Seok Kim
Sang-Min Lee
Yun-Ho Jung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industry Academic Cooperation Foundation of Yonsei University
Original Assignee
Industry Academic Cooperation Foundation of Yonsei University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industry Academic Cooperation Foundation of Yonsei University filed Critical Industry Academic Cooperation Foundation of Yonsei University
Publication of WO2009014291A1 publication Critical patent/WO2009014291A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2628—Inverse Fourier transform modulators, e.g. inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2649—Demodulators
    • H04L27/265—Fourier transform demodulators, e.g. fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0001—Arrangements for dividing the transmission path
    • H04L5/0014—Three-dimensional division
    • H04L5/0023—Time-frequency-space
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0058—Allocation criteria
    • H04L5/0064—Rate requirement of the data, e.g. scalable bandwidth, data priority

Definitions

  • the present invention relates to a fast Fourier transforming method for a 4X4 MIMO-OFDM WLAN system and an apparatus thereof. More particularly, the present invention relates to a fast Fourier transforming method for a 4 4 MIMO-OFDM WLAN system and apparatus thereof, in which an multi-channel MDC (Multi-path Delay Commutator) structure is formed to support multiplex data paths, four fast Fourier transform (hereinafter, referred to as "FFT") operations required for 4X4 MIMO (Multiple Input Multiple Output)- OFDM(Orthogonal Frequency Division Multiplexing) WLAN system can be processed by one processor, the number of non-trivial multiplications can be reduced as compared with an existing 4-chanle Radi ⁇ -4 MDC FFT processor using an efficient Radix decomposition based on a mixed Radix scheme, thereby reducing hardware complexity.
  • MDC Multi-path Delay Commutator
  • OFDM orthogonal frequency division multiplexing
  • a next-generation WLAN system that enables a high channel capacity and high-speed data transmission for use in a multimedia service such as an HDTV using a WLAN has been increasingly required.
  • an MIMO scheme has been suggested, in which a diversity gain is obtained by increasing the number of transmitting and receiving antennas.
  • the MIMO scheme can effectively overcome an influence due to a frequency selective fading environment when the MIMO scheme and the OFDM scheme are used together. Therefore, the MIMO scheme and the OFDM scheme are researched together.
  • the MIMO-OFDM scheme can improve the throughput due to an increase in the transmission amount and improvement of performance at the same band.
  • the IEEE 802. Hn standardized system is oriented to a high-speed WLAN system, and is being standardized to support a maximum of 4X4 MIMO system and a maximum of transmission rate of 300/600 Mbps.
  • the MIMO- OFDM system the high throughput is obtained, but system complexity is high.
  • the 4X4 MIMO system if an independent block is used for each data path, four OFDM baseband processors that operate in parallel are required, which results in increasing hardware complexity four times.
  • FIG. 1 is a block diagram illustrating a 4x4 MIMO system among the IEEE 802.Hn standardized systems. As can be seen from FIG. 1, if the MIMO technology is applied to the OFDM system, multiplex data paths are formed and hardware complexity is increased.
  • an efficient system block that can process multiplex data paths needs to be developed.
  • an FFT processor occupies about 30% with respect to 100% of hardware complexity of the entire system, complexity of the FFT processor is preferably reduced so as to reduce hardware complexity of the MIMO-OFDM WLAN system.
  • a non-trivial multiplier occupies a large portion of the FFT processor.
  • a Radi ⁇ -2 algorithm and a Radi ⁇ -4 algorithm are mainly used.
  • the Radi ⁇ -2 algorithm is efficient for an SISO (Single Input Single Output)-0FDM, but inefficient for the MIMO-OFDM.
  • the Radi ⁇ -4 algorithm requires a large number of non-trivial multipliers, which results in increasing hardware complexity. [Disclosure]
  • the present invention has been made to solve the above- described problem, and it is an object of the present invention to a fast Fourier transforming method for a 4x4 MIMO-OFDM WLAN system and apparatus thereof, in which an multi-channel MDC (Multi-path Delay Commutator) structure is formed to support multiplex data paths, four fast Fourier transform (hereinafter, referred to as "FFT") operations required for 4X4 MIMO (Multiple Input Multiple Output)-OFDM(Orthogonal Frequency Division Multiplexing) WLAN system can be processed by one processor, the number of non-trivial multiplications can be reduced as compared with an existing 4- chanle Radi ⁇ -4 MDC FFT processor using an efficient Radix decomposition based on a mixed Radix scheme, thereby reducing hardware complexity.
  • MDC Multi-path Delay Commutator
  • the fast Fourier transform method includes (a) a step of selecting an operation mode of a fast Fourier transform (FFT) or an inverse fast Fourier transform (IFFT), when 4- channel data is input; (b) a step of sequentially distributing the 4-channel data during the operation mode selected in the step of (a) and performing delay commutation; (c) a step of using a Radi ⁇ -4 butterfly operation to perform addition and subtraction of the 4-channel data, on which delay commutation is performed through the step of (b); (d) a trivial multiplication step of processing W 8 multiplication independently existing for each data path with respect to the data, on which addition or subtraction are performed through the step of (c); (e) a step of using a Radi ⁇ -2 butterfly operation to perform addition and subtraction of the data, on which trivial multiplication is performed through the step of (d); and
  • a fast. Fourier transform apparatus for a 4x4 MIMO-OFDM WLAN system.
  • the fast Fourier transform apparatus includes an operation mode selector that selects an operation mode of a fast Fourier transform (FFT) or an inverse fast Fourier transform (IFFT), when 4-channel data is input; a first delay commutator that sequentially distributes the 4-channel data to sequentially perform operations, performs a switching operation having 16, 32, and 48 delay symbols at the second, third, and fourth paths, respectively, and has 48, 32, and 16 delay symbols at the first, second, and third paths, respectively; a Radix-4 butterfly operator that performs addition or subtraction of the data that has passed the first delay commutator; a trivial multiplying unit that processes W 8 multiplication independently existing for each data path with respect to the data, on which the Radix-4 butterfly operation is performed; a Radix-2 butterfly operator that performs addition or subtraction of the data that has passed the trivial multiplying unit; a second delay commutator that arrange
  • multi-channel data can be processed by one FFT processor by using only an additional commutator having low complexity. According to the present invention, it is possible to achieve area reduction effects of 25% and 64%, as compared with FFT processors having the
  • the number of non-trivial multiplications that is most important in terms of complexity of an FFT process is reduced through an effective Radix decomposition, thereby reducing hardware complexity.
  • next-generation communication systems such as IEEE 802.16e Mobile WiMAX and 4G, which are defined in recent years, are based on an MIMO-OFDM. Accordingly, the present invention can be effectively applied to various systems.
  • FIG. 1 is a block diagram illustrating a 4x4 MIMO system among the IEEE 8.2. Hn standardized systems.
  • FIG. 2 is a signal flow graph of an FFT signal using an MR algorithm according to the preferred embodiment of the present invention.
  • FIG. 3 is a block diagram illustrating an FFT apparatus according to the preferred embodiment of the present invention.
  • FIG.4 is a block diagram illustrating an operation mode selector.
  • FIG.5 is a block diagram illustrating a first delay commutator.
  • FIG. 6 is a conceptual diagram illustrating a data arrangement pattern of a first delay commutator.
  • FIG.7 is a block diagram illustrating a second delay commutator.
  • FIG. 8 is a conceptual diagram illustrating a data arrangement pattern of a second delay commutator.
  • FIG.9 is a block diagram illustrating a third delay commutator.
  • FIG. 10 is a conceptual diagram illustrating a data arrangement pattern of a third delay commutator.
  • FIG. 11 is a block diagram illustrating a fourth delay commutator.
  • FIG. 12 is a conceptual diagram illustrating a data arrangement pattern of a fourth delay commutator.
  • FIG. 13 is a block diagram illustrating an operation structure of an R4BF operator.
  • FIG. 14 is a block diagram illustrating an operation structure of an R2BF operator.
  • FIG. 15 is a block diagram illustrating an operation structure of a trivial multiplying unit.
  • FIG. 16 is a block diagram illustrating an operation structure of a W 8 operator.
  • FIG. 17 is a block diagram illustrating an operation structure of a scaling factor operation unit.
  • FIG. 18 is a block diagram illustrating an operation structure of a W 8 operator.
  • FIG. 19 is a block diagram illustrating an operation structure of a W 8 operator.
  • FIG. 20 is a block diagram illustrating an operation structure of a non-trivial multiplying unit.
  • FIG. 21 is a block diagram illustrating an operation structure of W 64 among a non-trivial multiplying unit shown in FIG.20.
  • FIG. 22 is a block diagram illustrating an operation structure of an actual multiplying unit. [Best Mode]
  • DFT discrete Fourier transform
  • Equation 1 In order to represent Equation 1 in a mixed form of Radix-4 and Radix- 2, if n and k for three-dimensional decomposition are substituted for Equation 1, Equation 2 is obtained.
  • Equation 2 BF 4 is summarized as follows. [Equation 3]
  • Equation 4 A twiddle factor as a coefficient of DFT may be summarized again, as represented by Equation 4. [Equation 4]
  • Equation 5 Equation 5
  • Equation 6 Equation 6
  • H(n 3 , k 1 , k 2 ) means a Radi ⁇ -2 butterfly operation. Since W 8 is trivial multiplication, an operation amount is reduced. If the above decomposition process is applied to the remaining N/8 points, it is possible to obtain a final equation of an MR algorithm where Radix-2 is mixed on the basis of Radix-4.
  • An FFT processor of an MRMDC scheme has a four-stage butterfly structure, and performs trivial multiplication two times and non-trivial multiplication once. Meanwhile, an FFT processor of an R4MDC scheme has a three-stage butterfly structure, and performs non-trivial multiplication two times. In the case of the R4MDC scheme, the number of stages is small. However, since a Radix-4 butterfly is equivalent to four Radix-2 butterflies, the number of s;ages is the same in both the MRMDC scheme and the R4MDC scheme. In the case of the R4MDC scheme where non-trivial multiplying units that are more complex than the butterfly operator are large, hardware complexity is high.
  • FIG. 2 is a signal flow graph illustrating an FFT signal using an MR algorithm according to the preferred embodiment of the present invention.
  • the FFT method and apparatus according to the preferred embodiment of the present invention have the 64-point structure in relation to the IEEE 802. Hn standardized systems. Since the 64-point structure may be easily applied to both the Radi ⁇ -4 scheme and the Radix-2 scheme, the 64-point structure may be easily applied to a 4X4 MIMO-OFDM system.
  • a 64-point MR FFT algorithm is configured by four stages that include a first stage (Sl), a second stage (S2), a third stage (S3), and a fourth stage (S4). Further, the first stage (Sl), the second stage (S2), and the third stage (S3) include a stage of first trivial multiplication (Ml), a stage of non-trivial multiplication (M2), and a stage of second trivial multiplication (M3), respectively.
  • the first stage (Sl) is a portion where the Radix-4 butterfly operation is performed.
  • the Radix-4 butterfly operation is performed by a first Radi ⁇ -4 butterfly operator 300 and a first trivial multiplying unit 400 shown in FIG.3.
  • the second stage (S2) is a portion where the Radix-2 butterfly operation is performed.
  • the Radix-2 butterfly operation is performed by a first Radix-2 butterfly operator 600 and a non-trivial multiplying unit 700 shown in FIG. 3. In the non-trivial multiplication
  • the fourth stage (S4) is a portion where the Radi ⁇ -2 butterfly operation is performed, similar to the second stage (S2) .
  • FFT fast Fourier transform
  • FIG. 3 is a block diagram illustrating an FFT apparatus according to the preferred embodiment of the present invention.
  • the FFT apparatus is used for an OFDM system and has a pipe-line structure. Since data is sequentially processed because of a characteristic of the OFDM system, the OFDM system is preferably implemented by using the pipe-line structure. Meanwhile, in a single butterfly structure, hardware complexity is lowest. However, since all operations are performed by only one operator, data processing time is long. A parallel structure has a fast processing time, but has high hardware complexity.
  • the FFT apparatus Since the FFT apparatus according to the preferred embodiment of the present invention is used for the MIMO-OFDM system, the FFT apparatus has an MDC structure among the pipe-line structure.
  • the MDC scheme is a scheme in which an input data flow is divided into parallel data flows and data is sequentially processed. In the MDC scheme, the amount of data processed is increased, but utilization (time used by an operator) is reduced to half of the original time.
  • an SDF (Single-path Delay Feedback) structure is suitable for an SISO-OFDM in terms of the operation amount and memory consumption
  • an SDC (Single-path Delay Commutator) structure is complex in terms of control . Referring to FIG.
  • the FFT apparatus includes a first operation mode selector 100, a first delay commutator 200, a first Radi ⁇ -4 butterfly operator 300 (hereinafter, referred to as “first R4BF operator”), a first trivial multiplying unit 400, a second delay commutator 500, a first Radi ⁇ -2 butterfly operator 600 (hereinafter, referred to as “first R2BF operator”), a non-trivial multiplying unit 700, a third delay commutator 800, a second Radix-4 butterfly operator 900 (hereinafter, referred to as "secnd R4BF operator”), a second trivial multiplying unit 1000, a fourth delay commutator 1100, a second Radi ⁇ -2 butterfly operator 1200 (hereinafter, referred to as "second R2BF operator”), and a second operation mode selector 1300.
  • the first operation mode selector 100 and the second operation mode selector 1300 that select FFT/IFFT operations are first provided at the first stage of an input terminal and the last stage of an output terminal, respectively.
  • the first delay commutator 200 and the fourth delay commutator 1100 that distribute 4-channel data are provided at the input/output terminals, respectively.
  • the R4BF operators 300 and 900 and the R2BF operators 600 and 1200 are provided to perform a butterfly operation.
  • a multiplier is provided. The multiplier is divided into the trivial multiplying units 400 and 1000 and the non-trivial multiplying unit 700.
  • FIG. 4 is a block diagram illustrating an operation mode selector.
  • IN rea i and IN imag denote a real part and an imaginary part of input data, respectively
  • 0UT rea i and 0UTi mag denote a real part and an imaginary part of output data, respectively.
  • the first operation mode selector 100 and the second operation mode selector 1300 are provided at the first stage of the input terminal and the last stage of the output terminal, respectively, and select FFT/IFFT operations. Since the IFFT operation can be expressed as the FFT operation as represented by the following Equation, the FFT apparatus can perform both the FFT operation and the IFFT operation using one hardware. [Equation 7]
  • IFFT(X(K)) (1/N)FFT(X * (K)) * is realized.
  • an input value of the FFT operation may take X (k) that is a complex conjugate number of an input value X(k) in the IFFT operation
  • an output value IFFT(X(k)) in the IFFT operation may take FFT(X * (k)) * that is a complex
  • the first operation mode selector 100 and the second operation mode selector 1300 are provided at the starting portion and the ending portion of the FFT processor. According to whether the FFT operation is performed or the IFFT operation is performed, a sign shifter (complement) 10 selects whether or not to change a sign of an imaginary part of the data. In this way, the FFT and the IFFT may be implemented by one processor.
  • the first operation mode selector 100 and the second operation mode selector 1300 do not operate the sign shifter 110 and output an imaginary part (IN imag ) of the input data as it is (OUTimag).
  • the first operation mode selector 100 operates the sign shifter 110 to change a sign of the imaginary part of the input value X(k), such that X (k) is input to the FFT apparatus.
  • the second operation mode selector 1300 operates the sign shifter 110 to change a sign of the imaginary part of the output value
  • FIG. 5 is a block diagram illustrating a first delay commutator and FIG. 6 is a conceptual diagram illustrating a data arrangement pattern of a first delay commutator.
  • the first delay commutator 200 sequentially distributes 4-channel data and arranges the data, such that the individual operations are sequentially performed.
  • the second path of the input terminal has 16 delay symbols
  • the third path thereof has 32 delay symbols
  • the fourth path thereof has 48 delay symbols.
  • the first path of the output terminal has 48 delay symbols
  • the second path thereof has 32 delay symbols
  • the third path thereof has 16 delay symbols.
  • data which is arranged in series to have the data distance of 64 for each path at the input terminal of the switching unit 210, is distributed in parallel to have the data distance of 16 for every four paths at the output terminal of the switching unit 210.
  • the data from 0 to 15 is arranged in the first path
  • the data from 16 to 31 is arranged in the second path
  • the data from 32 to 47 is arranged in the third path
  • the data from 48 to 63 is arranged in the fourth path.
  • FIG.7 is a block diagram illustrating a second delay commutator.
  • FIG. 8 is a conceptual diagram illustrating a data arrangement pattern of a second delay commutator.
  • the second delay commutator 500 receives data that has passed the first R4BF operator 300 and rearranges the data according to the data distance required by an R2 butterfly operation before the data is input to the first R2BF operator 600.
  • a delay corresponding to 8 is needed in each of the two input paths. That is, on the basis of the switching unit 510, the second path of the input terminal has 8 delay symbols and the fourth path thereof has 8 delay symbols.
  • the first path of the output terminal has 8 delay symbols and the third path has 8 delay symbols.
  • a data arrangement pattern is configured in two types. One is a data arrangement type where input data is output without being changed, and the other is a data arrangement type where data is exchanged between two adjacent paths. If data having the length of 16 points is input for every channel (INPUT), delay symbols are added at the input terminal of the switching unit 510 and data is arranged such that the distance between the data becomes 8 (DELAY). Then, switching is made in various patterns in the switching unit 510. Then, in order to perform a butterfly operation in the first R2BF operator 600, the data distance for each path at one channel is preferably adjusted to the distance that is required by the R2BF operation. As a result, for every channel, the data distance is adjusted to 8.
  • the delay symbols are added and the data is arranged. Accordingly, at the output terminal of the switching unit 510, the data is distributed in parallel such that each of the four paths has the data distance of 8.
  • the data of 0 to 7/16 to 23 is arranged in the first path
  • the data of 8 to 15/24 to 31 is arranged in the second path
  • the data of 32 to 39/48 to 55 is arranged in the third path
  • the data of 40 to 47/56 to 63 is arranged in the fourth path.
  • FIG. 9 is a block diagram illustrating a third delay commutator
  • FIG. 10 is a concept diagram illustrating a data arrangement pattern of a third delay commutator.
  • the third delay commutator 800 receives data that has passed the first R2BF operator 600 and rearranges the data according to the data distance required by an R4 butterfly operation before the data is input to the second R4BF operator 900.
  • delays corresponding to 2, 4, and 6 are needed in the three input paths, respectively. That is, on the basis of the switching unit 810, the second path of the input terminal has 2 delay symbols, the third path thereof has 4 delay symbols, and the fourth path thereof has 6 delay symbols.
  • the first path of the output terminal has 6 delay symbols, the second path thereof has 4 delay symbols, and the third path thereof has 2 delay symbols.
  • FIG. 11 is a block diagram illustrating a fourth delay commutator
  • FIG. 12 is a conceptual diagram illustrating a data arrangement pattern of a fourth delay commutator.
  • the fourth delay commutator 1100 receives the data that has passed the second R4BF operator 900 and rearranges the data according to the data distance required by an R2 butterfly operation before the data is input to the second R2BF operator 1200 that exists at the last stage.
  • a delay corresponding to 1 is needed for each of the two input paths. That is, on the basis of the switching unit 1210, the second path of the input terminal has a 1 delay symbol and the fourth path thereof has a 1 delay symbol.
  • the first path of the output terminal has a 1 delay symbol and the third path thereof has a 1 delay symbol.
  • FIG. 13 is a block diagram illustrating an operation structure of an R4BF operator.
  • the two R4BF operators are used. One is the first R4BF operator 300 that performs an R4BF operation on data arranged by the first delay commutator 200 and the other is the second R4BF operator 900 that performs an R4BF operation on data arranged by the third delay commutator 800.
  • the R4BF operators 300 and 900 may perform only the addition and subtraction of data. Referring to FIG.
  • each of the R4BF operators 300 and 900 primarily includes an adder between real parts, a subtracter between the real parts, an adder between imaginary parts, and a subtracter between the imaginary parts.
  • Each of the R4BF operators 300 and 900 secondarily includes an adder and a subtracter that perform an operation between the real part and the imaginary part.
  • FIG. 14 is a block diagram illustrating an operation structure of an R2BF operator.
  • the four R2BF operators are used.
  • the four R2BF operators include a pair of first R2BF operators 600 that perform an R2BF operation on the data arranged by the second delay commutator 500, and a pair of second R2BF operators 1200 that perform an R2BF operation on data arranged by the fourth delay commutator 1100.
  • the R2BF operators 600 and 1200 may perform only addition and subtraction between the data. Meanw ⁇ ile, as shown in FIG. 14, since the R2BF operators 600 and 1200 independently perform two R2BF operations, the operators are configured as pairs for the four data paths.
  • FIG. 15 is a block diagram illustrating an operation structure of a trivial multiplying unit
  • FIG. 16 is a block diagram illustrating an operation structure of a W 8 operator
  • FIG. 17 is a block diagram illustrating an operation structure of a scaling factor operation unit.
  • FIG. 18 is a block diagram illustrating an operation structure of a W 8 operator.
  • FIG. 19 is a block diagram illustrating a structure of a W 8 operator.
  • the trivial multiplying units 400 and 1000 are composed of a first trivial multiplying unit 400 that is located between the first R4BF operator 300 and the second delay commutator 500 and a second trivial multiplying unit 1000 that is located between the second R4BF operator 900 and the fourth delay commutator 1100.
  • the trivial multiplying units 400 and 1000 process W 8
  • W 8 multiplication may be defined as trivial multiplication. Accordingly, the trivial multiplying units 400 and 1000 do not require a separate complex
  • the W 8 operator 410 includes a real number adder 412, a real number subtracter 414, and a scaling factor operation unit 416.
  • a scaling factor operation unit 416 includes a 1- bit shifter 416a, a 3-bit shifter 416b, a 4-bit shifter 416c, a 6-bit shifter 416d, and an adder 416e.
  • the W 8 operator 420 is composed of only a sign shifter 422. Referring to FIG. 18, a sign of the real value IN rea i of the input is changed through the sign shifter 422 and the real value becomes an imaginary value OUTimag of the output. The imaginary value IN ini ag of the input becomes a real value OUTreai of the output.
  • a W 8 operator 430 includes a real number adder
  • the W 8 operation is the same operation as a phase rotation of -135 degrees on a complex plane, and thus it is composed of multiplication of a
  • the scaling factor operation unit 436 has the same structure as the scaling factor operation unit 416 of the W 8 operator 410.
  • FIG. 20 is a block diagram illustrating an operation structure of a non-trivial multiplying unit
  • FIG. 21 is a block diagram illustrating an operation structure of W 64 among a non-trivial multiplying unit shown in FIG.
  • FIG. 20 is a block diagram illustrating an operation structure of an actual multiplying unit.
  • W 64 multiplication may be defined as non-trivial multiplication.
  • the non-trivial multiplying unit 700 is provided between the first R2BF operator 600 and the third delay commutator 800.
  • the non-trivial multiplying unit 700 needs to independently perform multiplication for each path, the total four W 64 operators are included.
  • the non-trivial i j k multiplying unit 700 includes a W 64 operator 710, a W 64 operator 720, a W 64
  • the operators 710, 720, 730, and 740 have the same structure, except for the order of indexes generated. Since the data indexes do not overlap, there is no operator that can be shared.
  • the W 64 operator 710 includes an index generator 712, a trigonometric function generator 714, and an actual multiplying unit 716.
  • the W 64 operator 710 that is a non-trivial multiplying unit has a difference value of i according to an index of data that is processed in an MDC structure, and a proper value of i needs to be generated according to each data index.
  • the index generator 712 is provided.
  • a trigonometric function generator 714 is provided, which generates sin(i) and cos(i) according to the value of i that is generated by the index generator 712.
  • the trigonometric function generator 714 may be implemented by using a ROM table.
  • the trigonometric function generator 714 uses the value of i that receives from the index generator 712 and supplies cos( ⁇ i/32) and sin( ⁇ i/32) to the actual multiplying unit 716.
  • the actual multiplying unit 716 includes multiplication and addition operations between a cos value, a sin value, a real part input value, and an imaginary part input value, as represented by the following Equation. [Equation 12]
  • the actual multiplying unit 716 includes four real number multipliers 716a, 716b, 716c, and 716d and two adders 716e and 716f (refer to FIG.22).
  • the FFT method according to the preferred embodiment of the present invention can be understood by those skilled in the art on the basis of the above description of the FFT apparatus, and thus the detailed description will be omitted.
  • the hardware structure of the suggested FFT processor is designed using a Verilog HDL and the designed result is synthesized using a CMOS cell library of 0.18 ⁇ m.
  • the synthesize result is represented by a gate count, which is shown by the following Table 2.
  • R2 3 SDF is most efficient.
  • R2 SDF needs 4 processors. Accordingly, in terms of the final complexity of the FFT process in order to implement the 4-channel MIMO-OFDM system, the 4-chnnal MRMDC scheme is most preferable.
  • the present invention can be applied to all radio communication systems, such as an IEEE 802. Hn WLAN system, and a 4G radio communication system, which uses a MIMO-OFDM.
  • radio communication systems such as an IEEE 802. Hn WLAN system
  • 4G radio communication system which uses a MIMO-OFDM.
  • MIMO-OFDM MIMO-OFDM

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Discrete Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Theoretical Computer Science (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Radio Transmission System (AREA)

Abstract

La présente invention concerne un procédé de transformation de Fourier rapide pour un système WLAN MIMO-OFDM 4X4 et un appareil associé. La présente invention concerne plus paticulièrement un procédé de transformation de Fourier rapide pour un système WLAN MIMO-OFDM 4X4 et un appareil associé, dans lequel une structure MDC (commutateur de retard multivoies) multicanal est formée pour supporter des voies de données multiplex, quatre opérations de transformation de Fourier rapide nécessaires pour un système WLAN OFDM (multiplexage par répartition de fréquence orthogonale) MIMO (entrées multiples sorties multiples) 4x4 peuvent être traitées par un processeur, le nombre de multiplications non triviales peut être réduit par rapport à un processeur FFT MDC Radix 4 à 4 canaux existant dans lequel est utilisée une décomposition Radix efficace basée sur un système Radix, réduisant ainsi la complexité du matériel.
PCT/KR2008/000285 2007-07-26 2008-01-17 Procédé de transformation de fourier rapide et processeur pour système wlan mimo-ofdm 4x4 Ceased WO2009014291A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2007-0074930 2007-07-26
KR1020070074930A KR100929393B1 (ko) 2007-07-26 2007-07-26 4×4 다중입출력 직교주파수분할다중화 무선랜 시스템을위한 고속푸리에변환 방법 및 그 장치

Publications (1)

Publication Number Publication Date
WO2009014291A1 true WO2009014291A1 (fr) 2009-01-29

Family

ID=40281519

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2008/000285 Ceased WO2009014291A1 (fr) 2007-07-26 2008-01-17 Procédé de transformation de fourier rapide et processeur pour système wlan mimo-ofdm 4x4

Country Status (2)

Country Link
KR (1) KR100929393B1 (fr)
WO (1) WO2009014291A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104572578A (zh) * 2013-10-17 2015-04-29 德克萨斯仪器股份有限公司 用于显著改进微控制器中fft性能的新颖方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101016470B1 (ko) * 2009-02-27 2011-02-24 인하대학교 산학협력단 Ｍｉｍｏ－ｏｆｄｍ 시스템에 효율적인 반송파 변복조 장치및 방법
KR101711783B1 (ko) * 2016-01-06 2017-03-02 인하대학교 산학협력단 이중 경로 공유 기법을 이용한 고속 저 복잡도의 혼합 기수 고속 푸리에 변환 장치 및 방법
KR102301144B1 (ko) * 2019-12-20 2021-09-10 한국항공대학교산학협력단 저 복잡도의 단시간 푸리에 변환 처리 장치 및 그 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0329023A2 (fr) * 1988-02-16 1989-08-23 Array Microsystems, Inc. Dispositif pour effectuer un traitement numérique du signal comportant des opérations papillon de transformée rapide de Fourier de racine 4
US4868776A (en) * 1987-09-14 1989-09-19 Trw Inc. Fast fourier transform architecture using hybrid n-bit-serial arithmetic
US6366936B1 (en) * 1999-01-12 2002-04-02 Hyundai Electronics Industries Co., Ltd. Pipelined fast fourier transform (FFT) processor having convergent block floating point (CBFP) algorithm
US20050015420A1 (en) * 2003-07-18 2005-01-20 Gibb Sean G. Recoded radix-2 pipeline FFT processor
US20060129620A1 (en) * 2004-12-14 2006-06-15 Samsung Electronics Co., Ltd. FFT apparatus for high data rate and method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868776A (en) * 1987-09-14 1989-09-19 Trw Inc. Fast fourier transform architecture using hybrid n-bit-serial arithmetic
EP0329023A2 (fr) * 1988-02-16 1989-08-23 Array Microsystems, Inc. Dispositif pour effectuer un traitement numérique du signal comportant des opérations papillon de transformée rapide de Fourier de racine 4
US6366936B1 (en) * 1999-01-12 2002-04-02 Hyundai Electronics Industries Co., Ltd. Pipelined fast fourier transform (FFT) processor having convergent block floating point (CBFP) algorithm
US20050015420A1 (en) * 2003-07-18 2005-01-20 Gibb Sean G. Recoded radix-2 pipeline FFT processor
US20060129620A1 (en) * 2004-12-14 2006-06-15 Samsung Electronics Co., Ltd. FFT apparatus for high data rate and method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104572578A (zh) * 2013-10-17 2015-04-29 德克萨斯仪器股份有限公司 用于显著改进微控制器中fft性能的新颖方法
CN104572578B (zh) * 2013-10-17 2021-01-26 德克萨斯仪器股份有限公司 用于显著改进微控制器中fft性能的新颖方法

Also Published As

Publication number Publication date
KR20090011398A (ko) 2009-02-02
KR100929393B1 (ko) 2009-12-02

Similar Documents

Publication Publication Date Title
US8027398B2 (en) Method for solving high PAPR problem of MCM communication system using unitary transform
US7693034B2 (en) Combined inverse fast fourier transform and guard interval processing for efficient implementation of OFDM based systems
US8266196B2 (en) Fast Fourier transform twiddle multiplication
US7626923B2 (en) Method and apparatus of the variable points IFFT/FFT
US8229014B2 (en) Fast fourier transform processing in an OFDM system
WO2009014291A1 (fr) Procédé de transformation de fourier rapide et processeur pour système wlan mimo-ofdm 4x4
US7856465B2 (en) Combined fast fourier transforms and matrix operations
CN101069398B (zh) 用于进行mimo-ofdm系统的多流fft的方法和装置
KR101332850B1 (ko) 다중입출력 직교주파수분할다중화 시스템을 위한 고속 푸리에 변환 장치 및 방법
KR100720949B1 (ko) 직교 주파수 분할 다중화 시스템에서의 고속 푸리에 변환프로세서 및 그 변환 방법
Raja et al. VLSI implementation of high throughput MIMO OFDM transceiver for 4th generation systems
KR101165079B1 (ko) 다중입출력 직교주파수분할다중화 시스템을 위한 고속 푸리에 변환 장치 및 그 방법
US7593754B2 (en) Receiving apparatus and receiving method of communication system with multiple antennas
Kirubanandasarathy et al. Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA
KR101259044B1 (ko) 다중입출력 직교주파수분할다중화 기반 소프트웨어 정의 무선 시스템을 위한 고속 푸리에 변환 장치 및 그 방법
KR101554667B1 (ko) 고속 푸리에 변환 장치
Ho et al. A reconfigurable systolic array architecture for multicarrier wireless and multirate applications
Chitra et al. Design of low power mixed radix FFT processor for MIMO OFDM systems
Kirubanandasarathy et al. VLSI design of pipelined R2MDC FFT for MIMO OFDM transceivers
Kirubanandasarathy et al. Design and Analysis of an Area Efficient and Low Power NEW-R2MDC FFT for MIMO OFDM in wireless Communication
Nageswaran et al. VLSI Design and Investigation of an Area Efficient and Low Power MOD-R2MDC FFT for MOMO-OFDM
Kirubanandasarathy et al. Synthesis And Simulation Of New-R2MDC FFT For OFDM Receivers
Senthil et al. Design of adaptive MC-CDMA receiver using low power parallel-pipelined FFT architecture

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08704821

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08704821

Country of ref document: EP

Kind code of ref document: A1