[go: up one dir, main page]

WO2009013819A1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

Info

Publication number
WO2009013819A1
WO2009013819A1 PCT/JP2007/064561 JP2007064561W WO2009013819A1 WO 2009013819 A1 WO2009013819 A1 WO 2009013819A1 JP 2007064561 W JP2007064561 W JP 2007064561W WO 2009013819 A1 WO2009013819 A1 WO 2009013819A1
Authority
WO
WIPO (PCT)
Prior art keywords
state
sense amplifier
memory cell
resistance value
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/064561
Other languages
French (fr)
Japanese (ja)
Inventor
Akira Kotabe
Satoru Hanzawa
Toshihiro Tanaka
Yoshikazu Iida
Takashi Yamaki
Yukiko Umemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2009524346A priority Critical patent/JP5043942B2/en
Priority to PCT/JP2007/064561 priority patent/WO2009013819A1/en
Publication of WO2009013819A1 publication Critical patent/WO2009013819A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell

Landscapes

  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Read Only Memory (AREA)

Abstract

A semiconductor memory device storing information by using a change in resistance is provided with a sense amplifier (SA), a data latch (LATR) holding the output of the sense amplifier, and a data latch control circuit (LATRC) controlling the latch timing of the data latch in such a manner that it differs in a reading operation from in a verifying operation. For example, the latch timing in the reading operation can determine the states of a memory cell having the highest resistance value (Rsmax) in a first state (a set state) and the memory cell having the lowest resistance value (Rrmin) in a second state(a reset state) by the sense amplifier with equal level margins. In the verifying operation to the second state, the latch timing can discriminate the memory cell having the lowest resistance value or above in the second state from the second state.
PCT/JP2007/064561 2007-07-25 2007-07-25 Semiconductor memory device Ceased WO2009013819A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009524346A JP5043942B2 (en) 2007-07-25 2007-07-25 Semiconductor memory device
PCT/JP2007/064561 WO2009013819A1 (en) 2007-07-25 2007-07-25 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/064561 WO2009013819A1 (en) 2007-07-25 2007-07-25 Semiconductor memory device

Publications (1)

Publication Number Publication Date
WO2009013819A1 true WO2009013819A1 (en) 2009-01-29

Family

ID=40281082

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/064561 Ceased WO2009013819A1 (en) 2007-07-25 2007-07-25 Semiconductor memory device

Country Status (2)

Country Link
JP (1) JP5043942B2 (en)
WO (1) WO2009013819A1 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011065745A (en) * 2010-11-01 2011-03-31 Sharp Corp Nonvolatile semiconductor memory device and method of controlling the same
JP2011103155A (en) * 2009-11-10 2011-05-26 Sony Corp Memory device and method of reading the same
JP2011187144A (en) * 2010-03-11 2011-09-22 Toshiba Corp Semiconductor memory device
WO2014062558A1 (en) * 2012-10-15 2014-04-24 Marvell World Trade Ltd. Systems and methods for reading resistive random access memory (rram) cells
US8885388B2 (en) 2012-10-24 2014-11-11 Marvell World Trade Ltd. Apparatus and method for reforming resistive memory cells
US9042162B2 (en) 2012-10-31 2015-05-26 Marvell World Trade Ltd. SRAM cells suitable for Fin field-effect transistor (FinFET) process
US9042159B2 (en) 2012-10-15 2015-05-26 Marvell World Trade Ltd. Configuring resistive random access memory (RRAM) array for write operations
US9142284B2 (en) 2012-11-12 2015-09-22 Marvell World Trade Ltd. Concurrent use of SRAM cells with both NMOS and PMOS pass gates in a memory system
US9208865B2 (en) 2012-09-12 2015-12-08 Kabushiki Kaisha Toshiba Resistance-change memory
JP2020009516A (en) * 2018-07-11 2020-01-16 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． Method of storing data in nonvolatile memory device, method of erasing data, and nonvolatile memory device performing the same
CN111095300A (en) * 2017-09-07 2020-05-01 松下电器产业株式会社 Neural network operation circuit using semiconductor memory elements
JP2025119569A (en) * 2024-02-01 2025-08-14 エルジー ディスプレイ カンパニー リミテッド display device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004087002A (en) * 2002-08-27 2004-03-18 Fujitsu Ltd AC sense type memory circuit
JP2005267837A (en) * 2004-02-20 2005-09-29 Renesas Technology Corp Semiconductor device
JP2006031752A (en) * 2004-07-12 2006-02-02 Fujitsu Ltd Semiconductor memory device and method for controlling semiconductor memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004087002A (en) * 2002-08-27 2004-03-18 Fujitsu Ltd AC sense type memory circuit
JP2005267837A (en) * 2004-02-20 2005-09-29 Renesas Technology Corp Semiconductor device
JP2006031752A (en) * 2004-07-12 2006-02-02 Fujitsu Ltd Semiconductor memory device and method for controlling semiconductor memory device

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011103155A (en) * 2009-11-10 2011-05-26 Sony Corp Memory device and method of reading the same
JP2011187144A (en) * 2010-03-11 2011-09-22 Toshiba Corp Semiconductor memory device
US8488366B2 (en) 2010-03-11 2013-07-16 Kabushiki Kaisha Toshiba Semiconductor memory device
JP2011065745A (en) * 2010-11-01 2011-03-31 Sharp Corp Nonvolatile semiconductor memory device and method of controlling the same
US9208865B2 (en) 2012-09-12 2015-12-08 Kabushiki Kaisha Toshiba Resistance-change memory
US9047945B2 (en) 2012-10-15 2015-06-02 Marvell World Trade Ltd. Systems and methods for reading resistive random access memory (RRAM) cells
US9042159B2 (en) 2012-10-15 2015-05-26 Marvell World Trade Ltd. Configuring resistive random access memory (RRAM) array for write operations
WO2014062558A1 (en) * 2012-10-15 2014-04-24 Marvell World Trade Ltd. Systems and methods for reading resistive random access memory (rram) cells
US8885388B2 (en) 2012-10-24 2014-11-11 Marvell World Trade Ltd. Apparatus and method for reforming resistive memory cells
US9129678B2 (en) 2012-10-24 2015-09-08 Marvell World Trade Ltd. Method and apparatus for reforming a memory cell of a memory
US9042162B2 (en) 2012-10-31 2015-05-26 Marvell World Trade Ltd. SRAM cells suitable for Fin field-effect transistor (FinFET) process
US9142284B2 (en) 2012-11-12 2015-09-22 Marvell World Trade Ltd. Concurrent use of SRAM cells with both NMOS and PMOS pass gates in a memory system
CN111095300A (en) * 2017-09-07 2020-05-01 松下电器产业株式会社 Neural network operation circuit using semiconductor memory elements
CN111095300B (en) * 2017-09-07 2023-04-18 松下控股株式会社 Neural network operation circuit using semiconductor memory element
JP2020009516A (en) * 2018-07-11 2020-01-16 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． Method of storing data in nonvolatile memory device, method of erasing data, and nonvolatile memory device performing the same
JP7308057B2 (en) 2018-07-11 2023-07-13 三星電子株式会社 Method for storing data in non-volatile memory device, method for erasing data, and non-volatile memory device performing the same
JP2025119569A (en) * 2024-02-01 2025-08-14 エルジー ディスプレイ カンパニー リミテッド display device
JP7771335B2 (en) 2024-02-01 2025-11-17 エルジー ディスプレイ カンパニー リミテッド display device

Also Published As

Publication number Publication date
JPWO2009013819A1 (en) 2010-09-30
JP5043942B2 (en) 2012-10-10

Similar Documents

Publication Publication Date Title
WO2009013819A1 (en) Semiconductor memory device
WO2007103220A3 (en) Calibration system for writing and reading multiple states into phase change memory
WO2009016824A1 (en) Nonvolatile storage device
TW200723275A (en) Nonvolatile memory device
WO2008002813A3 (en) Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells having enhanced read and write margins
WO2007005703A3 (en) Identifying and accessing individual memory devices in a memory channel
WO2008079910A3 (en) Strobe acquisition and tracking
DK1899975T3 (en) Integrated circuit with separate supply voltage for storage, which is different from the supply voltage of the logic circuit
JP2010009674A5 (en)
JP2005302091A5 (en)
WO2009158677A3 (en) Short reset pulse for non-volatile storage 19
TW200710661A (en) Memory controller interface for micro-tiled memory access
WO2008027691A3 (en) Phase-change random access memory employing read before write for resistance stabilization
WO2009034687A1 (en) Nonvolatile storage apparatus and method for writing data into nonvolatile storage apparatus
WO2008126166A1 (en) Nonvolatile semiconductor storage device and reading method thereof
ATE482452T1 (en) REDUCING ENERGY CONSUMPTION DURING READING OPERATIONS FROM A NON-VOLATILE MEMORY
SG151220A1 (en) Method and device for irreversibly programming and reading nonvolatile memory cells
WO2007005551A3 (en) Automatic detection of micro-tile enabled memory
TW200614235A (en) Data readout circuit and semiconductor device having the same
WO2005017907A3 (en) Read bias scheme for phase change memories
WO2009023785A3 (en) Static random access memory cell testing and biasing
TW200715291A (en) Semiconductor storage device having memory cell for storing data by using difference in threshold voltage
TW200710419A (en) Voltage glitch detection circuits and methods thereof
WO2007140031A3 (en) Sram split write control for a delay element
TW200729206A (en) Method of controlling memory and memory system thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07791277

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009524346

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07791277

Country of ref document: EP

Kind code of ref document: A1