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WO2009013849A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2009013849A1
WO2009013849A1 PCT/JP2008/000843 JP2008000843W WO2009013849A1 WO 2009013849 A1 WO2009013849 A1 WO 2009013849A1 JP 2008000843 W JP2008000843 W JP 2008000843W WO 2009013849 A1 WO2009013849 A1 WO 2009013849A1
Authority
WO
WIPO (PCT)
Prior art keywords
planarizing
layer
auxiliary layer
conductive films
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/000843
Other languages
English (en)
French (fr)
Inventor
Yasumori Fukushima
Yutaka Takafuji
Kazuhide Tomiyasu
Michiko Takei
Steven Droes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to US12/600,813 priority Critical patent/US8101502B2/en
Priority to CN200880021899.8A priority patent/CN101689479B/zh
Publication of WO2009013849A1 publication Critical patent/WO2009013849A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6725—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having supplementary regions or layers for improving the flatness of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

　デバイス部形成工程が、第２平坦化層を形成する前に複数の導電膜を覆う平坦化補助層を第１平坦化層に形成する補助層形成工程を含み、この補助層形成工程では、第１平坦化層における基体層とは反対側表面からの平坦化補助層の高さが、導電膜が形成されている領域の少なくとも一部と、導電膜が形成されていない領域の少なくとも一部とにおいて、互いに等しくなるように平坦化補助層を形成するようにした。
PCT/JP2008/000843 2007-07-26 2008-04-01 半導体装置及びその製造方法 Ceased WO2009013849A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/600,813 US8101502B2 (en) 2007-07-26 2008-04-01 Semiconductor device and its manufacturing method
CN200880021899.8A CN101689479B (zh) 2007-07-26 2008-04-01 半导体装置及其制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-195069 2007-07-26
JP2007195069 2007-07-26

Publications (1)

Publication Number Publication Date
WO2009013849A1 true WO2009013849A1 (ja) 2009-01-29

Family

ID=40281111

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/000843 Ceased WO2009013849A1 (ja) 2007-07-26 2008-04-01 半導体装置及びその製造方法

Country Status (3)

Country Link
US (1) US8101502B2 (ja)
CN (1) CN101689479B (ja)
WO (1) WO2009013849A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011097042A1 (en) * 2010-02-04 2011-08-11 S.O.I.Tec Silicon On Insulator Technologies Methods and structures for forming integrated semiconductor structures
CN105679654A (zh) * 2016-01-27 2016-06-15 武汉新芯集成电路制造有限公司 一种用于混合式键合工艺的晶圆预处理工艺
WO2023074378A1 (ja) * 2021-10-26 2023-05-04 東京エレクトロン株式会社 基板処理装置、及び基板処理方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102079253B1 (ko) * 2013-06-26 2020-02-20 삼성디스플레이 주식회사 박막트랜지스터 기판, 이를 구비하는 유기 발광 장치, 박막트랜지스터 기판 제조방법 및 유기 발광 장치 제조방법
WO2022193010A1 (en) * 2021-03-16 2022-09-22 Vuereal Inc. A gimbal bonding tool and a method to correct surface non-uniformities using a bonding tool
CN114823821A (zh) * 2022-04-07 2022-07-29 深圳市华星光电半导体显示技术有限公司 Oled显示面板、其制造方法和oled显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0837187A (ja) * 1994-05-19 1996-02-06 Sanyo Electric Co Ltd 半導体装置及び半導体装置の製造方法
JPH0951034A (ja) * 1995-05-29 1997-02-18 Fujitsu Ltd 半導体装置の製造方法
JPH0974136A (ja) * 1995-09-07 1997-03-18 Nec Corp 半導体装置の製造方法
JPH11297972A (ja) * 1998-04-10 1999-10-29 Fujitsu Ltd 半導体装置の製造方法
JP2001028354A (ja) * 1999-05-12 2001-01-30 Sony Corp 半導体装置の製造方法
JP2001332620A (ja) * 2000-05-25 2001-11-30 Sharp Corp 半導体装置の製造方法
JP2005093757A (ja) * 2003-09-18 2005-04-07 Sharp Corp 薄膜半導体装置および薄膜半導体装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003234455A (ja) 2002-02-07 2003-08-22 Matsushita Electric Ind Co Ltd 電子デバイスの製造方法、電子デバイスおよび電子デバイス装置
JP2004071554A (ja) * 2002-07-25 2004-03-04 Sanyo Electric Co Ltd 有機ｅｌパネルおよびその製造方法
JP2005026472A (ja) 2003-07-02 2005-01-27 Sharp Corp 半導体装置の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0837187A (ja) * 1994-05-19 1996-02-06 Sanyo Electric Co Ltd 半導体装置及び半導体装置の製造方法
JPH0951034A (ja) * 1995-05-29 1997-02-18 Fujitsu Ltd 半導体装置の製造方法
JPH0974136A (ja) * 1995-09-07 1997-03-18 Nec Corp 半導体装置の製造方法
JPH11297972A (ja) * 1998-04-10 1999-10-29 Fujitsu Ltd 半導体装置の製造方法
JP2001028354A (ja) * 1999-05-12 2001-01-30 Sony Corp 半導体装置の製造方法
JP2001332620A (ja) * 2000-05-25 2001-11-30 Sharp Corp 半導体装置の製造方法
JP2005093757A (ja) * 2003-09-18 2005-04-07 Sharp Corp 薄膜半導体装置および薄膜半導体装置の製造方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011097042A1 (en) * 2010-02-04 2011-08-11 S.O.I.Tec Silicon On Insulator Technologies Methods and structures for forming integrated semiconductor structures
CN102859681A (zh) * 2010-02-04 2013-01-02 索泰克公司 用于形成集成半导体结构的方法和结构
KR101398084B1 (ko) 2010-02-04 2014-05-23 소이텍 집적 반도체 구조 형성 방법들 및 구조들
CN102859681B (zh) * 2010-02-04 2015-04-08 索泰克公司 用于形成集成半导体结构的方法和结构
US9034727B2 (en) 2010-02-04 2015-05-19 Soitec Methods and structures for forming integrated semiconductor structures
CN105679654A (zh) * 2016-01-27 2016-06-15 武汉新芯集成电路制造有限公司 一种用于混合式键合工艺的晶圆预处理工艺
WO2023074378A1 (ja) * 2021-10-26 2023-05-04 東京エレクトロン株式会社 基板処理装置、及び基板処理方法
JPWO2023074378A1 (ja) * 2021-10-26 2023-05-04
JP7761357B2 (ja) 2021-10-26 2025-10-28 東京エレクトロン株式会社 基板処理装置、及び基板処理方法

Also Published As

Publication number Publication date
US8101502B2 (en) 2012-01-24
CN101689479A (zh) 2010-03-31
CN101689479B (zh) 2012-05-23
US20100155905A1 (en) 2010-06-24

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