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WO2009008080A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
WO2009008080A1
WO2009008080A1 PCT/JP2007/063877 JP2007063877W WO2009008080A1 WO 2009008080 A1 WO2009008080 A1 WO 2009008080A1 JP 2007063877 W JP2007063877 W JP 2007063877W WO 2009008080 A1 WO2009008080 A1 WO 2009008080A1
Authority
WO
WIPO (PCT)
Prior art keywords
testing
resistive element
rmt
memory cell
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/063877
Other languages
French (fr)
Japanese (ja)
Inventor
Masaharu Kinoshita
Nozomu Matsuzaki
Satoru Hanzawa
Norikatsu Takaura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to PCT/JP2007/063877 priority Critical patent/WO2009008080A1/en
Priority to JP2009522478A priority patent/JPWO2009008080A1/en
Publication of WO2009008080A1 publication Critical patent/WO2009008080A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

In a memory circuit region (Z2) of a silicon substrate (1), a memory cell comprising a memory cell transistor (QM) and a resistive element (RM) is formed. In a testing region (Z3), a resistive element for testing (RMT) is formed. The resistive element (RM) and the resistive element for testing (RMT) both have the same structure including a memory layer (36) comprising a phase-change material. To each of an upper electrode (37) and a lower electrode (33) of the resistive element for testing (RMT), a bonding pad for testing is electrically connected.
PCT/JP2007/063877 2007-07-12 2007-07-12 Semiconductor device Ceased WO2009008080A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2007/063877 WO2009008080A1 (en) 2007-07-12 2007-07-12 Semiconductor device
JP2009522478A JPWO2009008080A1 (en) 2007-07-12 2007-07-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/063877 WO2009008080A1 (en) 2007-07-12 2007-07-12 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2009008080A1 true WO2009008080A1 (en) 2009-01-15

Family

ID=40228277

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/063877 Ceased WO2009008080A1 (en) 2007-07-12 2007-07-12 Semiconductor device

Country Status (2)

Country Link
JP (1) JPWO2009008080A1 (en)
WO (1) WO2009008080A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9006701B2 (en) 2012-10-15 2015-04-14 Panasonic Intellectual Property Management Co., Ltd. Non-volatile memory device having bit lines and source lines arranged in parallel and manufacturing method thereof
US9595563B2 (en) 2014-04-15 2017-03-14 Panasonic Intellectual Property Management Co., Ltd. Nonvolatile memory device
CN115249691A (en) * 2022-07-25 2022-10-28 长江存储科技有限责任公司 Semiconductor test structure, manufacturing method and test method thereof, and semiconductor device
CN117596898A (en) * 2023-11-29 2024-02-23 新存科技(武汉)有限责任公司 Phase change memory and its formation method, leakage test method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213901A (en) * 1996-01-30 1997-08-15 Nec Corp Semiconductor memory having tegs and testing method thereof
JP2006244561A (en) * 2005-03-01 2006-09-14 Renesas Technology Corp Semiconductor apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213901A (en) * 1996-01-30 1997-08-15 Nec Corp Semiconductor memory having tegs and testing method thereof
JP2006244561A (en) * 2005-03-01 2006-09-14 Renesas Technology Corp Semiconductor apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9006701B2 (en) 2012-10-15 2015-04-14 Panasonic Intellectual Property Management Co., Ltd. Non-volatile memory device having bit lines and source lines arranged in parallel and manufacturing method thereof
US9595563B2 (en) 2014-04-15 2017-03-14 Panasonic Intellectual Property Management Co., Ltd. Nonvolatile memory device
CN115249691A (en) * 2022-07-25 2022-10-28 长江存储科技有限责任公司 Semiconductor test structure, manufacturing method and test method thereof, and semiconductor device
CN117596898A (en) * 2023-11-29 2024-02-23 新存科技(武汉)有限责任公司 Phase change memory and its formation method, leakage test method
CN117596898B (en) * 2023-11-29 2024-05-31 新存科技(武汉)有限责任公司 Phase change memory, forming method thereof and leakage testing method

Also Published As

Publication number Publication date
JPWO2009008080A1 (en) 2010-09-02

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