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WO2009004889A1 - 薄膜シリコンウェーハ及びその作製法 - Google Patents

薄膜シリコンウェーハ及びその作製法 Download PDF

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Publication number
WO2009004889A1
WO2009004889A1 PCT/JP2008/060263 JP2008060263W WO2009004889A1 WO 2009004889 A1 WO2009004889 A1 WO 2009004889A1 JP 2008060263 W JP2008060263 W JP 2008060263W WO 2009004889 A1 WO2009004889 A1 WO 2009004889A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon wafer
thin film
fabricating method
film silicon
gettering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/060263
Other languages
English (en)
French (fr)
Inventor
Toshimi Tobe
Takao Takenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to US12/664,232 priority Critical patent/US8728870B2/en
Priority to JP2009521560A priority patent/JP5201420B2/ja
Priority to KR1020097021061A priority patent/KR101436313B1/ko
Publication of WO2009004889A1 publication Critical patent/WO2009004889A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10P36/07
    • H10P36/00
    • H10P10/128

Landscapes

  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

 高いゲッタリング能力を持った薄膜シリコンウェーハ及びその作製法並びに薄層シリコンウェーハを積層してなる多層シリコンウェーハ及びその作製法を提供する。  半導体シリコンウェーハの表面近傍に形成されるデバイス層の直下にゲッタリング層を1層あるいは複数層形成し、前記半導体シリコンウェーハのデバイス層にデバイスを作製し、当該デバイスの作製後、前記ゲッタリング層を少なくとも1層残して前記半導体シリコンウェーハの裏面から前記ゲッタリング層の直下までの部分を除去することによって作製され、薄膜化してもゲッタリング能力を有するようにした。
PCT/JP2008/060263 2007-07-04 2008-06-04 薄膜シリコンウェーハ及びその作製法 Ceased WO2009004889A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/664,232 US8728870B2 (en) 2007-07-04 2008-06-04 Thin film silicon wafer and method for manufacturing the same
JP2009521560A JP5201420B2 (ja) 2007-07-04 2008-06-04 多層シリコンウェーハの作製法
KR1020097021061A KR101436313B1 (ko) 2007-07-04 2008-06-04 다층 실리콘 웨이퍼의 제작법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007176310 2007-07-04
JP2007-176310 2007-07-04

Publications (1)

Publication Number Publication Date
WO2009004889A1 true WO2009004889A1 (ja) 2009-01-08

Family

ID=40225945

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/060263 Ceased WO2009004889A1 (ja) 2007-07-04 2008-06-04 薄膜シリコンウェーハ及びその作製法

Country Status (4)

Country Link
US (1) US8728870B2 (ja)
JP (1) JP5201420B2 (ja)
KR (1) KR101436313B1 (ja)
WO (1) WO2009004889A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009277713A (ja) * 2008-05-12 2009-11-26 Shin Etsu Handotai Co Ltd 多層シリコン半導体ウェーハ及びその作製方法
WO2010016457A1 (ja) * 2008-08-06 2010-02-11 株式会社Sumco エピタキシャルシリコンウェーハ及びその製造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8187983B2 (en) * 2009-04-16 2012-05-29 Micron Technology, Inc. Methods for fabricating semiconductor components using thinning and back side laser processing
FR3006236B1 (fr) * 2013-06-03 2016-07-29 Commissariat Energie Atomique Procede de collage metallique direct
JP2016009730A (ja) * 2014-06-23 2016-01-18 株式会社東芝 半導体装置の製造方法
KR101581009B1 (ko) 2014-07-18 2015-12-30 주식회사 영진비앤비 디바이스 웨이퍼용 접착제시트 부착장치
KR101581012B1 (ko) 2014-07-18 2015-12-30 주식회사 영진비앤비 디바이스 웨이퍼 접착제 도포방법
FR3048306B1 (fr) * 2016-02-26 2018-03-16 Soitec Support pour une structure semi-conductrice
US10522367B2 (en) 2017-03-06 2019-12-31 Qualcomm Incorporated Gettering layer formation and substrate
CN114496733B (zh) * 2022-04-15 2022-07-29 济南晶正电子科技有限公司 一种高电阻率复合衬底、制备方法及电子元器件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317805A (ja) * 2004-04-28 2005-11-10 Sharp Corp 薄型半導体装置の製造方法
JP2005317735A (ja) * 2004-04-28 2005-11-10 Elpida Memory Inc 半導体装置及びその製造方法
JP2006005063A (ja) * 2004-06-16 2006-01-05 Sharp Corp 半導体装置、半導体装置の製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0430561A (ja) * 1990-05-28 1992-02-03 Hitachi Ltd 半導体集積回路装置およびその実装構造
US6548382B1 (en) * 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
US6005335A (en) * 1997-12-15 1999-12-21 Advanced Vision Technologies, Inc. Self-gettering electron field emitter
US6083324A (en) * 1998-02-19 2000-07-04 Silicon Genesis Corporation Gettering technique for silicon-on-insulator wafers
JP2000353797A (ja) * 1999-06-11 2000-12-19 Mitsubishi Electric Corp 半導体ウエハおよびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317805A (ja) * 2004-04-28 2005-11-10 Sharp Corp 薄型半導体装置の製造方法
JP2005317735A (ja) * 2004-04-28 2005-11-10 Elpida Memory Inc 半導体装置及びその製造方法
JP2006005063A (ja) * 2004-06-16 2006-01-05 Sharp Corp 半導体装置、半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009277713A (ja) * 2008-05-12 2009-11-26 Shin Etsu Handotai Co Ltd 多層シリコン半導体ウェーハ及びその作製方法
WO2010016457A1 (ja) * 2008-08-06 2010-02-11 株式会社Sumco エピタキシャルシリコンウェーハ及びその製造方法

Also Published As

Publication number Publication date
US20100171195A1 (en) 2010-07-08
KR20100033473A (ko) 2010-03-30
JP5201420B2 (ja) 2013-06-05
JPWO2009004889A1 (ja) 2010-08-26
KR101436313B1 (ko) 2014-09-01
US8728870B2 (en) 2014-05-20

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