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WO2009002301A1 - Système et procédé d'élimination automatique de chute de tension ou chute ir, de violations d'un bloc de schéma de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de schéma (lvs propre) - Google Patents

Système et procédé d'élimination automatique de chute de tension ou chute ir, de violations d'un bloc de schéma de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de schéma (lvs propre) Download PDF

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Publication number
WO2009002301A1
WO2009002301A1 PCT/US2007/014702 US2007014702W WO2009002301A1 WO 2009002301 A1 WO2009002301 A1 WO 2009002301A1 US 2007014702 W US2007014702 W US 2007014702W WO 2009002301 A1 WO2009002301 A1 WO 2009002301A1
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WO
WIPO (PCT)
Prior art keywords
voltage drop
clean
violation
layout
correctness
Prior art date
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Ceased
Application number
PCT/US2007/014702
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English (en)
Inventor
Dan Rittman
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Individual
Original Assignee
Individual
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Application filed by Individual filed Critical Individual
Priority to PCT/US2007/014702 priority Critical patent/WO2009002301A1/fr
Publication of WO2009002301A1 publication Critical patent/WO2009002301A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Definitions

  • the present invention is generally related to the field of integrated circuits, and more particularly to a system and method for automatic correction of voltage drop violations within a mask layout block in the metallic, polysilicon, contacts and VIA's interconnects of an integrated circuit device, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • Nanometer designs contain millions of devices and operate at very high frequencies.
  • the current densities (current per cross-sectional area) in the signal lines and power are consequently high and can result in either signal or power electromigration problems.
  • Microelectronic integrated circuits such as computer chips, are used in a variety of products including personal computers, automobiles, communication systems, and consumer electronics products.
  • ICs become increasingly more powerful, their internal circuitry become increasingly more complex.
  • a present day IC usually contains millions of microscopic circuit structures such as transistors, resistors, and capacitors on a small silicon die or core.
  • the entire silicon core is encapsulated in plastic or ceramic, with a number of lead pins exposed to the outside world.
  • Power is generally supplied to the IC through one or more of these lead pins.
  • Bond wires typically conduct the power from the lead pins to power pad cells located on the core.
  • the power pad cells connect to a power-bus
  • a power-bus grid comprising of thin metal wires which route power to IC structures throughout the core.
  • a power-bus grid is typically constructed on several vertical layers, with the number of layers dependent on the IC fabrication technology used. All the power-bus wires are generally routed running parallel to either the width (horizontally-oriented wires) or the length (vertically-oriented wires) of the core.
  • Power-bus layers are usually named Metal 1, Metal 2, Metal 3, and so on, with Metal 2 located above Metal 1, Metal 3 located above Metal 2, and so on. Generally, each layer is connected to the layer immediately above it by metal plugs or vias which run between intersecting wire lines.
  • the power-bus grid is typically connected to the rest of the IC structures with plugs or contacts running from the Metal 1 bus lines to the IC transistors.
  • CAD Computer-Aided Design
  • a typical IC design process begins with a design specification. The specification is set by the goals and limitations of the design project. For example, a design application specified for use in a portable device may
  • the specification helps the designer determine the IC fabrication technology, supply voltage, and core size needed to implement the design.
  • HDL Hardware Description Language
  • VHDL Hardware Description Language
  • the abstracted code is generally converted into a database listing or a circuit netlist.
  • a netlist is typically a list of individual circuit components with a description of the connections between their inputs and outputs. Since the netlist is produced from a behavioral description of the circuitry, it does not include information relating to the physical position of the circuit structures in the circuit. Therefore, information such as the distance of power-bus wires connecting to the circuit structures is usually not contained in the netlist.
  • the netlist is generally input to a simulator which performs a pre-layout simulation of the circuit design. Simulation permits the designer to test whether a particular design works before it is built.
  • a simulator can provide simulated output results for circuit designs. By comparing the simulation results with the expected simulation output, the designer can make sure the design works before actually building the IC. If the simulation results do not conform to the original design objectives, the designer can return to the HDL code and adjust the design accordingly. The designer may also use a simulator to compare several design approaches to each other and find the most favorable design approach.
  • Layout tools help the designer map the individual circuit structures to physical locations on the IC core.
  • layout tools help route a power-bus grid which supplies power to the IC core.
  • Layout tools typically contain libraries with information regarding the physical and geometrical properties of the circuit structures created during the fabrication process. Using place-and-route algorithms, the layout tools "seed" the circuit structures along the power- bus grid. Once the IC layout is completed, the layout tools back-annotate the original netlist with additional structural data such as parasitic resistance and capacitance values, as well as power-bus wire resistance parameters. The back-annotated netlist is then run through a post-layout simulation to ensure proper functionality.
  • Post-layout simulation is expected to represent the ICs true performance, rigorously testing the actual loading of the circuits and power-bus lines. Post-layout simulation usually requires a long time to complete, typically taking several days to finish. Results from this simulation can reveal problems such as excessive power-bus voltage drop and electromigration, which are generally not discoverable during pre-layout simulation.
  • Voltage drop problems are a result of a large drop in voltage across a wire conducting an electric current.
  • the amount of voltage drop across a wire is proportional to the amount of current the wire is conducting and the wire's internal resistance.
  • One factor affecting a wire's resistance is its cross- sectional area. As the cross-sectional area of a wire is made smaller, the wire's resistance increases, causing a larger drop in voltage.
  • a large voltage drop across a power-bus wire can cause a lower than desired level of voltage at a particular point in the IC. When this low voltage is used to supply power to a transistor, the transistor's output response time to a change in input signal generally slows down.
  • Electromigration is caused when electrons flowing through a wire randomly collide into the atoms of the wire, "carrying" the atoms along their path and causing wire deterioration, much like ocean currents carry beach sand and cause beach erosion. Electromigration is generally most pronounced in thin wires with a relatively large amount of current flow (high current density).
  • Electromigration causes a gradual thinning out of the wire, thereby exacerbating the electromigration problem even more and creating a positive feedback effect. Electromigration typically leads to voltage drop across a wire, and eventually to a break in the wire.
  • a drawback of over-estimating circuit power requirements is a sub-optimal use of the ICs available silicon core space. Since each component and wire within an IC takes up room on the silicon core, IC designers typically try to decrease the size of these components and wires so that ever more powerful circuits can be constructed in the IC core. Having more room on the IC core allows designers to add more circuit components and increase the ICs functionality. Thus, power-bus wires designed thicker than actually needed tend to waste valuable room on the IC.
  • a method for eliminating voltage drop violations of a mask layout block includes automatic correction of voltage drop violations within mask layout block if identified, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • an automated method for eliminating voltage drop violations of a mask layout block includes analyzing a selected polygon(s) or signals by their names in a mask layout block in GDSII format or any industry standard layout editor's database and obtaining one or more voltage drop information associated with the polygon from a technology or external constraints file.
  • the method provides a violation marker associated with the selected position for the polygon that graphically represents a space, width or length in the mask layout block where the selected polygon's position complies with the voltage drop requirements.
  • an automated method for eliminating voltage drop violations of a mask layout block includes analyzing a selected polygon or signal by its name in a mask layout block and identifying a voltage drop violation in the mask layout block if the selected position, with or length of the polygon creates a voltage drop value which is not permitted according to a technology or external constraints file. If a voltage drop violation is identified, the system automatically correcting the violation by moving, adjusting or modifying the problematic polygon or polygons, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness. The system works throughout entire layout block hierarchy.
  • a computer system for eliminating voltage drop violations of a mask layout block includes a processing resource coupled to a computer readable memory.
  • Processing instructions are encoded in the computer readable memory.
  • the instructions analyze a selected polygon or signal by its name in a mask layout block and identify a voltage drop violation in the mask layout block if the selected position is creating a voltage drop violations according to information extracted from a technology or external constraints file.
  • the instructions automatically correcting it via adjusting, moving or modifying the analyzed polygon or signal, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • Important technical advantages of certain embodiments of the present invention include a voltage drop Auto Correct (IR Drop ⁇ uito Correct) tool that automatically corrects voltage drop violations of a mask layout block while maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • a layout designer may execute an IC layout block with voltage drop violations.
  • the IR Drop AioitQ Correct tool highlights a violation marker that may represent a width, space or length in the layout block and eliminates the voltage drop violation according to technology or external constraints file.
  • the IU Drop A ⁇ fco Correct tool provides an information window with the current and fixed voltage drop conditions related to the selected polygon or signal.
  • the correction action may change polygon's width, length or space according to voltage drop rules taken from technology or external constraints file while maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • the system will automatically adjust the amount of contacts or vias according to voltage drop rules taken from technology or external constraints file.
  • the processed mask layout block therefore, may be free of voltage drop violations.
  • Another important technical advantage of certain embodiments of the present invention includes IR Drop A ⁇ tto Correct, tool that significantly reduces the design time for an integrated circuit. In a typical integrated
  • a voltage drop check (IR Drop Check) tool analyzes a mask layout file for voltage drop violations and identifies any violations in an output file.
  • a layout designer may use the output file to manually eliminate the identified voltage drop violations.
  • the same IC layout block needs to be re-checked for voltage drop again and also other checks like reliability (Electromigration & self heat), DRC (Design Rule Check) and LVS (Layout vs. Schematics) to make sure that the connectivity and geometrical sizes are still correct according to technology file and schematics respectfully.
  • the time needed to complete the entire design process for the integrated circuit therefore, may be substantially reduced since the steps of checking the layout with an IR Drop tool and manually correcting the identified voltage drop violations may be eliminated using the automated software as described in this invention.
  • FIG. 1 illustrates seven Metals wires. These wires are connected through VIAl (For Metall to Metal2 connection) and VIA2. (For Metal2 to Metal3 connection)
  • FIG. 2 illustrates seven Metals, each analyzed for voltage drop conditions, defined by the process technology and/or external constraints file. All Metal2 lines WIDTH was found smaller then required for voltage drop requirements. Metal3 line LENGTH was found shorter then required by voltage drop restrictions. The violation markers represent a voltage drop violations on the polygons that they are attached into.
  • Metal 2 wires have WIDTH violation shown by violation markers.
  • Metal 3 wire has LENGTH violation shown by violation markers.
  • FIG. 3 illustrates the Metal2 and Metal3 lines after the IR Drop Ainito Correct tool correction action.
  • the Metal2 lines are WIDER and include more VIAl's.
  • the Metal3 line is LONGER and includes more VIA2.
  • FIG. 4 illustrates a flow chart for one example of a method for automatic elimination of voltage drop violations of a mask layout block in accordance with teachings of the present invention.
  • the processing instructions may include a commercially available layout editor interfaced with a voltage drop Auto correct (IR Drop A ⁇ to Correct) tool or an independent IC layout block in GDSII format or any other commercial format database.
  • the IR Drop Auto Correct tool may provide the ability to analyze the width, length and placement of polygons in a mask layout block and determine if a voltage drop violation was created.
  • the IR Drop Auto Correct tool may provide the ability to analyze the number of contacts and VIA's, determine the amount needed in order to comply with voltage drop requirements.
  • the IR Drop Auto Correct tool may automatically connect, all voltage drop violation maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • the IR Drop Auto Correct tool reads the layout block information from GDSII format file or from industry standard layout editor's database system. In addition the IR Drop Auto Correct tool reads a technology and/or external constraints file corresponding to a desired manufacturing process. The technology file may contain design rules for the desired manufacturing process that ensures an integrated circuit fabricated on a semiconductor wafer, functions correctly. Furthermore, the tool has an option to read another constraints file which contains layout extraction information (resistance and capacitance values) per circuit net.
  • the voltage drop information may impact the minimum or maximum allowable feature dimensions (e.g., metal and polysilicons wires width, spaces and length) for the desired manufacturing process. In addition the voltage drop information may impact the correct number of contacts and VIA's in order to maintain accurate electrical current flow without causing metal lines failures.
  • the IR Drop Auto Correct tool then uses the voltage drop information to automatically fix voltage drop violations of the mask layout block.
  • the IR Drop Auto Correct tool uses the voltage drop information to graphically display the violations through a violation marker layer that is provided with industry standard layout editors.
  • the IR Drop Auto Correct tool may graphically represent the violation marker in the mask layout block by highlighting the required width, length or space with an appropriate color and/or pattern.
  • the violation marker color and/or pattern can be set in an initial tool setup.
  • the IR Drop Auto Correct tool may show an Information Window with the current and fixed results. The Information Window also provides with the option to accept the correct new layout or ignore the correction results.
  • the IR Drop Auto Correct tool may guide the layout designer about voltage drop violations within the mask layout block using violation marker. If the layout designer chooses to comply with the voltage drop corrections, the IR Drop Auto Correct tool automatically creates new layout cell that includes all corrections and maintains the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • the IR Drop Auto Correct operates in flat mode and hierarchical mode. When layout designer chooses to work in hierarchical mode, the IR Drop Auto Correct tool will work throughout the entire hierarchy correcting all voltage drop violations, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness. In Flat Mode the IR Drop Auto Correct tool will fix all voltage drop violations in the current cell level only, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • the IR Drop Auto Correct tool is included an entire layout block Check mode. This mode is aimed to be activated with the completion of the entire layout block. Using this feature the entire block will be analyzed for voltage drop violations. When analysis is complete all violations will be shown using violation marker. This mode operates in flat or fully hierarchical mode.
  • the processing instructions for automatic correction of voltage drop violations in a mask layout file may be encoded in computer-usable media.
  • Such computer-usable media may include, without limitation, storage media such as floppy disks, hard disks, CD-ROMS, DVDs, read-only memory, and random access memory; as well as communications media such wires, optical fibers, microwaves, radio waves, and other electromagnetic or optical carriers.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un système et un procédé de correction automatique de chute de tension (violation de chute IR) d'un bloc de schéma de masque, en maintenant l'exactitude des règles de conception de processus (DRC propre) et de la connectivité de schéma (LVS propre). Le procédé comprend l'analyse de polygones ou de signaux pour des violations de chute de tension, dans un bloc de schéma de masque, et l'obtention d'une ou de plusieurs informations de restriction de chute de tension associées à des polygones ou à des signaux par une technologie et un fichier de contraintes externe. Le système corrige automatiquement toutes les violations de chute de tension s'il y en a, en changeant l'espace, la largeur et la longueur des polygones. Le procédé comprend également l'analyse et la correction automatique de contacts et de VIA en fonction de la quantité et de l'emplacement, afin de répondre aux exigences de chute de tension provenant de la technologie ou d'un fichier de contraintes externe. Le procédé fournit un marqueur de violation associé à une position de polygones ou de signaux représentant graphiquement une violation de largeur, d'espace, ou de longueur.
PCT/US2007/014702 2007-06-25 2007-06-25 Système et procédé d'élimination automatique de chute de tension ou chute ir, de violations d'un bloc de schéma de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de schéma (lvs propre) Ceased WO2009002301A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2007/014702 WO2009002301A1 (fr) 2007-06-25 2007-06-25 Système et procédé d'élimination automatique de chute de tension ou chute ir, de violations d'un bloc de schéma de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de schéma (lvs propre)

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PCT/US2007/014702 WO2009002301A1 (fr) 2007-06-25 2007-06-25 Système et procédé d'élimination automatique de chute de tension ou chute ir, de violations d'un bloc de schéma de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de schéma (lvs propre)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10546089B1 (en) 2018-07-31 2020-01-28 International Business Machines Corporation Power plane shape optimization within a circuit board
CN110968979A (zh) * 2018-09-28 2020-04-07 台湾积体电路制造股份有限公司 静态电压（sir）下降违规预测系统和方法
CN112749526A (zh) * 2019-10-30 2021-05-04 瑞昱半导体股份有限公司 电源轨设计方法、装置及其非瞬时计算机可读介质
CN116127901A (zh) * 2023-01-06 2023-05-16 联芸科技(杭州)股份有限公司 电压降违例修复方法、相关装置和介质
CN117892681A (zh) * 2024-03-15 2024-04-16 北京壁仞科技开发有限公司 修复电压降的方法、电子设备、存储介质和程序产品

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050132306A1 (en) * 2002-06-07 2005-06-16 Praesagus, Inc., A Massachusetts Corporation Characterization and reduction of variation for integrated circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050132306A1 (en) * 2002-06-07 2005-06-16 Praesagus, Inc., A Massachusetts Corporation Characterization and reduction of variation for integrated circuits

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10546089B1 (en) 2018-07-31 2020-01-28 International Business Machines Corporation Power plane shape optimization within a circuit board
CN110968979A (zh) * 2018-09-28 2020-04-07 台湾积体电路制造股份有限公司 静态电压（sir）下降违规预测系统和方法
CN110968979B (zh) * 2018-09-28 2023-08-29 台湾积体电路制造股份有限公司 静态电压（sir）下降违规预测系统和方法
CN112749526A (zh) * 2019-10-30 2021-05-04 瑞昱半导体股份有限公司 电源轨设计方法、装置及其非瞬时计算机可读介质
CN112749526B (zh) * 2019-10-30 2024-05-07 瑞昱半导体股份有限公司 电源轨设计方法、装置及其非瞬时计算机可读介质
CN116127901A (zh) * 2023-01-06 2023-05-16 联芸科技(杭州)股份有限公司 电压降违例修复方法、相关装置和介质
CN117892681A (zh) * 2024-03-15 2024-04-16 北京壁仞科技开发有限公司 修复电压降的方法、电子设备、存储介质和程序产品

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